NSC 5962-9231401QLA, 5962-9231401QKA, 5962-9231401Q3A Datasheet

54ABT543
Octal Registered Transceiver with TRI-STATE

®

Outputs

General Description

The ’ABT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direc­tion. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow.

Features

n Back-to-back registers for storage

n Bidirectional data path
n A and B outputs have current sourcing capability of 24

mA and current sinking capability of 48 mA

n Separate controls for data flow in each direction
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire

power up and power down cycle

n Nondestructive hot insertion capability
n Standard Military Drawing (SMD) 5962-9231401

Ordering Code:

Military Package Package Description

Number

54ABT543J-QML J24A 24-Lead Ceramic Dual-In-Line
54ABT543W-QML W24C 24-Lead Cerpack
54ABT543E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C

Connection Diagrams

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Pin Assignment for

DIP and Flatpak

DS100218-1

Pin Assignment

for LCC

DS100218-2

August 1998

54ABT543 Octal Registered Transceiver with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100218 www.national.com

Pin Descriptions

Pin Names Description

OEAB , OEBA

Output Enable Inputs

LEAB , LEBA

Latch Enable Inputs

CEAB , CEBA

Chip Enable Inputs

A

0–A7

Side A Inputs or
TRI-STATE Outputs

B

0–B7

Side B Inputs or
TRI-STATE Outputs

Functional Description

The ’ABT543 contains two sets of D-type latches, with sepa­rate input and output controls for each. For data flow from A
to B, for example, the Ato B Enable (CEAB ) input must be
low in order to enter data from the A port or take data from
the B port as indicated in the Data I/O Control Table. With
CEAB low, a low signal on (LEAB ) input makes the A to B
latches transparent; a subsequent low to high transition of
the LEAB line puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB
and OEAB both low, the B output buffers are active and re­flect the data present on the output of the A latches. Control
of data flow from B toAis similar, but using the CEBA , LEBA
and OEBA .

Data I/O Control Table

Inputs Latch Status Output

Buffers

CEAB

LEAB OEAB

H X X Latched High Z
X H X Latched —
L L X Transparent —
X X H — High Z
L X L — Driving

H=High Voltage Level
L=Low Voltage Level
X=Immaterial

Logic Diagram

DS100218-3

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National SemiconductorSales Office/
Distributors for availability and specifications.

Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias

Ceramic −55˚C to +175˚C

V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disable or Power-Off State −0.5V to +5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Recommended Operating
Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns

DC Electrical Characteristics

Symbol Parameter ABT543 Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min I

IN

=

−18 mA (Non I/O Pins)

V

OH

Output HIGH Voltage 54ABT 2.5 I

OH

=

−3 mA, (A

n,Bn

)

54ABT 2.0 V Min I

OH

=

−24 mA, (A

n,Bn

)

V

OL

Output LOW Voltage 54ABT 0.55 V Min I

OL

=

48 mA, (A

n,Bn

)

V

ID

Input Leakage Test 4.75 V 0.0 I

ID

=

1.9 µA, (Non-I/O Pins)

All Other Pins Grounded

I

IH

Input HIGH Current

5 µA Max

V

IN

=

2.7V (Non-I/O Pins)

(Note 3)
V

IN

=

V

CC

(Non-I/O Pins)

I

BVI

Input HIGH Current Breakdown Test 7 µA Max V

IN

=

7.0V (Non-I/O Pins)

I

BVIT

Input HIGH Current 100 µA Max V

IN

=

5.5V (A

n,Bn

)

Breakdown Test (I/O)

I

IL

Input LOW Current

−5 µA Max

V

IN

=

0.5V (Non-I/O

Pins)(Note 3)
V

IN

=

0.0V (Non-I/O Pins)

I

IH+IOZH

Output Leakage Current 50 µA 0V–5.5V V

OUT

=

2.7V (A

n,Bn

);

OEAB or CEAB=2V

IIL+I

OZL

Output Leakage Current −50 µA 0V–5.5V V

OUT

=

0.5V (A

n,Bn

);

OEAB or CEAB=2V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

=

0V (A

n,Bn

)

I

CEX

Output HIGH Leakage Current 50 µA Max V

OUT

=

V

CC(An,Bn

)

I

ZZ

Bus Drainage Test 100 µA 0.0V V

OUT

=

5.5V (A

n,Bn

);

All Others GND

I

CCLH

Power Supply Current 50 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 50 µA Max Outputs TRI-STATE

All Others at V

CC

or GND

I

CCT

Additional ICC/Input 2.5 mA Max V

I

=

V

CC

− 2.1V

All Others at V

CC

or GND

I

CCD

Dynamic I

CC

No Load Outputs Open, CEAB

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