NSC 5962-9220001MLA, 5962-9220001MKA, 5962-9220001M3A Datasheet
54ACTQ841
Quiet Series 10-Bit Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’ACTQ841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ’841 is a 10-bit transparent latch,
a 10-bit version of the ’373. The ’ACTQ841 utilizes NSC
Quiet Series technology to guarantee quiet output switching
and improved dynamic threshold performance, FACT Quiet
Series
™
features GTO™output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n Improved latch-up immunity
n Outputs source/sink 24 mA
n ’ACTQ841 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD) 5962-92200
Logic Symbols
Pin Names Description
D
0–D9
Data Inputs
O
0–O9
TRI-STATE Outputs
OE
Output Enable
LE Latch Enable
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
DS100250-1
DS100250-2
August 1998
54ACTQ841 Quiet Series 10-Bit Transparent Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100250 www.national.com
Connection Diagrams
Functional Description
The ’ACTQ841 consists of ten D-type latches with
TRI-STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in
transition.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the
bus output is in the high impedance state.
Function Table
Inputs Internal Output Function
OE
LE D Q O
X X X X Z High Z
H H L L Z High Z
H H H H Z High Z
H L X NC Z Latched
L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impendance
NC=No Change
Logic Diagram
Pin Assignment
for DIP and Flatpack
DS100250-3
Pin Assignment
for LCC
DS100250-4
DS100250-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latch-Up Source
or Sink Current
±
300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
Note 2: All outputs loaded; thresholds on input associated with output under
test.
DC Electrical Characteristics for ’ACTQ Family Devices
Symbol Parameter V
CC
(V)
54ACTQ Units Conditions
T
A
=
−55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=
0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=
−50 µA
Output Voltage 5.5 5.4
(Note 3)
V
IN
=
V
IL
or V
IH
4.5 3.70 V I
OH
=
−24 mA
5.5 4.70 I
OH
=
−24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 3)
V
IN
=
V
IL
or V
IH
4.5 0.50 V I
OL
=
−24 mA
5.5 0.50 I
OL
=
−24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
OZ
Maximum 5.5
±
10.0 µA V
I
=
V
IL,VIH
TRI-STATE V
O
=
V
CC
, GND
Leakage Current
I
CCT
Maximum ICC/Input 5.5 1.6 mA V
I
=
V
CC
− 2.1V
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