NSC 5962-9160701MSA, 5962-9160701MRA, 5962-9160701M2A Datasheet
54ACT323
8-Bit Universal Shift/Storage Register with Synchronous
Reset and Common I/O Pins
General Description
The ’ACT323 is an 8-bit universal shift/storage register with
TRI-STATE
®
outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q
0
and Q7to allow easy
cascading. Four operation modes are possible: hold (store),
shift left, shift right and parallel load.
Features
n ICCand IOZreduced by 50
%
n Common parallel I/O for reduced pin count
n Additional serial inputs and outputs for expansion
n Four operating modes: shift left, shift right, load and
store
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n TTL-compatible inputs
n Standard Military Drawing (SMD)
—’ACT323: 5962-91607
Logic Symbols
Pin Name Description
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0,S1
Mode Select Inputs
SR
Synchronous Reset Input
OE
1
,OE2TRI-STATE Output Enable Inputs
I/O
0
–I/O
7
Multiplexed Parallel Data Inputs or
TRI-STATE Parallel Data Outputs
Q
0,Q7
Serial Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
DS100328-1
DS100328-5
July 1998
54ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
© 1998 National Semiconductor Corporation DS100328 www.national.com
Connection Diagrams Functional Description
The ’ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S1as shown
in the Mode Select Table.All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q7are
also brought out on other pins for expansion in serial shifting
of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
AHIGH signal on either OE
1
or OE2disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, load, hold and reset operations can
still occur.TheTRI-STATE buffers are also disabled by HIGH
signals on both S
0
and S1in preparation for a parallel load
operation.
Mode Select Table
Inputs Response
SR
S1S0CP
LXX
N
Synchronous Reset; Q0–Q
7
=
LOW
HHH
N
Parallel Load; I/O
n
→
Q
n
HLHNShift Right; DS
0
→
Q
0,Q0
→
Q
1
, etc.
HHL
N
Shift Left; DS
7
→
Q
7,Q7
→
Q
6
, etc.
H L L X Hold
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
N
=
LOW-to-HIGH Clock Transition
Pin Assignment for
DIP and Flatpak
DS100328-2
Pin Assignment
for LCC
DS100328-3
www.national.com 2
Logic Diagram
DS100328-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.national.com
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