NSC 5962-89749012A, 5962-8974901EA Datasheet

54AC191
Up/Down Counter with Preset and Ripple Clock

General Description

The ’AC191 is a reversible modulo 16 binary counter. It fea­tures synchronous counting and asynchronous presetting.
The preset featureallows the ’AC191 to be used in program­mable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a variety
of methods of implementing multistage counters. In the
counting modes, state changes are initiated by the rising
edge of the clock.

Features

n ICCreduced by 50

%

n High speed — 133 MHz typical count frequency
n Synchronous counting
n Asynchronous parallel load
n Cascadable
n Outputs source/sink 24 mA
n Standard Military Drawing (SMD)

— ’AC191: 5962-89749

Logic Symbols

Pin Names Description

CE

Count Enable Input
CP Clock Pulse Input
P

0–P3

Parallel Data Inputs
PL

Asynchronous Parallel Load Input
U/D

Up/Down Count Control Input
Q

0–Q3

Flip-Flop Outputs
RC

Ripple Clock Output
TC Terminal Count Output

Connection Diagrams

FACT™is a trademark of Fairchild Semiconductor Corporation.

DS100279-1

IEEE/IEC

DS100279-2

Pin Assignment

for DIP and Flatpack

DS100279-3

Pin Assignment for LCC

DS100279-4

July 1998

54AC191 Up/Down Counter with Preset and Ripple Clock

© 1998 National Semiconductor Corporation DS100279 www.national.com

Functional Description

The ’AC191 is a synchronous up/down counter. The ’AC191
is organized as a 4-bit binary counter. It contains four
edge-triggered flip-flops with internal gating and steering
logic to provide individual preset, count-up and count-down
operations.

Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Load inputs (P0–P3) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.

AHIGH signal on the CE input inhibits counting. When CE is
LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction
of counting is determined by the U/D input signal, as indi­cated in the Mode Select Table. CE and U/D can be changed
with the clock in either state, provided only that the recom­mended setup and hold times are observed.

Two types of outputs are provided as overflow/underflow in­dicators. The terminal count (TC) output is normally LOW. It
goes HIGH when the circuits reach zero in the count down
mode or 15 in the count up mode. The TC output will then re­main HIGH until a state change occurs, whether by counting
or presetting or until U/D is changed. The TC output should
not be used as a clock signal because it is subject to decod­ing spikes.

The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RCoutput wil go LOW when the
clock next goes LOW and will stay LOW until the clock goes
HIGH again. This feature simplifies the design of multistage
counters, as indicated in

Figure 1

and

Figure 2

.In

Figure 1

,
each RC output is used as the clock input for the next higher
stage. This configuration is particularly advantageous when
the clock source has a limited drive capability,since it drives
only the first stage. To prevent counting in all stages it is only
necessary to inhibit the first stage, since a HIGH signal on
CE inhibits the RC output pulse, as indicated in the RC Truth
Table. A disadvantage of this configuration, in some applica­tions, is the timing skew between state changes in the first
and last stages. This represents the cumulative delay of the
clock as it ripples through the preceding stages.

A method of causing state changes to occur simultaneously
in all stages is shown in

Figure 2

. All clock inputs are driven
in parallel and the RC outputs propagate the carry/borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the
negative-going edge of the carry/borrow signal to ripple
through to the last stage before the clock goes HIGH. There
is no such restriction on the HIGH state duration of the clock,
since the RC output of any device goes HIGH shortly after its
CP input goes HIGH.

The configuration shown in

Figure 3

avoids ripple delays and
their associated restrictions. The CE input for a given stage
is formed by combining the TC signals from all the preceding
stages. Note that in order to inhibit counting an enable signal
must be included in each carry gate. The simple inhibit
scheme of

Figure 1

and

Figure 2

doesn’t apply,because the

TC output of a given stage is not affected by its own CE.

Mode Select Table

Inputs Mode

PL

CE U/D CP

HL L

N

Count Up

HL H

N

Count Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)

RC Truth Table

Inputs Outputs

PL

CE TC

*

CP RC

HL H

JJ

HH X X H
HXLX H
LXXX H

*

TC is generated internally
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial

N

=

LOW-to-HIGH Transition

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Functional Description (Continued)

DS100279-7

FIGURE 1. N-Stage Counter Using Ripple Clock

DS100279-8

FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow

DS100279-9

FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow

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