NSC 54F258ALMQB, 54F258ADMQB Datasheet

TL/F/9508
54F/74F258A Quad 2-Input Multiplexer with TRI-STATE Outputs
November 1994
54F/74F258A Quad 2-Input Multiplexer with TRI-STATE
É
Outputs
General Description
) input, allowing
the outputs to interface directly with bus-oriented systems.
Features
Y
Multiplexer expansion by tying outputs together
Y
Inverting TRI-STATE outputs
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F258APC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F258ADM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F258ASC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F258ASJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F258AFM (Note 2) W16A 16-Lead Cerpack
54F258ALL (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/9508– 3
IEEE/IEC
TL/F/9508– 5
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9508– 1
Pin Assignment
for LCC
TL/F/9508– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
S Common Data Select Input 1.0/1.0 20 mA/b0.6 mA OE
TRI-STATE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
I
0a–I0d
Data Inputs from Source 0 1.0/1.0 20 mA/b0.6 mA
I
1a–I1d
Data Inputs from Source 1 1.0/1.0 20 mA/b0.6 mA
Za–Z
d
TRI-STATE Inverting Data Outputs 150/40 (33.3)b3 mA/24 mA (20 mA)
Functional Description
0x
inputs are selected and when Select is
HIGH, the I
1x
inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The ’F258A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equation for the outputs is shown below:
Z
n
e
OE#(I
1n
#
SaI
0n
#
S)
When the Output Enable input (OE
) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs of the TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.
Truth Table
Output Select Data
Output
Enable Input Inputs
OE SI
0
I
1
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
HXXXZ
X
e
Immaterial
LHXLH
Z
e
High Impedance
LHXHL LLLXH LLHXL
Logic Diagram
TL/F/9508– 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATE Output
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.5 I
OH
eb
1mA
Voltage 54F 10% V
CC
2.4 I
OH
eb
3mA
74F 10% V
CC
2.5 V Min
I
OH
eb
1mA
74F 10% V
CC
2.4 I
OH
eb
3mA
74F 5% V
CC
2.7 I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
3mA
V
OL
Output LOW 54F 10% V
CC
0.5 V Min
I
OL
e
20 mA
Voltage 74F 10% V
CC
0.5 I
OL
e
24 mA
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V
Breakdown Test 74F 7.0
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V
I
OZH
Output Leakage Current 50 mA Max V
OUT
e
2.7V
I
OZL
Output Leakage Current
b
50 mA Max V
OUT
e
0.5V
I
OS
Output Short-Circuit Current
b
60
b
150 mA Max V
OUT
e
0V
I
ZZ
Bus Drainage Test 500 mA 0.0V V
OUT
e
V
CC
I
CCH
Power Supply Current 6.2 9.5 mA Max V
O
e
HIGH
I
CCL
Power Supply Current 15.1 23 mA Max V
O
e
LOW
I
CCZ
Power Supply Current 11.3 17 mA Max V
O
e
HIGH Z
3
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