9SGNDBottom & IBI connectorsAudio signal ground.
10XEARBottom & IBI connectorsAnalog audio output.
11MBUSBottom & IBI connectorsBidirectional serial bus.
12FBUS_RXBottom & IBI connectorsSerial data in.
13FBUS_TXBottom & IBI connectorsSerial data out.
14L_GNDBottom charger contactsLogic and charging ground.
RF–Connector
The RF–connector is needed to utilize the external antenna with Car
Cradle. The RF–connector is located on the back side of the transceiver
on the top section. The connector is plug type connector with special mechanical switching.
Accessory side of connector
Part will be floating in
car holder
Phone side of connector
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System Module US4U/US4RM/US4RSMD
Technical Documentation
Battery Contacts
PinNameFunctionDescription
1BVOLTBattery voltageBattery voltage
2BSIBattery Size IndicatorInput voltage
3BTEMPBattery temperature indication
Phone power up
Battery power up
PWM to VIBRA BA TTERY
4BGNDGround
Input voltage
Input voltage
Output voltage
PWM output signal frequency
Operating Conditions
Environmental conditionAmbient temperatureNotes
Normal operation conditions +7 oC ... +40 oCSpecifications fulfilled and fast
Cessation of operation <–25 oC and >80 oCNo storage or operation attempt
Long term storage conditions 0 oC ... +40 oC Battery only up to +30 oC !
Short term storage, max. 96 h–25 oC ... +70 oCCumulative for life–time of bat-
Short term storage, max. 12 h–25 oC ... +80 oCCumulative for life–time of bat-
–25 oC ... +75 oCLCD operation
Short term operation > +70 oC
+55 oC ... +65 oCOperational only for short peri-
ods
–25 oC ... –10 oC and
+65
o
C ... +80 oC
Operation maybe not possible
but attempt to operate will not
damage the phone
possible without permanent
damage
tery
tery
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Technical Documentation
Functional Description
The US4U (Phase 1) / US4RM (Phase 2) / US4RSMSD (Phase 3) engine
consist of a Baseband/RF module with connections to a separate User
Interface module. Baseband and RF submodules are interconnected with
PCB wiring. The engine can be connected to accessories via bottom system
connector and an Intelligent Battery Interface (IBI) connector.
The RF submodule receives and demodulates radio frequency signals from
the base station and transmits modulated RF signals to the base station. It
consists of functional submodules Receiver, Frequency Synthesizer and
Transmitter . The RF submodule can further be devided into lower band and
upper band functions.
The Baseband module containes audio, control, signal processing and
power supply functions. It consists of functional submodules CTRLU
(Control Unit; MCU, DSP, logic and memories), PWRU (Power Supply;
regulators and charging) and AUDIO_RF (audio coding, RF–BB interface).
System Module US4U/US4RM/US4RSMD
Modes of Operation
US4U/US4RM/US4RSMD operates in five cellular modes and a local mode
for service:
– Analog Control Channel (ACCH) 800 MHz Mode,
– Analog Voice Channel (AVCH) 800 MHz Mode,
– Digital Control Channel (DCCH) 800 MHz Mode,
– Digital Traffic Channel (DTCH) 800 MHz Mode,
– Out of Range (OOR) Mode,
– Locals mode, used by Production and After Sales.
Analog Control Channel (ACCH) Mode
On analog control channel the phone receives continuous signalling
messages on Forward Control Channel (FOCC) from the base station, being
most of the time in IDLE mode. Only the receiver part is on. The phone scans
the preferred dedicated control channels to find and lock to the strongest
channel for reading information from this control channel.
DSP is not used on ACCH (it stays in sleep mode), except during channel
scanning for loading the synthesizers.
As a separate sleep clock is used, also the VCTCXO can be turned off
periodically with the RF parts. Only the sleep clock and necessary timers in
MCU are operational.
When registration is demanded the phone sends (TX on) it’s information on
Reverse Control Channel (RECC) to the base station. The phone’s location
is updated in the switching office.
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System Module US4U/US4RM/US4RSMD
If a call is initiated, either by the user or the base station, the phone moves
to the allocated analog voice channel or digital traffic channel depending on
the orders by the base station.
Analog Voice Channel (AVCH) Mode
The phone receives and transmits analog audio signal. All circuitry is
powered on (except the receiver parts used only in digital modes). DSP does
the audio processing and in Hands Free mode also performs
echo–cancellation and HF algorithms. The COBBA IC makes A/D
conversion for the MIC signal, and D/A conversion for the EAR signal.
With audio signal also the Supervisory Audio Tone (SAT) is being received
from the base station. The SA T frequency can be 5970 Hz, 6000Hz or 6030
Hz, defined by the base station. The DSP phase lock loop locks to the SA T,
detects if the frequency is the expected one and examines the signal quality .
DSP reports SAT quality figures regularily to the MCU. The received SAT
signal is transmitted back (transponded) to the base station.
Technical Documentation
The base station can send signalling messages on Forward Voice Channel
(FVC) to the phone, by replacing the audio with a burst of Wide Band Data
(WBD). These are typically hand–off or power level messages. The RX
modem in System Logic receives the signalling message burst and gives an
interrupt to the MCU for reading the data. MCU gives a message to DSP to
mute the audio path during the burst. MCU can acknowledge the messages
on Reverse V oice Channel (RVC), where DSP sends the WBD to transmitter
RF.
Digital Control Channel (DCCH) 800 MHz Mode
On digital control channel (DCCH) DSP receives the paging information from
the Paging channels and sends the messages to MCU for processing.
Each Hyperframe (HFC) comprises two Superframes (SF), the Primary (p)
and the Secondary (s) paging frame. The assigned Page Frame Class (PFC)
defines the frames which must be received, and thus defines when the
receiver must be on.
The phone is in sleep mode between the received time slots. The sleep clock
timer is set and MCU, DSP and RF parts (including VCTCXO) are powered
down. Only sleep clock and the respective timers are running.
From DCCH phone may be ordered to analog control channel or to analog
or digital traffic channel.
Digital Traffic Channel (DTCH) 800 MHz Mode
Digital Voice Channel (S–DTCH)
On digital voice channel DSP processes the speech signal in 20 ms time
slots. DSP performs the speech and channel functions in time shared
fashion and is in sleep mode whenever possible. RX and TX parts are
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powered on and off according to the slot timing. MCU is waken up mainly
by DSP, when there is signalling information for the Cellular Software.
Digital Data Channel (D–DTCH)
In Digital Data Channel Mode audio processing is not needed and audio
circuitry can be shut down. Otherwise the mode is similar to Digital Voice
Channel Mode.
Out of Range (OOR) Mode
If the phone can’t find signal from the base station on any control channel
(analog or digital) it can go into OOR mode for power saving. All RF circuits
are powered down and the baseband circuits in a low power mode, VCTCXO
stopped and only the sleep clock running. After a programmable timer in
MCU has elapsed the phone turns the receiver on and tries to receive
signalling data from base station. If it succeeds, the phone goes to standby
mode on analog or digital control channel. If the connection can not be
established the phone returns to OOR mode until the timer elapses again.
System Module US4U/US4RM/US4RSMD
Locals Mode
Locals mode is used for testing purposes by Product Development,
Production and After Sales. The Cellular Software is stopped (no signalling
to base station), and the phone is controlled by MBUS/FBUS messages by
the controlling PC.
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System Module US4U/US4RM/US4RSMD
Power Distribution Diagram
UT4U Engine
PENTA
Charger
CCONT
Charge
control
VR8
VR9
VR10
VR11
VR12
VR1
VR2
VR3
VR4
VR5
VR6
VR7
VREF
VSIM
Technical Documentation
PA 1900 MHz
PA 800 MHz
RF
1900 MHz
800 MHz
Battery
VBB
V5V
UI Module
Baseband
COBBA
analog
Flash
ROM
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External interfaces
4
Battery
Pack
3
Charger
IBI
Connector NameNotes
Antenna
US4U
ENGINE
6
Accessories
Bottom
connectorconnector
System Module US4U/US4RM/US4RSMD
User
28
22
Mic
Interface
Module
Display
Keyboard
Backlights
Speaker
Buzzer
Bottom connector + IBI connectorIncludes control, data, charging and audio sig-
led, and earpiece signals
Battery connectorVBAT, GND, BTYPE, BTEMP
RF–interfaceConnection
Signals between baseband and User Interface section
The User interface section is implemented on separate UI board, which
connects to the engine board with a board to board spring connector.
User Interface module connection
The User interface section comprises the keyboard with keyboard lights,
display module with display lights, an earphone and a buzzer.
Earphone
The internal earphone is connected to the UI board by means of mounting springs for automatic assembly. The low impedance, dynamic type
earphone is connected to a differential output in the COBBA audio codec.
The voltage level at each output is given as reference to ground. Earphone levels are given to 32 ohm load.
Buzzer
Alerting tones and/or melodies as a signal of an incoming call are generated with a buzzer that is controlled with a PWM signal by the MAD. The
buzzer is a SMD device and is placed on the UI board.
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System Module US4U/US4RM/US4RSMD
Baseband Module
Power Distribution
In normal operation the baseband is powered from the phone‘s battery.
The battery consists of one Lithium–cell. There is also a possibility to use
batteries consisting of three Nickel– cells. An external charger can be
used for recharging the battery and supplying power to the phone. The
charger can be either so called fast charger, which can deliver supply current up to 850 mA or a standard charger that can deliver around 300 mA.
VCXO
CHAPS
VCHAR
BATTERY
Technical Documentation
COBBALCD–DRVR
MAD
VBAT
CCONT
PWM
V2V
VR1_SW
VR1
VR6
VBB
FLASH
SIO
VSIM
V5V
Vref
RF
VR1–VR7
Battery voltage VBAT is connected to CCONT which regulates all the supply voltages VBB, VR1–VR7, V2V, VR1_SW, VSIM and V5V. VR7 is divided into VR7 and VR7_bias. VR7_bias is for RF, because PA is heating
and this reduces the heat. CCONT enables automatically VR1, VBB,
V2V_core, VR6 and Vref in power–up.
VBB is used as baseband power supply for all digital parts, and it is
constantly on whenever the phone is powered up. There is also another
Baseband voltage, V2V, which is reserved for later version of MAD circuit.
V2V will be used as a lower core voltage for MAD internal parts, by supplying it to specific MAD core voltage pins. Until that time, VBB will be
used for all MAD pins. VSIM can be used as programming voltage for the
Flash memory, if re–flashing is needed after initial flash programming in
production. V5V is used for RF parts only.
VR1 is used for the VCXO supply. VR1_SW is derived from VR1 inside
CCONT, and is actually the same voltage, but can be separately switched
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on and off. This VR1_SW is used as bias voltage for microphone, during
talk modes. Voltage VR6 is used in COBBA for analog parts and also
in RF parts. RFCEN signal to CCONT controls both the VR1 and VR6
regulators; they can be switched off in sleep modes, during standby.
CCONT regulators are controlled either through SIO from MAD or timing
sensitive regulators are controlled directly to their control pins. These two
control methods form a logical OR–function, i.e. the regulator is enabled
when either of the controls is active. Most of the regulators can be individually controlled.
CHAPS connects the charger voltage (VCHAR) to battery. MCU of MAD
controls the charging through CCONT. MAD sets the parameters to
PWM–generator in CCONT and PWM–output controls the charging voltage in charger.
When battery voltage is under 3.0V, CHAPS controls independently the
charging current to battery.
Charging Control
System Module US4U/US4RM/US4RSMD
System
Connector
To
charger
Charging is controlled by MCU SW, which writes control data to CCONT
via serial bus. CCONT output pin PWMOUT (Pulse Width Modulation)
can be used to control both the charger and the CHAPS circuit inside
phone.
2–wire charging
Vin
PWMOUT
Charging Control
CHAPS
BATTERY
MAD
CCONT
serial control
With 2–wire charging the charger provides constant output current, and
the charging is controlled by PWMOUT signal from CCONT to CHAPS.
PWMOUT signal frequency is selected to be 1 Hz, and the charging
switch in CHAPS is pulsed on and off at this frequency. The final charged
energy to battery is controlled by adjusting the PWMOUT signal pulse
width.
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System Module US4U/US4RM/US4RSMD
Both the PWMOUT frequency selection and pulse width control are made
MCU which writes these values to CCONT.
3–wire charging
With 3–wire charging the charger provides adjustable output current, and
the charging is controlled by PWMOUT signal from CCONT to Charger,
with the bottom connector signal. PWMOUT signal frequency is selected
to be 32 Hz, and the charger output voltage is controlled by adjusting the
PWMOUT signal pulse width. The charger switch in CHAPS is constantly
on in this case.
Watchdog
VCXO
Technical Documentation
BATTERY
MADCOBBA
CCONT
32 kHz
VR1
VR6
VBB
SLCLK
MCU
LOGIC
SIO
Both MAD and CCONT include a watchdog, and both use the 32 kHz
sleep clock. The watchdog in MAD is the primary one, and this is called
SW–watchdog. MCU has to update it regularly. If it is not updated, logic
inside MAD gives reset to MAD. After the reset, MCU can read an internal status bit to see the reason for reset, whether it was from MAD or
CCONT. The SW–watchdog delay can be set between 0 and 63 seconds
at 250 millisecond steps; and after power–up the default value is the max.
time.
MAD must reset CCONT watchdog regularly. CCONT watchdog time can
be set through SIO between 0 and 63 seconds at 1 second steps. After
power–up the default value is 32 seconds. If watchdog elapses, CCONT
will cut off all supply voltages.
After total cut–off the phone can be re–started through any normal power–up procedure.
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Power up
When the battery is connected to phone, nothing will happen until the
power–up procedure is initiated, for instance by pressing the power–button (or by connecting charger voltage). After that the 32kHz crystal oscillator of CCONT is started (can take up to 1 sec), as well as the regulators
are powered up.
If power down is done, and the battery remains connected, the 32 kHz
crystal oscillator keeps still running in the CCONT. When power–up is initiated again, the complete power–up sequence is like in the figure below.
This time the power–up sequence is faster, because the oscillator is already running.
Power up when power–button is pushed
PWRONX
System Module US4U/US4RM/US4RSMD
VR1, VBB, VR6
RFCEN
RFCSETTLED
RFC (VCXO)
COBBACLK
PURX
SLCLK
t1
t2
t3
t1< 1 ms
t21 – 6 ms, VCXO settled
t362 ms, PURX delay generated by CCONT
After PWR–key has been pushed, CCONT gives PURX reset to MAD and
COBBA, and turns on VR1, VBB and VR6 regulators (if battery voltage
has exceeded 3.0 V). VR1 supplies VCXO, VBB supplies MAD and digital
parts of COBBA, and VR6 supplies analog parts of COBBA and some RF
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System Module US4U/US4RM/US4RSMD
parts. After the initial delay t2 VCXO starts to give proper RFC to COBBA
that further divides it to COBBACLK for MAD. COBBA will output the
COBBACLK only after the PURX reset has been removed. After delay t3
CCONT releases PURX and MAD can take control of the operation of the
phone.
After that MCU–SW in MAD detects that the PWR–key is still pushed and
shows the user that the phone is powering up by starting the LCD and
turning on the lights. MCU–SW must start also RF receiver parts at this
point.
CCONT will automatically power–up also VSIM–regulator (used for possible reFlashing), regardless of the control pin SIMPWR state, and the
regulator default voltage is 3V. VSIM voltage could be selected to be 5V,
by writing the selection via serial bus to CCONT, but that is not needed
with the new Flash versions (Jaguar).
V5V–regulator (for RF) default value is off in power–up, and can be controlled on via serial bus when needed.
Technical Documentation
IBI (Intelligent Battery Interface)
Phone can be powered up by external device (accessory or similar) by
providing a start pulse to the battery signal BTEMP; this is detected by
CCONT. After that the power–up procedure is similar to pushing power–
button.
Mixed trigger to power up
It is possible that PWR–key is pushed during charger initiated power–up
procedure or charger is connected during PWR–key initiated power up
procedure. In this kind of circumstances the power–up procedure (in HW
point of view) continues as nothing had happened.
When the Baseband HW is working normally and SW is running, SW detects that both conditions are fulfilled and then acts accordingly.
Power Off
Power off by pushing Power–key
MAD (MCU SW) detects that PWR–key is pressed long enough time. After that the lights and LCD are turned off. MCU stops all the activities it
was doing (e.g. ends a call), sends power off command to CCONT (i.e.
gives a short watchdog time) and goes to idle–task. After the delay
CCONT cuts all the supply voltages from the phone. Only the 32 kHz
sleep clock remains running.
Note that the phone doesn’t go to power off (from HW point of view) when
the charger is connected and PWR–key is pushed. It is shown to user
that the phone is in power off, but in fact the phone is just acting being
powered off (this state is usually called acting dead).
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Power off when battery voltage low
During normal discharge the phone indicates the user that the battery will
drain after some time. If not recharged, SW detects that battery voltage is
too low and shuts the phone off through a normal power down procedure.
Anyway, if the SW fails to power down the phone, CCONT will make a reset and power down the phone if the battery voltage drops below 2.8 V.
Power off when fault in the transmitter
If the MAD receives fault indication, from the line TXF, that the transmitter
is on although it shouldn’t be, the control SW will power down the phone.
Sleep Mode
The phone can enter SLEEP only when both MCU and DSP request it. A
substantial amount of current is saved in SLEEP. When going to SLEEP
following things will happen
System Module US4U/US4RM/US4RSMD
1.Both MCU and DSP enable sleep mode, set the sleep timer
and enter sleep mode
2.RFCEN and RFCSETTLED –> 0 –> COBBACLK will stop
(gated in COBBA). Also VR1 is disabled –> VCXO supply voltage is cut off –> RFC stops.
3.LCD display remains the same, no changes
4.Sleep clock (SLCLK) and watchdog in CCONT running
5.Sleep counter in MAD running, uses SLCLK
Waking up from the Sleep–mode
In the typical case phone leaves the SLEEP–mode when the SLEEP–
counter in MAD expires. After that MAD enables VR1 ⇒ VCXO starts running ⇒ after a pre–programmed delay RFCSETTLED rises => MAD receives COBBACLK clock ⇒ MAD operation re–starts.
There are also many other cases when the SLEEP mode can be interrupted, in these cases MAD enables the VR1 and operation is started
similarly
– some MCU or DSP timer expires
– DSP regular event interrupt happens
– MBUS activity is detected
– FBUS activity is detected
– Charger is connected, Charger interrupt to MAD
– any key on keyboard is pressed, interrupt to MAD
– HEADSETINT, from system connector XMIC line (EAD)
– HOOKINT, from system connector XEAR line
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System Module US4U/US4RM/US4RSMD
Baseband submodules
CTRLU
CTRLU comprises MAD ASIC (MCU, DSP, System Logic) and Memories.
The environment consists of three memory circuits (FLASH,SRAM,EE-
PROM), 22–bit address bus and 8/16–bit data bus. Besides there are
ROM1SELX, ROM2SELX, RAMSELX and EEPROMSELX signals for chip
select.
MCU main features
System control
Cellular Software (CS)
Cellular Software takes care of communication with switching
office, as well call build–up, maintenance and termination.
Technical Documentation
Communication control
M2BUS is used to communicate to external devices. This interface is also used for factory testing, service and maintenance purposes.
User Interface (UI)
PWR–key, keyboard, LCD, flip/door switch, backlight, mic, ear
and alert (buzzer, vibra, led) control. Serial interface from MAD
to LCD (common for CCONT).
Authentication
Authentication is used to prevent fraud usage of cellular
phones.
RF monitoring
RF temperature monitoring by VCXOTEMP, ADC in CCONT.
Received signal strength monitoring by RSSI, ADC in CCONT.
False transmission detection by TXF signal, digital IO–pin.
Power up/down and Watchdog control
When power key is pressed, initial reset (PURX) has happened
and default regulators have powered up in CCONT, MCU and
DSP take care of the rest of power up procedures (LCD, COBBA, RF). MCU must regularly reset Watchdog counter in
CCONT, otherwise the power will be switched off.
Accessory monitoring
Page 3 – 22
Accessory detection by EAD (XMIC/HEADSETINT), AD–con-
verter in CCONT. Connection (FBUS) for data transfer.
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Battery and charging monitoring
MCU reads the battery type (BTYPE), temperature (BTEMP)
and voltage (VBAT) values by AD–converter in CCONT, and
phone’s operation is allowed only if the values are reasonable.
Charging current is controlled by writing suitable values to
PWM control in CCONT. MCU reads also charger voltage
(VCHAR) and charging current values (ICHAR).
Production/after sales tests and tuning
Flash and EEPROM loading, baseband tests, RF tuning
Control of CCONT via serial bus
MCU writes controls (regulators on/off, Watchdog reset,
charge PWM control) and reads AD–conversion values. For
AD–conversions MCU gives the clock for CCONT (bus clock),
because the only clock in CCONT is sleep clock, which has too
low frequency.
System Module US4U/US4RM/US4RSMD
DSP main features
DSP (Digital Signal Processor) is in charge of the channel and speech
coding according to the IS–136 specification. The block consists of a DSP
and internal ROM and RAM memory. The input clock is 9.72 MHz, and
DSP has it’s own internal PLL–multiplier. Main interfaces are to MCU,
and via System Logic to COBBA and RF.
System Logic main features
– MCU related clocking, timing and interrupts (CTIM)
– DSP related clocking, timing and interrupts (CTID)
– DSP general IO–port
–reset and interrupts to MCU and DSP
– interface between MCU and DSP (API)
– MCU interface to System Logic (MCUif)
– MCU controlled PWMs, general IO–port and USART for MBUS (PUP)
– Receive Modem (Rxmodem)
– Interface to Keyboard, CCONT and LCD Drivers (UIF)
– Interface to MCU memories, address lines and chip select decoding
(BUSC)
– DSP interface to System Logic (DSPif)
– serial accessory interface (AccIf, DSP–UART)
– Modulation, transmit filter and serial interface to COBBA (MFI)
– Serial interface for RF synthesizer control (SCU)
Memories
The speed requirement of FLASH and SRAM is assumed to be 120 ns.
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System Module US4U/US4RM/US4RSMD
FLASH
– size 8 Mbit (512k * 16 bit), optional 4 Mbit and 16 Mbit, all made layout
compatible by having additional higher address lines ready in the layout.
Flash memory contains the main program code for the MCU, and EEPROM default values.
SRAM
– size 64k * 8 bit (US4U Phase1) / 128k/256 * 8 bit (US4RM Phase2)
both in STSOP32 package
EEPROM
– size 16k * 8 bit, optional 8k * 8 bit
– serial or optional parallel interface can be used (MAD1 supports both),
but serial interface is used.
AUDIO–RF
Audio interface and baseband–RF interface converters are integrated into
COBBA circuit.
Technical Documentation
Cobba main features
The codec includes microphone and earpiece amplifier and all the necessary switches for routing. There are 2 different possibilities for routing;
internal and external devices. There are also all the AD– and DA– converters for the RF interface.
New solution, DEMO block, is used for FM–demodulation in analog
mode.
A slow speed DA–converter provides automatic frequency control (AFC).
In addition, there is a DA–converters for transmitter power control (TXC).
COBBA also passes the RFC (19.44 MHz) to MAD as COBBACLK (9.72
MHz).
COBBA is connected to MAD via two serial busses:
– RXTXSIO, for interfacing the RF–DACs and DEMO; and also for audio
codec and general control. Signals used: COBBACLK (9.72 MHz, from
COBBA), COBBACSX, COBBASD (bi–directional data) and COBBADAX (data ready flag for rx–samples).
– Codec SIO, for interfacing the audio ADCs / DACs (PCM–samples).
The speech coding functions are performed by the DSP in the MAD and
the coded speech blocks are transferred to the COBBA for digital to analog conversion, down link direction. In the up link direction the PCM coded
speech blocks are read from the COBBA by the DSP.
There are two separate interfaces between MAD and COBBA: 2 serial
buses. The first serial interface is used to transfer all the COBBA control
information (both the RFI part and the audio part). The second serial interface between MAD and COBBa includes transmit and receive data,
clock and frame synchronisation signals. It is used to transfer the PCM
samples. The frame synchronisation frequency is 8 kHz ( the sample rate
is in digital mode 8.0 kHz and in analog mode 8.1 kHz) which indicates
the rate of the PCM samples and the clock frequency is 1 MHz. COBBA is
generating both clocks.
Alert Signal Generation
System Module US4U/US4RM/US4RSMD
A buzzer is used for giving alerting tones and/or melodies as a signal of
an incoming call. The buzzer is controlled with a BuzzerPWM output signal from the MAD. A dynamic type of buzzer must be used since the supply voltage available can not produce the required sound pressure for a
piezo type buzzer. The low impedance buzzer is connected to an output
transistor that gets drive current from the PWM output. The alert volume
can be adjusted either by changing the pulse width causing the level to
change or by changing the frequency to utilize the resonance frequency
range of the buzzer.
A vibra alerting device is used for giving silent signal to the user of an incoming call. The device is controlled with a VibraPWM output signal from
the MAD. The vibra alert can be adjusted either by changing the pulse
width or by changing the pulse frequency. The vibra device is not inside
the phone, but in a special vibra battery.
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System Module US4U/US4RM/US4RSMD
PWRU
PWRU comprises CCONT circuit and CHAPS circuit.
CCONT main features
CCONT generates regulated supply voltages for baseband and RF.
There are seven 2.8 V linear regulators for RF, one 2.8 V regulator for
baseband, one special switched output (VR1_SW), one programmable
2V output (V2V), one 3/5 V output (VSIM), one 5V output (V5V), and one
1.5 V +/– 1.5% reference voltage for RF and COBBA.
Other functions are
– power up/down procedures and reset logic
– charging control (PWM), charger detection
– watchdog
– sleep clock (32 kHz) and control
– 8–channel AD–converter.
Technical Documentation
CHAPS main features
CHAPS comprises the hardware for charging the battery and protecting
the phone from over–voltage in charger connector.
The main function are
– transient, over–voltage and reverse charger voltage protection
– limited start–up charge current for a totally empty battery
– voltage limit when battery removed
– with SW protection protection against too high charging current
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Technical Documentation
RF Module
RF Frequency Plan
Intermediate frequencies of the RX are the same in all operation modes.
LO and modulator frequencies in TDMA800 operation modes. See figure
1 for details.
869.01–893.97 MHz
1st IF
116.19 MHz
System Module US4U/US4RM/US4RSMD
2nd IF
450 kHz
116.64 MHz
IF2 A–mode
450 kHz
IF2 D–mode
450 kHz
LO 1
LO 3PLL
824.01–848.97 MHz
985.20–1010.16 MHz
161.19 MHz
322.38 MHz
LO 2
DC Characteristics
Power Distribution Diagram
Power distribution in a 800 MHz DAMPS phone. Current consumptions in
the diagrams are only suggestive.
NOTES: * Mean value (ON/OFF=8/20ms), peak current 32.0 mA
** Mean value (ON/OFF=7/20ms), peak current 37.0 mA
*** Cobba_D mean current consumption estimated to be 30 mA
’ Mean value (ON/OFF=6.6/20ms), peak current 180.0 mA
’’ Mean value (ON/OFF=8/20ms), peak current 10.0 mA
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System Module US4U/US4RM/US4RSMD
Functional Description
Receiver
DAMPS800 RX
The receiver is a double conversion receiver. Most of the RX functions
are integrated in two ICs, namely receiver front end and PLUSSA. Receiver front end contains a LNA and the 1st mixer. Analog and digital IF–
parts are integrated in the PLUSSA.
The received RF signal from the antenna is fed via a duplex filter to the
receiver unit. The signal is amplified by a low noise preamplifier. In digital mode the gain of the amplifier is controlled by the AGC2 control line.
The nominal gain of 17 – 19 dB is reduced in the strong signal condition
about 15 dB (in the digital mode). After the preamplifier the signal is filtered by SAW RF filter. The filter rejects spurious signals coming from the
antenna and spurious emissions coming from the mixer and IF parts.
AGC2 gain step is also used to improve receiver’s performance against
spurious responses in real field situations, when received signal level is
high enough for reduced gain and there are radio signals causing on
channel intermodulation results.
Technical Documentation
The filtered RF–signal is down converted by an active mixer. The frequency of the first IF is 116.19 MHz. The first local signal is generated in
the UHF synthesizer. The IF signal is fed to a SAW IF–filter. The filter re-
jects intermodulating signals and the second IF image signal. The filtered
1st IF is amplified and fed to the receiver section of the integrated RF circuit PLUSSA, which has separate IF paths for analog and digital modes
of operation.
In digital mode the IF1 signal is amplified by an AGC amplifier, which has
gain control range of 57 dB. The gain is controlled by an analog signal via
AGC1–line. The amplified IF signal is down converted to the second IF in
the mixer of PLUSSA. The second local signal is the 6th overtone of the
19.44 MHz VCTCXO. LO frequency multiplier is implemented in two
stages. First multiplication by 3 is done within the VCTCXO–module and
the second multiplication by 2 is done in the PLUSSA.
The second IF frequency is 450 kHz. The second IF is filtered by a ceramic filter. The filter rejects signals of the adjacent channels. The filtered second IF is fed back to PLUSSA, where it is amplified and fed out
to COBBA_D via balanced IF2D lines.
In analog mode the filtered and amplified IF1 signal is fed to a mixer. This
mixer has been optimized for low current consumption. After this the mixer down converted signal is fed through the same IF2 filter as in digital
mode and finally it is amplified in the limiter amplifier. The limited IF2 signal is fed via balanced IF2A lines to COBBA_D, which has a FM–detector.
The limiter amplifier produces also a RSSI voltage for analog mode field
strength indication.
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Technical Documentation
Transmitter
DAMPS800 TX
The TX intermediate frequency is modulated in digital mode by an I/Q
modulator contained in the transmitter section of PLUSSA IC. The TX I
and TXQ signals are generated in the COBBA_D interface circuit and
they are fed differentially to the modulator. In analog mode the FM modulation is also generated in the I/Q modulator.
Intermediate frequency level at the modulator output is controlled via serial bus. Modulator output level control is used to tune out tolerances of the
TX chain and expand the range of the VGA. The output level of the modulator is typically –18dBm on the highest power level (PL2). For lower power levels modulator output is reduced by 4 dB for each power level. In
analog mode PLUSSA modulator has fixed output level. All power levels
are defined by adjusting driver amplifier’s gain.
The output signal from PLUSSA modulator is filtered to reduce harmonics
and RX–band noise. The final TX signal is achieved by mixing the UHF
VCO signal and the modulated TX intermediate signal in an active mixer.
After the mixing TX signal is amplified by a driver stage. Driver amplifier
has a gain control stage, which is used for power level adjustment and
generating ramps. From driver stage the signal is fed trough TX filter to
PA MMIC.
System Module US4U/US4RM/US4RSMD
The PA amplifies the signal TX 27–30 dB. Amplified TX signal is filtered in
duplex filter. Then signal is fed to the antenna switch, where the signal is
coupled either to antenna or to external antenna connector. The typical
maximum output level is 600 mW.
The power control loop controls the gain of the driver amplifier. The power detector consists of a directional coupler and a diode rectifier. The output voltage of the detector is compared to TXC voltage in PLUSSA. The
power control signal (TXC), comes from the RF interface circuit, COBBA_D. TXP signal sets driver power down to ensure off–burst level requiremensts.
False transmission indication is used to protect transmitter against false
transmission caused by component failure. Protection circuit is in Plussa.
The level for TXF is set by internal resistor values in Plussa.
Frequency Synthesizers
The stable frequency reference for the synthesizers and base band circuits is a voltage controlled temperature compensated crystal oscillator
VCTCXO. Frequency of the oscillator is 19.44 MHz. It is controlled by an
AFC voltage, which is generated in the base band circuits. In digital mode
operation, the receiver is locked to base station frequency by AFC. Next
to detector diode, there is a sensor for temperature measurement. Voltage RFTEMP from this sensor is fed to baseband for A/D conversion.
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System Module US4U/US4RM/US4RSMD
This information of RF PA–block temperature is used as input for compensation algorithms.
The ON/OFF switching of the VCTCXO is controlled by the sleep clock in
the baseband via RFCEN. Other parts of the synthesizer section are 1
GHz VCO, 2 GHz VCO, VHF VCO, PLL for 2 GHz VCO and PLL sections
of the Plussa IC.
DAMPS800 operation
1GHz UHF synthesizer generates the down conversion injection for the
receiver and the up conversion injection for the transmitter. UHF frequency is 985.20 ... 1010.16 MHz, depending on the channel which is used.
1GHz UHF VCO is a module. The PLL circuit is dual PLL, common for
both UHF and VHF synthesizers. These PLLs are included in the PLUSSA IC.
LO signal for the 2nd RX mixer is multiplied from the VCTCXO frequency
as described above.
Technical Documentation
VHF synthesizer is running only on digital or analog traffic channel.
322.38 MHz signal (divided by 2 in Plussa) is used as a LO signal in the
I/Q modulator of the transmitter chain.
Because of wide temperature range and poor cooling of the RF block, it is
neccessary to compensate the effect of temperature on the output power.
To monitor this environment change, temperature measurement is done
by using NTC resistor. Factor table is used for temperature compensation,. The table contains common values for all power levels and operating modes. Table values are defined without factory measurements. Temperature is measured and right compensation value is added to TXC–val-
ue. Requirement for compensation update is for every 1 minutes or after
every 5 degrees C of temperature change. This means, that during analog mode transmission there will be a need for temperature reading and
TXC compensation update. Because of poor cooling of RF block and insufficient linearity in high temperatures, output power is reduced from level 2 to level 2.5 when temperature inside the phone is above +55 C in
analog mode and above +60 C in digital mode.
System Module US4U/US4RM/US4RSMD
Power Levels (TXC) vs. Channel
Duplexer frequency response ripple is compensated by software. Power
levels are calibrated on four channels in production. Values for channels
between these tuned channels are calculated by using linear interpolation.
Power levels vs. Battery Voltage
For saving battery capacity and because of insufficient linearity in digital
mode, output power is decreased from level 2 to level 2.5, when battery
voltage drops below 3.3V. (tbd.). The power reduction is done linearly as
a function of battery voltage. Vcc 3.3V ... 3.1V –> PL2 ... PL2.5.
TX Power Up/Down Ramps
Transmitter output power up/down ramps are controlled by SW. A special
ramp tables are used for that. Requirement is for nine different ramps in
digital mode for both operating bands and one ramp for analog mode.
Separate ramps are used in power up and power down ramps.
Modulator Output Level
For optimum linerity and efficiency the output level of the modulator is adjusted in the production. AGC amplifier is used as 2 dB step attenuator to
define power levels. The 0 dB level is the production tuned reference level.
Digital Mode RSSI
Digital mode RSSI vs. input signal is calibrated in production, but RSSI
vs. temperature and RSSI vs. channel are compensated by software.
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System Module US4U/US4RM/US4RSMD
RF Block Specifications
Receiver
DAMPS 800 Mhz Front End
ParameterMinimumTypical /
Gain, LNA gain enabled
(gain variations vs temp. included)
Gain, LNA gain disabled–10dB
Gain step15dB
Gain variation vs temp –30...+85 dC,
amplifier enabled, ref. to nominal gain
Noise figure, LNA enabled2.53.0dB
Technical Documentation
MaximumUnit /
Nominal
192123dB
1.5dB
Notes
First IF Filter
ParameterMinimumTypical /
Nominal
Operation frequency116.19MHz
Supply voltage2.72.82.9V
Current consumption1.01.5mA
Insertion gain1014dB
Noise figure3dB
IIP3–20dBm
Input impedanceTBDmatched to the IF filter
Output impedanceTBDmatched to PLUSSA
MaximumUnit / Notes
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System Module US4U/US4RM/US4RSMD
Transmitter
RF Characteristics
ItemDAMPS
TX frequency range824.01...848.97 MHz
TypeUpconversion
Intermediate frequency161.19 MHz
Nominal power on highest power level0.6 W ( 27.8 dBm)
Power control range30+38 dB
Maximum rms error vector12.5 %
Power Levels
( see tuning table within Section: tuning Instructions (pages 17 & 18).
Synthesizers
UHF
ParameterUHF 800MHz
analog mode
rx/tx injec-
tion
Frequency range985.20 ...
1010.16
Reference frequency3030kHz
Reference peaks @ 30 kHz
OFF
Current100uA
Load capacitance10pF
Timing inaccuracy10us
DSP
Page 3 – 41
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upcon.
PAMS
System Module US4U/US4RM/US4RSMD
Signal
name
TXP2MAD
1)
TXPWR1MAD
Control
(MFI,
TXP)
3)
(CTID,
TXPWR1
)
Penta
reg,
TX driver,
TX PA,
TX PA,
in
tdma1900
mode
CCONT
Logic high ”1”2.0VSupply voltage VR11
Logic low ”0”0.5VSupply voltage VR11
Current100uA
Load capacitance10pF
Timing inaccuracy10us
Logic high ”1”2.0VSupply voltage VR5
Logic low ”0”0.5VSupply voltage VR5
Technical Documentation
FunctionUnitMaxTypMinParameterToFrom/
ON
OFF
DSP
ON, TX power control
enable.
800 tx–mixer enable
OFF, TX power control
disable
800 tx–mixer disable
TXPWR2MAD
(CTID,
1)
TXPWR3MADRF
(CTID,
BENA)
(CTID,
BENA)
RF
2v8
regul.
800 MHz
upcon.
1) Signal in use only in dual band engine
2) Valid from MAD80
3) Multiplexed with band signal at BB
Current50uA
Timing inaccuracy8us
Logic high ”1”2.0VSupply voltage VR12
Logic low ”0”0.5VSupply voltage VR12
Current50uA
Timing inaccuracy1us
Logic high ”1”2.0VUpconv enabled
Logic low ”0”0.5VUpconv disabled
Current50uA
Timing inaccuracy1us
DSP
ON
OFF
DSP
DSP
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Data Interface and Timing
PLUSSA is programmed via a 3 wire serial bus. Control wires in the RF/
BB interface are named SENA1, SDATA and SCLK.
SDAT: Serial data input
The PLUSSA programming data is applied to that pin. The data is qualified by SCLK clock.
SCLK: Serial clock input
Qualifies the data applied to SDAT pin. Rising edge of the SCLK signal
shifts the data to the PLUSSA’s internal shift register. The falling edge af-
ter the third rising edge qualifies the internal addressing
SLE: Serial latch enable (active low)
By forcing SLE line down the serial interface of the PLUSSA is activated.
During the active state PLUSSA interface accepts the clocking and the
data applied to the SCLK and SDAT pins. While SLE is high the interface
is completely inactive, so multiple devices can share the same SCLK and
SDAT lines.
System Module US4U/US4RM/US4RSMD
SLE
SDAT
SCLK
t
t
slc
sdc
t
clhcl
t
ch
t
t
lh
Serial data input timing
Timing ratings.
abbrDefinitionMin [ns]Max [ns]
tslcSLE to SCLK setup time40
tsdcSDAT to SCLK setup time20
tchSCLK high period50
tclSCLK low period50
thclSCLK to SLE hold time20
tlhSLE high period4000
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ÇÇ
Ä
Ä
PAMS
System Module US4U/US4RM/US4RSMD
Digital control channels
SPWR1
SPWR2
SPWR3
5 ms
RX
5 ms
NL or MACA
546 us
N x 20 ms
RX
Technical Documentation
TX
min 22 ms
546 us
RXPWR1
RXPWR2
AGC1
AGC2
TXPWR1
TXLX
TXP1
TXA
TXC
AFC
200 us
100 us
2 ms
RFCEN
SDATA, SCLK
Page 3 – 44
VHF synth init & load
NL or MACA
ch loads 0 ... 24 pcs
UHF synth.
1GHz
ch load
1GHz UHF synth.
TXAGC
TDMA800 digital control channel timing diagram
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Analog control channel
A4
B4 A5 B5 DS A1 B1A2..B4 A5 B5DS A1 B1A2..B4 A5B5
VRBB
AGC2
RXPWR1
RXPWR2
”1”
1.5 ms
System Module US4U/US4RM/US4RSMD
92.6 ms
46.3 ms
A1 B1
S
D
AFC
SPWR1
RFCEN
3.0 ms
3.0 ms
6 ms
Extended stand by mode timings
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Technical Documentation
Parts list of US4U Phase1 (EDMS Issue 8.3)Code: 0200973
Z9014511137Saw filter836.5+–12.5 M/3.5DB 4X4
Z9104512081Dupl 824–849/869–894mhz 19.1x11.9
Z9704550047Dipl 824–894/1850–1990mhz 3.4x2.7
V1504210037TransistorBCW30pnp 32 V 0.1 A
V1514110067Schottky diodeMBR0520L20 V 0.5 A SOD123
V1524210052TransistorDTC114EEnpn RB V EM3
V1534211202DM MosFetp–ch 50 V 0.13 A
V2004110072Diode x 2BAV99W70 V 0.2 A SOT323
V2014110072Diode x 2BAV99W70 V 0.2 A SOT323
V2024110072Diode x 2BAV99W70 V 0.2 A SOT323
V2504210100TransistorBC848Wnpn 30 V SOT323
V2514210052TransistorDTC114EEnpn RB V EM3
V2534211231MosFetNDS33SOT23
V2544110072Diode x 2BAV99W70 V 0.2 A SOT323
V7414210066TransistorBFR93AWnpn 12 V 35 mA
V8004219903Transistor x 2BFM505npn 20 V 20V18 mA
V8034110018Cap. diodeBB13530 V SOD323
V8404210066TransistorBFR93AWnpn 12 V 35 mA
V8504210100TransistorBC848Wnpn 30 V SOT323