NEC V850ES-SJ3 User Manual

User’s Manual

V850ES/SJ3

32-bit Single-Chip Microcontrollers

Hardware

μPD70F3344(A)
μPD70F3345(A)
μPD70F3346(A)
μPD70F3347(A)
μPD70F3348(A)
μPD70F3354(A)
μPD70F3355(A)
μPD70F3356(A)
μPD70F3357(A)
μPD70F3358(A)
μPD70F3364(A)
μPD70F3365(A)
μPD70F3366(A)
μPD70F3367(A)
μPD70F3368(A)

Document No. U17790EJ3V1UD00 (3rd edition)
Date Published March 2008 N

Printed in Japan

2006

[MEMO]

2

User’s Manual U17790EJ3V1UD

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

IL

CMOS device stays in the area between V

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

V

IH

(MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

IL

(MAX) and

DD

or GND

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

User’s Manual U17790EJ3V1UD

3

Caution: This product uses SuperFlash

®

technology licensed from Silicon Storage Technology, Inc.

IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.

MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a

trademark in the United States of America.

EEPROM, IEBus, and Inter Equipment Bus are trademarks of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

4

User’s Manual U17790EJ3V1UD

•

The information in this document is current as of December, 2007. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

•

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative

•

purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.

•

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

•

"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer­designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.

(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

User’s Manual U17790EJ3V1UD

5

PREFACE

Readers This manual is intended for users who wish to understand the functions of the

V850ES/SJ3 and design application systems using the V850ES/SJ3.

Purpose This manual is intended to give users an understanding of the hardware functions of

the V850ES/SJ3 shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture

(V850ES Architecture User’s Manual).

Hardware Architecture

• Pin functions • Data types

• CPU function • Register set

• On-chip peripheral functions • Instruction format and instruction set

• Flash memory programming • Interrupts and exceptions

• Electrical specifications • Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

Cautions 1. The application examples in this manual apply to “standard”

quality grade products for general electronic systems. When

using an example in this manual for an application that requires a

“special” quality grade product, thoroughly evaluate the

component and circuit to be actually used to see if they satisfy the

special quality grade.

2. When using this manual as a manual for a special grade product,

read the part numbers as follows.

μ

PD70F3344 → μPD70F3344(A)

μ

PD70F3345 → μPD70F3345(A)

μ

PD70F3346 → μPD70F3346(A)

μ

PD70F3347 → μPD70F3347(A)

μ

PD70F3348 → μPD70F3348(A)

μ

PD70F3354 → μPD70F3354(A)

μ

PD70F3355 → μPD70F3355(A)

μ

PD70F3356 → μPD70F3356(A)

μ

PD70F3357 → μPD70F3357(A)

μ

PD70F3358 → μPD70F3358(A)

μ

PD70F3364 → μPD70F3364(A)

μ

PD70F3365 → μPD70F3365(A)

μ

PD70F3366 → μPD70F3366(A)

μ

PD70F3367 → μPD70F3367(A)

μ

PD70F3368 → μPD70F3368(A)

6

User’s Manual U17790EJ3V1UD

To understand the overall functions of the V850ES/SJ3
→ Read this manual according to the CONTENTS.

To find the details of a register where the name is known
→ Use APPENDIX C REGISTER INDEX.

Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the

register format of each register is defined as a reserved word in the device file.

To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/SJ3
→ See CHAPTER 32 ELECTRICAL SPECIFICATIONS.

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note

with caution that if “xxx.yyy” is described as is in a program, however, the

compiler/assembler cannot recognize it correctly.

The mark <R> shows major revised points. The revised points can be easily

searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field.

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Memory map address: Higher addresses on the top and lower addresses on

the bottom

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2

(address space, memory

capacity): K (kilo): 2

M (mega): 2

G (giga): 2

10

= 1,024

20

= 1,0242

30

= 1,0243

User’s Manual U17790EJ3V1UD

7

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/SJ3

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/SJ3 Hardware User’s Manual This manual

V850ES/SJ2, V850ES/SJ2-H Hardware User’s Manual U16603E

Documents related to development tools

Document Name Document No.

IE-V850ES-G1 (In-Circuit Emulator) U16313E

IE-703288-G1-EM1 (In-Circuit Emulator Option Board) U16697E

IE-V850E1-CD-NW (PCMCIA Card Type On-Chip Debug Emulator) U16647E

QB-V850ESSX2 (In-Circuit Emulator) U17091E

QB-V850MINI (On-Chip Debug Emulator) U17638E

QB-MINI2 (On-Chip Debug Emulator with Programming Function) U18371E

CA850 Ver. 3.00 C Compiler Package

PM+ Ver. 6.30 Project Manager U18416E

ID850 Ver. 3.00 Integrated Debugger Operation U17358E

ID850QB Ver. 3.40 Integrated Debugger Operation U18604E

TW850 Ver. 2.00 Performance Analysis Tuning Tool U17241E

RX850 Ver. 3.20 Real-Time OS

RX850 Pro Ver. 3.21 Real-Time OS

AZ850 Ver. 3.30 System Performance Analyzer U17423E

PG-FP4 Flash Memory Programmer U15260E

PG-FP5 Flash Memory Programmer U18865E

Operation U17293E

C Language U17291E

Assembly Language U17292E

Link Directives U17294E

Operation U18601E SM+ System Simulator

User Open Interface U18212E

Basics U13430E

Installation U17419E

Technical U13431E

Task Debugger U17420E

Basics U18165E

Installation U17421E

Technical U13772E

Task Debugger U17422E

8

User’s Manual U17790EJ3V1UD

CONTENTS

CHAPTER 1 INTRODUCTION ................................................................................................................. 21

1.1 General .....................................................................................................................................21

1.2 Features....................................................................................................................................23

1.3 Application Fields ...................................................................................................................24

1.4 Ordering Information ..............................................................................................................25

1.5 Pin Configuration (Top View).................................................................................................26

1.6 Function Block Configuration................................................................................................ 29

1.6.1 Internal block diagram ............................................................................................................... 29

1.6.2 Internal units.............................................................................................................................. 30

CHAPTER 2 PIN FUNCTIONS................................................................................................................33

2.1 List of Pin Functions...............................................................................................................33

2.2 Pin States .................................................................................................................................44

2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins.........45

2.4 Cautions ................................................................................................................................... 49

CHAPTER 3 CPU FUNCTION.................................................................................................................50

3.1 Features....................................................................................................................................50

3.2 CPU Register Set.....................................................................................................................51

3.2.1 Program register set.................................................................................................................. 52

3.2.2 System register set.................................................................................................................... 53

3.3 Operation Modes .....................................................................................................................59

3.3.1 Specifying operation mode ........................................................................................................ 59

3.4 Address Space ........................................................................................................................60

3.4.1 CPU address space................................................................................................................... 60

3.4.2 Wraparound of CPU address space.......................................................................................... 61

3.4.3 Memory map..............................................................................................................................62

3.4.4 Areas......................................................................................................................................... 64

3.4.5 Recommended use of address space ....................................................................................... 72

3.4.6 Peripheral I/O registers.............................................................................................................. 75

3.4.7 Programmable peripheral I/O registers...................................................................................... 89

3.4.8 Special registers........................................................................................................................ 90

3.4.9 Cautions .................................................................................................................................... 94

CHAPTER 4 PORT FUNCTIONS............................................................................................................98

4.1 Features....................................................................................................................................98

4.2 Basic Port Configuration ........................................................................................................98

4.3 Port Configuration................................................................................................................... 99

4.3.1 Port 0....................................................................................................................................... 104

4.3.2 Port 1....................................................................................................................................... 108

4.3.3 Port 3....................................................................................................................................... 109

4.3.4 Port 4....................................................................................................................................... 116

4.3.5 Port 5....................................................................................................................................... 119

4.3.6 Port 6....................................................................................................................................... 123

4.3.7 Port 7....................................................................................................................................... 127

4.3.8 Port 8....................................................................................................................................... 129

User’s Manual U17790EJ3V1UD

9

4.3.9 Port 9.......................................................................................................................................131

4.3.10 Port CD....................................................................................................................................139

4.3.11 Port CM ...................................................................................................................................140

4.3.12 Port CS .................................................................................................................................... 142

4.3.13 Port CT ....................................................................................................................................144

4.3.14 Port DH....................................................................................................................................146

4.3.15 Port DL ....................................................................................................................................148

4.4 Block Diagrams..................................................................................................................... 151

4.5 Port Register Settings When Alternate Function Is Used ................................................ 188

4.6 Cautions ................................................................................................................................ 198

4.6.1 Cautions on setting port pins ................................................................................................... 198

4.6.2 Cautions on bit manipulation instruction for port n register (Pn)...............................................201

4.6.3 Cautions on on-chip debug pins...............................................................................................202

4.6.4 Cautions on P05/INTP2/DRST pin...........................................................................................202

4.6.5 Cautions on P53 pin when power is turned on.........................................................................202

4.6.6 Hysteresis characteristics ........................................................................................................ 202

<R>

4.6.7 Cautions on separate bus mode..............................................................................................202

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 203

5.1 Features................................................................................................................................. 203

5.2 Bus Control Pins................................................................................................................... 204

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............204

5.2.2 Pin status in each operation mode...........................................................................................204

5.3 Memory Block Function....................................................................................................... 205

5.4 External Bus Interface Mode Control Function................................................................. 206

5.5 Bus Access ........................................................................................................................... 207

5.5.1 Number of clocks for access....................................................................................................207

5.5.2 Bus size setting function.......................................................................................................... 207

5.5.3 Access by bus size .................................................................................................................. 208

5.6 Wait Function ........................................................................................................................ 215

5.6.1 Programmable wait function .................................................................................................... 215

5.6.2 External wait function...............................................................................................................216

5.6.3 Relationship between programmable wait and external wait ...................................................217

5.6.4 Programmable address wait function.......................................................................................218

5.7 Idle State Insertion Function ............................................................................................... 219

5.8 Bus Hold Function................................................................................................................ 220

5.8.1 Functional outline.....................................................................................................................220

5.8.2 Bus hold procedure..................................................................................................................221

5.8.3 Operation in power save mode................................................................................................221

5.9 Bus Priority ........................................................................................................................... 222

5.10 Bus Timing ............................................................................................................................ 223

CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 229

6.1 Overview................................................................................................................................ 229

6.2 Configuration ........................................................................................................................ 230

6.3 Registers ............................................................................................................................... 232

6.4 Operation............................................................................................................................... 237

6.4.1 Operation of each clock........................................................................................................... 237

6.4.2 Clock output function ...............................................................................................................237

10

User’s Manual U17790EJ3V1UD

6.5

PLL Function..........................................................................................................................238

6.5.1 Overview .................................................................................................................................238

6.5.2 Registers ................................................................................................................................. 238

6.5.3 Usage...................................................................................................................................... 242

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................243

7.1 Overview.................................................................................................................................243

7.2 Functions ...............................................................................................................................243

7.3 Configuration.........................................................................................................................244

7.4 Registers ................................................................................................................................246

7.5 Timer Output Operations...................................................................................................... 259

7.6 Operation................................................................................................................................260

7.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 267

7.6.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)................................................. 279

7.6.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)..................................... 288

7.6.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 300

7.6.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 307

7.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101).................................................... 316

7.6.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 334

7.7 Selector Function ..................................................................................................................340

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................342

8.1 Overview.................................................................................................................................342

8.2 Functions ...............................................................................................................................342

8.3 Configuration.........................................................................................................................343

8.4 Registers ................................................................................................................................346

8.5 Timer Output Operations...................................................................................................... 361

8.6 Operation................................................................................................................................362

8.6.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000)............................................................ 370

8.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001)................................................ 381

8.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010).................................... 391

8.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) ............................................. 404

8.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100)............................................................. 413

8.6.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) ................................................... 424

8.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................445

8.7 Selector Function ..................................................................................................................450

CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................451

9.1 Overview.................................................................................................................................451

9.2 Configuration.........................................................................................................................452

9.3 Register ..................................................................................................................................453

9.4 Operation................................................................................................................................454

9.4.1 Interval timer mode.................................................................................................................. 454

9.4.2 Cautions .................................................................................................................................. 458

CHAPTER 10 WATCH TIMER FUNCTIONS .......................................................................................459

10.1 Functions ...............................................................................................................................459

10.2 Configuration .........................................................................................................................460

10.3 Control Registers ..................................................................................................................462

User’s Manual U17790EJ3V1UD

11

10.4

Operation ............................................................................................................................... 466

10.4.1 Operation as watch timer .........................................................................................................466

10.4.2 Operation as interval timer ....................................................................................................... 467

10.4.3 Cautions................................................................................................................................... 468

CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 469

11.1 Functions............................................................................................................................... 469

11.2 Configuration ........................................................................................................................ 470

11.3 Registers ............................................................................................................................... 471

11.4 Operation ............................................................................................................................... 474

CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 475

12.1 Function................................................................................................................................. 475

12.2 Configuration ........................................................................................................................ 476

12.3 Registers ............................................................................................................................... 478

12.4 Operation ............................................................................................................................... 480

12.5 Usage ..................................................................................................................................... 481

12.6 Cautions ................................................................................................................................ 481

CHAPTER 13 A/D CONVERTER ......................................................................................................... 482

13.1 Overview ................................................................................................................................ 482

13.2 Functions............................................................................................................................... 482

13.3 Configuration ........................................................................................................................ 483

13.4 Registers ............................................................................................................................... 486

13.5 Operation ............................................................................................................................... 497

13.5.1 Basic operation ........................................................................................................................ 497

13.5.2 Conversion operation timing ....................................................................................................498

13.5.3 Trigger mode ........................................................................................................................... 499

13.5.4 Operation mode .......................................................................................................................501

13.5.5 Power-fail compare mode ........................................................................................................ 505

13.6 Cautions ................................................................................................................................ 510

13.7 How to Read A/D Converter Characteristics Table ........................................................... 515

CHAPTER 14 D/A CONVERTER ......................................................................................................... 519

14.1 Functions............................................................................................................................... 519

14.2 Configuration ........................................................................................................................ 519

14.3 Registers ............................................................................................................................... 520

14.4 Operation ............................................................................................................................... 522

14.4.1 Operation in normal mode .......................................................................................................522

14.4.2 Operation in real-time output mode.......................................................................................... 522

14.4.3 Cautions................................................................................................................................... 523

CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 524

15.1 Mode Switching of UARTA and Other Serial Interfaces ................................................... 524

15.1.1 CSIB4 and UARTA0 mode switching ....................................................................................... 524

15.1.2 UARTA2 and I2C00 mode switching.........................................................................................525

15.1.3 UARTA1 and I2C02 mode switching.........................................................................................526

15.2 Features ................................................................................................................................. 527

15.3 Configuration ........................................................................................................................ 528

12

User’s Manual U17790EJ3V1UD

<R>

<R>

<R>

<R>

<R>

<R>

<R>

15.4

Registers ................................................................................................................................530

15.5 Interrupt Request Signals..................................................................................................... 537

15.6 Operation................................................................................................................................ 538

15.6.1 Data format.............................................................................................................................. 538

15.6.2 SBF transmission/reception format.......................................................................................... 540

15.6.3 SBF transmission .................................................................................................................... 542

15.6.4 SBF reception .......................................................................................................................... 543

15.6.5 UART transmission.................................................................................................................. 544

15.6.6 Continuous transmission procedure ........................................................................................ 545

15.6.7 UART reception ....................................................................................................................... 547

15.6.8 Reception errors ...................................................................................................................... 548

15.6.9 Parity types and operations ..................................................................................................... 550

15.6.10 Receive data noise filter ..........................................................................................................551

15.7 Dedicated Baud Rate Generator .......................................................................................... 552

15.8 Cautions .................................................................................................................................560

CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................561

16.1 Mode Switching of CSIB and Other Serial Interfaces ........................................................ 561

16.1.1 CSIB4 and UARTA0 mode switching ...................................................................................... 561

16.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 562

16.2 Features.................................................................................................................................. 562

16.3 Configuration .........................................................................................................................563

16.4 Registers ................................................................................................................................565

16.5 Interrupt Request Signals..................................................................................................... 573

16.6 Operation................................................................................................................................ 574

16.6.1 Single transfer mode (master mode, transmission mode) ....................................................... 574

16.6.2 Single transfer mode (master mode, reception mode)............................................................. 576

16.6.3 Single transfer mode (master mode, transmission/reception mode)........................................ 578

16.6.4 Single transfer mode (slave mode, transmission mode) .......................................................... 580

16.6.5 Single transfer mode (slave mode, reception mode) ...............................................................582

16.6.6 Single transfer mode (slave mode, transmission/reception mode) ..........................................584

16.6.7 Continuous transfer mode (master mode, transmission mode) ............................................... 586

16.6.8 Continuous transfer mode (master mode, reception mode)..................................................... 588

16.6.9 Continuous transfer mode (master mode, transmission/reception mode)................................ 591

16.6.10 Continuous transfer mode (slave mode, transmission mode).................................................. 595

16.6.11 Continuous transfer mode (slave mode, reception mode) ....................................................... 597

16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .................................. 600

16.6.13 Reception error........................................................................................................................ 604

16.6.14 Clock timing............................................................................................................................. 605

16.7 Output Pins ............................................................................................................................607

16.8 Baud Rate Generator ............................................................................................................608

16.8.1 Baud rate generation ...............................................................................................................609

16.9 Cautions .................................................................................................................................610

CHAPTER 17 I

2

C BUS...........................................................................................................................611

17.1 Mode Switching of I2C Bus and Other Serial Interfaces ....................................................611

17.1.1 UARTA2 and I2C00 mode switching ........................................................................................611

17.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 612

17.1.3 UARTA1 and I2C02 mode switching ........................................................................................613

User’s Manual U17790EJ3V1UD

13

17.2

Features ................................................................................................................................. 614

17.3 Configuration ........................................................................................................................ 615

17.4 Registers ............................................................................................................................... 619

17.5 I2C Bus Mode Functions....................................................................................................... 635

17.5.1 Pin configuration ...................................................................................................................... 635

17.6 I2C Bus Definitions and Control Methods .......................................................................... 636

17.6.1 Start condition .......................................................................................................................... 636

17.6.2 Addresses ................................................................................................................................ 637

17.6.3 Transfer direction specification ................................................................................................638

17.6.4 ACK .........................................................................................................................................639

17.6.5 Stop condition .......................................................................................................................... 640

17.6.6 Wait state ................................................................................................................................. 641

17.6.7 Wait state cancellation method ................................................................................................643

17.7 I2C Interrupt Request Signals (INTIICn) .............................................................................. 644

17.7.1 Master device operation...........................................................................................................645

17.7.2 Slave device operation (when receiving slave address (address match))................................ 648

17.7.3 Slave device operation (when receiving extension code) ........................................................652

17.7.4 Operation without communication ............................................................................................ 656

17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................657

17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................659

17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 666

17.9 Address Match Detection Method ...................................................................................... 667

17.10 Error Detection...................................................................................................................... 667

17.11 Extension Code..................................................................................................................... 668

17.12 Arbitration ............................................................................................................................. 669

17.13 Wakeup Function.................................................................................................................. 670

17.14 Communication Reservation............................................................................................... 671

17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................671

17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................675

17.15 Cautions ................................................................................................................................ 676

17.16 Communication Operations ............................................................................................... 677

17.16.1 Master operation in single master system................................................................................678

17.16.2 Master operation in multimaster system ..................................................................................679

17.16.3 Slave operation........................................................................................................................682

17.17 Timing of Data Communication .......................................................................................... 686

CHAPTER 18 IEBus CONTROLLER................................................................................................... 693

18.1 Functions............................................................................................................................... 693

18.1.1 Communication protocol of IEBus............................................................................................ 693

18.1.2 Determination of bus mastership (arbitration) ..........................................................................694

18.1.3 Communication mode ..............................................................................................................694

18.1.4 Communication address ..........................................................................................................694

18.1.5 Broadcast communication........................................................................................................695

18.1.6 Transfer format of IEBus..........................................................................................................695

18.1.7 Transfer data ...........................................................................................................................705

18.1.8 Bit format .................................................................................................................................707

18.2 Configuration ........................................................................................................................ 708

18.3 Registers ............................................................................................................................... 710

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User’s Manual U17790EJ3V1UD

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18.4

Interrupt Operations of IEBus Controller............................................................................ 740

18.4.1 Interrupt control block .............................................................................................................. 740

18.4.2 Example of identifying interrupt ............................................................................................... 742

18.4.3 Interrupt source list .................................................................................................................. 745

18.4.4 Communication error source processing list............................................................................ 746

18.5 Interrupt Request Signal Generation Timing and Main CPU Processing........................ 748

18.5.1 Master transmission ................................................................................................................ 748

18.5.2 Master reception ...................................................................................................................... 750

18.5.3 Slave transmission .................................................................................................................. 752

18.5.4 Slave reception ........................................................................................................................ 754

18.5.5 Interval of occurrence of interrupt request signal for IEBus control ......................................... 756

CHAPTER 19 CAN CONTROLLER ......................................................................................................760

19.1 Overview................................................................................................................................. 760

19.1.1 Features .................................................................................................................................. 760

19.1.2 Overview of functions .............................................................................................................. 761

19.1.3 Configuration ........................................................................................................................... 762

19.2 CAN Protocol .........................................................................................................................763

19.2.1 Frame format ........................................................................................................................... 763

19.2.2 Frame types ............................................................................................................................ 764

19.2.3 Data frame and remote frame.................................................................................................. 764

19.2.4 Error frame .............................................................................................................................. 772

19.2.5 Overload frame........................................................................................................................ 773

19.3 Functions ...............................................................................................................................774

19.3.1 Determining bus priority........................................................................................................... 774

19.3.2 Bit stuffing................................................................................................................................ 774

19.3.3 Multi masters ........................................................................................................................... 774

19.3.4 Multi cast ................................................................................................................................. 774

19.3.5 CAN sleep mode/CAN stop mode function.............................................................................. 775

19.3.6 Error control function ............................................................................................................... 775

19.3.7 Baud rate control function........................................................................................................ 782

19.4 Connection with Target System ..........................................................................................786

19.5 Internal Registers of CAN Controller ..................................................................................787

19.5.1 CAN controller configuration.................................................................................................... 787

19.5.2 Register access type ............................................................................................................... 788

19.5.3 Register bit configuration ......................................................................................................... 822

19.6 Registers ................................................................................................................................826

19.7 Bit Set/Clear Function ...........................................................................................................862

19.8 CAN Controller Initialization ................................................................................................864

19.8.1 Initialization of CAN module..................................................................................................... 864

19.8.2 Initialization of message buffer ................................................................................................ 864

19.8.3 Redefinition of message buffer ................................................................................................ 864

19.8.4 Transition from initialization mode to operation mode.............................................................. 865

19.8.5 Resetting error counter CnERC of CAN module...................................................................... 866

19.9 Message Reception ............................................................................................................... 867

19.9.1 Message reception .................................................................................................................. 867

19.9.2 Reading reception data............................................................................................................ 868

19.9.3 Receive history list function ..................................................................................................... 869

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15

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19.9.4 Mask function...........................................................................................................................871

19.9.5 Multi buffer receive block function............................................................................................ 873

19.9.6 Remote frame reception ..........................................................................................................874

19.10 Message Transmission ........................................................................................................ 875

19.10.1 Message transmission .............................................................................................................875

19.10.2 Transmit history list function ....................................................................................................877

19.10.3 Automatic block transmission (ABT) ........................................................................................ 879

19.10.4 Transmission abort process.....................................................................................................881

19.10.5 Remote frame transmission ..................................................................................................... 882

19.11 Power Saving Modes............................................................................................................ 883

19.11.1 CAN sleep mode...................................................................................................................... 883

19.11.2 CAN stop mode .......................................................................................................................885

19.11.3 Example of using power saving modes....................................................................................886

19.12 Interrupt Function................................................................................................................. 887

19.13 Diagnosis Functions and Special Operational Modes ..................................................... 888

19.13.1 Receive-only mode ..................................................................................................................888

19.13.2 Single-shot mode.....................................................................................................................889

19.13.3 Self-test mode..........................................................................................................................890

19.13.4 Transmission/reception operation in each operation mode...................................................... 891

19.14 Time Stamp Function ........................................................................................................... 892

19.14.1 Time stamp function ................................................................................................................892

19.15 Baud Rate Settings............................................................................................................... 894

19.15.1 Bit rate setting conditions......................................................................................................... 894

19.15.2 Representative examples of baud rate settings ....................................................................... 898

19.16 Operation of CAN Controller ............................................................................................... 902

CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) ................................................................... 928

20.1 Features ................................................................................................................................. 928

20.2 Configuration ........................................................................................................................ 929

20.3 Registers ............................................................................................................................... 930

20.4 Transfer Targets ................................................................................................................... 939

20.5 Transfer Modes ..................................................................................................................... 939

20.6 Transfer Types ...................................................................................................................... 940

20.7 DMA Channel Priorities........................................................................................................ 941

20.8 Time Related to DMA Transfer ............................................................................................ 941

20.9 DMA Transfer Start Factors................................................................................................. 942

20.10 DMA Abort Factors............................................................................................................... 943

20.11 End of DMA Transfer............................................................................................................ 943

20.12 Operation Timing .................................................................................................................. 943

20.13 Cautions ................................................................................................................................ 948

CHAPTER 21 CRC FUNCTION............................................................................................................ 952

21.1 Functions............................................................................................................................... 952

21.2 Configuration ........................................................................................................................ 952

21.3 Registers ............................................................................................................................... 953

21.4 Operation ............................................................................................................................... 954

21.5 Usage Method ....................................................................................................................... 955

CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 957

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User’s Manual U17790EJ3V1UD

22.1

Features.................................................................................................................................. 957

22.2 Non-Maskable Interrupts ......................................................................................................962

22.2.1 Operation................................................................................................................................. 964

22.2.2 Restore .................................................................................................................................... 965

22.2.3 NP flag..................................................................................................................................... 966

22.3 Maskable Interrupts ..............................................................................................................967

22.3.1 Operation................................................................................................................................. 967

22.3.2 Restore .................................................................................................................................... 969

22.3.3 Priorities of maskable interrupts .............................................................................................. 970

22.3.4 Interrupt control register (xxICn) .............................................................................................. 974

22.3.5 Interrupt mask registers 0 to 4 (IMR0 to IMR4)........................................................................ 978

22.3.6 In-service priority register (ISPR)............................................................................................. 980

22.3.7 ID flag ......................................................................................................................................981

22.3.8 Watchdog timer mode register 2 (WDTM2) ............................................................................. 981

22.4 Software Exception ...............................................................................................................982

22.4.1 Operation................................................................................................................................. 982

22.4.2 Restore .................................................................................................................................... 983

22.4.3 EP flag ..................................................................................................................................... 984

22.5 Exception Trap ......................................................................................................................985

22.5.1 Illegal opcode definition ........................................................................................................... 985

22.5.2 Debug trap ............................................................................................................................... 987

22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP8) .................................... 989

22.6.1 Noise elimination ..................................................................................................................... 989

22.6.2 Edge detection......................................................................................................................... 989

22.7 Interrupt Acknowledge Time of CPU ................................................................................... 995

22.8 Periods in Which Interrupts Are Not Acknowledged by CPU...........................................997

22.9 Cautions .................................................................................................................................997

CHAPTER 23 KEY INTERRUPT FUNCTION ......................................................................................998

23.1 Function .................................................................................................................................998

23.2 Register ..................................................................................................................................999

23.3 Cautions .................................................................................................................................999

CHAPTER 24 STANDBY FUNCTION................................................................................................. 1000

24.1 Overview............................................................................................................................... 1000

24.2 Registers ..............................................................................................................................1002

24.3 HALT Mode........................................................................................................................... 1005

24.3.1 Setting and operation status.................................................................................................. 1005

24.3.2 Releasing HALT mode .......................................................................................................... 1005

24.4 IDLE1 Mode ..........................................................................................................................1007

24.4.1 Setting and operation status.................................................................................................. 1007

24.4.2 Releasing IDLE1 mode .......................................................................................................... 1007

24.5 IDLE2 Mode ..........................................................................................................................1009

24.5.1 Setting and operation status.................................................................................................. 1009

24.5.2 Releasing IDLE2 mode .......................................................................................................... 1009

24.5.3 Securing setup time when releasing IDLE2 mode .................................................................1011

24.6 STOP Mode ..........................................................................................................................1012

24.6.1 Setting and operation status.................................................................................................. 1012

24.6.2 Releasing STOP mode.......................................................................................................... 1012

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17

24.6.3 Securing oscillation stabilization time when releasing STOP mode .......................................1015

24.7 Subclock Operation Mode ................................................................................................. 1016

24.7.1 Setting and operation status ..................................................................................................1016

24.7.2 Releasing subclock operation mode ......................................................................................1016

24.8 Sub-IDLE Mode ................................................................................................................... 1018

24.8.1 Setting and operation status ..................................................................................................1018

24.8.2 Releasing sub-IDLE mode ..................................................................................................... 1018

CHAPTER 25 RESET FUNCTIONS ................................................................................................... 1020

25.1 Overview .............................................................................................................................. 1020

25.2 Registers to Check Reset Source ..................................................................................... 1022

25.3 Operation ............................................................................................................................. 1023

25.3.1 Reset operation via RESET pin .............................................................................................1023

25.3.2 Reset operation by watchdog timer 2 (WDT2RES)................................................................ 1025

25.3.3 Reset operation by low-voltage detector (LVIRES) ................................................................ 1027

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25.3.4 Reset operation by clock monitor (CLMRES) ........................................................................ 1028

25.3.5 Operation after reset release .................................................................................................1030

25.3.6 Reset function operation flow.................................................................................................1031

CHAPTER 26 CLOCK MONITOR ...................................................................................................... 1032

26.1 Functions............................................................................................................................. 1032

26.2 Configuration ...................................................................................................................... 1032

26.3 Register ............................................................................................................................... 1033

26.4 Operation ............................................................................................................................. 1034

CHAPTER 27 LOW-VOLTAGE DETECTOR ..................................................................................... 1037

27.1 Functions............................................................................................................................. 1037

27.2 Configuration ...................................................................................................................... 1037

27.3 Registers ............................................................................................................................. 1038

27.4 Operation ............................................................................................................................. 1040

27.4.1 To use for internal reset signal (LVIRES)............................................................................... 1040

27.4.2 To use for interrupt (INTLVI) ..................................................................................................1041

27.5 RAM Retention Voltage Detection Operation .................................................................. 1042

27.6 Emulation Function ............................................................................................................ 1043

CHAPTER 28 REGULATOR ............................................................................................................... 1044

28.1 Overview .............................................................................................................................. 1044

28.2 Operation ............................................................................................................................. 1045

CHAPTER 29 ROM CORRECTION FUNCTION............................................................................... 1046

29.1 Overview .............................................................................................................................. 1046

29.2 Registers ............................................................................................................................. 1047

29.3 ROM Correction Operation and Program Flow ............................................................... 1049

29.4 Cautions .............................................................................................................................. 1051

CHAPTER 30 FLASH MEMORY........................................................................................................ 1052

30.1 Features ............................................................................................................................... 1052

30.2 Memory Configuration ....................................................................................................... 1053

30.3 Functional Outline .............................................................................................................. 1055

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User’s Manual U17790EJ3V1UD

30.4

Rewriting by Dedicated Flash Memory Programmer.......................................................1058

30.4.1 Programming environment .................................................................................................... 1058

30.4.2 Communication mode............................................................................................................ 1059

30.4.3 Flash memory control ............................................................................................................ 1065

30.4.4 Selection of communication mode......................................................................................... 1066

30.4.5 Communication commands ................................................................................................... 1067

30.4.6 Pin connection....................................................................................................................... 1068

30.5 Rewriting by Self Programming.........................................................................................1073

30.5.1 Overview ............................................................................................................................... 1073

30.5.2 Features ................................................................................................................................ 1074

30.5.3 Standard self programming flow ............................................................................................1075

30.5.4 Flash functions ......................................................................................................................1076

30.5.5 Pin processing....................................................................................................................... 1076

30.5.6 Internal resources used .........................................................................................................1077

CHAPTER 31 ON-CHIP DEBUG FUNCTION....................................................................................1078

31.1 Features................................................................................................................................ 1078

31.2 Connection Circuit Example ..............................................................................................1079

31.3 Interface Signals..................................................................................................................1079

31.4 Register ................................................................................................................................1081

31.5 Operation.............................................................................................................................. 1083

31.6 ROM Security Function....................................................................................................... 1084

31.6.1 Security ID ............................................................................................................................. 1084

31.6.2 Setting ................................................................................................................................... 1085

31.7 Cautions ...............................................................................................................................1087

CHAPTER 32 ELECTRICAL SPECIFICATIONS................................................................................1088

32.1 Absolute Maximum Ratings ...............................................................................................1088

32.2 Capacitance .........................................................................................................................1090

32.3 Operating Conditions..........................................................................................................1090

32.4 Oscillator Characteristics...................................................................................................1091

32.4.1 Main clock oscillator characteristics....................................................................................... 1091

32.4.2 Subclock oscillator characteristics .........................................................................................1094

32.4.3 PLL characteristics ................................................................................................................ 1095

32.4.4 Internal oscillator characteristics............................................................................................ 1095

32.5 Regulator Characteristics ..................................................................................................1095

32.6 DC Characteristics ..............................................................................................................1096

32.6.1 I/O level ................................................................................................................................. 1096

32.6.2 Supply current ....................................................................................................................... 1098

32.7 Data Retention Characteristics ..........................................................................................1099

32.8 AC Characteristics ..............................................................................................................1100

32.8.1 CLKOUT output timing .......................................................................................................... 1101

32.8.2 Bus timing.............................................................................................................................. 1102

32.9 Basic Operation ...................................................................................................................1115

32.10 Flash Memory Programming Characteristics ..................................................................1124

CHAPTER 33 PACKAGE DRAWING .................................................................................................1126

CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS .........................................................1128

User’s Manual U17790EJ3V1UD

19

APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1130

A.1 Software Package............................................................................................................... 1135

A.2 Language Processing Software........................................................................................ 1135

A.3 Control Software................................................................................................................. 1135

A.4 Debugging Tools (Hardware) ............................................................................................ 1136

A.4.1 When using in-circuit emulator IE-V850ES-G1 ......................................................................1136

A.4.2 When using IECUBE QB-V850ESSX2 ..................................................................................1138

A.4.3 When using on-chip debug emulator IE-V850E1-CD-NW......................................................1140

A.4.4 When using QB-V850MINI (MINICUBE)................................................................................1141

A.5 Debugging Tools (Software).............................................................................................. 1142

A.6 Embedded Software ........................................................................................................... 1143

A.7 Flash Memory Writing Tools ............................................................................................. 1143

APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/SJ3 AND V850ES/SJ2 .................. 1144

APPENDIX C REGISTER INDEX ....................................................................................................... 1146

APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1161

D.1 Conventions ........................................................................................................................ 1161

D.2 Instruction Set (in Alphabetical Order) ............................................................................ 1164

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APPENDIX E LIST OF CAUTIONS ................................................................................................... 1171

APPENDIX F REVISION HISTORY.................................................................................................... 1210

F.1 Major Revisions in This Edition ........................................................................................ 1210

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F.2 Revision History of Previous Editions ............................................................................. 1216

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User’s Manual U17790EJ3V1UD

CHAPTER 1 INTRODUCTION

The V850ES/SJ3 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low-

power operation for real-time control applications.

1.1 General

The V850ES/SJ3 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral

functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. As for

automotive LAN, the V850ES/SJ3 is provided with IEBus

provided with CAN (Controller Area Network).

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/SJ3 features

multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware

multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the

V850ES/SJ3 enables an extremely high cost-performance for applications that require a low power consumption, such

as audio and car audio.

Table 1-1 lists the products of the V850ES/SJ3.

A model of the V850ES/SJ3 with reduced I/O, timer/counter, and serial interface functions, V850ES/SG3, is also

available. See Table 1-2 V850ES/SG3 Product List.

TM

(Inter Equipment BusTM), and some of the models are also

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21

CHAPTER 1 INTRODUCTION

Table 1-1. V850ES/SJ3 Product List

Function

Part Number

μ

PD70F3344 384 KB 32 KB

μ

PD70F3345 512 KB 40 KB

μ

PD70F3346 640 KB 48 KB

μ

PD70F3347 768 KB 60 KB

μ

PD70F3348 1024 KB 60 KB

μ

PD70F3354 384 KB 32 KB

μ

PD70F3355 512 KB 40 KB

μ

PD70F3356 640 KB 48 KB

μ

PD70F3357 768 KB 60 KB

μ

PD70F3358 1024 KB 60 KB

μ

PD70F3364 384 KB 32 KB

μ

PD70F3365 512 KB 40 KB

μ

PD70F3366 640 KB 48 KB

μ

PD70F3367 768 KB 60 KB

μ

PD70F3368

ROM Maskable Interrupts

Type Size

Flash

memory

1024 KB 60 KB

RAM Size

Operating

Frequency

(MAX.)

32 MHz On-chip On-chip

2

C IEBus CAN

I

None

Remark The part numbers of the V850ES/SJ3 are shown as follows in this manual.

• CAN controller version

μ

PD70F3354, 70F3355, 70F3356, 70F3357, 70F3358, 70F3364, 70F3365, 70F3366, 70F3367,

70F3368

• CAN controller (2-channel) version

μ

PD70F3364, 70F3365, 70F3366, 70F3367, 70F3368

Table 1-2. V850ES/SG3 Product List

Function

Part Number

μ

PD70F3333 256 KB 24 KB

μ

PD70F3334 384 KB 32 KB

μ

PD70F3335 256 KB 24 KB

μ

PD70F3336 384 KB 32 KB

μ

PD70F3340 512 KB 40 KB

μ

PD70F3341 640 KB 48 KB

μ

PD70F3342 768 KB 60 KB

μ

PD70F3343 1024 KB 60 KB

μ

PD70F3350 512 KB 40 KB

μ

PD70F3351 640 KB 48 KB

μ

PD70F3352 768 KB 60 KB

μ

PD70F3353

ROM Maskable Interrupts

Type Size

Flash

memory

1024 KB 60 KB

RAM Size

Operating

Frequency

(MAX.)

32 MHz On-chip On-chip

2

I

C IEBus CAN

None

None

1 ch

2 ch

1 ch

1 ch

Non-

64

68

Maskable

Interrupts

2

Non-

Maskable

Interrupts

External Internal

9

External Internal

8 51 2

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User’s Manual U17790EJ3V1UD

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CHAPTER 1 INTRODUCTION

1.2 Features

Minimum instruction execution time: 31.25 ns (operating with main clock (fXX) of 32 MHz)
General-purpose registers: 32 bits × 32 registers
CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks

Signed multiplication (32 × 32 → 64): 1 to 5 clocks

Saturated operations (overflow and underflow detection functions included)

32-bit shift instruction: 1 clock

Bit manipulation instructions

Load/store instructions with long/short format

Memory space: 64 MB of linear address space (for programs and data)

External expansion: Up to 16 MB

• Internal memory: RAM: 32/40/48/60 KB (see Tabl e 1 - 1)

Flash memory: 384/512/640/768/1024 KB (see Table 1-1)

• External bus interface: Separate bus/multiplexed bus output selectable

8-/16-bit data bus sizing function

Wait function

• Programmable wait function

• External wait function

Idle state function

Bus hold function

Interrupts and exceptions: Non-maskable interrupts: 2 sources

Maskable interrupts: 73/77 sources (see Table 1-1)

Software exceptions: 32 sources

Exception trap: 2 sources

I/O lines: I/O ports: 128

Timer function: 16-bit interval timer M (TMM): 1 channel

16-bit timer/event counter P (TMP): 9 channels

16-bit timer/event counter Q (TMQ): 1 channel

Watch timer: 1 channel

Watchdog timer: 1 channel

Real-time output port: 6 bits × 2 channels

Serial interface: Asynchronous serial interface A (UARTA)

3-wire variable-length serial interface B (CSIB)

I

UARTA/CSIB: 1 channel

UARTA/I

CSIB/I

CSIB: 4 channels

UARTA: 1 channel

IEBus controller: 1 channel

CAN controller: 1/2 channels (CAN controller version only)

A/D converter: 10-bit resolution: 16 channels

D/A converter: 8-bit resolution: 2 channels

2

C bus interface (I2C)

2

C: 2 channels

2

C: 1 channel

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23

CHAPTER 1 INTRODUCTION

DMA controller: 4 channels

CRC function: Generates 16-bit error detection code for data in 8-bit units

On-chip debug function: JTAG interface

ROM correction: 4 correction addresses specifiable

Clock generator: During main clock or subclock operation

7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

Clock-through mode/PLL mode selectable

Internal oscillation clock: 220 kHz (TYP.)

Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Package: 144-pin plastic LQFP (fine pitch) (20 × 20)

1.3 Application Fields

Audio, car audio, other consumer devices

24

User’s Manual U17790EJ3V1UD

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CHAPTER 1 INTRODUCTION

1.4 Ordering Information

Part Number Package Internal ROM

μ

PD70F3344GJ(A)-GAE-AX

μ

PD70F3345GJ(A)-GAE-AX

μ

PD70F3346GJ(A)-GAE-AX

μ

PD70F3346GJ(A)-UEN-A

μ

PD70F3347GJ(A)-GAE-AX

μ

PD70F3347GJ(A)-UEN-A

μ

PD70F3348GJ(A)-GAE-AX

μ

PD70F3348GJ(A)-UEN-A

μ

PD70F3354GJ(A)-GAE-AX

μ

PD70F3355GJ(A)-GAE-AX

μ

PD70F3356GJ(A)-GAE-AX

μ

PD70F3356GJ(A)-UEN-A

μ

PD70F3357GJ(A)-GAE-AX

μ

PD70F3357GJ(A)-UEN-A

μ

PD70F3358GJ(A)-GAE-AX

μ

PD70F3358GJ(A)-UEN-A

μ

PD70F3364GJ(A)-GAE-AX

μ

PD70F3365GJ(A)-GAE-AX

μ

PD70F3366GJ(A)-GAE-AX

μ

PD70F3366GJ(A)-UEN-A

μ

PD70F3367GJ(A)-GAE-AX

μ

PD70F3367GJ(A)-UEN-A

μ

PD70F3368GJ(A)-GAE-AX

μ

PD70F3368GJ(A)-UEN-A

Remark The V850ES/SJ3 products are lead-free.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.

144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)

384 KB (flash memory)

512 KB (flash memory)

640 KB (flash memory)

640 KB (flash memory)

768 KB (flash memory)

768 KB (flash memory)

1024 KB (flash memory)

1024 KB (flash memory)

384 KB (flash memory)

512 KB (flash memory)

640 KB (flash memory)

640 KB (flash memory)

768 KB (flash memory)

768 KB (flash memory)

1024 KB (flash memory)

1024 KB (flash memory)

384 KB (flash memory)

512 KB (flash memory)

640 KB (flash memory)

640 KB (flash memory)

768 KB (flash memory)

768 KB (flash memory)

1024 KB (flash memory)

1024 KB (flash memory)

User’s Manual U17790EJ3V1UD

25

1.5 Pin Configuration (Top View)

144-pin plastic LQFP (fine pitch) (20 × 20)

μ

<R>

<R>

PD70F3344GJ(A)-GAE-AX

μ

PD70F3345GJ(A)-GAE-AX

μ

PD70F3346GJ(A)-GAE-AX

μ

PD70F3346GJ(A)-UEN-A

μ

PD70F3347GJ(A)-GAE-AX

μ

PD70F3347GJ(A)-UEN-A

μ

PD70F3348GJ(A)-GAE-AX

μ

PD70F3348GJ(A)-UEN-A

CHAPTER 1 INTRODUCTION

μ

PD70F3354GJ(A)-GAE-AX

μ

PD70F3355GJ(A)-GAE-AX

μ

PD70F3356GJ(A)-GAE-AX

μ

PD70F3356GJ(A)-UEN-A

μ

PD70F3357GJ(A)-GAE-AX

μ

PD70F3357GJ(A)-UEN-A

μ

PD70F3358GJ(A)-GAE-AX

μ

PD70F3358GJ(A)-UEN-A

μ

PD70F3364GJ(A)-GAE-AX

μ

PD70F3365GJ(A)-GAE-AX

μ

PD70F3366GJ(A)-GAE-AX

μ

PD70F3366GJ(A)-UEN-A

μ

PD70F3367GJ(A)-GAE-AX

μ

PD70F3367GJ(A)-UEN-A

μ

PD70F3368GJ(A)-GAE-AX

μ

PD70F3368GJ(A)-UEN-A

26

User’s Manual U17790EJ3V1UD

P10/ANO0
P11/ANO1

P00/TIP61/TOP61
P01/TIP60/TOP60

FLMD0

REGC

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

P05/INTP2/DRST

P06/INTP3

P40/SIB0/SDA01

P41/SOB0/SCL01

P42/SCKB0

P30/TXDA0/SOB4

P31/RXDA0/INTP7/SIB4

P32/ASCKA0/SCKB4/TIP00/TOP00

P33/TIP01/TOP01/CTXD1

P34/TIP10/TOP10/CRXD1

P35/TIP11/TOP11

P36/IETX0/CTXD0

P37/IERX0/CRXD0

P38/TXDA2/SDA00
P39/RXDA2/SCL00

AV

AV

AV

Note 1

Note 2

RESET

XT1
XT2

Note 3

Note 4

Note 4

Note 5

Note 5

EV
EV

CHAPTER 1 INTRODUCTION

Note 7

Note 7

Note 7

Note 7

Note 7

P710/ANI10

P711/ANI11

P712/ANI12

P713/ANI13

134

133

132

131

Note 7

P714/ANI14

P715/ANI15

PDH7/A23

PDH6/A22

130

129

128

127

PDH5/A21

PDH4/A20

PDH3/A19

126

125

124

PDH2/A18

PDH1/A17

PDH0/A16

123

122

121

PDL15/AD15

PDL14/AD14

PDL13/AD13

PDL12/AD12

120

119

118

117

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

116

115

114

113

PDL7/AD7

PDL6/AD6

PDL5/AD5/FLMD1

PDL4/AD4

112

111

110

109

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

72

PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0

DD

BV
BV

SS

PCT7
PCT6/ASTB
PCT5
PCT4/RD
PCT3
PCT2
PCT1/WR1
PCT0/WR0
PCS7
PCS6
PCS5
PCS4
PCM5
PCM4
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
PCD2
PCD1
PCD0

Note 6

P915/A15

Note 6

P914/A14

Note 6

P913/A13

Note 6

P912/A12

/INTP6/TIP50/TOP50
/INTP5/TIP51/TOP51
/INTP4
/SCKB3

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

144

143

142

141

140

139

138

137

136

REF0

1

SS

2
3
4

REF1

5
6
7
8

V

DD

9
10

V

SS

11

X1

12

X2

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SS

33

DD

34
35
36

135

3738394041424344454647484950515253545556575859606162636465666768697071

<R>

<R>

<R>

P614

P60/RTP10

P61/RTP11

P62/RTP12

P63/RTP13

P64/RTP14

P54/SOB2/KR4/RTP04/DCK

P50/TIQ01/KR0/TOQ01/RTP00

P55/SCKB2/KR5/RTP05/DMS

P51/TIQ02/KR1/TOQ02/RTP01

P66/SIB5

P67/SOB5

P65/RTP15

P68/SCKB5

P610/TIP71

P611/TOP71

P69/TIP70/TOP70

P612/TIP80/TOP80

P613/TIP81/TOP81

P615

P81/TXDA3

/TIP41/TOP41

Note 6

P80/RXDA3/INTP8

/KR6/TXDA1/SDA02

/KR7/RXDA1/SCL02

Note 6

Note 6

P92/A2

P91/A1

P90/A0

/TIP40/TOP40

/TIP31/TOP31

/TIP30/TOP30

Note 6

Note 6

Note 6

P93/A3

P94/A4

P95/A5

/SIB3

/SOB1

/SCKB1

Note 6

Note 6

Note 6

Note 6

/TIP21/TOP21

P98/A8

Note 6

P99/A9

P910/A10

/SIB1/TIP20/TOP20

Note 6

P96/A6

P97/A7

/SOB3

P911/A11

P52/TIQ03/KR2/TOQ03/RTP02/DDI

P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO

Notes 1. Connect this pin to V

2. Connect the REGC pin to V

SS in the normal mode.

SS via a 4.7

μ

F capacitor.

3. Fix this pin to the low level from when the reset status has been released until the OCDM.OCDM0 bit is

cleared (0) when the on-chip debug function is not used. For details, see 4.6.3 Cautions on on-chip

debug pins.

4. CTXD1 and CRXD1 are valid only in the CAN controller (2-channel) version.

5. CTXD0 and CRXD0 are valid only in the CAN controller version.

6. Port 9 cannot be used as port pins or other alternate-function pins when the A0 to A15 pins are used in

the separate bus mode.

7. To use port 7 (P70/ANI0 to P715/ANI15) as A/D converter function pins and port I/O pins in mix, be

sure to observe usage cautions (see 13.6 (4) Alternate I/O).

User’s Manual U17790EJ3V1UD

27

Pin names

A0 to A23:

AD0 to AD15:

ADTRG:

ANI0 to ANI15:

ANO0, ANO1:

ASCKA0:

ASTB:

AV

REF0, AVREF1:

AV

SS:

BVDD:

BV

SS:

CLKOUT:

CRXD0, CRXD1:

CS0 to CS3:

CTXD0, CTXD1:

DCK:

DDI:

DDO:

DMS:

DRST:

EV

DD:

EVSS:

FLMD0, FLMD1:

HLDAK:

HLDRQ:

IERX0:

IETX0:

INTP0 to INTP8:

KR0 to KR7:

NMI:

P00 to P06:

P10, P11:

P30 to P39:

P40 to P42:

P50 to P55:

P60 to P615:

P70 to P715:

P80, P81:

P90 to P915:

PCD0 to PCD3:

PCM0 to PCM5:

PCS0 to PCS7:

CHAPTER 1 INTRODUCTION

Address bus

Address/data bus

A/D trigger input

Analog input

Analog output

Asynchronous serial clock

Address strobe

Analog reference voltage

Analog V

SS

Power supply for bus interface

Ground for bus interface

Clock output

CAN receive data

Chip select

CAN transmit data

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for port

Ground for port

Flash programming mode

Hold acknowledge

Hold request

IEBus receive data

IEBus transmit data

External interrupt input

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port CD

Port CM

Port CS

PCT0 to PCT7:

PDH0 to PDH7:

PDL0 to PDL15:

RD:

REGC:

RESET:

RTP00 to RTP05,

RTP10 to RTP15:

RXDA0 to RXDA3:

SCKB0 to SCKB5:

SCL00 to SCL02:

SDA00 to SDA02:

SIB0 to SIB5:

SOB0 to SOB5:

TIP00, TIP01,

TIP10, TIP11,

TIP20, TIP21,

TIP30, TIP31,

TIP40, TIP41,

TIP50, TIP51,

TIP60, TIP61,

TIP70, TIP71,

TIP80, TIP81,

TIQ00 to TIQ03:

TOP00, TOP01,

TOP10, TOP11,

TOP20, TOP21,

TOP30, TOP31,

TOP40, TOP41,

TOP50, TOP51,

TOP60, TOP61,

TOP70, TOP71,

TOP80, TOP81,

TOQ00 to TOQ03:

TXDA0 to TXDA3:

V

DD:

VSS:

WAIT:

WR0:

WR1:

X1, X2:

XT1, XT2:

Port CT

Port DH

Port DL

Read strobe

Regulator control

Reset

Real-time output port

Receive data

Serial clock

Serial clock

Serial data

Serial input

Serial output

Timer input

Timer output

Transmit data

Power supply

Ground

Wait

Lower byte write strobe

Upper byte write strobe

Crystal for main clock

Crystal for subclock

28

User’s Manual U17790EJ3V1UD

1.6 Function Block Configuration

1.6.1 Internal block diagram

NMI

INTP0 to INTP8

TIQ00 to TIQ03

TOQ00 to TOQ03

TIP00 to TIP80,

TIP01 to TIP81

TOP00 to TOP80,

TOP01 to TOP81

INTC

16-bit timer/

counter Q:

1 ch

16-bit timer/

counter P:

9 ch

16-bit interval

timer M:

1 ch

CHAPTER 1 INTRODUCTION

ROM

Note 1

RAM

Note 2

ROM

correction

DMAC

PC

32-bit barrel

shifter

System

registers

General-purpose

registers 32 bits × 32

CPU

Multiplier

16 × 16 → 32

ALU

Instruction

queue

BCU

HLDRQ
HLDAK
ASTB
RD
WAIT

WR0, WR1

A0 to A23
AD0 to AD15
CS0 to CS3

RTP00 to RTP05,

RTP10 to RTP15

SOB0/SCL01

SIB0/SDA01

SCKB0

SOB1 to SOB3, SOB5

SIB1 to SIB3, SIB5

SCKB1 to SCKB3, SCKB5

TXDA0/SOB4

RXDA0/SIB4

ASCKA0/SCKB4

TXDA1/SDA02
RXDA1/SCL02

TXDA2/SDA00
RXDA2/SCL00

TXDA3
RXDA3

RTO

CSIB0 I2C01

CSIB1 to CSIB3,

CSIB5

UARTA0

CSIB4

UARTA1

I2C02

UARTA2

I2C00

UARTA3

PCT0 to PCT7

PCS0 to PCS7

PDH0 to PDH7

PCM0 to PCM5

PDL0 to PDL15

A/D

converter

D/A

converter

Key return

function

Watchdog

timer 2

Ports

P80, P81

P90 to P915

P70 to P715

PCD0 to PCD3

Watch timer

IETX0

IERX0

IEBus

CAN0
CAN1

Note 3

Note 4

,

Notes 1. 384/512/640/768/1024 KB (flash memory) (see Table 1-1)

2. 32/40/48/60 KB (see Ta ble 1-1)

3. CAN controller version only

4. CAN controller (2-channel) version only

P50 to P55

P40 to P42

P30 to P39

P60 to P615

ANI0 to ANI15
AV

SS

AVREF0
ADTRG

AVREF1
ANO0, ANO1

KR0 to KR7

Note 3

CTXD0

Note 3

CRXD0

P10, P11

P00 to P06

, CTXD1
, CRXD1

Internal

oscillator

Note 4

Note 4

CLM

Regulator

On-chip

debug

function

CG

PLL

LVI

CLKOUT

XT1

XT2
X1
X2

RESET

VDD

VSS

REGC

FLMD0

FLMD1

BVDD

BVSS

EVDD

EVSS

DRST

DMS

DDI

DCK

DDO

User’s Manual U17790EJ3V1UD

29

CHAPTER 1 INTRODUCTION

1.6.2 Internal units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic

logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32

bits) contribute to faster complex processing.

(2) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an

instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the

BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is

stored in an instruction queue.

(3) ROM

This is a 1024/768/640/512/384 KB flash memory mapped to addresses 0000000H to 00FFFFFH/0000000H to

00BFFFFH/0000000H to 009FFFFH//0000000H to 007FFFFH/0000000H to 005FFFFH. It can be accessed

from the CPU in one clock during instruction fetch.

(4) RAM

This is a 60/48/40/32 KB RAM mapped to addresses 3FF0000H to 3FFEFFFH/3FF3000H to

3FFEFFFH/3FF5000H to 3FFEFFFH /3FF7000H to 3FFEFFFH. It can be accessed from the CPU in one

clock during data access.

(5) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP8) from on-chip peripheral hardware

and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and

multiple servicing control can be performed.

(6) Clock generator (CG)

A main clock oscillator that generates the main clock oscillation frequency (f

generates the subclock oscillation frequency (f

XT) are available. As the main clock frequency (fXX), fX is used as

X) and a subclock oscillator that

is in the clock-through mode and is multiplied by four or eight in the PLL mode.

The CPU clock frequency (f

CPU) can be selected from seven types: fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.

(7) Internal oscillator

An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP.). An internal oscillator

supplies the clock for watchdog timer 2 and timer M.

(8) Timer/counter

Nine-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-

channel 16-bit interval timer M (TMM) are provided on chip.

(9) Watch timer

This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or

the 32.768 kHz f

BRG from prescaler 3). The watch timer can also be used as an interval timer for the main

clock.

30

User’s Manual U17790EJ3V1UD