User’s Manual
V850ES/JG2
32-bit Single-Chip Microcontrollers
Hardware
μ
PD70F3715
μ
PD70F3716
μ
PD70F3717
μ
PD70F3718
μ
PD70F3719
Document No. U17715EJ2V0UD00 (2nd edition)
Date Published January 2007 N CP(K)
Printed in Japan
2005
[MEMO]
2
User’s Manual U17715EJ2V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17715EJ2V0UD
3
IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in
the United States of America.
EEPROM is a trademark of NEC Electronics Corporation
Applilet is a registered trademark of NEC Electronics in Japan, Germany, Hong Kong, China, the Republic of
Korea, the United Kingdom, and the United States of America.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.
4
User’s Manual U17715EJ2V0UD
•
The information in this document is current as of August, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
User’s Manual U17715EJ2V0UD
5
PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/JG2 and design application systems using these products.
Purpose This manual is intended to give users an understanding of the hardware functions of
the V850ES/JG2 shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User’s Manual).
Hardware Architecture
• Pin functions • Data types
• CPU function • Register set
• On-chip peripheral functions • Instruction format and instruction set
• Flash memory programming • Interrupts and exceptions
• Electrical specifications • Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/JG2
→ Read this manual according to the CONTENTS.
To find the details of a register where the name is known
→ Use APPENDIX B REGISTER INDEX.
Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/JG2
→ See CHAPTER 28 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched
by copying an “<R>” in the PDF file and specifying it in the “Find what:” field.
6
User’s Manual U17715EJ2V0UD
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on
the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2 (address space, memory capacity):
K (kilo): 2
M (mega): 2
G (giga): 2
10
= 1,024
20
= 1,0242
30
= 1,0243
User’s Manual U17715EJ2V0UD
7
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/JG2
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/JG2 Hardware User’s Manual This manual
Documents related to development tools
Document Name Document No.
QB-V850ESSX2 In-Circuit Emulator U17091E
QB-V850MINI On-Chip Debug Emulator U17638E
QB-MINI2 On-Chip Debug Emulator with Flash Programming Function To be prepared
CA850 Ver. 3.00 C Compiler Package
PM+ Ver. 6.20 Project Manager U17990E
ID850QB Ver. 3.20 Integrated Debugger Operation U17964E
SM850 Ver. 2.50 System Simulator Operation U16218E
SM850 Ver. 2.00 or Later System Simulator External Part User Open
RX850 Ver. 3.20 Real-Time OS
RX850 Pro Ver. 3.20 Real-Time OS
AZ850 Ver. 3.30 System Performance Analyzer U17423E
PG-FP4 Flash Memory Programmer U15260E
Operation U17293E
C Language U17291E
Assembly Language U17292E
Link Directives U17294E
U14873E
Interface Specification
Operation U17246E SM+ System Simulator
User Open Interface U17247E
Basics U13430E
Installation U17419E
Technical U13431E
Task Debugger U17420E
Basics U13773E
Installation U17421E
Technical U13772E
Task Debugger U17422E
8
User’s Manual U17715EJ2V0UD
CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................18
1.1 General .....................................................................................................................................18
1.2 Features....................................................................................................................................21
1.3 Application Fields ...................................................................................................................22
1.4 Ordering Information ..............................................................................................................22
1.5 Pin Configuration (Top View).................................................................................................23
1.6 Function Block Configuration................................................................................................ 26
1.6.1 Internal block diagram ............................................................................................................... 26
1.6.2 Internal units .............................................................................................................................. 27
CHAPTER 2 PIN FUNCTIONS................................................................................................................30
2.1 List of Pin Functions...............................................................................................................30
2.2 Pin States .................................................................................................................................40
2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins........41
2.4 Cautions ...................................................................................................................................45
CHAPTER 3 CPU FUNCTION.................................................................................................................46
3.1 Features....................................................................................................................................46
3.2 CPU Register Set.....................................................................................................................47
3.2.1 Program register set .................................................................................................................. 48
3.2.2 System register set .................................................................................................................... 49
3.3 Operation Modes .....................................................................................................................55
3.3.1 Specifying operation mode ........................................................................................................55
3.4 Address Space ........................................................................................................................56
3.4.1 CPU address space................................................................................................................... 56
3.4.2 Wraparound of CPU address space .......................................................................................... 57
3.4.3 Memory map.............................................................................................................................. 58
3.4.4 Areas .........................................................................................................................................60
3.4.5 Recommended use of address space ....................................................................................... 67
3.4.6 Peripheral I/O registers.............................................................................................................. 70
3.4.7 Special registers ........................................................................................................................ 80
3.4.8 Cautions .................................................................................................................................... 84
CHAPTER 4 PORT FUNCTIONS............................................................................................................88
4.1 Features....................................................................................................................................88
4.2 Basic Port Configuration ........................................................................................................88
4.3 Port Configuration................................................................................................................... 89
4.3.1 Port 0 ......................................................................................................................................... 94
4.3.2 Port 1 ......................................................................................................................................... 97
4.3.3 Port 3 ......................................................................................................................................... 98
4.3.4 Port 4 ....................................................................................................................................... 104
4.3.5 Port 5 ....................................................................................................................................... 106
4.3.6 Port 7 ....................................................................................................................................... 110
4.3.7 Port 9 ....................................................................................................................................... 112
4.3.8 Port CM ................................................................................................................................... 120
4.3.9 Port CT ....................................................................................................................................122
User’s Manual U17715EJ2V0UD
9
4.3.10 Port DH....................................................................................................................................124
4.3.11 Port DL ....................................................................................................................................126
4.4 Block Diagrams..................................................................................................................... 129
4.5 Port Register Settings When Alternate Function Is Used ................................................ 159
4.6 Cautions ................................................................................................................................ 167
4.6.1 Cautions on setting port pins ................................................................................................... 167
4.6.2 Cautions on bit manipulation instruction for port n register (Pn)............................................... 170
4.6.3 Cautions on on-chip debug pins............................................................................................... 171
4.6.4 Cautions on P05/INTP2/DRST pin...........................................................................................171
4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ...............................................171
4.6.6 Hysteresis characteristics ........................................................................................................171
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 172
5.1 Features................................................................................................................................. 172
5.2 Bus Control Pins................................................................................................................... 173
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ............... 173
5.2.2 Pin status in each operation mode ........................................................................................... 173
5.3 Memory Block Function....................................................................................................... 174
5.4 External Bus Interface Mode Control Function................................................................. 175
5.5 Bus Access ........................................................................................................................... 176
5.5.1 Number of clocks for access .................................................................................................... 176
5.5.2 Bus size setting function ..........................................................................................................176
5.5.3 Access by bus size ..................................................................................................................177
5.6 Wait Function ........................................................................................................................ 184
5.6.1 Programmable wait function ....................................................................................................184
5.6.2 External wait function ............................................................................................................... 185
5.6.3 Relationship between programmable wait and external wait ...................................................186
5.6.4 Programmable address wait function ....................................................................................... 187
5.7 Idle State Insertion Function ............................................................................................... 188
5.8 Bus Hold Function................................................................................................................ 189
5.8.1 Functional outline.....................................................................................................................189
5.8.2 Bus hold procedure.................................................................................................................. 190
5.8.3 Operation in power save mode ................................................................................................190
5.9 Bus Priority ........................................................................................................................... 191
5.10 Bus Timing ............................................................................................................................ 192
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 198
6.1 Overview................................................................................................................................ 198
6.2 Configuration ........................................................................................................................ 199
6.3 Registers ............................................................................................................................... 201
6.4 Operation............................................................................................................................... 206
6.4.1 Operation of each clock ...........................................................................................................206
6.4.2 Clock output function ...............................................................................................................206
6.5 PLL Function......................................................................................................................... 207
6.5.1 Overview .................................................................................................................................. 207
6.5.2 Registers.................................................................................................................................. 207
6.5.3 Usage ......................................................................................................................................210
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 211
10
User’s Manual U17715EJ2V0UD
7.1
Overview.................................................................................................................................211
7.2 Functions ...............................................................................................................................211
7.3 Configuration.........................................................................................................................212
7.4 Registers ................................................................................................................................214
7.5 Operation................................................................................................................................226
7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ............................................................. 227
7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ................................................. 237
7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..................................... 245
7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 257
7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 264
7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 273
7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 290
7.5.8 Timer output operations........................................................................................................... 296
7.6 Selector Function ..................................................................................................................297
7.7 Cautions .................................................................................................................................298
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................299
8.1 Overview.................................................................................................................................299
8.2 Functions ...............................................................................................................................299
8.3 Configuration.........................................................................................................................300
8.4 Registers ................................................................................................................................302
8.5 Operation................................................................................................................................318
8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) ............................................................ 319
8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ................................................ 328
8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .................................... 337
8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) ............................................. 350
8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) .............................................................359
8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) ................................................... 370
8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................ 390
8.5.8 Timer output operations........................................................................................................... 396
8.6 Cautions .................................................................................................................................397
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................398
9.1 Overview.................................................................................................................................398
9.2 Configuration.........................................................................................................................399
9.3 Register ..................................................................................................................................400
9.4 Operation................................................................................................................................401
9.4.1 Interval timer mode .................................................................................................................. 401
9.4.2 Cautions .................................................................................................................................. 405
CHAPTER 10 WATCH TIMER FUNCTIONS .......................................................................................406
10.1 Functions ...............................................................................................................................406
10.2 Configuration.........................................................................................................................407
10.3 Control Registers ..................................................................................................................409
10.4 Operation................................................................................................................................413
10.4.1 Operation as watch timer......................................................................................................... 413
10.4.2 Operation as interval timer....................................................................................................... 414
10.4.3 Cautions ..................................................................................................................................415
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2....................................................................416
User’s Manual U17715EJ2V0UD
11
11.1
Functions............................................................................................................................... 416
11.2 Configuration ........................................................................................................................ 417
11.3 Registers ............................................................................................................................... 418
11.4 Operation............................................................................................................................... 420
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 421
12.1 Function................................................................................................................................. 421
12.2 Configuration ........................................................................................................................ 422
12.3 Registers ............................................................................................................................... 424
12.4 Operation............................................................................................................................... 426
12.5 Usage ..................................................................................................................................... 427
12.6 Cautions ................................................................................................................................ 427
CHAPTER 13 A/D CONVERTER ......................................................................................................... 428
13.1 Overview................................................................................................................................ 428
13.2 Functions............................................................................................................................... 428
13.3 Configuration ........................................................................................................................ 429
13.4 Registers ............................................................................................................................... 432
13.5 Operation............................................................................................................................... 443
13.5.1 Basic operation ........................................................................................................................ 443
13.5.2 Conversion operation timing ....................................................................................................444
13.5.3 Trigger mode ...........................................................................................................................445
13.5.4 Operation mode ....................................................................................................................... 447
13.5.5 Power-fail compare mode ........................................................................................................ 451
13.6 Cautions ................................................................................................................................ 456
13.7 How to Read A/D Converter Characteristics Table........................................................... 460
CHAPTER 14 D/A CONVERTER ......................................................................................................... 464
14.1 Functions............................................................................................................................... 464
14.2 Configuration ........................................................................................................................ 464
14.3 Registers ............................................................................................................................... 465
14.4 Operation............................................................................................................................... 467
14.4.1 Operation in normal mode .......................................................................................................467
14.4.2 Operation in real-time output mode..........................................................................................467
14.4.3 Cautions...................................................................................................................................468
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 469
15.1 Mode Switching of UARTA and Other Serial Interfaces ................................................... 469
15.1.1 CSIB4 and UARTA0 mode switching....................................................................................... 469
15.1.2 UARTA2 and I2C00 mode switching.........................................................................................470
15.1.3 UARTA1 and I2C02 mode switching.........................................................................................471
15.2 Features................................................................................................................................. 472
15.3 Configuration ........................................................................................................................ 473
15.4 Registers ............................................................................................................................... 475
15.5 Interrupt Request Signals.................................................................................................... 481
15.6 Operation............................................................................................................................... 482
15.6.1 Data format..............................................................................................................................482
15.6.2 SBF transmission/reception format..........................................................................................484
15.6.3 SBF transmission.....................................................................................................................486
12
User’s Manual U17715EJ2V0UD
15.6.4 SBF reception.......................................................................................................................... 487
15.6.5 UART transmission.................................................................................................................. 488
15.6.6 Continuous transmission procedure ........................................................................................489
15.6.7 UART reception....................................................................................................................... 491
15.6.8 Reception errors ...................................................................................................................... 492
15.6.9 Parity types and operations ..................................................................................................... 494
15.6.10 Receive data noise filter ..........................................................................................................495
15.7 Dedicated Baud Rate Generator .......................................................................................... 496
15.8 Cautions .................................................................................................................................504
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................505
16.1 Mode Switching of CSIB and Other Serial Interfaces........................................................ 505
16.1.1 CSIB4 and UARTA0 mode switching ...................................................................................... 505
16.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 506
16.2 Features..................................................................................................................................507
16.3 Configuration.........................................................................................................................508
16.4 Registers ................................................................................................................................510
16.5 Interrupt Request Signals.....................................................................................................517
16.6 Operation................................................................................................................................518
16.6.1 Single transfer mode (master mode, transmission mode) .......................................................518
16.6.2 Single transfer mode (master mode, reception mode)............................................................. 520
16.6.3 Single transfer mode (master mode, transmission/reception mode)........................................ 522
16.6.4 Single transfer mode (slave mode, transmission mode).......................................................... 524
16.6.5 Single transfer mode (slave mode, reception mode) ...............................................................526
16.6.6 Single transfer mode (slave mode, transmission/reception mode) ..........................................528
16.6.7 Continuous transfer mode (master mode, transmission mode) ............................................... 530
16.6.8 Continuous transfer mode (master mode, reception mode)..................................................... 532
16.6.9 Continuous transfer mode (master mode, transmission/reception mode)................................ 535
16.6.10 Continuous transfer mode (slave mode, transmission mode).................................................. 539
16.6.11 Continuous transfer mode (slave mode, reception mode) ....................................................... 541
16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .................................. 544
16.6.13 Reception error........................................................................................................................ 548
16.6.14 Clock timing............................................................................................................................. 549
16.7 Output Pins ............................................................................................................................551
16.8 Baud Rate Generator ............................................................................................................552
16.8.1 Baud rate generation ............................................................................................................... 553
16.9 Cautions .................................................................................................................................554
CHAPTER 17 I2C BUS...........................................................................................................................555
17.1 Mode Switching of I2C Bus and Other Serial Interfaces ....................................................555
17.1.1 UARTA2 and I2C00 mode switching ........................................................................................555
17.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 556
17.1.3 UARTA1 and I2C02 mode switching ........................................................................................557
17.2 Features..................................................................................................................................558
17.3 Configuration.........................................................................................................................559
17.4 Registers ................................................................................................................................563
17.5 I2C Bus Mode Functions .......................................................................................................579
17.5.1 Pin configuration...................................................................................................................... 579
17.6 I2C Bus Definitions and Control Methods ...........................................................................580
17.6.1 Start condition.......................................................................................................................... 580
User’s Manual U17715EJ2V0UD
13
17.6.2 Addresses................................................................................................................................ 581
17.6.3 Transfer direction specification ................................................................................................582
17.6.4 ACK .........................................................................................................................................583
17.6.5 Stop condition .......................................................................................................................... 584
17.6.6 Wait state................................................................................................................................. 585
17.6.7 Wait state cancellation method ................................................................................................ 587
17.7 I2C Interrupt Request Signals (INTIICn) .............................................................................. 588
17.7.1 Master device operation...........................................................................................................588
17.7.2 Slave device operation (when receiving slave address data (address match))........................ 591
17.7.3 Slave device operation (when receiving extension code) ........................................................595
17.7.4 Operation without communication............................................................................................ 599
17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................599
17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................601
17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 608
17.9 Address Match Detection Method ...................................................................................... 610
17.10 Error Detection...................................................................................................................... 610
17.11 Extension Code..................................................................................................................... 610
17.12 Arbitration ............................................................................................................................. 611
17.13 Wakeup Function.................................................................................................................. 612
17.14 Communication Reservation............................................................................................... 613
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................613
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................617
17.15 Cautions ................................................................................................................................ 618
17.16 Communication Operations................................................................................................. 619
17.16.1 Master operation in single master system ................................................................................620
17.16.2 Master operation in multimaster system ...................................................................................621
17.16.3 Slave operation........................................................................................................................624
17.17 Timing of Data Communication .......................................................................................... 627
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 634
18.1 Features................................................................................................................................. 634
18.2 Configuration ........................................................................................................................ 635
18.3 Registers ............................................................................................................................... 636
18.4 Transfer Targets ................................................................................................................... 643
18.5 Transfer Modes..................................................................................................................... 643
18.6 Transfer Types...................................................................................................................... 644
18.7 DMA Channel Priorities........................................................................................................ 645
18.8 Time Related to DMA Transfer ............................................................................................ 645
18.9 DMA Transfer Start Factors................................................................................................. 646
18.10 DMA Abort Factors ............................................................................................................... 647
18.11 End of DMA Transfer ............................................................................................................ 647
18.12 Operation Timing .................................................................................................................. 647
18.13 Cautions ................................................................................................................................ 652
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 657
19.1 Features................................................................................................................................. 657
19.2 Non-Maskable Interrupts ..................................................................................................... 661
19.2.1 Operation................................................................................................................................. 663
19.2.2 Restore ....................................................................................................................................664
19.2.3 NP flag.....................................................................................................................................665
14
User’s Manual U17715EJ2V0UD
19.3
Maskable Interrupts ..............................................................................................................666
19.3.1 Operation................................................................................................................................. 666
19.3.2 Restore.................................................................................................................................... 668
19.3.3 Priorities of maskable interrupts ..............................................................................................669
19.3.4 Interrupt control register (xxICn) .............................................................................................. 673
19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................ 675
19.3.6 In-service priority register (ISPR)............................................................................................. 677
19.3.7 ID flag ...................................................................................................................................... 678
19.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................678
19.4 Software Exception...............................................................................................................679
19.4.1 Operation................................................................................................................................. 679
19.4.2 Restore.................................................................................................................................... 680
19.4.3 EP flag..................................................................................................................................... 681
19.5 Exception Trap ......................................................................................................................682
19.5.1 Illegal opcode .......................................................................................................................... 682
19.5.2 Debug trap............................................................................................................................... 684
19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) .................................... 686
19.6.1 Noise elimination ..................................................................................................................... 686
19.6.2 Edge detection......................................................................................................................... 686
19.7 Interrupt Acknowledge Time of CPU...................................................................................691
19.8 Periods in Which Interrupts Are Not Acknowledged by CPU...........................................692
19.9 Cautions .................................................................................................................................692
CHAPTER 20 KEY INTERRUPT FUNCTION ......................................................................................693
20.1 Function .................................................................................................................................693
20.2 Register ..................................................................................................................................694
20.3 Cautions .................................................................................................................................694
CHAPTER 21 STANDBY FUNCTION................................................................................................... 695
21.1 Overview.................................................................................................................................695
21.2 Registers ................................................................................................................................697
21.3 HALT Mode.............................................................................................................................700
21.3.1 Setting and operation status .................................................................................................... 700
21.3.2 Releasing HALT mode ............................................................................................................ 700
21.4 IDLE1 Mode............................................................................................................................702
21.4.1 Setting and operation status .................................................................................................... 702
21.4.2 Releasing IDLE1 mode............................................................................................................ 702
21.5 IDLE2 Mode............................................................................................................................704
21.5.1 Setting and operation status .................................................................................................... 704
21.5.2 Releasing IDLE2 mode............................................................................................................ 704
21.5.3 Securing setup time when releasing IDLE2 mode ................................................................... 706
21.6 STOP Mode ............................................................................................................................707
21.6.1 Setting and operation status .................................................................................................... 707
21.6.2 Releasing STOP mode............................................................................................................ 707
21.6.3 Securing oscillation stabilization time when releasing STOP mode......................................... 710
21.7 Subclock Operation Mode....................................................................................................711
21.7.1 Setting and operation status .................................................................................................... 711
21.7.2 Releasing subclock operation mode........................................................................................ 711
21.8 Sub-IDLE Mode......................................................................................................................713
21.8.1 Setting and operation status .................................................................................................... 713
User’s Manual U17715EJ2V0UD
15
21.8.2 Releasing sub-IDLE mode ....................................................................................................... 713
CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 715
22.1 Overview................................................................................................................................ 715
22.2 Registers to Check Reset Source....................................................................................... 716
22.3 Operation............................................................................................................................... 717
22.3.1 Reset operation via RESET pin ...............................................................................................717
22.3.2 Reset operation by watchdog timer 2.......................................................................................719
22.3.3 Reset operation by low-voltage detector..................................................................................721
22.3.4 Operation after reset release ...................................................................................................722
22.3.5 Reset function operation flow................................................................................................... 725
CHAPTER 23 CLOCK MONITOR ........................................................................................................ 726
23.1 Functions............................................................................................................................... 726
23.2 Configuration ........................................................................................................................ 726
23.3 Register ................................................................................................................................. 727
23.4 Operation............................................................................................................................... 728
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) ............................................................................. 731
24.1 Functions............................................................................................................................... 731
24.2 Configuration ........................................................................................................................ 731
24.3 Registers ............................................................................................................................... 732
24.4 Operation............................................................................................................................... 734
24.4.1 To use for internal reset signal.................................................................................................734
24.4.2 To use for interrupt ..................................................................................................................735
24.5 RAM Retention Voltage Detection Operation .................................................................... 736
24.6 Emulation Function .............................................................................................................. 737
CHAPTER 25 REGULATOR ................................................................................................................. 738
25.1 Outline 738
25.2 Operation............................................................................................................................... 739
CHAPTER 26 FLASH MEMORY.......................................................................................................... 740
26.1 Features................................................................................................................................. 740
26.2 Memory Configuration ......................................................................................................... 741
26.3 Functional Outline ................................................................................................................ 742
26.4 Rewriting by Dedicated Flash Programmer....................................................................... 745
26.4.1 Programming environment....................................................................................................... 745
26.4.2 Communication mode..............................................................................................................746
26.4.3 Flash memory control ..............................................................................................................754
26.4.4 Selection of communication mode ...........................................................................................755
26.4.5 Communication commands .....................................................................................................756
26.4.6 Pin connection .........................................................................................................................757
26.5 Rewriting by Self Programming.......................................................................................... 761
26.5.1 Overview.................................................................................................................................. 761
26.5.2 Features...................................................................................................................................762
26.5.3 Standard self programming flow ..............................................................................................763
26.5.4 Flash functions.........................................................................................................................764
26.5.5 Pin processing .........................................................................................................................764
16
User’s Manual U17715EJ2V0UD
26.5.6 Internal resources used ........................................................................................................... 765
CHAPTER 27 ON-CHIP DEBUG FUNCTION......................................................................................766
27.1 Debugging with DCU.............................................................................................................767
27.1.1 Connection circuit example ........................................................................................................767
27.1.2 Interface signals .........................................................................................................................767
27.1.3 Maskable functions..................................................................................................................... 769
27.1.4 Register...................................................................................................................................... 769
27.1.5 Operation ................................................................................................................................... 771
27.1.6 Cautions ..................................................................................................................................... 771
27.2 Debugging Without Using DCU ...........................................................................................773
27.2.1 Circuit connection examples ...................................................................................................... 773
27.2.2 Maskable functions..................................................................................................................... 774
27.2.3 Securement of user resources ...................................................................................................775
27.2.4 Cautions ..................................................................................................................................... 781
27.3 ROM Security Function...........................................................................................................783
27.3.1 Security ID.................................................................................................................................. 783
27.3.2 Setting........................................................................................................................................ 784
CHAPTER 28 ELECTRICAL SPECIFICATIONS..................................................................................786
CHAPTER 29 PACKAGE DRAWINGS................................................................................................. 821
<R>
<R>
<R>
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS ...........................................................823
APPENDIX A DEVELOPMENT TOOLS ...............................................................................................824
A.1 Software Package..................................................................................................................826
A.2 Language Processing Software...........................................................................................826
A.3 Control Software ...................................................................................................................826
A.4 Debugging Tools (Hardware) ...............................................................................................827
A.4.1 When using IECUBE QB-V850ESSX2 .................................................................................... 827
A.4.2 When using MINICUBE QB-V850MINI .................................................................................... 830
A.4.3 When using MINICUBE2 QB-MINI2 ........................................................................................831
A.5 Debugging Tools (Software) ................................................................................................ 832
A.6 Embedded Software..............................................................................................................833
A.7 Flash Memory Writing Tools ................................................................................................834
APPENDIX B REGISTER INDEX ..........................................................................................................835
APPENDIX C INSTRUCTION SET LIST..............................................................................................845
C.1 Conventions........................................................................................................................... 845
C.2 Instruction Set (in Alphabetical Order) ...............................................................................848
APPENDIX D LIST OF CAUTIONS......................................................................................................855
<R>
APPENDIX E REVISION HISTORY ......................................................................................................891
E.1 Major Revisions in This Edition...............................................................................................891
User’s Manual U17715EJ2V0UD
17
CHAPTER 1 INTRODUCTION
The V850ES/JG2 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low-
power operation for real-time control applications.
1.1 General
The V850ES/JG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral
functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG2 features
multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware
multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the
V850ES/JG2 enables an extremely high cost-performance for applications that require low power consumption, such
as home audio, printers, and digital home electronics.
Table 1-1 lists the products of the V850ES/JG2.
A model of the V850ES/JG2 with expanded I/O, timer/counter, and serial interface functions, V850ES/JJ2, is also
available. See Table 1-2 V850ES/JJ2 Product List.
18
User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
Table 1-1. V850ES/JG2 Product List
Part Number
Internal
memory
Memory
space
Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB
RAM 12 KB 24 KB 32 KB 40 KB 48 KB
Logical space 64 MB
External memory area 16 MB
External bus interface
μ
PD70F3715
Address bus: 22 bits
μ
PD70F3716
μ
PD70F3717
μ
PD70F3718
μ
PD70F3719
Data bus: 8/16 bits
Multiplex bus mode/separate bus mode
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Ceramic/crystal/external clock
(in PLL mode: f
in clock through mode: f
X = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8),
X = 2.5 to 10 MHz)
Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz)
Internal oscillator fR = 200 kHz (TYP.)
Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz)
DSP function
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O port I/O: 84 (5 V tolerant/N-ch open-drain output selectable: 40)
Timer
16-bit timer/event counter P: 6 channels
16-bit timer/event counter Q: 1 channel
16-bit interval timer M: 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
Real-time output port 6 bits × 1 channel
A/D converter 10-bit resolution × 12 channels
D/A converter 8-bit resolution × 2 channels
Serial interface
UART/CSI: 1 channel
2
UART/ I
C bus: 2 channels
CSI: 3 channels
2
C bus: 1 channel
CSI/I
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source External: 9 (9)
Note
, internal: 48
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-DLE mode
Reset RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
DCU Provided (RUN/break)
Operating power supply voltage 2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
100-pin plastic LQFP (fine pitch) (14 × 14 mm) Package
100-pin plastic QFP (14 × 20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
User’s Manual U17715EJ2V0UD
19
CHAPTER 1 INTRODUCTION
Table 1-2. V850ES/JJ2 Product List
Part Number
Internal
memory
Memory
space
Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB
RAM 12 KB 24 KB 32 KB 40 KB 48 KB
Logical space 64 MB
External memory area 16 MB
External bus interface
μ
PD70F3720
Address bus: 24 bits
μ
PD70F3721
μ
PD70F3722
μ
PD70F3723
μ
PD70F3724
Data bus: 8/16 bits
Multiplex bus mode/separate bus mode
Chip select signal: 4
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Ceramic/crystal/external clock
(in PLL mode: f
in clock through mode: f
X = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8),
X = 2.5 to 10 MHz)
Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz)
Internal oscillator fR = 200 kHz (TYP.)
Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz)
DSP function
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O port I/O: 128 (5 V tolerant/N-ch open-drain output selectable: 60)
Timer
16-bit timer/event counter P: 9 channels
16-bit timer/event counter Q: 1 channel
16-bit interval timer M: 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
Real-time output port 6 bits × 2 channels
A/D converter 10-bit resolution × 16 channels
D/A converter 8-bit resolution × 2 channels
Serial interface
UART: 1 channel
UART/CSI: 1 channel
2
UART/ I
C bus: 2 channels
CSI: 4 channels
2
C bus: 1 channel
CSI/I
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source External: 10 (10)
Note
, internal: 61
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
DCU Provided (RUN/break)
Operating power supply voltage 2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
Package 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
20
User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
1.2 Features
{ Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz)
{ General-purpose registers: 32 bits × 32 registers
{ CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space: 64 MB of linear address space (for programs and data)
External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
• Internal memory: RAM: 12/24/32/40/48 KB (see Table 1-1)
Flash memory: 128/256/384/512/640 KB (see Table 1-1)
• External bus interface: Separate bus/multiplexed bus output selectable
8/16 bit data bus sizing function
Wait function
• Programmable wait function
• External wait function
Idle state function
Bus hold function
{ Interrupts and exceptions: Non-maskable interrupts: 2 sources
Maskable interrupts: 55 sources
Software exceptions: 32 sources
Exception trap: 2 sources
{ I/O lines: I/O ports: 84
{ Timer function: 16-bit interval timer M (TMM): 1 channel
16-bit timer/event counter P (TMP): 6 channels
16-bit timer/event counter Q (TMQ): 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
{ Real-time output port: 6 bits × 1 channel
{ Serial interface: Asynchronous serial interface A (UARTA)
3-wire variable-length serial interface B (CSIB)
I
UARTA/CSIB: 1 channel
UARTA/I
CSIB/I
CSIB: 3 channels
{ A/D converter: 10-bit resolution: 12 channels
{ D/A converter: 8-bit resolution: 2 channels
{ DMA controller: 4 channels
{ DCU (debug control unit): JTAG interface
{ Clock generator: During main clock or subclock operation
7-level CPU clock (f
Clock-through mode/PLL mode selectable
2
C bus interface (I2C)
2
C: 2 channels
2
C: 1 channel
XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
User’s Manual U17715EJ2V0UD
21
CHAPTER 1 INTRODUCTION
{ Internal oscillation clock: 200 kHz (TYP.)
{ Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ Package: 100-pin plastic QFP (14 × 20) (
100-pin plastic LQFP (fine pitch) (14 × 14)
μ
PD70F3715, 70F3716, 70F3717 only)
1.3 Application Fields
Home audio, printers, digital home electronics, other consumer devices
1.4 Ordering Information
Part Number Package Internal Flash Memory
μ
PD70F3715GF-JBT-A
μ
PD70F3715GC-8EA-A
μ
PD70F3716GF-JBT-A
μ
PD70F3716GC-8EA-A
μ
PD70F3717GF-JBT-A
μ
PD70F3717GC-8EA-A
μ
PD70F3718GC-8EA-A
μ
PD70F3719GC-8EA-A
Remark Products with -A at the end of the part number are lead-free products.
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
128 KB
128 KB
256 KB
256 KB
384 KB
384 KB
512 KB
640 KB
22
User’s Manual U17715EJ2V0UD
1.5 Pin Configuration (Top View)
100-pin plastic QFP (14 × 20)
μ
PD70F3715GF-JBT-A
μ
CHAPTER 1 INTRODUCTION
PD70F3716GF-JBT-A
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDH1/A17
PDH0/A16
PDL15/AD15
PDL14/AD14
99989796959493929190898887868584838281
100
μ
PD70F3717GF-JBT-A
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
P71/ANI1
P70/ANI0
AV
REF0
AVSS
P10/ANO0
P11/ANO1
AV
REF1
PDH4/A20
PDH5/A21
Note 1
FLMD0
VDD
Note 2
REGC
VSS
X1
X2
RESET
XT1
XT2
P03/INTP0/ADTRG
P41/SOB0/SCL01
P30/TXDA0/SOB4
P32/ASCKA0/SCKB4/TIP00/TOP00
P31/RXDA0/INTP7/SIB4
P33/TIP01/TOP01
P02/NMI
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/SDA01
P42/SCKB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
SS
P36
P37
EV
EVDD
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BV
DD
BVSS
PCT6/ASTB
PCT4/RD
PCT1/WR1
PCT0/WR0
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PDH3/A19
PDH2/A18
P915/A15/INTP6/TIP50/TOP50
P914/A14/INTP5/TIP51/TOP51
P913/A13/INTP4
P912/A12/SCKB3
P911/A11/SOB3
P910/A10/SIB3
P99/A9/SCKB1
P98/A8/SOB1
P97/A7/SIB1/TIP20/TOP20
P96/A6/TIP21/TOP21
P34/TIP10/TOP10
P35/TIP11/TOP11
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to V
SS via a 4.7
User’s Manual U17715EJ2V0UD
P38/TXDA2/SDA00
P39/RXDA2/SCL00
P90/A0/KR6/TXDA1/SDA02
P54/SOB2/KR4/RTP04/DCK
P50/TIQ01/KR0/TOQ01/RTP00
P51/TIQ02/KR1/TOQ02/RTP01
μ
F capacitor.
P55/SCKB2/KR5/RTP05/DMS
P52/TIQ03/KR2/TOQ03/RTP02/DDI
P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO
P92/A2/TIP41/TOP41
P93/A3/TIP40/TOP40
P94/A4/TIP31/TOP31
P95/A5/TIP30/TOP30
P91/A1/KR7/RXDA1/SCL02
23
100-pin plastic LQFP (fine pitch) (14 × 14)
μ
PD70F3715GC-8EA-A
μ
PD70F3716GC-8EA-A
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
CHAPTER 1 INTRODUCTION
μ
PD70F3717GC-8EA-A
μ
PD70F3718GC-8EA-A
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDH1/A17
PDH0/A16
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
μ
PD70F3719GC-8EA-A
PDL8/AD8
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
AV
REF0
AV
P10/ANO0
P11/ANO1
AV
REF1
PDH4/A20
PDH5/A21
Note 1
FLMD0
V
Note 2
REGC
V
X1
X2
RESET
XT1
XT2
P03/INTP0/ADTRG
P41/SOB0/SCL01
P30/TXDA0/SOB4
P02/NMI
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/SDA01
P42/SCKB0
9998979695949392919089888786858483828180797877
100
1
SS
DD
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
SS
DD
P36
P37
EV
EV
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BV
DD
BV
SS
PCT6/ASTB
PCT4/RD
PCT1/WR1
PCT0/WR0
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PDH3/A19
PDH2/A18
P915/A15/INTP6/TIP50/TOP50
P914/A14/INTP5/TIP51/TOP51
P913/A13/INTP4
P912/A12/SCKB3
P911/A11/SOB3
P910/A10/SIB3
P99/A9/SCKB1
P98/A8/SOB1
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
P31/RXDA0/INTP7/SIB4
P32/ASCKA0/SCKB4/TIP00/TOP00
P38/TXDA2/SDA00
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to V
SS via a 4.7
24
User’s Manual U17715EJ2V0UD
P39/RXDA2/SCL00
P50/TIQ01/KR0/TOQ01/RTP00
μ
P54/SOB2/KR4/RTP04/DCK
P51/TIQ02/KR1/TOQ02/RTP01
P52/TIQ03/KR2/TOQ03/RTP02/DDI
P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO
F capacitor.
P92/A2/TIP41/TOP41
P93/A3/TIP40/TOP40
P90/A0/KR6/TXDA1/SDA02
P91/A1/KR7/RXDA1/SCL02
P55/SCKB2/KR5/RTP05/DMS
P94/A4/TIP31/TOP31
P95/A5/TIP30/TOP30
P96/A6/TIP21/TOP21
P97/A7/SIB1/TIP20/TOP20
Pin names
A0 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI11:
ANO0, ANO1:
ASCKA0:
ASTB:
AV
REF0, AVREF1:
AV
SS:
BVDD:
BV
SS:
CLKOUT:
DCK:
DDI:
DDO:
DMS:
DRST:
EV
DD:
EVSS:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
INTP0 to INTP7:
KR0 to KR7:
NMI:
P02 to P06:
P10, P11:
P30 to P39:
P40 to P42:
P50 to P55:
P70 to P711:
P90 to P915:
PCM0 to PCM3:
PCT0, PCT1,
PCT4, PCT6:
CHAPTER 1 INTRODUCTION
Address bus
Address/data bus
A/D trigger input
Analog input
Analog output
Asynchronous serial clock
Address strobe
Analog reference voltage
Analog V
SS
Power supply for bus interface
Ground for bus interface
Clock output
Debug clock
Debug data input
Debug data output
Debug mode select
Debug reset
Power supply for port
Ground for port
Flash programming mode
Hold acknowledge
Hold request
External interrupt input
Key return
Non-maskable interrupt request
Port 0
Port 1
Port 3
Port 4
Port 5
Port 7
Port 9
Port CM
Port CT
PDH0 to PDH5:
PDL0 to PDL15:
RD:
REGC:
RESET:
RTP00 to RTP05:
RXDA0 to RXDA2:
SCKB0 to SCKB4:
SCL00 to SCL02:
SDA00 to SDA02:
SIB0 to SIB4:
SOB0 to SOB4:
TIP00, TIP01,
TIP10, TIP11,
TIP20, TIP21,
TIP30, TIP31,
TIP40, TIP41,
TIP50, TIP51,
TIQ00 to TIQ03:
TOP00, TOP01,
TOP10, TOP11,
TOP20, TOP21,
TOP30, TOP31,
TOP40, TOP41,
TOP50, TOP51,
TOQ00 to TOQ03:
TXDA0 to TXDA2:
V
DD:
V
SS:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Port DH
Port DL
Read strobe
Regulator control
Reset
Real-time output port
Receive data
Serial clock
Serial clock
Serial data
Serial input
Serial output
Timer input
Timer output
Transmit data
Power supply
Ground
Wait
Lower byte write strobe
Upper byte write strobe
Crystal for main clock
Crystal for subclock
User’s Manual U17715EJ2V0UD
25
1.6 Function Block Configuration
1.6.1 Internal block diagram
NMI
INTP0 to INTP7
TIQ00 to TIQ03
TOQ00 to TOQ03
TIP00 to TIP50,
TIP01 to TIP51
TOP00 to TOP50,
TOP01 to TOP51
INTC
16-bit timer/
counter Q:
1 ch
16-bit timer/
counter P:
6 ch
16-bit interval
timer M:
1 ch
CHAPTER 1 INTRODUCTION
ROM
Note 1
RAM
Note 2
DMAC
PC
32-bit barrel
shifter
System
registers
General-purpose
registers 32 bits × 32
CPU
Multiplier
16 × 16 → 32
ALU
Instruction
queue
BCU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
A0 to A21
AD0 to AD15
RTP00 to RTP05
RTO
Ports
SOB0/SCL01
SIB0/SDA01
SCKB0
SOB1
SIB1
SCKB1
SOB2
SIB2
SCKB2
SOB3
SIB3
SCKB3
TXDA0/SOB4
RXDA0/SIB4
ASCKA0/SCKB4
TXDA1/SDA02
RXDA1/SCL02
TXDA2/SDA00
RXDA2/SCL00
CSIB0 I2C01
CSIB1
CSIB2
CSIB3
UARTA0
CSIB4
I2C02
UARTA1
I2C00
UARTA2
P50 to P55
P90 to P915
P70 to P711
PDH0 to PDH5
PCM0 to PCM3
PDL0 to PDL15
PCT0, PCT1, PCT4, PCT6
A/D
converter
D/A
converter
Key return
function
Watchdog
timer 2
Watch timer
Notes 1. 128/256/384/512/640 KB (flash memory) (see Table 1-1)
2. 12/24/32/40/48 KB (see Table 1-1)
P10, P11
P40 to P42
P30 to P39
P02 to P06
ANI0 to ANI11
AV
SS
AV
REF0
ADTRG
AV
REF1
ANO0, ANO1
KR0 to KR7
Internal
oscillator
CLM
DCU
CG
PLL
LVI
Regulator
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
FLMD0
FLMD1
DD
BV
BV
SS
EV
DD
EV
SS
DRST
DMS
DDI
DCK
DDO
26
User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
1.6.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits) contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue.
(3) ROM
This is a 640/512/384/256/128 KB flash memory mapped to addresses 0000000H to 009FFFFH/0000000H to
007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH/0000000H to 001FFFFH.
It can be accessed from the CPU in one clock during instruction fetch.
(4) RAM
This is a 48/40/32/24/12 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to
3FFEFFFH/3FF7000H to 3FFEFFFH/3FF9000H to 3FFEFFFH/3FFC000H to 3FFEFFFH. It can be accessed
from the CPU in one clock during data access.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiplexed servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency
(f
X) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as
the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4 or 8.
The CPU clock frequency (f
CPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-
channel 16-bit interval timer M (TMM), are provided on chip.
(9) Watch timer
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the
32.768 kHz clock f
BRG from prescaler 3). The watch timer can also be used as an interval timer for the main
clock.
User’s Manual U17715EJ2V0UD
27
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/JG2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire
variable-length serial interface B (CSIB), and an I
In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.
In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to
SCKB4 pins.
In the case of I
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
(12) A/D converter
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
(13) D/A converter
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
(14) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(15) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
(16) Real-time output function
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer
compare register match signal.
(17) DCU (debug control unit)
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is
provided. Switching between the normal port function and on-chip debugging function is done with the
control pin input level and the OCDM register.
CHAPTER 1 INTRODUCTION
2
C bus interface (I2C).
28
User’s Manual U17715EJ2V0UD
(18) Ports
CHAPTER 1 INTRODUCTION
The following general-purpose port functions and control pin functions are available.
Port I/O Alternate Function
P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset
P1 2-bit I/O D/A converter analog output
P3 10-bit I/O External interrupt, serial interface, timer I/O
P4 3-bit I/O Serial interface
P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O
P7 12-bit I/O A/D converter analog input
P9 16-bit I/O External address bus, serial interface, key interrupt input, timer I/O, external interrupt
PCM 4-bit I/O External control signal
PCT 4-bit I/O External control signal
PDH 6-bit I/O External address bus
PDL 16-bit I/O External address/data bus
User’s Manual U17715EJ2V0UD
29
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
The names and functions of the pins in the V850ES/JG2 are described below.
There are four types of pin I/O buffer power supplies: AV
these power supplies and the pins is described below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 Port 7
AVREF1 Port 1
BVDD Ports CM, CT, DH (bits 0 to 3), DL
EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5)
REF0, AVREF1, BVDD, and EVDD. The relationship between
30
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(1) Port pins
Pin No. Pin Name
GF GC
P02 19 17 NMI
P03 20 18 INTP0/ADTRG
P04 21 19 INTP1
Note
P05
22 20 INTP2/DRST
P06 23 21
P10 5 3 ANO0
P11 6 4
P30 27 25 TXDA0/SOB4
P31 28 26 RXDA0/INTP7/SIB4
P32 29 27 ASCKA0/SCKB4/TIP00/TOP00
P33 30 28 TIP01/TOP01
P34 31 29 TIP10/TOP10
P35 32 30 TIP11/TOP11
P36 33 31
P37 34 32
P38 37 35 TXDA2/SDA00
P39 38 36
P40 24 22 SIB0/SDA01
P41 25 23 SOB0/SCL01
P42 26 24
P50 39 37 TIQ01/KR0/TOQ01/RTP00
P51 40 38 TIQ02/KR1/TOQ02/RTP01
P52 41 39 TIQ03/KR2/TOQ03/RTP02/DDI
P53 42 40
P54 43 41 SOB2/KR4/RTP04/DCK
P55 44 42
I/O Function Alternate Function
I/O
I/O
I/O
I/O
I/O
Por t 0
5-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open-drain output can be specified in 1-bit units.
5 V tolerant.
Por t 1
2-bit I/O port
Input/output can be specified in 1-bit units.
Por t 3
10-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open-drain output can be specified in 1-bit units.
5 V tolerant.
Por t 4
3-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open-drain output can be specified in 1-bit units.
5 V tolerant.
Por t 5
6-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open-drain output can be specified in 1-bit units.
5 V tolerant.
INTP3
ANO1
−
−
RXDA2/SCL00
SCKB0
SIB2/KR3/TIQ00/TOQ00/RTP03/
DDO
SCKB2/KR5/RTP05/DMS
Note Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit to 0.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(1/3)
User’s Manual U17715EJ2V0UD
31
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
GF GC
P70 2 100 ANI0
P71 1 99 ANI1
P72 100 98 ANI2
P73 99 97 ANI3
P74 98 96 ANI4
P75 97 95 ANI5
P76 96 94 ANI6
P77 95 93 ANI7
P78 94 92 ANI8
P79 93 91 ANI9
P710 92 90 ANI10
P711 91 89
P90 45 43 A0/KR6/TXDA1/SDA02
P91 46 44 A1/KR7/RXDA1/SCL02
P92 47 45 A2/TIP41/TOP41
P93 48 46 A3/TIP40/TOP40
P94 49 47 A4/TIP31/TOP31
P95 50 48 A5/TIP30/TOP30
P96 51 49 A6/TIP21/TOP21
P97 52 50 A7/SIB1/TIP20/TOP20
P98 53 51 A8/SOB1
P99 54 52 A9/SCKB1
P910 55 53 A10/SIB3
P911 56 54 A11/SOB3
P912 57 55 A12/SCKB3
P913 58 56 A13/INTP4
P914 59 57 A14/INTP5/TIP51/TOP51
P915 60 58
PCM0 63 61 WAIT
PCM1 64 62 CLKOUT
PCM2 65 63 HLDAK
PCM3 66 64
PCT0 67 65 WR0
PCT1 68 66 WR1
PCT4 69 67 RD
PCT6 70 68
I/O Function Alternate Function
I/O
I/O
I/O
I/O
Por t 7
12-bit I/O port
Input/output can be specified in 1-bit units.
ANI11
Por t 9
16-bit I/O port
Input/output can be specified in 1-bit units.
N-ch open-drain output can be specified in 1-bit units.
5 V tolerant.
A15/INTP6/TIP50/TOP50
Por t CM
4-bit I/O port
Input/output can be specified in 1-bit units.
HLDRQ
Por t CT
4-bit I/O port
Input/output can be specified in 1-bit units.
ASTB
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(2/3)
32
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
GF GC
PDH0 89 87 A16
PDH1 90 88 A17
PDH2 61 59 A18
PDH3 62 60 A19
PDH4 8 6 A20
PDH5 9 7
PDL0 73 71 AD0
PDL1 74 72 AD1
PDL2 75 73 AD2
PDL3 76 74 AD3
PDL4 77 75 AD4
PDL5 78 76 AD5/FLMD1
PDL6 79 77 AD6
PDL7 80 78 AD7
PDL8 81 79 AD8
PDL9 82 80 AD9
PDL10 83 81 AD10
PDL11 84 82 AD11
PDL12 85 83 AD12
PDL13 86 84 AD13
PDL14 87 85 AD14
PDL15 88 86
I/O Function Alternate Function
I/O
I/O
Port DH
6-bit I/O port
Input/output can be specified in 1-bit units.
A21
Por t DL
16-bit I/O port
Input/output can be specified in 1-bit units.
AD15
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(3/3)
User’s Manual U17715EJ2V0UD
33
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin No. Pin Name
GF GC
A0 45 43 P90/KR6/TXDA1/SDA02
A1 46 44 P91/KR7/RXDA1/SCL02
A2 47 45 P92/TIP41/TOP41
A3 48 46 P93/TIP40/TOP40
A4 49 47 P94/TIP31/TOP31
A5 50 48 P95/TIP30/TOP30
A6 51 49 P96/TIP21/TOP21
A7 52 50 P97/SIB1/TIP20/TOP20
A8 53 51 P98/SOB1
A9 54 52 P99/SCKB1
A10 55 53 P910/SIB3
A11 56 54 P911/SOB3
A12 57 55 P912/SCKB3
A13 58 56 P913/INTP4
A14 59 57 P914/INTP5/TIP51/TOP51
A15 60 58
A16 89 87 PDH0
A17 90 88 PDH1
A18 61 59 PDH2
A19 62 60 PDH3
A20 8 6 PDH4
A21 9 7
AD0 73 71 PDL0
AD1 74 72 PDL1
AD2 75 73 PDL2
AD3 76 74 PDL3
AD4 77 75 PDL4
AD5 78 76 PDL5/FLMD1
AD6 79 77 PDL6
AD7 80 78 PDL7
AD8 81 79 PDL8
AD9 82 80 PDL9
AD10 83 81 PDL10
AD11 84 82 PDL11
AD12 85 83 PDL12
AD13 86 84 PDL13
AD14 87 85 PDL14
AD15 88 86
I/O Function Alternate Function
Output Address bus for external memory
(when using separate bus)
N-ch open-drain output selectable.
5 V tolerant.
P915/INTP6/TIP50/TOP50
Output Address bus for external memory
PDH5
I/O Address bus/data bus for external memory
PDL15
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(1/6)
34
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
GF GC
ADTRG 20 18 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0
ANI0 2 100 P70
ANI1 1 99 P71
ANI2 100 98 P72
ANI3 99 97 P73
ANI4 98 96 P74
ANI5 97 95 P75
ANI6 96 94 P76
ANI7 95 93 P77
ANI8 94 92 P78
ANI9 93 91 P79
ANI10 92 90 P710
ANI11 91 89
ANO0 5 3 P10
ANO1 6 4
ASCKA0 29 27 Input UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00
ASTB 70 68 Output Address strobe signal output for external memory PCT6
AVREF0 3 1 Reference voltage input for A/D converter/positive power
AVREF1 7 5 − Reference voltage input for D/A converter/positive power
AVSS 4 2 − Ground potential for A/D and D/A converters (same
BVDD 72 70 − Positive power supply pin for bus interface and alternate-
BVSS 71 69 − Ground potential for bus interface and alternate-function ports
CLKOUT 64 62 Output Internal system clock output PCM1
DCK 43 41 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04
DDI 41 39 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02
Note
DDO
42 40 Output Debug data output. N-ch open-drain output selectable.
DMS 44 42 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05
DRST 22 20 Input Debug reset input. 5 V tolerant. P05/INTP2
EVDD 36 34 − Positive power supply for external (same potential as VDD)
EVSS 35 33 − Ground potential for external (same potential as VSS)
FLMD0 10 8
FLMD1 78 76
HLDAK 65 63 Output Bus hold acknowledge output PCM2
HLDRQ 66 64 Input Bus hold request input PCM3
I/O Function Alternate Function
Input Analog voltage input for A/D converter
P711
Output Analog voltage output for D/A converter
P11
−
supply for port 7
−
supply for port 1
−
potential as V
function ports
5 V tolerant.
Input Flash memory programming mode setting pin
SS)
−
−
P53/SIB2/KR3/TIQ00/TOQ00/
RTP03
−
−
−
PDL5/AD5
Note In the on-chip debug mode, high-level output is forcibly set.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(2/6)
User’s Manual U17715EJ2V0UD
35
CHAPTER 2 PIN FUNCTIONS
(3/6)
Pin No. Pin Name
GF GC
INTP0 20 18 P03/ADTRG
INTP1 21 19 P04
INTP2 22 20 P05/DRST
INTP3 23 21 P06
INTP4 58 56 P913/A13
INTP5 59 57 P914/A14/TIP51/TOP51
INTP6 60 58 P915/A15/TIP50/TOP50
INTP7 28 26
Note 1
KR0
39 37 P50/TIQ01/TOQ01/RTP00
Note 1
KR1
40 38 P51/TIQ02/TOQ02/RTP01
Note 1
KR2
41 39 P52/TIQ03/TOQ03/RTP02/DDI
Note 1
KR3
42 40
Note 1
KR4
43 41 P54/SOB2/RTP04/DCK
Note 1
KR5
44 42 P55/SCKB2/RTP05/DMS
Note 1
KR6
45 43 P90/A0/TXDA1/SDA02
Note 1
KR7
46 44
Note 2
NMI
19 17 Input
RD 69 67 Output Read strobe signal output for external memory PCT4
REGC 12 10
RESET 16 14 Input System reset input
RTP00 39 37 P50/TIQ01/KR0/TOQ01
RTP01 40 38 P51/TIQ02/KR1/TOQ02
RTP02 41 39 P52/TIQ03/KR2/TOQ03/DDI
RTP03 42 40
RTP04 43 41 P54/SOB2/KR4/DCK
RTP05 44 42
RXDA0 28 26 P31/INTP7/SIB4
RXDA1 46 44 P91/A1/KR7/SCL02
RXDA2 38 36
I/O Function Alternate Function
Input
External interrupt request input (maskable, analog noise
elimination).
Analog noise elimination or digital noise elimination
selectable for INTP3 pin.
5 V tolerant.
P31/RXDA0/SIB4
Input
Key interrupt input (on-chip analog noise eliminator).
5 V tolerant.
P53/SIB2/TIQ00/TOQ00/
RTP03/DDO
P91/A1/RXDA1/SCL02
External interrupt input (non-maskable, analog noise
P02
elimination). 5 V tolerant.
Connection of regulator output stabilization capacitance
−
μ
F)
(4.7
−
−
Output
Real-time output port.
N-ch open-drain output selectable.
5 V tolerant.
P53/SIB2/KR3/TIQ00/TOQ00/
DDO
P55/SCKB2/KR5/DMS
Input Serial receive data input (UARTA0 to UARTA2)
5 V tolerant.
P39/SCL00
Notes 1. Connect a pull-up resistor externally.
2. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI
pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is “No edge detected”. Select the NMI
pin valid edge using INTF0 and INTR0 registers.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
36
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
I/O Function Alternate Function
GF GC
SCKB0 26 24 P42
SCKB1 54 52 P99/A9
SCKB2 44 42 P55/KR5/RTP05/DMS
I/O Serial clock I/O (CSIB0 to CSIB4)
N-ch open-drain output selectable.
5 V tolerant.
SCKB3 57 55 P912/A12
SCKB4 29 27
SCL00 38 36 P39/RXDA2
SCL01 25 23 P41/SOB0
SCL02 46 44
SDA00 37 35 P38/TXDA2
SDA01 24 22 P40/SIB0
SDA02 45 43
SIB0 24 22 P40/SDA01
SIB1 52 50 P97/A7/TIP20/TOP20
I/O Serial clock I/O (I
N-ch open-drain output selectable.
5 V tolerant.
I/O Serial transmit/receive data I/O (I
N-ch open-drain output selectable.
5 V tolerant.
Input Serial receive data input (CSIB0 to CSIB4)
5 V tolerant.
2
C00 to I2C02)
2
C00 to I2C02)
P32/ASCKA0/TIP00/TOP00
P91/A1/KR7/RXDA1
P90/A0/KR6/TXDA1
SIB2 42 40 P53/KR3/TIQ00/TOQ00/
RTP03/DDO
SIB3 55 53 P910/A10
SIB4 28 26
SOB0 25 23 P41/SCL01
SOB1 53 51 P98/A8
SOB2 43 41 P54/KR4/RTP04/DCK
Output Serial transmit data output (CSIB0 to CSIB4)
N-ch open-drain output selectable.
5 V tolerant.
P31/RXDA0/INTP7
SOB3 56 54 P911/A11
SOB4 27 25
P30/TXDA0
(4/6)
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
User’s Manual U17715EJ2V0UD
37
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
GF GC
TIP00 29 27 External event count input/capture trigger input/external
TIP01 30 28 Capture trigger input (TMP0). 5 V tolerant. P33/TOP01
TIP10 31 29 External event count input/capture trigger input/external
TIP11 32 30 Capture trigger input (TMP1). 5 V tolerant. P35/TOP11
TIP20 52 50 External event count input/capture trigger input/external
TIP21 51 49 Capture trigger input (TMP2). 5 V tolerant.
TIP30 50 48
TIP31 49 47
TIP40 48 46
TIP41 47 45
TIP50 60 58
TIP51 59 57
TIQ00 42 40
TIQ01 39 37 P50/KR0/TOQ01/RTP00
TIQ02 40 38 P51/KR1/TOQ02/RTP01
TIQ03 41 39
I/O Function Alternate Function
Input
trigger input (TMP0). 5 V tolerant.
trigger input (TMP1). 5 V tolerant.
trigger input (TMP2). 5 V tolerant.
External event count input/capture trigger input/external
trigger input (TMP3). 5 V tolerant.
Capture trigger input (TMP3). 5 V tolerant.
External event count input/capture trigger input/external
trigger input (TMP4). 5 V tolerant.
Capture trigger input (TMP4). 5 V tolerant.
External event count input/capture trigger input/external
trigger input (TMP5). 5 V tolerant.
Capture trigger input (TMP5). 5 V tolerant.
External event count input/capture trigger input/external
trigger input (TMQ0). 5 V tolerant.
Capture trigger input (TMQ0). 5 V tolerant.
P32/ASCKA0/SCKB4/TOP00
P34/TOP10
P97/A7/SIB1/TOP20
P96/A6/TOP21
P95/A5/TOP30
P94/A4/TOP31
P93/A3/TOP40
P92/A2/TOP41
P915/A15/INTP6/TOP50
P914/A14/INTP5/TOP51
P53/SIB2/KR3/TOQ00/RTP03/
DDO
P52/KR2/TOQ03/RTP02/
DDI
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(5/6)
38
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Name
GF GC
TOP00 29 27 P32/ASCKA0/SCKB4/TIP00
TOP01 30 28
TOP10 31 29 P34/TIP10
TOP11 32 30
TOP20 52 50 P97/A7/SIB1/TIP20
TOP21 51 49
TOP30 50 48 P95/A5/TIP30
TOP31 49 47
TOP40 48 46 P93/A3/TIP40
TOP41 47 45
TOP50 60 58 P915/A15/INTP6/TIP50
TOP51 59 57
TOQ00 42 40
TOQ01 39 37 P50/TIQ01/KR0/RTP00
TOQ02 40 38 P51/TIQ02/KR1/RTP01
TOQ03 41 39
TXDA0 27 25 P30/SOB4
TXDA1 45 43 P90/A0/KR6/SDA02
TXDA2 37 35
VDD 11 9 − Positive power supply pin for internal
VSS 13 11 − Ground potential for internal
WAIT 63 61 Input External wait input PCM0
WR0 67 65 Write strobe for external memory (lower 8 bits) PCT0
WR1 68 66
X1 14 12 Input
X2 15 13
XT1 17 15 Input
XT2 18 16
I/O Function Alternate Function
Output
Output
Output
Output
Timer output (TMP0)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMP1)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMP2)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMP3)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMP4)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMP5)
N-ch open-drain output selectable. 5 V tolerant.
Timer output (TMQ0)
N-ch open-drain output selectable. 5 V tolerant.
Serial transmit data output (UARTA0 to UARTA2)
N-ch open-drain output selectable.
5 V tolerant.
Write strove for external memory (higher 8 bits) PCT1
Connection of resonator for main clock
−
Connection of resonator for subclock
−
P33/TIP01
P35/TIP11
P96/A6/TIP21
P94/A4/TIP31
P92/A2/TIP41
P914/A14/INTP5/TIP51
P53/SIB2/KR3/TIQ00/RTP03/
DDO
P52/TIQ03/KR2/RTP02/DDI
P38/SDA00
−
−
−
−
−
−
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(6/6)
User’s Manual U17715EJ2V0UD
39
CHAPTER 2 PIN FUNCTIONS
2.2 Pin States
The operation states of pins in the various modes are described below.
Table 2-2. Pin Operation States in Various Modes
Pin Name
When Power
Is Turned
Note 1
On
During Reset
(Except When
Powe r I s
HALT Mode
Turned On)
P05/DRST Pulled down Pulled down
P10/ANO0,
Undefined
Note 4
Held Held Held Held Held
Hi-Z Held Held Hi-Z Held Held
P11/ANO1
P53/DDO
AD0 to AD15 Notes 7, 8
Hi-Z
Note 6
Hi-Z
Note 5
Hi-Z
Held Held Held Held Held
Note 6
A0 to A15 Undefined
A16 to A21 Undefined
WAIT
CLKOUT Operating L L Operating Operating
WR0, WR1
RD
ASTB
HLDAK
Operating
HLDRQ
Other port pins Hi-Z Hi-Z Held Held Held Held Held
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower
limit) when the power is turned on.
2. Operates while an alternate function is operating.
3. In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In
multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the
state of this pin differs according to the OCDM.OCDM0 bit setting.
5. DDO output is specified in the on-chip debug mode.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port
mode).
7. Operates even in the HALT mode, during DMA operation.
8. In separate bus mode: Hi-Z
In multiplexed bus mode: Undefined
9. In separate bus mode
Remark Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L: Low-level output
H: High-level output
−: Input without sampling (not acknowledged)
Note 2
IDLE1, IDLE2,
Sub-IDLE
Mode
Note 2
STOP
Mode
Note 2
Idle
State
Note 3
Bus Hold
Hi-Z Hi-Z Held Hi-Z
Notes 7, 9
Note 7
− − − − −
Note 7
Hi-Z
H
Note 7
H H H
− − −
Operating
L
40
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins
Pin No. Pin Alternate Function
GF GC
P02 NMI 19 17
P03 INTP0/ADTRG 20 18
P04 INTP1 21 19
P05 INTP2/DRST 22 20 10-N
P06 INTP3 23 21 10-D
P10, P11 ANO0, ANO1 5, 6 3, 4 12-D
P30 TXDA0/SOB4 27 25 10-G
P31 RXDA0/INTP7/SIB4 28 26
P32 ASCKA0/SCKB4/TIP00 29 27
P33 TIP01/TOP01 30 28
P34 TIP10/TOP10 31 29
P35 TIP11/TOP11 32 30
P36
P37
−
−
33 31
34 32
P38 TXDA2/SDA00 37 35
P39 RXDA2/SCL00 38 36
P40 SIB0/SDA01 24 22
P41 SOB0/SCL01 25 23
P42 SCKB0 26 24
P50 TIQ01/KR0/TOQ01/RTP00 39 37
P51 TIQ02/KR1/TOQ02/RTP01 40 38
P52 TIQ03/KR2/TOQ03/RTP02/DDI 41 39
P53
SIB2/KR3/TIQ00/TOQ00/RTP03/
42 40
DDO
P54 SOB2/KR4/RTP04/DCK 43 41
P55 SCKB2/KR5/RTP05/DMS 44 42
P70 to P711 ANI0 to ANI11
2, 1,
100-89 11-G
100-91
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
I/O Circuit Type Recommended Connection
10-D
Input: Independently connect to EV
EV
SS via a resistor.
Output: Leave open.
Input: Independently connect to EV
a resistor.
Fixing to V
DD level is prohibited.
Output: Leave open.
Internally pull-down after reset by
RESET pin.
Input: Independently connect to EV
EV
SS via a resistor.
Output: Leave open.
Input: Independently connect to AV
AV
SS via a resistor.
Output: Leave open.
Input: Independently connect to EV
EV
10-D
SS via a resistor.
Output: Leave open.
10-G
10-D
Input: Independently connect to AV
SS via a resistor.
AV
Output: Leave open.
(1/3)
DD or
SS via
DD or
REF1 or
DD or
REF0 or
User’s Manual U17715EJ2V0UD
41
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Alternate Function
I/O Circuit Type Recommended Connection
GF GC
P90 A0/KR6/TXDA1/SDA02 45 43
P91 A1/KR7/RXDA1/SCL02 46 44
P92 A2/TIP41/TOP41 47 45
10-D
Input: Independently connect to EV
EV
SS via a resistor.
Output: Leave open.
P93 A3/TIP40/TOP40 48 46
P94 A4/TIP31/TOP31 49 47
P95 A5/TIP30/TOP30 50 48
P96 A6/TIP21/TOP21 51 49
P97 A7/SIB1/TIP20/TOP20 52 50
P98 A8/SOB1 53 51 10-G
P99 A9/SCKB1 54 52
10-D
P910 A10/SIB3 55 53
P911 A11/SOB3 56 54 10-G
P912 A12/SCKB3 57 55
10-D
P913 A13/INTP4 58 56
P914 A14/INTP5/TIP51/TOP51 59 57
P915 A15/INTP6/TIP50/TOP50 60 58
PCM0 WAIT 63 61
5
PCM1 CLKOUT 64 62
PCM2 HLDAK 65 63
Input: Independently connect to BV
SS via a resistor.
BV
Output: Leave open.
PCM3 HLDRQ 66 64
PCT0, PCT1 WR0, WR1 67, 68 65, 66
PCT4 RD 69 67
PCT6 ASTB 70 68
89, 90
61, 62
87, 88
59, 60
Input: Independently connect to EV
EV
SS via a resistor.
PDH0 to
PDH3
PDH4,
PDH5
A16 to A19
A20, A21 8, 9 6, 7
Output: Leave open.
PDL0 to
AD0 to AD4 73-77 71-75
PDL4
PDL5 AD5/FLMD1 78 76
PDL6 to
AD6 to AD15 79-88 77-86
Input: Independently connect to BV
SS via a resistor.
BV
Output: Leave open.
PDL15
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(2/3)
DD or
DD or
DD or
DD or
42
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin No. Pin Alternate Function
GF GC
AVREF0
AVREF1
AVSS
BVDD
BVSS
EVDD
EVSS
FLMD0
REGC
RESET
VDD
VSS
X1
X2
XT1
XT2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3 1
7 5
4 2
72 70
71 69
36 34
35 33
10 8
12 10
16 14 2
11 9
13 11
14 12
15 13
17 15 16 Connect to VSS.
18 16 16 Leave open.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
I/O Circuit Type Recommended Connection
−
Directly connect to V
DD and always supply
power.
−
Directly connect to V
DD and always supply
power.
−
Directly connect to V
SS and always supply
power.
−
Directly connect to V
DD and always supply
power.
−
Directly connect to V
SS and always supply
power.
− −
− −
−
Directly connect to V
SS in a mode other
than the flash memory programming mode.
−
Connect regulator output stabilization
μ
capacitance (4.7
F (preliminary value)).
−
− −
− −
− −
− −
(3/3)
User’s Manual U17715EJ2V0UD
43
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits
Type 2
Type 10-N
EV
DD
IN
Schmitt-triggered input with hysteresis characteristics
Type 5
EV
DD
/BV
DD
Data
Output
disable
Input
enable
P-ch
N-ch
EVSS/BV
SS
Type 10-D
DD
EV
Data
Open drain
Output
disable
Note
EV
P-ch
N-ch
SS
IN/OUT
IN/OUT
Data
Open drain
Output
disable
Input
enable
Type 11-G
Data
Output
disable
Comparator
(Threshold voltage)
Input enable
OCDM0 bit
+
_
REF0
AV
Note
AV
P-ch
IN/OUT
N-ch
EV
SS
N-ch
AV
REF0
P-ch
IN/OUT
N-ch
AV
SS
P-ch
N-ch
SS
Type 10-G
Data
Open drain
Output
disable
Input
enable
Input
enable
EV
EV
DD
P-ch
IN/OUT
N-ch
SS
Type 12-D
Data
Output
disable
Input
enable
Type 16
Analog output
voltage
P-ch
N-ch
AV
AV
REF1
P-ch
N-ch
SS
IN/OUT
Feedback cut-off
P-ch
XT1 XT2
Note Hysteresis characteristics are not available in port mode.
44
User’s Manual U17715EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.4 Cautions
When the power is turned on, the following pins may output an undefined level temporarily even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
User’s Manual U17715EJ2V0UD
45
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/JG2 is based on RISC architecture and executes almost all instructions with one clock by
using a 5-stage pipeline.
3.1 Features
Minimum instruction execution time: 50 ns (at 20 MHz operation)
30.5
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
μ
s (with subclock (fXT) = 32.768 kHz operation)
46
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
3.2 CPU Register Set
The registers of the V850ES/JG2 can be classified into two types: general-purpose program registers and
dedicated system registers. All the registers are 32 bits wide.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set
(2) System register set
31 0 31 0
r0
(Zero register)
(Assembler-reserved register)
r1
r2
r3
(Stack pointer (SP))
r4
(Global pointer (GP))
r5
(Text pointer (TP))
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
(Element pointer (EP))
r31
(Link pointer (LP))
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
(Interrupt status saving register)
(Interrupt status saving register)
(NMI status saving register)
(NMI status saving register)
(Interrupt source register)
(Program status word)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
(CALLT base pointer)
31 0
PC
(Program counter)
User’s Manual U17715EJ2V0UD
47
CHAPTER 3 CPU FUNCTION
3.2.1 Program register set
The program registers include general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a
data variable or an address variable.
However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are
used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the
SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31
are implicitly used by the assembler and C compiler. When using these registers, save their contents for
protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS.
If the real-time OS does not use r2, it can be used as a register for variables.
Table 3-1. Program Registers
Name Usage Operation
r0 Zero register Always holds 0.
r1 Assembler-reserved register Used as working register to create 32-bit immediate data
r2 Register for address/data variable (if real-time OS does not use r2)
r3 Stack pointer Used to create a stack frame when a function is called
r4 Global pointer Used to access a global variable in the data area
r5 Text pointer Used as register that indicates the beginning of a text area (area
where program codes are located)
r6 to r29 Register for address/data variable
r30 Element pointer Used as base pointer to access memory
r31 Link pointer Used when the compiler calls a function
PC Program counter Holds the instruction address during program execution
Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to
the CA850 (C Compiler Package) Assembly Language User’s Manual.
(2) Program counter (PC)
The program counter holds the instruction address during program execution. The lower 32 bits of this register
are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.
Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.
31 26 25 1 0
PC
Fixed to 0 Instruction address during program execution
0
Default value
00000000H
48
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
3.2.2 System register set
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using
the system register numbers listed below.
Table 3-2. System Register Numbers
System Register Name
Register
Number
Note 1
Note 1
Note 1
Note 1
0 Interrupt status saving register (EIPC)
1 Interrupt status saving register (EIPSW)
2 NMI status saving register (FEPC)
3 NMI status saving register (FEPSW)
4 Interrupt source register (ECR)
5 Program status word (PSW)
6 to 15 Reserved for future function expansion (operation is not guaranteed if these
Operand Specification System
LDSR Instruction STSR Instruction
√ √
√ √
√ √
√ √
× √
√ √
× ×
registers are accessed)
16 CALLT execution status saving register (CTPC)
17 CALLT execution status saving register (CTPSW)
18 Exception/debug trap status saving register (DBPC) √
19 Exception/debug trap status saving register (DBPSW) √
20 CALLT base pointer (CTBP)
21 to 31 Reserved for future function expansion (operation is not guaranteed if these
√ √
√ √
Note 2
√
Note 2
√
√ √
× ×
Note 2
Note 2
registers are accessed)
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
program if multiple interrupts are enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP
instruction or illegal opcode and DBRET instruction execution.
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
Remark √: Can be accessed
×: Access prohibited
User’s Manual U17715EJ2V0UD
49
CHAPTER 3 CPU FUNCTION
(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are used to save the status when an interrupt occurs.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to
EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to
the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
The address of the instruction next to the instruction under execution, except some instructions (see 19.8
Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception
or a maskable interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one set of interrupt status saving registers is available, the contents of these registers must be
saved by program when multiple interrupts are enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.
EIPC
EIPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Contents of saved PC)
87
(Contents of
saved PSW)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
50
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program
status word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is
saved to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved
by program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
FEPC
FEPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Contents of saved PC)
87
(Contents of
saved PSW)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt
occurs. This register holds the exception code of each interrupt source. Because this register is a read-only
register, data cannot be written to this register using the LDSR instruction.
ECR
31 0
FECC EICC
16 15
Default value
00000000H
Bit position Bit name Meaning
31 to 16 FECC Exception code of non-maskable interrupt (NMI)
15 to 0 EICC Exception code of exception or maskable interrupt
User’s Manual U17715EJ2V0UD
51
CHAPTER 3 CPU FUNCTION
(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the status of the program (result of
instruction execution) and the status of the CPU.
If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are
validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1,
interrupt requests will not be acknowledged while the LDSR instruction is being executed.
Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).
PSW
31 0
RFU
87NP6EP5ID4
SAT3CY2OV
1
SZ
Default value
00000020H
Bit position Flag name Meaning
31 to 8 RFU Reserved field. Fixed to 0.
7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an
NMI request is acknowledged, disabling multiple interrupts.
0: NMI is not being serviced.
1: NMI is being serviced.
6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception
occurs. Even if this bit is set, interrupt requests are acknowledged.
0: Exception is not being processed.
1: Exception is being processed.
5 ID Indicates whether a maskable interrupt can be acknowledged.
0: Interrupt enabled
1: Interrupt disabled
4 SAT
3 CY Indicates whether a carry or a borrow occurs as a result of an operation.
2 OV
1 S
0 Z Indicates whether the result of an operation is 0.
Note
Indicates that the result of a saturation operation has overflowed and is saturated. Because
this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is
saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.
Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by
execution of an arithmetic operation instruction.
0: Not saturated
1: Saturated
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
Note
Indicates whether an overflow occurs during operation.
0: Overflow does not occur.
1: Overflow occurs.
Note
Indicates whether the result of an operation is negative.
0: The result is positive or 0.
1: The result is negative.
0: The result is not 0.
1: The result is 0.
(1/2)
Remark Also read Note on the next page.
52
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Note The result of the operation that has performed saturation processing is determined by the contents of the
OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is
performed.
SAT OV S
Maximum positive value is exceeded 1 1 0 7FFFFFFFH
Maximum negative value is exceeded 1 1 1 80000000H
Positive (maximum value is not exceeded) 0
Negative (maximum value is not exceeded)
Holds value
before operation
Flag Status Status of Operation Result
0
1
Result of Operation of
Saturation Processing
Operation result itself
(5) CALLT execution status saving registers (CTPC and CTPSW)
CTPC and CTPSW are CALLT execution status saving registers.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and
those of the program status word (PSW) are saved to CTPSW.
The contents saved to CTPC are the address of the instruction next to CALLT.
The current contents of the PSW are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).
CTPC
CTPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(2/2)
User’s Manual U17715EJ2V0UD
53
CHAPTER 3 CPU FUNCTION
(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and
those of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is being executed
when an exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
This register can be read or written only during the interval between the execution of the DBTRAP instruction
or illegal opcode and the DBRET instruction.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.
DBPC
DBPSW
31 0
00
31 0
00
26 25
0 0 0 0
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(Saved PC contents)
87
(Saved PSW
contents)
Default value
0xxxxxxxH
(x: Undefined)
Default value
000000xxH
(x: Undefined)
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed
to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
CTBP
31 0
00
26 25
0 0 0 0 0
(Base address)
Default value
0xxxxxxxH
(x: Undefined)
54
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
3.3 Operation Modes
The V850ES/JG2 has the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/JG2 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications.
For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION.
3.3.1 Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
Operation When Reset Is Released
FLMD0 FLMD1
Operation Mode After Reset
L
H L Flash memory programming mode
H H Setting prohibited
×
Normal operation mode
Remark L: Low-level input
H: High-level input
×: Don’t care
User’s Manual U17715EJ2V0UD
55
CHAPTER 3 CPU FUNCTION
3.4 Address Space
3.4.1 CPU address space
For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus
an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand
addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space,
however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical
address space is accessed regardless of the value of bits 31 to 26.
Figure 3-1. Image on Address Space
Image 63
16 MB
Program space
Use-prohibited area
Internal RAM area
Use-prohibited area
External memory area
4 GB
64 MB
Image 1
Image 0
Data space
Peripheral I/O area
Internal RAM area
Use-prohibited area
64 MB
External memory area
Internal ROM area
(external memory area)
56
Internal ROM area
(external memory area)
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
3.4.2 Wraparound of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid.
The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are
contiguous addresses. That the highest address and the lowest address of the program space are contiguous
in this way is called wraparound.
Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O
area, instructions cannot be fetched from this area. Therefore, do not execute an operation in
which the result of a branch address calculation affects this area.
00000001H
00000000H
03FFFFFFH
03FFFFFEH
Program space
(+) direction (−) direction
Program space
(2) Data space
The result of an operand address calculation operation that exceeds 32 bits is ignored.
Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are
contiguous, and wraparound occurs at the boundary of these addresses.
00000001H
00000000H
FFFFFFFFH
Data space
(+) direction (−) direction
FFFFFFFEH
Data space
User’s Manual U17715EJ2V0UD
57
CHAPTER 3 CPU FUNCTION
3.4.3 Memory map
The areas shown below are reserved in the V850ES/JG2.
Figure 3-2. Data Memory Map (Physical Addresses)
03FFFFFFH
(64 KB)
03FF0000H
03FEFFFFH
Use prohibited
01000000H
00FFFFFFH
On-chip peripheral I/O area
(4 KB)
Internal RAM area
(60 KB)
03FFFFFFH
03FFF000H
03FFEFFFH
03FF0000H
External memory area
(14 MB)
00200000H
001FFFFFH
(2 MB)
00000000H
Note 1
External memory area
(1 MB)
Internal ROM area
(1 MB)
Note 1
Note 2
001FFFFFH
00100000H
000FFFFFH
00000000H
Notes 1. The V850ES/JG2 has 22 address pins, so the external memory area appears as a repeated 4 MB
image.
2. Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM
area. However, data write access to these addresses is made to the external memory area.
58
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Figure 3-3. Program Memory Map
03FFFFFFH
03FFF000H
03FFEFFFH
03FF0000H
03FEFFFFH
01000000H
00FFFFFFH
Use prohibited
(program fetch prohibited area)
Internal RAM area (60 KB)
Use prohibited
(program fetch prohibited area)
Note
Note
00200000H
001FFFFFH
00100000H
000FFFFFH
00000000H
External memory area
External memory area
(14 MB)
(1 MB)
Internal ROM area
(1 MB)
Note The V850ES/JG2 has 22 address pins, so the external memory area appears as a repeated 4 MB image.
User’s Manual U17715EJ2V0UD
59
3.4.4 Areas
(1) Internal ROM area
Up to 1 MB is reserved as an internal ROM area.
(a) Internal ROM (128 KB)
128 KB are allocated to addresses 00000000H to 0001FFFFH in the
Accessing addresses 00020000H to 000FFFFFH is prohibited.
Figure 3-4. Internal ROM Area (128 KB)
CHAPTER 3 CPU FUNCTION
000FFFFFH
Access-prohibited
area
μ
PD70F3715.
(b) Internal ROM (256 KB)
256 KB are allocated to addresses 00000000H to 0003FFFFH in the
Accessing addresses 00040000H to 000FFFFFH is prohibited.
00020000H
0001FFFFH
00000000H
Internal ROM
(128 KB)
Figure 3-5. Internal ROM Area (256 KB)
000FFFFFH
Access-prohibited
area
00040000H
0003FFFFH
Internal ROM
(256 KB)
μ
PD70F3716.
60
00000000H
User’s Manual U17715EJ2V0UD
(c) Internal ROM (384 KB)
384 KB are allocated to addresses 00000000H to 0005FFFFH in the
Accessing addresses 00060000H to 000FFFFFH is prohibited.
CHAPTER 3 CPU FUNCTION
Figure 3-6. Internal ROM Area (384 KB)
000FFFFFH
Access-prohibited
area
00060000H
0005FFFFH
Internal ROM
(384 KB)
μ
PD70F3717.
(d) Internal ROM (512 KB)
512 KB are allocated to addresses 00000000H to 0007FFFFH in the
Accessing addresses 00080000H to 000FFFFFH is prohibited.
00000000H
Figure 3-7. Internal ROM Area (512 KB)
000FFFFFH
Access-prohibited
area
00080000H
0007FFFFH
Internal ROM
(512 KB)
00000000H
μ
PD70F3718.
User’s Manual U17715EJ2V0UD
61
(e) Internal ROM (640 KB)
640 KB are allocated to addresses 00000000H to 0009FFFFH in the
Accessing addresses 000A0000H to 000FFFFFH is prohibited.
CHAPTER 3 CPU FUNCTION
Figure 3-8. Internal ROM Area (640 KB)
μ
PD70F3719.
000FFFFFH
000A0000H
0009FFFFH
00000000H
Access-prohibited
area
Internal ROM
(640 KB)
62
User’s Manual U17715EJ2V0UD
(2) Internal RAM area
Up to 60 KB are reserved as the internal RAM area.
(a) Internal RAM (12 KB)
12 KB are allocated to addresses 03FFC000H to 03FFEFFFH of the
Accessing addresses 03FF0000H to 03FFBFFFH is prohibited.
Figure 3-9. Internal RAM Area (12 KB)
Physical address space
CHAPTER 3 CPU FUNCTION
Logical address space
μ
PD70F3715.
(b) Internal RAM (24 KB)
24 KB are allocated to addresses 03FF9000H to 03FFEFFFH of the
Accessing addresses 03FF0000H to 03FF8FFFH is prohibited.
03FFEFFFH
03FFC000H
03FFBFFFH
03FF0000H
Figure 3-10. Internal RAM Area (24 KB)
Physical address space
Internal RAM
(12 KB)
Access-prohibited
area
FFFFEFFFH
FFFFC000H
FFFFBFFFH
FFFF0000H
μ
PD70F3716.
Logical address space
03FFEFFFH
Internal RAM
(24 KB)
03FF9000H
03FF8FFFH
Access-prohibited
area
03FF0000H
FFFFEFFFH
FFFF9000H
FFFF8FFFH
FFFF0000H
User’s Manual U17715EJ2V0UD
63
(c) Internal RAM (32 KB)
32 KB are allocated to addresses 03FF7000H to 03FFEFFFH of the
Accessing addresses 03FF0000H to 03FF6FFFH is prohibited.
CHAPTER 3 CPU FUNCTION
Figure 3-11. Internal RAM Area (32 KB)
Physical address space
μ
PD70F3717.
Logical address space
(d) Internal RAM (40 KB)
40 KB are allocated to addresses 03FF5000H to 03FFEFFFH of the
Accessing addresses 03FF0000H to 03FF4FFFH is prohibited.
03FFEFFFH
03FF7000H
03FF6FFFH
03FF0000H
Figure 3-12. Internal RAM Area (40 KB)
Physical address space
Internal RAM
(32 KB)
Access-prohibited
area
FFFFEFFFH
FFFF7000H
FFFF6FFFH
FFFF0000H
μ
PD70F3718.
Logical address space
64
03FFEFFFH
03FF5000H
03FF4FFFH
03FF0000H
User’s Manual U17715EJ2V0UD
Internal RAM
(40 KB)
Access-prohibited
area
FFFFEFFFH
FFFF5000H
FFFF4FFFH
FFFF0000H
(e) Internal RAM area (48 KB)
48 KB are allocated to addresses 03FF3000H to 03FFEFFFH of the
Accessing addresses 03FF0000H to 03FF2FFFH is prohibited.
CHAPTER 3 CPU FUNCTION
Figure 3-13. Internal RAM Area (48 KB)
Physical address space
μ
PD70F3719.
Logical address space
03FFEFFFH
03FF3000H
03FF2FFFH
03FF0000H
Internal RAM
(48 KB)
Access-prohibited
area
FFFFEFFFH
FFFF3000H
FFFF2FFFH
FFFF0000H
User’s Manual U17715EJ2V0UD
65
CHAPTER 3 CPU FUNCTION
(3) On-chip peripheral I/O area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Figure 3-14. On-Chip Peripheral I/O Area
Physical address space Logical address space
03FFFFFFH
On-chip peripheral I/O area
(4 KB)
03FFF000H
FFFFFFFFH
FFFFF000H
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-
chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword
units in the order of lower area and higher area, with the lower 2 bits of the address
ignored.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
bits are undefined when the register is read, and data is written to the lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion. The operation is
undefined and not guaranteed when these addresses are accessed.
(4) External memory area
15 MB (00100000H to 00FFFFFFH) are allocated as the external memory area. For details, see CHAPTER 5
BUS CONTROL FUNCTION.
Caution The V850ES/JG2 has 22 address pins (A0 to A21), so the external memory area appears as a
repeated 4 MB image. In the separate bus mode or when the A20 and A21 pins are used, it is
necessary that EV
DD = BVDD = VDD.
66
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
3.4.5 Recommended use of address space
The architecture of the V850ES/JG2 requires that a register that serves as a pointer be secured for address
generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be
directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be
used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a
pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the
program size can be reduced.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access the following addresses.
Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation
(invalid fetch) straddling the on-chip peripheral I/O area does not occur.
RAM Size Access Address
48 KB 03FF3000H to 03FFEFFFH
40 KB 03FF5000H to 03FFEFFFH
32 KB 03FF7000H to 03FFEFFFH
24 KB 03FF9000H to 03FFEFFFH
12 KB 03FFC000H to 03FFEFFFH
User’s Manual U17715EJ2V0UD
67
CHAPTER 3 CPU FUNCTION
(2) Data space
With the V850ES/JG2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address
space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated
as an address.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H
±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can
be addressed by one pointer.
The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers
dedicated to pointers.
Example:
μ
PD70F3717
0005FFFFH
00007FFFH
(R = )
00000000H
FFFFF000H
FFFFEFFFH
FFFF8000H
Internal ROM area
On-chip peripheral
I/O area
Internal RAM area
32 KB
4 KB
28 KB
68
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Figure 3-15. Recommended Memory Map
FFFFFFFFH
FFFFF000H
FFFFEFFFH
FFFF0000H
FFFEFFFFH
04000000H
03FFFFFFH
03FFF000H
03FFEFFFH
03FF7000H
03FF6FFFH
03FF0000H
03FEFFFFH
Use prohibited
Internal RAM
Data spaceProgram space
On-chip
peripheral I/O
Internal RAM
On-chip
peripheral I/O
Internal RAM
Use prohibited
FFFFFFFFH
FFFFF000H
FFFFEFFFH
FFFF7000H
FFFF6FFFH
FFFF0000H
FFFEFFFFH
Program space
64 MB
01000000H
00FFFFFFH
00100000H
000FFFFFH
00060000H
0005FFFFH
00000000H
Use prohibited
External
Note
memory
Internal ROM
Internal ROM
External
Note
memory
Internal ROM
00100000H
000FFFFFH
00000000H
Note The V850ES/JG2 has 22 address pins, so the external memory area appears as a repeated 4 MB image.
Remarks 1.
indicates the recommended area.
2. This figure is the recommended memory map of the μPD70F3717.
User’s Manual U17715EJ2V0UD
69
CHAPTER 3 CPU FUNCTION
3.4.6 Peripheral I/O registers
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
FFFFF004H Port DL register PDL √ 0000H
FFFFF004H Port DL register L PDLL
FFFFF005H Port DL register H PDLH
FFFFF006H Port DH register PDH
FFFFF00AH Port CT register PCT
FFFFF00CH Port CM register PCM
R/W
√ √
√ √
√ √
√ √
√ √
FFFFF024H Port DL mode register PMDL
FFFFF024H Port DL mode register L PMDLL
FFFFF025H Port DL mode register H PMDLH
FFFFF026H Port DH mode register PMDH
FFFFF02AH Port CT mode register PMCT
FFFFF02CH Port CM mode register PMCM
√ √
√ √
√ √
√ √
√ √
FFFFF044H Port DL mode control register PMCDL
FFFFF044H Port DL mode control register L PMCDLL
FFFFF045H Port DL mode control register H PMCDLH
FFFFF046H Port DH mode control register PMCDH
FFFFF04AH Port CT mode control register PMCCT
FFFFF04CH Port CM mode control register PMCCM
√ √
√ √
√ √
√ √
√ √
FFFFF066H Bus size configuration register BSC
FFFFF06EH System wait control register VSWC
√
FFFFF080H DMA source address register 0L DSA0L
FFFFF082H DMA source address register 0H DSA0H
FFFFF084H DMA destination address register 0L DDA0L
FFFFF086H DMA destination address register 0H DDA0H
FFFFF088H DMA source address register 1L DSA1L
FFFFF08AH DMA source address register 1H DSA1H
FFFFF08CH DMA destination address register 1L DDA1L
FFFFF08EH DMA destination address register 1H DDA1H
FFFFF090H DMA source address register 2L DSA2L
FFFFF092H DMA source address register 2H DSA2H
FFFFF094H DMA destination address register 2L DDA2L
FFFFF096H DMA destination address register 2H DDA2H
FFFFF098H DMA source address register 3L DSA3L
FFFFF09AH DMA source address register 3H DSA3H
FFFFF09CH DMA destination address register 3L DDA3L
FFFFF09EH DMA destination address register 3H DDA3H
FFFFF0C0H DMA transfer count register 0 DBC0
FFFFF0C2H DMA transfer count register 1 DBC1
FFFFF0C4H DMA transfer count register 2 DBC2
FFFFF0C6H DMA transfer count register 3 DBC3
FFFFF0D0H DMA addressing control register 0 DADC0
√ 0000H
Default Value
00H
00H
00H
00H
00H
FFFFH
√
FFH
FFH
FFH
FFH
FFH
0000H
√
00H
00H
00H
00H
00H
5555H
√
77H
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Note The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.
Note
Note
Note
Note
Note
(1/10)
Note
70
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Manipulatable BitsAddress Function Register Name Symbol R/W
1 8 16
FFFFF0D2H DMA addressing control register 1 DADC1
FFFFF0D4H DMA addressing control register 2 DADC2
FFFFF0D6H DMA addressing control register 3 DADC3
FFFFF0E0H DMA channel control register 0 DCHC0
FFFFF0E2H DMA channel control register 1 DCHC1
FFFFF0E4H DMA channel control register 2 DCHC2
FFFFF0E6H DMA channel control register 3 DCHC3
FFFFF100H Interrupt mask register 0 IMR0
FFFFF100H Interrupt mask register 0L IMR0L
FFFFF101H Interrupt mask register 0H IMR0H
FFFFF102H Interrupt mask register 1 IMR1
FFFFF102H Interrupt mask register 1L IMR1L
FFFFF103H Interrupt mask register 1H IMR1H
FFFFF104H Interrupt mask register 2 IMR2
FFFFF104H Interrupt mask register 2L IMR2L
FFFFF105H Interrupt mask register 2H IMR2H
FFFFF106H Interrupt mask register 3 IMR3
FFFFF106H Interrupt mask register 3L IMR3L
FFFFF107H Interrupt mask register 3H IMR3H
FFFFF110H Interrupt control register LVIIC
FFFFF112H Interrupt control register PIC0
FFFFF114H Interrupt control register PIC1
FFFFF116H Interrupt control register PIC2
FFFFF118H Interrupt control register PIC3
FFFFF11AH Interrupt control register PIC4
FFFFF11CH Interrupt control register PIC5
FFFFF11EH Interrupt control register PIC6
FFFFF120H Interrupt control register PIC7
FFFFF122H Interrupt control register
FFFFF124H Interrupt control register TQ0CCIC0
FFFFF126H Interrupt control register TQ0CCIC1
FFFFF128H Interrupt control register TQ0CCIC2
FFFFF12AH Interrupt control register TQ0CCIC3
FFFFF12CH Interrupt control register TP0OVIC
FFFFF12EH Interrupt control register TP0CCIC0
FFFFF130H Interrupt control register TP0CCIC1
FFFFF132H Interrupt control register TP1OVIC
FFFFF134H Interrupt control register TP1CCIC0
FFFFF136H Interrupt control register TP1CCIC1
FFFFF138H Interrupt control register TP2OVIC
FFFFF13AH Interrupt control register TP2CCIC0
FFFFF13CH Interrupt control register TP2CCIC1
FFFFF13EH Interrupt control register TP3OVIC
TQ0OVIC
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Default Value
0000H
√
0000H
√
0000H
√
00H
00H
00H
00H
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
FFFFH
√
FFH
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
(2/10)
User’s Manual U17715EJ2V0UD
71
CHAPTER 3 CPU FUNCTION
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
FFFFF140H Interrupt control register TP3CCIC0
FFFFF142H Interrupt control register TP3CCIC1
FFFFF144H Interrupt control register TP4OVIC
FFFFF146H Interrupt control register TP4CCIC0
FFFFF148H Interrupt control register TP4CCIC1
FFFFF14AH Interrupt control register TP5OVIC
FFFFF14CH Interrupt control register TP5CCIC0
FFFFF14EH Interrupt control register TP5CCIC1
FFFFF150H Interrupt control register TM0EQIC0
FFFFF152H Interrupt control register CB0RIC/IICIC1
FFFFF154H Interrupt control register CB0TIC
FFFFF156H Interrupt control register CB1RIC
FFFFF158H Interrupt control register CB1TIC
FFFFF15AH Interrupt control register CB2RIC
FFFFF15CH Interrupt control register CB2TIC
FFFFF15EH Interrupt control register CB3RIC
FFFFF160H Interrupt control register CB3TIC
FFFFF162H Interrupt control register
FFFFF164H Interrupt control register UA0TIC/CB4TIC
FFFFF166H Interrupt control register UA1RIC/IICIC2
FFFFF168H Interrupt control register UA1TIC
FFFFF16AH Interrupt control register UA2RIC/IICIC0
FFFFF16CH Interrupt control register UA2TIC
FFFFF16EH Interrupt control register ADIC
FFFFF170H Interrupt control register DMAIC0
FFFFF172H Interrupt control register DMAIC1
FFFFF174H Interrupt control register DMAIC2
FFFFF176H Interrupt control register DMAIC3
FFFFF178H Interrupt control register KRIC
FFFFF17AH Interrupt control register WTIIC
FFFFF17CH Interrupt control register WTIC
FFFFF1FAH In-service priority register ISPR R
FFFFF1FCH Command register PRCMD W
FFFFF1FEH Power save control register PSC
FFFFF200H A/D converter mode register 0 ADA0M0
FFFFF201H A/D converter mode register 1 ADA0M1
FFFFF202H A/D converter channel specification register ADA0S
FFFFF203H A/D converter mode register 2 ADA0M2
FFFFF204H Power-fail compare mode register ADA0PFM
FFFFF205H Power-fail compare threshold value register ADA0PFT
FFFFF210H A/D conversion result register 0 ADA0CR0
FFFFF211H A/D conversion result register 0H ADA0CR0H
FFFFF212H A/D conversion result register 1 ADA0CR1
FFFFF213H A/D conversion result register 1H ADA0CR1H
UA0RIC/CB4RIC
R/W
R/W
R
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
√
00H
00H
00H
00H
00H
00H
00H
√
Undefined
√
√
Undefined
√
(3/10)
Default Value
Undefined
Undefined
72
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Manipulatable BitsAddress Function Register Name Symbol R/W
Default Value
1 8 16
FFFFF214H A/D conversion result register 2 ADA0CR2
FFFFF215H A/D conversion result register 2H ADA0CR2H
FFFFF216H A/D conversion result register 3 ADA0CR3
FFFFF217H A/D conversion result register 3H ADA0CR3H
FFFFF218H A/D conversion result register 4 ADA0CR4
FFFFF219H A/D conversion result register 4H ADA0CR4H
FFFFF21AH A/D conversion result register 5 ADA0CR5
FFFFF21BH A/D conversion result register 5H ADA0CR5H
FFFFF21CH A/D conversion result register 6 ADA0CR6
FFFFF21DH A/D conversion result register 6H ADA0CR6H
FFFFF21EH A/D conversion result register 7 ADA0CR7
FFFFF21FH A/D conversion result register 7H ADA0CR7H
FFFFF220H A/D conversion result register 8 ADA0CR8
FFFFF221H A/D conversion result register 8H ADA0CR8H
FFFFF222H A/D conversion result register 9 ADA0CR9
FFFFF223H A/D conversion result register 9H ADA0CR9H
FFFFF224H A/D conversion result register 10 ADA0CR10
FFFFF225H A/D conversion result register 10H ADA0CR10H
FFFFF226H A/D conversion result register 11 ADA0CR11
FFFFF227H A/D conversion result register 11H ADA0CR11H
FFFFF280H D/A conversion value setting register 0 DA0CS0
FFFFF281H D/A conversion value setting register 1 DA0CS1
FFFFF282H D/A converter mode register DA0M
FFFFF300H Key return mode register KRM
FFFFF308H Selector operation control register 0 SELCNT0
FFFFF318H Noise elimination control register NFC
FFFFF320H Prescaler mode register 1 PRSM1
FFFFF321H Prescaler compare register 1 PRSCM1
FFFFF324H Prescaler mode register 2 PRSM2
FFFFF325H Prescaler compare register 2 PRSCM2
FFFFF328H Prescaler mode register 3 PRSM3
FFFFF329H Prescaler compare register 3 PRSCM3
FFFFF340H IIC division clock select register OCKS0
FFFFF344H IIC division clock select register OCKS1
FFFFF400H Port 0 register P0
FFFFF402H Port 1 register P1
R
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
√
Undefined
√
00H
√
00H
√
00H
00H
00H
00H
√
00H
00H
√
00H
00H
√
00H
00H
√
00H
√
00H
√
00H
00H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note
Note
FFFFF406H Port 3 register P3 √ 0000H
FFFFF406H Port 3 register L P3L
FFFFF407H Port 3 register H P3H
FFFFF408H Port 4 register P4
FFFFF40AH Port 5 register P5
FFFFF40EH Port 7 register L P7L
FFFFF40FH Port 7 register H P7H
√ √
√ √
√ √
√ √
√ √
√ √
00H
00H
00H
00H
00H
00H
Note
Note
Note
Note
Note
Note
Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.
(4/10)
Note
User’s Manual U17715EJ2V0UD
73
CHAPTER 3 CPU FUNCTION
Manipulatable Bits Address Function Register Name Symbol R/W
Default Value
1 8 16
FFFFF412H Port 9 register P9 √ 0000H
FFFFF412H Port 9 register L P9L
FFFFF413H Port 9 register H P9H
FFFFF420H Port 0 mode register PM0
FFFFF422H Port 1 mode register PM1
FFFFF426H Port 3 mode register PM3
FFFFF426H Port 3 mode register L PM3L
FFFFF427H Port 3 mode register H PM3H
FFFFF428H Port 4 mode register PM4
FFFFF42AH Port 5 mode register PM5
FFFFF42EH Port 7 mode register L PM7L
FFFFF42FH Port 7 mode register H PM7H
FFFFF432H Port 9 mode register PM9
FFFFF432H Port 9 mode register L PM9L
FFFFF433H Port 9 mode register H PM9H
FFFFF440H Port 0 mode control register PMC0
FFFFF446H Port 3 mode control register PMC3
FFFFF446H Port 3 mode control register L PMC3L
FFFFF447H Port 3 mode control register H PMC3H
FFFFF448H Port 4 mode control register PMC4
FFFFF44AH Port 5 mode control register PMC5
FFFFF452H Port 9 mode control register PMC9
FFFFF452H Port 9 mode control register L PMC9L
FFFFF453H Port 9 mode control register H PMC9H
FFFFF460H Port 0 function control register PFC0
FFFFF466H Port 3 function control register PFC3
FFFFF466H Port 3 function control register L PFC3L
FFFFF467H Port 3 function control register H PFC3H
FFFFF468H Port 4 function control register PFC4
FFFFF46AH Port 5 function control register PFC5
FFFFF472H Port 9 function control register PFC9
FFFFF472H Port 9 function control register L PFC9L
FFFFF473H Port 9 function control register H PFC9H
FFFFF484H Data wait control register 0 DWC0
FFFFF488H Address wait control register AWC
FFFFF48AH Bus cycle control register BCC
FFFFF540H TMQ0 control register 0 TQ0CTL0
FFFFF541H TMQ0 control register 1 TQ0CTL1
FFFFF542H TMQ0 I/O control register 0 TQ0IOC0
FFFFF543H TMQ0 I/O control register 1 TQ0IOC1
FFFFF544H TMQ0 I/O control register 2 TQ0IOC2
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Note
00H
Note
00H
FFH
FFH
FFFFH
√
FFH
FFH
FFH
FFH
FFH
FFH
FFFFH
√
FFH
FFH
00H
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
00H
0000H
√
00H
00H
00H
00H
0000H
√
00H
00H
7777H
√
FFFFH
√
AAAAH
√
00H
00H
00H
00H
00H
Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.
(5/10)
Note
74
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Manipulatable BitsAddress Function Register Name Symbol R/W
1 8 16
FFFFF545H TMQ0 option register 0 TQ0OPT0
FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0
FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1
FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2
FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3
FFFFF54EH TMQ0 counter read buffer register TQ0CNT R
FFFFF590H TMP0 control register 0 TP0CTL0
FFFFF591H TMP0 control register 1 TP0CTL1
FFFFF592H TMP0 I/O control register 0 TP0IOC0
FFFFF593H TMP0 I/O control register 1 TP0IOC1
FFFFF594H TMP0 I/O control register 2 TP0IOC2
FFFFF595H TMP0 option register 0 TP0OPT0
FFFFF596H TMP0 capture/compare register 0 TP0CCR0
FFFFF598H TMP0 capture/compare register 1 TP0CCR1
FFFFF59AH TMP0 counter read buffer register TP0CNT R
FFFFF5A0H TMP1 control register 0 TP1CTL0
FFFFF5A1H TMP1 control register 1 TP1CTL1
FFFFF5A2H TMP1 I/O control register 0 TP1IOC0
FFFFF5A3H TMP1 I/O control register 1 TP1IOC1
FFFFF5A4H TMP1 I/O control register 2 TP1IOC2
FFFFF5A5H TMP1 option register 0 TP1OPT0
FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0
FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1
FFFFF5AAH TMP1 counter read buffer register TP1CNT R
FFFFF5B0H TMP2 control register 0 TP2CTL0
FFFFF5B1H TMP2 control register 1 TP2CTL1
FFFFF5B2H TMP2 I/O control register 0 TP2IOC0
FFFFF5B3H TMP2 I/O control register 1 TP2IOC1
FFFFF5B4H TMP2 I/O control register 2 TP2IOC2
FFFFF5B5H TMP2 option register 0 TP2OPT0
FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0
FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1
FFFFF5BAH TMP2 counter read buffer register TP2CNT R
FFFFF5C0H TMP3 control register 0 TP3CTL0
FFFFF5C1H TMP3 control register 1 TP3CTL1
FFFFF5C2H TMP3 I/O control register 0 TP3IOC0
FFFFF5C3H TMP3 I/O control register 1 TP3IOC1
FFFFF5C4H TMP3 I/O control register 2 TP3IOC2
FFFFF5C5H TMP3 option register 0 TP3OPT0
FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0
FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1
FFFFF5CAH TMP3 counter read buffer register TP3CNT R
FFFFF5D0H TMP4 control register 0 TP4CTL0
FFFFF5D1H TMP4 control register 1 TP4CTL1
R/W
R/W
R/W
R/W
R/W
R/W
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
Default Value
00H
0000H
√
0000H
√
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
(6/10)
User’s Manual U17715EJ2V0UD
75
CHAPTER 3 CPU FUNCTION
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
FFFFF5D2H TMP4 I/O control register 0 TP4IOC0
FFFFF5D3H TMP4 I/O control register 1 TP4IOC1
FFFFF5D4H TMP4 I/O control register 2 TP4IOC2
FFFFF5D5H TMP4 option register 0 TP4OPT0
FFFFF5D6H TMP4 capture/compare register 0 TP4CCR0
FFFFF5D8H TMP4 capture/compare register 1 TP4CCR1
FFFFF5DAH TMP4 counter read buffer register TP4CNT R
FFFFF5E0H TMP5 control register 0 TP5CTL0
FFFFF5E1H TMP5 control register 1 TP5CTL1
FFFFF5E2H TMP5 I/O control register 0 TP5IOC0
FFFFF5E3H TMP5 I/O control register 1 TP5IOC1
FFFFF5E4H TMP5 I/O control register 2 TP5IOC2
FFFFF5E5H TMP5 option register 0 TP5OPT0
FFFFF5E6H TMP5 capture/compare register 0 TP5CCR0
FFFFF5E8H TMP5 capture/compare register 1 TP5CCR1
FFFFF5EAH TMP5 counter read buffer register TP5CNT R
FFFFF680H Watch timer operation mode register WTM
FFFFF690H TMM0 control register 0 TM0CTL0
FFFFF694H TMM0 compare register 0 TM0CMP0
FFFFF6C0H Oscillation stabilization time select register OSTS
FFFFF6C1H PLL lockup time specification register PLLS
FFFFF6D0H Watchdog timer mode register 2 WDTM2
FFFFF6D1H Watchdog timer enable register WDTE
FFFFF6E0H Real-time output buffer register 0L RTBL0
FFFFF6E2H Real-time output buffer register 0H RTBH0
FFFFF6E4H Real-time output port mode register 0 RTPM0
FFFFF6E5H Real-time output port control register 0 RTPC0
FFFFF706H Port 3 function control expansion register L PFCE3L
FFFFF70AH Port 5 function control expansion register PFCE5
FFFFF712H Port 9 function control expansion register PFCE9
FFFFF712H Port 9 function control expansion register L PFCE9L
FFFFF713H Port 9 function control expansion register H PFCE9H
FFFFF802H System status register SYS
FFFFF80CH Internal oscillation mode register RCM
FFFFF810H DMA trigger factor register 0 DTFR0
FFFFF812H DMA trigger factor register 1 DTFR1
FFFFF814H DMA trigger factor register 2 DTFR2
FFFFF816H DMA trigger factor register 3 DTFR3
FFFFF820H Power save mode register PSMR
FFFFF822H Clock control register CKC
FFFFF824H Lock register LOCKR R
FFFFF828H Processor clock control register PCC
FFFFF82CH PLL control register PLLCTL
R/W
R/W
R/W
R/W
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ 0000H
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
Default Value
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
00H
00H
00H
00H
0000H
√
0000H
√
00H
00H
0000H
√
06H
03H
67H
9AH
00H
00H
00H
00H
00H
00H
0000H
√
00H
00H
00H
00H
00H
00H
00H
00H
00H
0AH
00H
03H
01H
(7/10)
76
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Manipulatable BitsAddress Function Register Name Symbol R/W
1 8 16
FFFFF82EH CPU operation clock status register CCLS R
Note
R/W
R/W
R/W
R/W
FFFFF870H Clock monitor mode register CLM
FFFFF888H Reset source flag register RESF
FFFFF890H Low-voltage detection register LVIM
FFFFF891H Low-voltage detection level select register LVIS
FFFFF892H Internal RAM data status register RAMS
FFFFF8B0H Prescaler mode register 0 PRSM0
FFFFF8B1H Prescaler compare register 0 PRSCM0
FFFFF9FCH On-chip debug mode register OCDM
FFFFF9FEH Peripheral emulation register 1 PEMU1
FFFFFA00H UARTA0 control register 0 UA0CTL0
FFFFFA01H UARTA0 control register 1 UA0CTL1
FFFFFA02H UARTA0 control register 2 UA0CTL2
FFFFFA03H UARTA0 option control register 0 UA0OPT0
FFFFFA04H UARTA0 status register UA0STR
FFFFFA06H UARTA0 receive data register UA0RX R
FFFFFA07H UARTA0 transmit data register UA0TX
FFFFFA10H UARTA1 control register 0 UA1CTL0
FFFFFA11H UARTA1 control register 1 UA1CTL1
FFFFFA12H UARTA1 control register 2 UA1CTL2
FFFFFA13H UARTA1 option control register 0 UA1OPT0
FFFFFA14H UARTA1 status register UA1STR
FFFFFA16H UARTA1 receive data register UA1RX R
FFFFFA17H UARTA1 transmit data register UA1TX
FFFFFA20H UARTA2 control register 0 UA2CTL0
FFFFFA21H UARTA2 control register 1 UA2CTL1
FFFFFA22H UARTA2 control register 2 UA2CTL2
FFFFFA23H UARTA2 option control register 0 UA2OPT0
FFFFFA24H UARTA2 status register UA2STR
FFFFFA26H UARTA2 receive data register UA2RX R
FFFFFA27H UARTA2 transmit data register UA2TX
FFFFFC00H External interrupt falling edge specification register 0 INTF0
FFFFFC06H External interrupt falling edge specification register 3 INTF3
FFFFFC13H External interrupt falling edge specification register 9H INTF9H
FFFFFC20H External interrupt rising edge specification register 0 INTR0
FFFFFC26H External interrupt rising edge specification register 3 INTR3
FFFFFC33H External interrupt rising edge specification register 9H INTR9H
FFFFFC60H Port 0 function register PF0
FFFFFC66H Port 3 function register PF3
FFFFFC66H Port 3 function register L PF3L
FFFFFC67H Port 3 function register H PF3H
FFFFFC68H Port 4 function register PF4
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
Note Only during emulation
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Default Value
00H
00H
00H
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
0000H
√
00H
00H
00H
(8/10)
User’s Manual U17715EJ2V0UD
77
CHAPTER 3 CPU FUNCTION
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
FFFFFC6AH Port 5 function register PF5
FFFFFC72H Port 9 function register PF9
FFFFFC72H Port 9 function register L PF9L
FFFFFC73H Port 9 function register H PF9H
FFFFFD00H CSIB0 control register 0 CB0CTL0
FFFFFD01H CSIB0 control register 1 CB0CTL1
FFFFFD02H CSIB0 control register 2 CB0CTL2
FFFFFD03H CSIB0 status register CB0STR
FFFFFD04H CSIB0 receive data register CB0RX
FFFFFD04H CSIB0 receive data register L CB0RXL
FFFFFD06H CSIB0 transmit data register CB0TX
FFFFFD06H CSIB0 transmit data register L CB0TXL
FFFFFD10H CSIB1 control register 0 CB1CTL0
FFFFFD11H CSIB1 control register 1 CB1CTL1
FFFFFD12H CSIB1 control register 2 CB1CTL2
FFFFFD13H CSIB1 status register CB1STR
FFFFFD14H CSIB1 receive data register CB1RX
FFFFFD14H CSIB1 receive data register L CB1RXL
FFFFFD16H CSIB1 transmit data register CB1TX
FFFFFD16H CSIB1 transmit data register L CB1TXL
FFFFFD20H CSIB2 control register 0 CB2CTL0
FFFFFD21H CSIB2 control register 1 CB2CTL1
FFFFFD22H CSIB2 control register 2 CB2CTL2
FFFFFD23H CSIB2 status register CB2STR
FFFFFD24H CSIB2 receive data register CB2RX
FFFFFD24H CSIB2 receive data register L CB2RXL
FFFFFD26H CSIB2 transmit data register CB2TX
FFFFFD26H CSIB2 transmit data register L CB2TXL
FFFFFD30H CSIB3 control register 0 CB3CTL0
FFFFFD31H CSIB3 control register 1 CB3CTL1
FFFFFD32H CSIB3 control register 2 CB3CTL2
FFFFFD33H CSIB3 status register CB3STR
FFFFFD34H CSIB3 receive data register CB3RX
FFFFFD34H CSIB3 receive data register L CB3RXL
FFFFFD36H CSIB3 transmit data register CB3TX
FFFFFD36H CSIB3 transmit data register L CB3TXL
FFFFFD40H CSIB4 control register 0 CB4CTL0
FFFFFD41H CSIB4 control register 1
FFFFFD42H CSIB4 control register 2 CB4CTL2
FFFFFD43H CSIB4 status register CB4STR
FFFFFD44H CSIB4 receive data register CB4RX
FFFFFD44H CSIB4 receive data register L CB4RXL
CB4CTL1
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Default Value
00H
0000H
√
00H
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
01H
00H
00H
00H
0000H
√
00H
0000H
√
00H
01H
00H
00H
00H
0000H
√
00H
(9/10)
78
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
Manipulatable BitsAddress Function Register Name Symbol R/W
1 8 16
FFFFFD46H CSIB4 transmit data register CB4TX
FFFFFD46H CSIB4 transmit data register L CB4TXL
FFFFFD80H IIC shift register 0 IIC0
FFFFFD82H IIC control register 0 IICC0
FFFFFD83H Slave address register 0 SVA0
FFFFFD84H IIC clock select register 0 IICCL0
FFFFFD85H IIC function expansion register 0 IICX0
FFFFFD86H IIC status register 0 IICS0 R
FFFFFD8AH IIC flag register 0 IICF0
FFFFFD90H IIC shift register 1 IIC1
FFFFFD92H IIC control register 1 IICC1
FFFFFD93H Slave address register 1 SVA1
FFFFFD94H IIC clock select register 1 IICCL1
FFFFFD95H IIC function expansion register 1 IICX1
FFFFFD96H IIC status register 1 IICS1 R
FFFFFD9AH IIC flag register 1 IICF1
FFFFFDA0H IIC shift register 2 IIC2
FFFFFDA2H IIC control register 2 IICC2
FFFFFDA3H Slave address register 2 SVA2
FFFFFDA4H IIC clock select register 2 IICCL2
FFFFFDA5H IIC function expansion register 2 IICX2
FFFFFDA6H IIC status register 2 IICS2 R
FFFFFDAAH IIC flag register 2 IICF2
FFFFFDBEH External bus interface mode control register EXIMC
R/W
R/W
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√
√
√
√
√
√
√
Default Value
0000H
√
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
(10/10)
User’s Manual U17715EJ2V0UD
79
CHAPTER 3 CPU FUNCTION
3.4.7 Special registers
Special registers are registers that are protected from being written with illegal data due to a program hang-up. The
V850ES/JG2 has the following eight special registers.
• Power save control register (PSC)
• Clock control register (CKC)
• Processor clock control register (PCC)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
• Internal RAM data status register (RAMS)
• On-chip debug mode register (OCDM)
In addition, the PRCDM register is provided to protect against a write access to the special registers so that the
application system does not inadvertently stop due to a program hang-up. A write access to the special registers is
made in a specific sequence, and an illegal store operation is reported to the SYS register.
80
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
(1) Setting data to special registers
Set data to the special registers in the following sequence.
<1> Disable DMA operation.
<2> Prepare data to be set to the special register in a general-purpose register.
<3> Write the data prepared in <2> to the PRCMD register.
<4> Write the setting data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
(<5> to <9> Insert NOP instructions (5 instructions).)
Note
<10> Enable DMA operation if necessary.
[Example] With PSC register (setting standby mode)
ST.B r11, PSMR[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
<1>CLR1 0, DCHCn[r0] ; Disable DMA operation. n = 0 to 3
<2>MOV0x02, r10
<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.
<4>ST.B r10, PSC[r0] ; Set PSC register.
<5>NOP
<6>NOP
<7>NOP
<8>NOP
<9>NOP
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
Note
; Dummy instruction
<10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3
(next instruction)
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2
mode, or STOP mode (by setting the PSC.STP bit to 1).
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are
not acknowledged. This is because it is assumed that steps <3> and <4> above are
performed by successive store instructions. If another instruction is placed between <3>
and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may
not be established, causing malfunction.
2. Although dummy data is written to the PRCMD register, use the same general-purpose
register used to set the special register (<4> in Example) to write data to the PRCMD
register (<3> in Example). The same applies when a general-purpose register is used for
addressing.
User’s Manual U17715EJ2V0UD
81
CHAPTER 3 CPU FUNCTION
(2) Command register (PRCMD)
The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application
system from being written, so that the system does not inadvertently stop due to a program hang-up. The first
write access to a special register is valid after data has been written in advance to the PRCMD register. In this
way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register
from an illegal write access.
The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).
After reset: Undefined W Address: FFFFF1FCH
7
REG7PRCMD
6
REG65REG54REG43REG32REG21REG10REG0
82
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFF802H
SYS 0 0 0 0 0 0 PRERR
0
< >
PRERR
0
Protection error did not occur
1
Protection error occurred
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1)
Setting data to special registers is not the setting of a special register)
Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction)
between an operation to write the PRCMD register and an operation to write a special register,
the PRERR flag is not set, and the set data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0
(the write access takes precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately
after a write access to the PRCMD register, the PRERR bit is set to 1.
Detects protection error
User’s Manual U17715EJ2V0UD
83
CHAPTER 3 CPU FUNCTION
3.4.8 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG2.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-
related registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The
V850ES/JG2 requires wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (fCLK) Set Value of VSWC Number of Waits
32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits)
16.6 MHz ≤ fCLK ≤ 20 MHz 01H 1
(b) On-chip debug mode register (OCDM)
For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register
to activate this operation.
For details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.
84
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait status. If this wait status occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks)
at this time are shown below.
Peripheral Function Register Name Access k
16-bit timer/event counter P (TMP)
(n = 0 to 5)
16-bit timer/event counter Q (TMQ)
Watchdog timer 2 (WDT2) WDTM2
Real-time output function (RTO) RTBL0, RTBH0
A/D converter
I2C00 to I2C02 IICS0 to IICS2 Read 1
TPnCNT Read 1 or 2
TPnCCR0, TPnCCR1
TQ0CNT Read 1 or 2
TQ0CCR0 to TQ0CCR3
ADA0M0 Read 1 or 2
ADA0CR0 to ADA0CR11 Read 1 or 2
ADA0CR0H to ADA0CR11H Read 1 or 2
Write
Read 1 or 2
Write
Read 1 or 2
Write
(when WDT2 operating)
Write
(RTPC0.RTPOE0 bit = 0)
• 1st access: No wait
• Continuous write: 3 or 4
• 1st access: No wait
• Continuous write: 3 or 4
3
1
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is
generated, it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
Remark i: Values (0) of higher 4 bits of VSWC register
j: Values (0 or 1) of lower 4 bits of VSWC register
User’s Manual U17715EJ2V0UD
85
CHAPTER 3 CPU FUNCTION
(3) System reserved area
In the V850ES/JG2, 0000007AH to 0000007FH is a system reserved area for function expansion, and
therefore it is recommended that this area not be used.
00000080H
0000007FH
0000007AH
00000079H
00000070H
System reserved area
Security ID
(10 bytes)
Note
00000000H
Note For the security ID, see 27.3.1 Security ID.
Caution When the data in the flash memory has been deleted, all the bits are cleared to 1.
86
User’s Manual U17715EJ2V0UD
CHAPTER 3 CPU FUNCTION
(4) Restriction on conflict between sld instruction and interrupt request
(a) Description
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld
instruction following an instruction in <1> and an interrupt request before the instruction in <1> is
complete, the execution result of the instruction in <1> may not be stored in a register.
Instruction <1>
• ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu
• sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu
• Multiplication instruction: mul, mulh, mulhi, mulu
Instruction <2>
mov reg1, reg2
satadd reg1, reg2
and reg1, reg2
add reg1, reg2
mulh reg1, reg2
not reg1, reg2
satadd imm5, reg2
tst reg1, reg2
add imm5, reg2
shr imm5, reg2
satsubr reg1, reg2
or reg1, reg2
subr reg1, reg2
cmp reg1, reg2
sar imm5, reg2
<Example>
<i> ld.w [r11], r10 If the decode operation of the mov instruction <ii> immediately before the sld
•
•
•
instruction <iii> and an interrupt request conflict before execution of the ld
instruction <i> is complete, the execution result of instruction <i> may not be
stored in a register.
<ii> mov r10, r28
<iii> sld.w 0x28, r10
(b) Countermeasure
<1> When compiler (CA850) is used
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
<2> For assembler
When executing the sld instruction immediately after instruction <ii>, avoid the above operation using
either of the following methods.
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction <ii>
executed immediately before the sld instruction.
satsub reg1, reg2
xor reg1, reg2
sub reg1, reg2
cmp imm5, reg2
shl imm5, reg2
User’s Manual U17715EJ2V0UD
87
CHAPTER 4 PORT FUNCTIONS
4.1 Features
{ I/O ports: 84
• 5 V tolerant/N-ch open-drain output selectable: 40 (ports 0, 3 to 5, 9)
{ Input/output specifiable in 1-bit units
4.2 Basic Port Configuration
The V850ES/JG2 features a total of 84 I/O ports consisting of ports 0, 1, 3 to 5, 7, 9, CM, CT, DH, and DL. The
port configuration is shown below.
Figure 4-1. Port Configuration Diagram
Port 0
Port 1
Port 3
Port 4
Port 5
Port 7
P02
P06
P10
P11
P30
P39
P40
P42
P50
P55
P70
P711
P90
P915
PCM0
PCM3
PCT0
PCT1
PCT4
PCT6
PDH0
PDH5
PDL0
PDL15
Port 9
Port CM
Port CT
Port DH
Port DL
Caution Ports 0, 3 to 5, and 9 are 5 V tolerant.
Table 4-1. I/O Buffer Power Supplies for Pins
88
Power Supply Corresponding Pins
AVREF0 Port 7
AVREF1 Port 1
BVDD Ports CM, CT, DH (bits 0 to 3), DL
EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5)
User’s Manual U17715EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.3 Port Configuration
Table 4-2. Port Configuration
Item Configuration
Control register
Ports I/O: 84
(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CD, CM, CT, DH, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL)
Port n function control register (PFCn: n = 0, 3 to 5, 9)
Port n function control expansion register (PFCEn: n = 3, 5, 9)
Port n function register (PFn: n = 0, 3 to 5, 9)
After reset: 00H (output latch) R/W
01237567
Pn
Pn7
Pnm
0
1
Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0
Control of output data (in output mode)
Output 0.
Output 1.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Table 4-3. Writing/Reading Pn Register
Setting of PMn Register Writing to Pn Register Reading from Pn Register
Note
Note
.
.
The value of the output latch is read.
The pin status is read.
Output mode
(PMnm = 0)
Input mode
(PMnm = 1)
Data is written to the output latch
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
Data is written to the output latch.
The pin status is not affected
Note The value written to the output latch is retained until a new value is written to the output latch.
User’s Manual U17715EJ2V0UD
89
CHAPTER 4 PORT FUNCTIONS
(2) Port n mode register (PMn)
The PMn register specifies the input or output mode of the corresponding port pin.
Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit
units.
After reset: FFH R/W
PMn
PMn7
PMnm
0
1
PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0
Control of input/output mode
Output mode
Input mode
(3) Port n mode control register (PMCn)
The PMCn register specifies the port mode or alternate function.
Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit
units.
After reset: 00H R/W
PMCn
PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0
PMCnm
0
1
Port mode
Alternate function mode
Specification of operation mode
90
User’s Manual U17715EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
(4) Port n function control register (PFCn)
The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be
specified in 1-bit units.
After reset: 00H R/W
PFCn
PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0
PFCnm
0
1
Alternate function 1
Alternate function 2
Specification of alternate function
(5) Port n function control expansion register (PFCEn)
The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more
alternate functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be
specified in 1-bit units.
After reset: 00H R/W
PFCEn
PFCn
PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0
PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0
PFCEnm
PFCnm
0
0
1
1
0
Alternate function 1
1
Alternate function 2
0
Alternate function 3
1
Alternate function 4
Specification of alternate function
User’s Manual U17715EJ2V0UD
91
CHAPTER 4 PORT FUNCTIONS
(6) Port n function register (PFn)
The PFn register specifies normal output or N-ch open-drain output.
Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified
in 1-bit units.
After reset: 00H R/W
PFn
PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0
PFnm
Note
0
Normal output (CMOS output)
1
N-ch open-drain output
Control of normal output/N-ch open-drain output
Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the
output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode
is specified), the set value of the PFn register is invalid.
92
User’s Manual U17715EJ2V0UD
(7) Port setting
Set a port as illustrated below.
Port mode
CHAPTER 4 PORT FUNCTIONS
Figure 4-2. Setting of Each Register and Pin Function
Output mode
Input mode
Alternate function
(when two alternate
functions are available)
Alternate function 1
Alternate function 2
Alternate function
(when three or more alternate
functions are available)
Alternate function 1
Alternate function 2
Alternate function 3
Alternate function 4
(a)
(b)
(c)
(d)
“0”
“1”
“0”
“1”
PMn register
PFCn register
PFCn register
PFCEn register
“0”
“1”
(a)
(b)
(c)
(d)
PMCn register
PFCEnm
0
0
1
1
PFCnm
0
1
0
1
Remark Set the alternate functions in the following sequence.
<1> Set the PFCn and PFCEn registers.
<2> Set the PFCn register.
<3> Set the INTRn or INTFn register (to specify an external interrupt pin).
If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn
registers are being set.
User’s Manual U17715EJ2V0UD
93
CHAPTER 4 PORT FUNCTIONS
4.3.1 Port 0
Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units.
Port 0 includes the following alternate-function pins.
Table 4-4. Port 0 Alternate-Function Pins
Pin No. Pin Name
GF GC
P02 19 17 NMI Input L-1
P03 20 18 INTP0/ADTRG Input N-1
P04 21 19 INTP1 Input L-1
P05 22 20 INTP2/DRST
P06 23 21 INTP3 Input
Alternate-Function Pin Name I/O Remark Block Type
Selectable as N-ch open-drain output
Note
Input AA-1
L-1
Note The DRST pin is used for on-chip debugging.
If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of
the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0).
For details, see 4.6.3 Cautions on on-chip debug pins.
Caution The P02 to P06 pins have hysteresis characteristics in the input mode of the alternate function,
but do not have hysteresis characteristics in the port mode.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(1) Port 0 register (P0)
After reset: 00H (output latch) R/W Address: FFFFF400H
94
P0n
0
1
0
Output data control (in output mode) (n = 2 to 6)
Outputs 0
Outputs 1
User’s Manual U17715EJ2V0UD
P0 P06 P05 P04 P03 P02 0 0
(2) Port 0 mode register (PM0)
After reset: FFH R/W Address: FFFFF420H
CHAPTER 4 PORT FUNCTIONS
PM0 PM06 PM05 PM04 PM03 PM02 1 1
1
PM0n
0
1
Output mode
Input mode
(3) Port 0 mode control register (PMC0)
After reset: 00H R/W Address: FFFFF440H
0PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 0 0
PMC06
0
I/O port
1
INTP3 input
PMC05
0
I/O port
1
INTP2 input
I/O mode control (n = 2 to 6)
Specification of P06 pin operation mode
Specification of P05 pin operation mode
PMC04
0
1
PMC03
0
1
PMC02
0
1
I/O port
INTP1 input
I/O port
INTP0 input/ADTRG input
I/O port
NMI input
Specification of P04 pin operation mode
Specification of P03 pin operation mode
Specification of P02 pin operation mode
Caution The P05/INTP2/DRST pin becomes the DRST pin regardless of the value of the PMC05 bit
when the OCDM.OCDM0 bit = 1.
User’s Manual U17715EJ2V0UD
95
(4) Port 0 function control register (PFC0)
After reset: 00H R/W Address: FFFFF460H
CHAPTER 4 PORT FUNCTIONS
PFC0
0 0 0 0 PFC03 0 0 0
PFC03
0
1
INTP0 input
ADTRG input
Specification of P03 pin alternate function
(5) Port 0 function register (PF0)
After reset: 00H R/W Address: FFFFFC60H
PF0 PF06 PF05 PF04 PF03 PF02 0 0
0
PF0n
0
1
Control of normal output or N-ch open-drain output (n = 2 to 6)
Normal output (CMOS output)
N-ch open drain output
Caution When an output pin is pulled up at EVDD or higher, be sure to set the PF0n bit to 1.
96
User’s Manual U17715EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.3.2 Port 1
Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units.
Port 1 includes the following alternate-function pins.
Table 4-5. Port 1 Alternate-Function Pins
Pin No. Pin Name
GF GC
P10 5 3 ANO0 Output
P11 6 4 ANO1 Output
Alternate-Function Pin Name I/O Remark Block Type
−
−
A-2
A-2
Caution When the power is turned on, the P10 and P11 pins may output an undefined level temporarily
even during reset.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
(1) Port 1 register (P1)
After reset: 00H (output latch) R/W Address: FFFFF402H
P1 0 0 0 0 0 P11 P10
0
P1n
0
1
Outputs 0
Outputs 1
Output data control (in output mode) (n = 0, 1)
Caution Do not read or write the P1 register during D/A conversion (see 14.4.3 Cautions).
(2) Port 1 mode register (PM1)
After reset: FFH R/W Address: FFFFF422H
PM1 1 1 1 1 1 PM11 PM10
1
PM1n
0
1
I/O mode control (n = 0, 1)
Output mode
Input mode
Cautions 1. When using P1n as the alternate function (ANOn pin output), set the PM1n bit to 1.
2. When using one of the P10 and P11 pins as an I/O port and the other as a D/A output
pin, do so in an application where the port I/O level does not change during D/A
output.
User’s Manual U17715EJ2V0UD
97
CHAPTER 4 PORT FUNCTIONS
4.3.3 Port 3
Port 3 is a 10-bit port for which I/O settings can be controlled in 1-bit units.
Port 3 includes the following alternate-function pins.
Table 4-6. Port 3 Alternate-Function Pins
Pin No. Pin Name
GF GC
P30 27 25 TXDA0/SOB4 Output G-3
P31 28 26 RXDA0/INTP7/SIB4
P32 29 27 ASCKA0/SCKB4/TIP00/TOP00 I/O U-1
P33 30 28 TIP01/TOP01
P34 31 29 TIP10/TOP10
P35 32 30 TIP11/TOP11
P36 33 31
P37 34 32
P38 37 35 TXDA2/SDA00
P39 38 36 RXDA2/SCL00
Alternate-Function Pin Name I/O Remark Block Type
Selectable as N-ch open-drain output
− −
− −
Input N-3
I/O G-1
I/O G-1
I/O G-1
C-1
C-1
I/O G-12
I/O
G-6
Caution The P31 to P35, P38, and P39 pins have hysteresis characteristics in the input mode of the
alternate-function pin, but do not have the hysteresis characteristics in the port mode.
Remark GF: 100-pin plastic QFP (14 × 20)
GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
98
User’s Manual U17715EJ2V0UD
(1) Port 3 register (P3)
After reset: 0000H (output latch) R/W Address: P3 FFFFF406H,
P3 (P3H)
CHAPTER 4 PORT FUNCTIONS
P3L FFFFF406H, P3H FFFFF407H
0 0 0 0 0 0 P39 P38
89101112131415
(P3L)
P37 P36 P35 P34 P33 P32 P31 P30
P3n
0
1
Outputs 0
Outputs 1
Output data control (in output mode) (n = 0 to 9)
Remarks 1. The P3 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the P3 register as the P3H register and the lower 8
bits as the P3L register, P3 can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of
the P3H register.
(2) Port 3 mode register (PM3)
After reset: FFFFH R/W Address: PM3 FFFFF426H,
PM3 (PM3H)
1
1 1 1 1 1 PM39 PM38
PM3L FFFFF426H, PM3H FFFFF427H
89101112131415
(PM3L)
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
0
1
Output mode
Input mode
I/O mode control (n = 0 to 9)
Remarks 1. The PM3 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PM3 register as the PM3H register and the
lower 8 bits as the PM3L register, PM3 can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify them as bits 0 to 7
of the PM3H register.
User’s Manual U17715EJ2V0UD
99
(3) Port 3 mode control register (PMC3)
After reset: 0000H R/W Address: PMC3 FFFFF446H,
PMC3 (PMC3H)
0 0 0 0 0 0 PMC39 PMC38
CHAPTER 4 PORT FUNCTIONS
PMC3L FFFFF446H, PMC3H FFFFF447H
89101112131415
(PMC3L)
0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
PMC39
0
1
PMC38
0
1
PMC35
0
1
PMC34
0
1
PMC33
0
1
I/O port
RXDA2 input/SCL00 I/O
I/O port
TXDA2 output/SDA00 I/O
I/O port
TIP11 input/TOP11 output
I/O port
TIP10 input/TOP10 output
I/O port
TIP01 input/TOP01 output
Specification of P39 pin operation mode
Specification of P38 pin operation mode
Specification of P35 pin operation mode
Specification of P34 pin operation mode
Specification of P33 pin operation mode
PMC32
0
1
PMC31
0
1
PMC30
0
1
I/O port
ASCKA0 input/SCKB4 I/O/TIP00 input/TOP00 output
I/O port
RXDA0 input/SIB4 input/INTP7 input
I/O port
TXDA0 output/SOB4 output
Specification of P32 pin operation mode
Specification of P31 pin operation mode
Specification of P30 pin operation mode
Caution Be sure to clear bits 15 to 10, 7, and 6 to “0”.
Remarks 1. The PMC3 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PMC3 register as the PMC3H register and the
lower 8 bits as the PMC3L register, PMC3 can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify them as bits 0 to
7 of the PMC3H register.
100
User’s Manual U17715EJ2V0UD
Loading...