NEC V850ES-JG2 User Manual
User’s Manual
V850ES/JG2
32-bit Single-Chip Microcontrollers
Hardware
μ
PD70F3715
μ
PD70F3716
μ
PD70F3717
μ
PD70F3718
μ
PD70F3719
Document No. U17715EJ2V0UD00 (2nd edition)
Date Published January 2007 N CP(K)
Printed in Japan
2005
[MEMO]
2
User’s Manual U17715EJ2V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17715EJ2V0UD
3
IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in
the United States of America.
EEPROM is a trademark of NEC Electronics Corporation
Applilet is a registered trademark of NEC Electronics in Japan, Germany, Hong Kong, China, the Republic of
Korea, the United Kingdom, and the United States of America.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.
4
User’s Manual U17715EJ2V0UD
•
The information in this document is current as of August, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
User’s Manual U17715EJ2V0UD
5
PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/JG2 and design application systems using these products.
Purpose This manual is intended to give users an understanding of the hardware functions of
the V850ES/JG2 shown in the Organization below.
Organization This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User’s Manual).
Hardware Architecture
• Pin functions • Data types
• CPU function • Register set
• On-chip peripheral functions • Instruction format and instruction set
• Flash memory programming • Interrupts and exceptions
• Electrical specifications • Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/JG2
→ Read this manual according to the CONTENTS.
To find the details of a register where the name is known
→ Use APPENDIX B REGISTER INDEX.
Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/JG2
→ See CHAPTER 28 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched
by copying an “<R>” in the PDF file and specifying it in the “Find what:” field.
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User’s Manual U17715EJ2V0UD
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on
the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2 (address space, memory capacity):
K (kilo): 2
M (mega): 2
G (giga): 2
10
= 1,024
20
= 1,0242
30
= 1,0243
User’s Manual U17715EJ2V0UD
7
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/JG2
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/JG2 Hardware User’s Manual This manual
Documents related to development tools
Document Name Document No.
QB-V850ESSX2 In-Circuit Emulator U17091E
QB-V850MINI On-Chip Debug Emulator U17638E
QB-MINI2 On-Chip Debug Emulator with Flash Programming Function To be prepared
CA850 Ver. 3.00 C Compiler Package
PM+ Ver. 6.20 Project Manager U17990E
ID850QB Ver. 3.20 Integrated Debugger Operation U17964E
SM850 Ver. 2.50 System Simulator Operation U16218E
SM850 Ver. 2.00 or Later System Simulator External Part User Open
RX850 Ver. 3.20 Real-Time OS
RX850 Pro Ver. 3.20 Real-Time OS
AZ850 Ver. 3.30 System Performance Analyzer U17423E
PG-FP4 Flash Memory Programmer U15260E
Operation U17293E
C Language U17291E
Assembly Language U17292E
Link Directives U17294E
U14873E
Interface Specification
Operation U17246E SM+ System Simulator
User Open Interface U17247E
Basics U13430E
Installation U17419E
Technical U13431E
Task Debugger U17420E
Basics U13773E
Installation U17421E
Technical U13772E
Task Debugger U17422E
8
User’s Manual U17715EJ2V0UD
CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................18
1.1 General .....................................................................................................................................18
1.2 Features....................................................................................................................................21
1.3 Application Fields ...................................................................................................................22
1.4 Ordering Information ..............................................................................................................22
1.5 Pin Configuration (Top View).................................................................................................23
1.6 Function Block Configuration................................................................................................ 26
1.6.1 Internal block diagram ............................................................................................................... 26
1.6.2 Internal units .............................................................................................................................. 27
CHAPTER 2 PIN FUNCTIONS................................................................................................................30
2.1 List of Pin Functions...............................................................................................................30
2.2 Pin States .................................................................................................................................40
2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins........41
2.4 Cautions ...................................................................................................................................45
CHAPTER 3 CPU FUNCTION.................................................................................................................46
3.1 Features....................................................................................................................................46
3.2 CPU Register Set.....................................................................................................................47
3.2.1 Program register set .................................................................................................................. 48
3.2.2 System register set .................................................................................................................... 49
3.3 Operation Modes .....................................................................................................................55
3.3.1 Specifying operation mode ........................................................................................................55
3.4 Address Space ........................................................................................................................56
3.4.1 CPU address space................................................................................................................... 56
3.4.2 Wraparound of CPU address space .......................................................................................... 57
3.4.3 Memory map.............................................................................................................................. 58
3.4.4 Areas .........................................................................................................................................60
3.4.5 Recommended use of address space ....................................................................................... 67
3.4.6 Peripheral I/O registers.............................................................................................................. 70
3.4.7 Special registers ........................................................................................................................ 80
3.4.8 Cautions .................................................................................................................................... 84
CHAPTER 4 PORT FUNCTIONS............................................................................................................88
4.1 Features....................................................................................................................................88
4.2 Basic Port Configuration ........................................................................................................88
4.3 Port Configuration................................................................................................................... 89
4.3.1 Port 0 ......................................................................................................................................... 94
4.3.2 Port 1 ......................................................................................................................................... 97
4.3.3 Port 3 ......................................................................................................................................... 98
4.3.4 Port 4 ....................................................................................................................................... 104
4.3.5 Port 5 ....................................................................................................................................... 106
4.3.6 Port 7 ....................................................................................................................................... 110
4.3.7 Port 9 ....................................................................................................................................... 112
4.3.8 Port CM ................................................................................................................................... 120
4.3.9 Port CT ....................................................................................................................................122
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4.3.10 Port DH....................................................................................................................................124
4.3.11 Port DL ....................................................................................................................................126
4.4 Block Diagrams..................................................................................................................... 129
4.5 Port Register Settings When Alternate Function Is Used ................................................ 159
4.6 Cautions ................................................................................................................................ 167
4.6.1 Cautions on setting port pins ................................................................................................... 167
4.6.2 Cautions on bit manipulation instruction for port n register (Pn)............................................... 170
4.6.3 Cautions on on-chip debug pins............................................................................................... 171
4.6.4 Cautions on P05/INTP2/DRST pin...........................................................................................171
4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ...............................................171
4.6.6 Hysteresis characteristics ........................................................................................................171
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 172
5.1 Features................................................................................................................................. 172
5.2 Bus Control Pins................................................................................................................... 173
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ............... 173
5.2.2 Pin status in each operation mode ........................................................................................... 173
5.3 Memory Block Function....................................................................................................... 174
5.4 External Bus Interface Mode Control Function................................................................. 175
5.5 Bus Access ........................................................................................................................... 176
5.5.1 Number of clocks for access .................................................................................................... 176
5.5.2 Bus size setting function ..........................................................................................................176
5.5.3 Access by bus size ..................................................................................................................177
5.6 Wait Function ........................................................................................................................ 184
5.6.1 Programmable wait function ....................................................................................................184
5.6.2 External wait function ............................................................................................................... 185
5.6.3 Relationship between programmable wait and external wait ...................................................186
5.6.4 Programmable address wait function ....................................................................................... 187
5.7 Idle State Insertion Function ............................................................................................... 188
5.8 Bus Hold Function................................................................................................................ 189
5.8.1 Functional outline.....................................................................................................................189
5.8.2 Bus hold procedure.................................................................................................................. 190
5.8.3 Operation in power save mode ................................................................................................190
5.9 Bus Priority ........................................................................................................................... 191
5.10 Bus Timing ............................................................................................................................ 192
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 198
6.1 Overview................................................................................................................................ 198
6.2 Configuration ........................................................................................................................ 199
6.3 Registers ............................................................................................................................... 201
6.4 Operation............................................................................................................................... 206
6.4.1 Operation of each clock ...........................................................................................................206
6.4.2 Clock output function ...............................................................................................................206
6.5 PLL Function......................................................................................................................... 207
6.5.1 Overview .................................................................................................................................. 207
6.5.2 Registers.................................................................................................................................. 207
6.5.3 Usage ......................................................................................................................................210
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 211
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User’s Manual U17715EJ2V0UD
7.1
Overview.................................................................................................................................211
7.2 Functions ...............................................................................................................................211
7.3 Configuration.........................................................................................................................212
7.4 Registers ................................................................................................................................214
7.5 Operation................................................................................................................................226
7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) ............................................................. 227
7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ................................................. 237
7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ..................................... 245
7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 257
7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 264
7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 273
7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 290
7.5.8 Timer output operations........................................................................................................... 296
7.6 Selector Function ..................................................................................................................297
7.7 Cautions .................................................................................................................................298
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................299
8.1 Overview.................................................................................................................................299
8.2 Functions ...............................................................................................................................299
8.3 Configuration.........................................................................................................................300
8.4 Registers ................................................................................................................................302
8.5 Operation................................................................................................................................318
8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) ............................................................ 319
8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ................................................ 328
8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .................................... 337
8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) ............................................. 350
8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) .............................................................359
8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) ................................................... 370
8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................ 390
8.5.8 Timer output operations........................................................................................................... 396
8.6 Cautions .................................................................................................................................397
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................398
9.1 Overview.................................................................................................................................398
9.2 Configuration.........................................................................................................................399
9.3 Register ..................................................................................................................................400
9.4 Operation................................................................................................................................401
9.4.1 Interval timer mode .................................................................................................................. 401
9.4.2 Cautions .................................................................................................................................. 405
CHAPTER 10 WATCH TIMER FUNCTIONS .......................................................................................406
10.1 Functions ...............................................................................................................................406
10.2 Configuration.........................................................................................................................407
10.3 Control Registers ..................................................................................................................409
10.4 Operation................................................................................................................................413
10.4.1 Operation as watch timer......................................................................................................... 413
10.4.2 Operation as interval timer....................................................................................................... 414
10.4.3 Cautions ..................................................................................................................................415
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2....................................................................416
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11.1
Functions............................................................................................................................... 416
11.2 Configuration ........................................................................................................................ 417
11.3 Registers ............................................................................................................................... 418
11.4 Operation............................................................................................................................... 420
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 421
12.1 Function................................................................................................................................. 421
12.2 Configuration ........................................................................................................................ 422
12.3 Registers ............................................................................................................................... 424
12.4 Operation............................................................................................................................... 426
12.5 Usage ..................................................................................................................................... 427
12.6 Cautions ................................................................................................................................ 427
CHAPTER 13 A/D CONVERTER ......................................................................................................... 428
13.1 Overview................................................................................................................................ 428
13.2 Functions............................................................................................................................... 428
13.3 Configuration ........................................................................................................................ 429
13.4 Registers ............................................................................................................................... 432
13.5 Operation............................................................................................................................... 443
13.5.1 Basic operation ........................................................................................................................ 443
13.5.2 Conversion operation timing ....................................................................................................444
13.5.3 Trigger mode ...........................................................................................................................445
13.5.4 Operation mode ....................................................................................................................... 447
13.5.5 Power-fail compare mode ........................................................................................................ 451
13.6 Cautions ................................................................................................................................ 456
13.7 How to Read A/D Converter Characteristics Table........................................................... 460
CHAPTER 14 D/A CONVERTER ......................................................................................................... 464
14.1 Functions............................................................................................................................... 464
14.2 Configuration ........................................................................................................................ 464
14.3 Registers ............................................................................................................................... 465
14.4 Operation............................................................................................................................... 467
14.4.1 Operation in normal mode .......................................................................................................467
14.4.2 Operation in real-time output mode..........................................................................................467
14.4.3 Cautions...................................................................................................................................468
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 469
15.1 Mode Switching of UARTA and Other Serial Interfaces ................................................... 469
15.1.1 CSIB4 and UARTA0 mode switching....................................................................................... 469
15.1.2 UARTA2 and I2C00 mode switching.........................................................................................470
15.1.3 UARTA1 and I2C02 mode switching.........................................................................................471
15.2 Features................................................................................................................................. 472
15.3 Configuration ........................................................................................................................ 473
15.4 Registers ............................................................................................................................... 475
15.5 Interrupt Request Signals.................................................................................................... 481
15.6 Operation............................................................................................................................... 482
15.6.1 Data format..............................................................................................................................482
15.6.2 SBF transmission/reception format..........................................................................................484
15.6.3 SBF transmission.....................................................................................................................486
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User’s Manual U17715EJ2V0UD
15.6.4 SBF reception.......................................................................................................................... 487
15.6.5 UART transmission.................................................................................................................. 488
15.6.6 Continuous transmission procedure ........................................................................................489
15.6.7 UART reception....................................................................................................................... 491
15.6.8 Reception errors ...................................................................................................................... 492
15.6.9 Parity types and operations ..................................................................................................... 494
15.6.10 Receive data noise filter ..........................................................................................................495
15.7 Dedicated Baud Rate Generator .......................................................................................... 496
15.8 Cautions .................................................................................................................................504
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................505
16.1 Mode Switching of CSIB and Other Serial Interfaces........................................................ 505
16.1.1 CSIB4 and UARTA0 mode switching ...................................................................................... 505
16.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 506
16.2 Features..................................................................................................................................507
16.3 Configuration.........................................................................................................................508
16.4 Registers ................................................................................................................................510
16.5 Interrupt Request Signals.....................................................................................................517
16.6 Operation................................................................................................................................518
16.6.1 Single transfer mode (master mode, transmission mode) .......................................................518
16.6.2 Single transfer mode (master mode, reception mode)............................................................. 520
16.6.3 Single transfer mode (master mode, transmission/reception mode)........................................ 522
16.6.4 Single transfer mode (slave mode, transmission mode).......................................................... 524
16.6.5 Single transfer mode (slave mode, reception mode) ...............................................................526
16.6.6 Single transfer mode (slave mode, transmission/reception mode) ..........................................528
16.6.7 Continuous transfer mode (master mode, transmission mode) ............................................... 530
16.6.8 Continuous transfer mode (master mode, reception mode)..................................................... 532
16.6.9 Continuous transfer mode (master mode, transmission/reception mode)................................ 535
16.6.10 Continuous transfer mode (slave mode, transmission mode).................................................. 539
16.6.11 Continuous transfer mode (slave mode, reception mode) ....................................................... 541
16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .................................. 544
16.6.13 Reception error........................................................................................................................ 548
16.6.14 Clock timing............................................................................................................................. 549
16.7 Output Pins ............................................................................................................................551
16.8 Baud Rate Generator ............................................................................................................552
16.8.1 Baud rate generation ............................................................................................................... 553
16.9 Cautions .................................................................................................................................554
CHAPTER 17 I2C BUS...........................................................................................................................555
17.1 Mode Switching of I2C Bus and Other Serial Interfaces ....................................................555
17.1.1 UARTA2 and I2C00 mode switching ........................................................................................555
17.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 556
17.1.3 UARTA1 and I2C02 mode switching ........................................................................................557
17.2 Features..................................................................................................................................558
17.3 Configuration.........................................................................................................................559
17.4 Registers ................................................................................................................................563
17.5 I2C Bus Mode Functions .......................................................................................................579
17.5.1 Pin configuration...................................................................................................................... 579
17.6 I2C Bus Definitions and Control Methods ...........................................................................580
17.6.1 Start condition.......................................................................................................................... 580
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17.6.2 Addresses................................................................................................................................ 581
17.6.3 Transfer direction specification ................................................................................................582
17.6.4 ACK .........................................................................................................................................583
17.6.5 Stop condition .......................................................................................................................... 584
17.6.6 Wait state................................................................................................................................. 585
17.6.7 Wait state cancellation method ................................................................................................ 587
17.7 I2C Interrupt Request Signals (INTIICn) .............................................................................. 588
17.7.1 Master device operation...........................................................................................................588
17.7.2 Slave device operation (when receiving slave address data (address match))........................ 591
17.7.3 Slave device operation (when receiving extension code) ........................................................595
17.7.4 Operation without communication............................................................................................ 599
17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................599
17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................601
17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 608
17.9 Address Match Detection Method ...................................................................................... 610
17.10 Error Detection...................................................................................................................... 610
17.11 Extension Code..................................................................................................................... 610
17.12 Arbitration ............................................................................................................................. 611
17.13 Wakeup Function.................................................................................................................. 612
17.14 Communication Reservation............................................................................................... 613
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................613
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................617
17.15 Cautions ................................................................................................................................ 618
17.16 Communication Operations................................................................................................. 619
17.16.1 Master operation in single master system ................................................................................620
17.16.2 Master operation in multimaster system ...................................................................................621
17.16.3 Slave operation........................................................................................................................624
17.17 Timing of Data Communication .......................................................................................... 627
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 634
18.1 Features................................................................................................................................. 634
18.2 Configuration ........................................................................................................................ 635
18.3 Registers ............................................................................................................................... 636
18.4 Transfer Targets ................................................................................................................... 643
18.5 Transfer Modes..................................................................................................................... 643
18.6 Transfer Types...................................................................................................................... 644
18.7 DMA Channel Priorities........................................................................................................ 645
18.8 Time Related to DMA Transfer ............................................................................................ 645
18.9 DMA Transfer Start Factors................................................................................................. 646
18.10 DMA Abort Factors ............................................................................................................... 647
18.11 End of DMA Transfer ............................................................................................................ 647
18.12 Operation Timing .................................................................................................................. 647
18.13 Cautions ................................................................................................................................ 652
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 657
19.1 Features................................................................................................................................. 657
19.2 Non-Maskable Interrupts ..................................................................................................... 661
19.2.1 Operation................................................................................................................................. 663
19.2.2 Restore ....................................................................................................................................664
19.2.3 NP flag.....................................................................................................................................665
14
User’s Manual U17715EJ2V0UD
19.3
Maskable Interrupts ..............................................................................................................666
19.3.1 Operation................................................................................................................................. 666
19.3.2 Restore.................................................................................................................................... 668
19.3.3 Priorities of maskable interrupts ..............................................................................................669
19.3.4 Interrupt control register (xxICn) .............................................................................................. 673
19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................ 675
19.3.6 In-service priority register (ISPR)............................................................................................. 677
19.3.7 ID flag ...................................................................................................................................... 678
19.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................678
19.4 Software Exception...............................................................................................................679
19.4.1 Operation................................................................................................................................. 679
19.4.2 Restore.................................................................................................................................... 680
19.4.3 EP flag..................................................................................................................................... 681
19.5 Exception Trap ......................................................................................................................682
19.5.1 Illegal opcode .......................................................................................................................... 682
19.5.2 Debug trap............................................................................................................................... 684
19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) .................................... 686
19.6.1 Noise elimination ..................................................................................................................... 686
19.6.2 Edge detection......................................................................................................................... 686
19.7 Interrupt Acknowledge Time of CPU...................................................................................691
19.8 Periods in Which Interrupts Are Not Acknowledged by CPU...........................................692
19.9 Cautions .................................................................................................................................692
CHAPTER 20 KEY INTERRUPT FUNCTION ......................................................................................693
20.1 Function .................................................................................................................................693
20.2 Register ..................................................................................................................................694
20.3 Cautions .................................................................................................................................694
CHAPTER 21 STANDBY FUNCTION................................................................................................... 695
21.1 Overview.................................................................................................................................695
21.2 Registers ................................................................................................................................697
21.3 HALT Mode.............................................................................................................................700
21.3.1 Setting and operation status .................................................................................................... 700
21.3.2 Releasing HALT mode ............................................................................................................ 700
21.4 IDLE1 Mode............................................................................................................................702
21.4.1 Setting and operation status .................................................................................................... 702
21.4.2 Releasing IDLE1 mode............................................................................................................ 702
21.5 IDLE2 Mode............................................................................................................................704
21.5.1 Setting and operation status .................................................................................................... 704
21.5.2 Releasing IDLE2 mode............................................................................................................ 704
21.5.3 Securing setup time when releasing IDLE2 mode ................................................................... 706
21.6 STOP Mode ............................................................................................................................707
21.6.1 Setting and operation status .................................................................................................... 707
21.6.2 Releasing STOP mode............................................................................................................ 707
21.6.3 Securing oscillation stabilization time when releasing STOP mode......................................... 710
21.7 Subclock Operation Mode....................................................................................................711
21.7.1 Setting and operation status .................................................................................................... 711
21.7.2 Releasing subclock operation mode........................................................................................ 711
21.8 Sub-IDLE Mode......................................................................................................................713
21.8.1 Setting and operation status .................................................................................................... 713
User’s Manual U17715EJ2V0UD
15
21.8.2 Releasing sub-IDLE mode ....................................................................................................... 713
CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 715
22.1 Overview................................................................................................................................ 715
22.2 Registers to Check Reset Source....................................................................................... 716
22.3 Operation............................................................................................................................... 717
22.3.1 Reset operation via RESET pin ...............................................................................................717
22.3.2 Reset operation by watchdog timer 2.......................................................................................719
22.3.3 Reset operation by low-voltage detector..................................................................................721
22.3.4 Operation after reset release ...................................................................................................722
22.3.5 Reset function operation flow................................................................................................... 725
CHAPTER 23 CLOCK MONITOR ........................................................................................................ 726
23.1 Functions............................................................................................................................... 726
23.2 Configuration ........................................................................................................................ 726
23.3 Register ................................................................................................................................. 727
23.4 Operation............................................................................................................................... 728
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) ............................................................................. 731
24.1 Functions............................................................................................................................... 731
24.2 Configuration ........................................................................................................................ 731
24.3 Registers ............................................................................................................................... 732
24.4 Operation............................................................................................................................... 734
24.4.1 To use for internal reset signal.................................................................................................734
24.4.2 To use for interrupt ..................................................................................................................735
24.5 RAM Retention Voltage Detection Operation .................................................................... 736
24.6 Emulation Function .............................................................................................................. 737
CHAPTER 25 REGULATOR ................................................................................................................. 738
25.1 Outline 738
25.2 Operation............................................................................................................................... 739
CHAPTER 26 FLASH MEMORY.......................................................................................................... 740
26.1 Features................................................................................................................................. 740
26.2 Memory Configuration ......................................................................................................... 741
26.3 Functional Outline ................................................................................................................ 742
26.4 Rewriting by Dedicated Flash Programmer....................................................................... 745
26.4.1 Programming environment....................................................................................................... 745
26.4.2 Communication mode..............................................................................................................746
26.4.3 Flash memory control ..............................................................................................................754
26.4.4 Selection of communication mode ...........................................................................................755
26.4.5 Communication commands .....................................................................................................756
26.4.6 Pin connection .........................................................................................................................757
26.5 Rewriting by Self Programming.......................................................................................... 761
26.5.1 Overview.................................................................................................................................. 761
26.5.2 Features...................................................................................................................................762
26.5.3 Standard self programming flow ..............................................................................................763
26.5.4 Flash functions.........................................................................................................................764
26.5.5 Pin processing .........................................................................................................................764
16
User’s Manual U17715EJ2V0UD
26.5.6 Internal resources used ........................................................................................................... 765
CHAPTER 27 ON-CHIP DEBUG FUNCTION......................................................................................766
27.1 Debugging with DCU.............................................................................................................767
27.1.1 Connection circuit example ........................................................................................................767
27.1.2 Interface signals .........................................................................................................................767
27.1.3 Maskable functions..................................................................................................................... 769
27.1.4 Register...................................................................................................................................... 769
27.1.5 Operation ................................................................................................................................... 771
27.1.6 Cautions ..................................................................................................................................... 771
27.2 Debugging Without Using DCU ...........................................................................................773
27.2.1 Circuit connection examples ...................................................................................................... 773
27.2.2 Maskable functions..................................................................................................................... 774
27.2.3 Securement of user resources ...................................................................................................775
27.2.4 Cautions ..................................................................................................................................... 781
27.3 ROM Security Function...........................................................................................................783
27.3.1 Security ID.................................................................................................................................. 783
27.3.2 Setting........................................................................................................................................ 784
CHAPTER 28 ELECTRICAL SPECIFICATIONS..................................................................................786
CHAPTER 29 PACKAGE DRAWINGS................................................................................................. 821
<R>
<R>
<R>
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS ...........................................................823
APPENDIX A DEVELOPMENT TOOLS ...............................................................................................824
A.1 Software Package..................................................................................................................826
A.2 Language Processing Software...........................................................................................826
A.3 Control Software ...................................................................................................................826
A.4 Debugging Tools (Hardware) ...............................................................................................827
A.4.1 When using IECUBE QB-V850ESSX2 .................................................................................... 827
A.4.2 When using MINICUBE QB-V850MINI .................................................................................... 830
A.4.3 When using MINICUBE2 QB-MINI2 ........................................................................................831
A.5 Debugging Tools (Software) ................................................................................................ 832
A.6 Embedded Software..............................................................................................................833
A.7 Flash Memory Writing Tools ................................................................................................834
APPENDIX B REGISTER INDEX ..........................................................................................................835
APPENDIX C INSTRUCTION SET LIST..............................................................................................845
C.1 Conventions........................................................................................................................... 845
C.2 Instruction Set (in Alphabetical Order) ...............................................................................848
APPENDIX D LIST OF CAUTIONS......................................................................................................855
<R>
APPENDIX E REVISION HISTORY ......................................................................................................891
E.1 Major Revisions in This Edition...............................................................................................891
User’s Manual U17715EJ2V0UD
17
CHAPTER 1 INTRODUCTION
The V850ES/JG2 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low-
power operation for real-time control applications.
1.1 General
The V850ES/JG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral
functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG2 features
multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware
multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the
V850ES/JG2 enables an extremely high cost-performance for applications that require low power consumption, such
as home audio, printers, and digital home electronics.
Table 1-1 lists the products of the V850ES/JG2.
A model of the V850ES/JG2 with expanded I/O, timer/counter, and serial interface functions, V850ES/JJ2, is also
available. See Table 1-2 V850ES/JJ2 Product List.
18
User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
Table 1-1. V850ES/JG2 Product List
Part Number
Internal
memory
Memory
space
Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB
RAM 12 KB 24 KB 32 KB 40 KB 48 KB
Logical space 64 MB
External memory area 16 MB
External bus interface
μ
PD70F3715
Address bus: 22 bits
μ
PD70F3716
μ
PD70F3717
μ
PD70F3718
μ
PD70F3719
Data bus: 8/16 bits
Multiplex bus mode/separate bus mode
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Ceramic/crystal/external clock
(in PLL mode: f
in clock through mode: f
X = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8),
X = 2.5 to 10 MHz)
Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz)
Internal oscillator fR = 200 kHz (TYP.)
Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz)
DSP function
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O port I/O: 84 (5 V tolerant/N-ch open-drain output selectable: 40)
Timer
16-bit timer/event counter P: 6 channels
16-bit timer/event counter Q: 1 channel
16-bit interval timer M: 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
Real-time output port 6 bits × 1 channel
A/D converter 10-bit resolution × 12 channels
D/A converter 8-bit resolution × 2 channels
Serial interface
UART/CSI: 1 channel
2
UART/ I
C bus: 2 channels
CSI: 3 channels
2
C bus: 1 channel
CSI/I
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source External: 9 (9)
Note
, internal: 48
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-DLE mode
Reset RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
DCU Provided (RUN/break)
Operating power supply voltage 2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
100-pin plastic LQFP (fine pitch) (14 × 14 mm) Package
100-pin plastic QFP (14 × 20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
User’s Manual U17715EJ2V0UD
19
CHAPTER 1 INTRODUCTION
Table 1-2. V850ES/JJ2 Product List
Part Number
Internal
memory
Memory
space
Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB
RAM 12 KB 24 KB 32 KB 40 KB 48 KB
Logical space 64 MB
External memory area 16 MB
External bus interface
μ
PD70F3720
Address bus: 24 bits
μ
PD70F3721
μ
PD70F3722
μ
PD70F3723
μ
PD70F3724
Data bus: 8/16 bits
Multiplex bus mode/separate bus mode
Chip select signal: 4
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Ceramic/crystal/external clock
(in PLL mode: f
in clock through mode: f
X = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8),
X = 2.5 to 10 MHz)
Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz)
Internal oscillator fR = 200 kHz (TYP.)
Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz)
DSP function
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O port I/O: 128 (5 V tolerant/N-ch open-drain output selectable: 60)
Timer
16-bit timer/event counter P: 9 channels
16-bit timer/event counter Q: 1 channel
16-bit interval timer M: 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
Real-time output port 6 bits × 2 channels
A/D converter 10-bit resolution × 16 channels
D/A converter 8-bit resolution × 2 channels
Serial interface
UART: 1 channel
UART/CSI: 1 channel
2
UART/ I
C bus: 2 channels
CSI: 4 channels
2
C bus: 1 channel
CSI/I
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source External: 10 (10)
Note
, internal: 61
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
DCU Provided (RUN/break)
Operating power supply voltage 2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
Package 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
20
User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
1.2 Features
{ Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz)
{ General-purpose registers: 32 bits × 32 registers
{ CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space: 64 MB of linear address space (for programs and data)
External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
• Internal memory: RAM: 12/24/32/40/48 KB (see Table 1-1)
Flash memory: 128/256/384/512/640 KB (see Table 1-1)
• External bus interface: Separate bus/multiplexed bus output selectable
8/16 bit data bus sizing function
Wait function
• Programmable wait function
• External wait function
Idle state function
Bus hold function
{ Interrupts and exceptions: Non-maskable interrupts: 2 sources
Maskable interrupts: 55 sources
Software exceptions: 32 sources
Exception trap: 2 sources
{ I/O lines: I/O ports: 84
{ Timer function: 16-bit interval timer M (TMM): 1 channel
16-bit timer/event counter P (TMP): 6 channels
16-bit timer/event counter Q (TMQ): 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
{ Real-time output port: 6 bits × 1 channel
{ Serial interface: Asynchronous serial interface A (UARTA)
3-wire variable-length serial interface B (CSIB)
I
UARTA/CSIB: 1 channel
UARTA/I
CSIB/I
CSIB: 3 channels
{ A/D converter: 10-bit resolution: 12 channels
{ D/A converter: 8-bit resolution: 2 channels
{ DMA controller: 4 channels
{ DCU (debug control unit): JTAG interface
{ Clock generator: During main clock or subclock operation
7-level CPU clock (f
Clock-through mode/PLL mode selectable
2
C bus interface (I2C)
2
C: 2 channels
2
C: 1 channel
XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
User’s Manual U17715EJ2V0UD
21
CHAPTER 1 INTRODUCTION
{ Internal oscillation clock: 200 kHz (TYP.)
{ Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ Package: 100-pin plastic QFP (14 × 20) (
100-pin plastic LQFP (fine pitch) (14 × 14)
μ
PD70F3715, 70F3716, 70F3717 only)
1.3 Application Fields
Home audio, printers, digital home electronics, other consumer devices
1.4 Ordering Information
Part Number Package Internal Flash Memory
μ
PD70F3715GF-JBT-A
μ
PD70F3715GC-8EA-A
μ
PD70F3716GF-JBT-A
μ
PD70F3716GC-8EA-A
μ
PD70F3717GF-JBT-A
μ
PD70F3717GC-8EA-A
μ
PD70F3718GC-8EA-A
μ
PD70F3719GC-8EA-A
Remark Products with -A at the end of the part number are lead-free products.
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
128 KB
128 KB
256 KB
256 KB
384 KB
384 KB
512 KB
640 KB
22
User’s Manual U17715EJ2V0UD
1.5 Pin Configuration (Top View)
100-pin plastic QFP (14 × 20)
μ
PD70F3715GF-JBT-A
μ
CHAPTER 1 INTRODUCTION
PD70F3716GF-JBT-A
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDH1/A17
PDH0/A16
PDL15/AD15
PDL14/AD14
99989796959493929190898887868584838281
100
μ
PD70F3717GF-JBT-A
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
P71/ANI1
P70/ANI0
AV
REF0
AVSS
P10/ANO0
P11/ANO1
AV
REF1
PDH4/A20
PDH5/A21
Note 1
FLMD0
VDD
Note 2
REGC
VSS
X1
X2
RESET
XT1
XT2
P03/INTP0/ADTRG
P41/SOB0/SCL01
P30/TXDA0/SOB4
P32/ASCKA0/SCKB4/TIP00/TOP00
P31/RXDA0/INTP7/SIB4
P33/TIP01/TOP01
P02/NMI
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/SDA01
P42/SCKB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
SS
P36
P37
EV
EVDD
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BV
DD
BVSS
PCT6/ASTB
PCT4/RD
PCT1/WR1
PCT0/WR0
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PDH3/A19
PDH2/A18
P915/A15/INTP6/TIP50/TOP50
P914/A14/INTP5/TIP51/TOP51
P913/A13/INTP4
P912/A12/SCKB3
P911/A11/SOB3
P910/A10/SIB3
P99/A9/SCKB1
P98/A8/SOB1
P97/A7/SIB1/TIP20/TOP20
P96/A6/TIP21/TOP21
P34/TIP10/TOP10
P35/TIP11/TOP11
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to V
SS via a 4.7
User’s Manual U17715EJ2V0UD
P38/TXDA2/SDA00
P39/RXDA2/SCL00
P90/A0/KR6/TXDA1/SDA02
P54/SOB2/KR4/RTP04/DCK
P50/TIQ01/KR0/TOQ01/RTP00
P51/TIQ02/KR1/TOQ02/RTP01
μ
F capacitor.
P55/SCKB2/KR5/RTP05/DMS
P52/TIQ03/KR2/TOQ03/RTP02/DDI
P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO
P92/A2/TIP41/TOP41
P93/A3/TIP40/TOP40
P94/A4/TIP31/TOP31
P95/A5/TIP30/TOP30
P91/A1/KR7/RXDA1/SCL02
23
100-pin plastic LQFP (fine pitch) (14 × 14)
μ
PD70F3715GC-8EA-A
μ
PD70F3716GC-8EA-A
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
CHAPTER 1 INTRODUCTION
μ
PD70F3717GC-8EA-A
μ
PD70F3718GC-8EA-A
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDH1/A17
PDH0/A16
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
μ
PD70F3719GC-8EA-A
PDL8/AD8
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
AV
REF0
AV
P10/ANO0
P11/ANO1
AV
REF1
PDH4/A20
PDH5/A21
Note 1
FLMD0
V
Note 2
REGC
V
X1
X2
RESET
XT1
XT2
P03/INTP0/ADTRG
P41/SOB0/SCL01
P30/TXDA0/SOB4
P02/NMI
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/SDA01
P42/SCKB0
9998979695949392919089888786858483828180797877
100
1
SS
DD
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
SS
DD
P36
P37
EV
EV
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BV
DD
BV
SS
PCT6/ASTB
PCT4/RD
PCT1/WR1
PCT0/WR0
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PDH3/A19
PDH2/A18
P915/A15/INTP6/TIP50/TOP50
P914/A14/INTP5/TIP51/TOP51
P913/A13/INTP4
P912/A12/SCKB3
P911/A11/SOB3
P910/A10/SIB3
P99/A9/SCKB1
P98/A8/SOB1
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
P31/RXDA0/INTP7/SIB4
P32/ASCKA0/SCKB4/TIP00/TOP00
P38/TXDA2/SDA00
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to V
SS via a 4.7
24
User’s Manual U17715EJ2V0UD
P39/RXDA2/SCL00
P50/TIQ01/KR0/TOQ01/RTP00
μ
P54/SOB2/KR4/RTP04/DCK
P51/TIQ02/KR1/TOQ02/RTP01
P52/TIQ03/KR2/TOQ03/RTP02/DDI
P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO
F capacitor.
P92/A2/TIP41/TOP41
P93/A3/TIP40/TOP40
P90/A0/KR6/TXDA1/SDA02
P91/A1/KR7/RXDA1/SCL02
P55/SCKB2/KR5/RTP05/DMS
P94/A4/TIP31/TOP31
P95/A5/TIP30/TOP30
P96/A6/TIP21/TOP21
P97/A7/SIB1/TIP20/TOP20
Pin names
A0 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI11:
ANO0, ANO1:
ASCKA0:
ASTB:
AV
REF0, AVREF1:
AV
SS:
BVDD:
BV
SS:
CLKOUT:
DCK:
DDI:
DDO:
DMS:
DRST:
EV
DD:
EVSS:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
INTP0 to INTP7:
KR0 to KR7:
NMI:
P02 to P06:
P10, P11:
P30 to P39:
P40 to P42:
P50 to P55:
P70 to P711:
P90 to P915:
PCM0 to PCM3:
PCT0, PCT1,
PCT4, PCT6:
CHAPTER 1 INTRODUCTION
Address bus
Address/data bus
A/D trigger input
Analog input
Analog output
Asynchronous serial clock
Address strobe
Analog reference voltage
Analog V
SS
Power supply for bus interface
Ground for bus interface
Clock output
Debug clock
Debug data input
Debug data output
Debug mode select
Debug reset
Power supply for port
Ground for port
Flash programming mode
Hold acknowledge
Hold request
External interrupt input
Key return
Non-maskable interrupt request
Port 0
Port 1
Port 3
Port 4
Port 5
Port 7
Port 9
Port CM
Port CT
PDH0 to PDH5:
PDL0 to PDL15:
RD:
REGC:
RESET:
RTP00 to RTP05:
RXDA0 to RXDA2:
SCKB0 to SCKB4:
SCL00 to SCL02:
SDA00 to SDA02:
SIB0 to SIB4:
SOB0 to SOB4:
TIP00, TIP01,
TIP10, TIP11,
TIP20, TIP21,
TIP30, TIP31,
TIP40, TIP41,
TIP50, TIP51,
TIQ00 to TIQ03:
TOP00, TOP01,
TOP10, TOP11,
TOP20, TOP21,
TOP30, TOP31,
TOP40, TOP41,
TOP50, TOP51,
TOQ00 to TOQ03:
TXDA0 to TXDA2:
V
DD:
V
SS:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Port DH
Port DL
Read strobe
Regulator control
Reset
Real-time output port
Receive data
Serial clock
Serial clock
Serial data
Serial input
Serial output
Timer input
Timer output
Transmit data
Power supply
Ground
Wait
Lower byte write strobe
Upper byte write strobe
Crystal for main clock
Crystal for subclock
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1.6 Function Block Configuration
1.6.1 Internal block diagram
NMI
INTP0 to INTP7
TIQ00 to TIQ03
TOQ00 to TOQ03
TIP00 to TIP50,
TIP01 to TIP51
TOP00 to TOP50,
TOP01 to TOP51
INTC
16-bit timer/
counter Q:
1 ch
16-bit timer/
counter P:
6 ch
16-bit interval
timer M:
1 ch
CHAPTER 1 INTRODUCTION
ROM
Note 1
RAM
Note 2
DMAC
PC
32-bit barrel
shifter
System
registers
General-purpose
registers 32 bits × 32
CPU
Multiplier
16 × 16 → 32
ALU
Instruction
queue
BCU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
A0 to A21
AD0 to AD15
RTP00 to RTP05
RTO
Ports
SOB0/SCL01
SIB0/SDA01
SCKB0
SOB1
SIB1
SCKB1
SOB2
SIB2
SCKB2
SOB3
SIB3
SCKB3
TXDA0/SOB4
RXDA0/SIB4
ASCKA0/SCKB4
TXDA1/SDA02
RXDA1/SCL02
TXDA2/SDA00
RXDA2/SCL00
CSIB0 I2C01
CSIB1
CSIB2
CSIB3
UARTA0
CSIB4
I2C02
UARTA1
I2C00
UARTA2
P50 to P55
P90 to P915
P70 to P711
PDH0 to PDH5
PCM0 to PCM3
PDL0 to PDL15
PCT0, PCT1, PCT4, PCT6
A/D
converter
D/A
converter
Key return
function
Watchdog
timer 2
Watch timer
Notes 1. 128/256/384/512/640 KB (flash memory) (see Table 1-1)
2. 12/24/32/40/48 KB (see Table 1-1)
P10, P11
P40 to P42
P30 to P39
P02 to P06
ANI0 to ANI11
AV
SS
AV
REF0
ADTRG
AV
REF1
ANO0, ANO1
KR0 to KR7
Internal
oscillator
CLM
DCU
CG
PLL
LVI
Regulator
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
FLMD0
FLMD1
DD
BV
BV
SS
EV
DD
EV
SS
DRST
DMS
DDI
DCK
DDO
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User’s Manual U17715EJ2V0UD
CHAPTER 1 INTRODUCTION
1.6.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits) contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue.
(3) ROM
This is a 640/512/384/256/128 KB flash memory mapped to addresses 0000000H to 009FFFFH/0000000H to
007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH/0000000H to 001FFFFH.
It can be accessed from the CPU in one clock during instruction fetch.
(4) RAM
This is a 48/40/32/24/12 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to
3FFEFFFH/3FF7000H to 3FFEFFFH/3FF9000H to 3FFEFFFH/3FFC000H to 3FFEFFFH. It can be accessed
from the CPU in one clock during data access.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiplexed servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency
(f
X) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as
the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4 or 8.
The CPU clock frequency (f
CPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-
channel 16-bit interval timer M (TMM), are provided on chip.
(9) Watch timer
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the
32.768 kHz clock f
BRG from prescaler 3). The watch timer can also be used as an interval timer for the main
clock.
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(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/JG2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire
variable-length serial interface B (CSIB), and an I
In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.
In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to
SCKB4 pins.
In the case of I
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
(12) A/D converter
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
(13) D/A converter
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
(14) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(15) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
(16) Real-time output function
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer
compare register match signal.
(17) DCU (debug control unit)
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is
provided. Switching between the normal port function and on-chip debugging function is done with the
control pin input level and the OCDM register.
CHAPTER 1 INTRODUCTION
2
C bus interface (I2C).
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User’s Manual U17715EJ2V0UD
(18) Ports
CHAPTER 1 INTRODUCTION
The following general-purpose port functions and control pin functions are available.
Port I/O Alternate Function
P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset
P1 2-bit I/O D/A converter analog output
P3 10-bit I/O External interrupt, serial interface, timer I/O
P4 3-bit I/O Serial interface
P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O
P7 12-bit I/O A/D converter analog input
P9 16-bit I/O External address bus, serial interface, key interrupt input, timer I/O, external interrupt
PCM 4-bit I/O External control signal
PCT 4-bit I/O External control signal
PDH 6-bit I/O External address bus
PDL 16-bit I/O External address/data bus
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CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
The names and functions of the pins in the V850ES/JG2 are described below.
There are four types of pin I/O buffer power supplies: AV
these power supplies and the pins is described below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 Port 7
AVREF1 Port 1
BVDD Ports CM, CT, DH (bits 0 to 3), DL
EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5)
REF0, AVREF1, BVDD, and EVDD. The relationship between
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User’s Manual U17715EJ2V0UD
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