NEC V850ES-IE2 User Manual
μ
User’s Manual
V850ES/IE2
32-bit Single-Chip Microcontrollers
Hardware
PD70F3713
μ
PD70F3714
Document No. U17716EJ2V0UD00 (2nd edition)
Date Published February 2008 N
Printed in Japan
2005
[MEMO]
2
User’s Manual U17716EJ2V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17716EJ2V0UD
3
•
The information in this document is current as of January, 2008. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
•
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
•
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics
(as defined above).
M8E 02. 11-1
4
User’s Manual U17716EJ2V0UD
PREFACE
Readers This manual is intended for users who wish to understand the functions of the
V850ES/IE2 to design application systems using the V850ES/IE2.
Purpose This manual is intended to give users an understanding of the hardware functions.
Organization The V850ES/IE2 User’s Manual is divided into two parts: Hardware (this manual) and
Architecture (V850ES Architecture User’s Manual). The organization of each manual
is as follows:
Hardware Architecture
• Pin functions • Data type
• CPU function • Register set
• On-chip peripheral functions • Instruction format and instruction set
• Flash memory programming • Interrupts and exceptions
• Electrical specifications • Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To understand the overall functions of the V850ES/IE2
→ Read this manual according to the CONTENTS.
• To find the details of a register where the name is known
→ See APPENDIX B REGISTER INDEX.
• How to interpret the register format
→ For a bit whose bit number is enclosed in angle brackets < >, its bit name is
defined as a reserved word in the device file.
• To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual.
• To know the electrical specifications of the V850ES/IE2
→ See CHAPTER 19 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched
by copying an “<R>” in the PDF file and specifying it in the "Find what:" field.
User’s Manual U17716EJ2V0UD
5
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher addresses on the top and lower addresses on
the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity): K (kilo): 2
M (mega): 2
G (giga): 2
10
= 1,024
20
= 1,0242
30
= 1,0243
Data type: Word ... 32 bits
Halfword ... 16 bits
Byte ... 8 bits
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User’s Manual U17716EJ2V0UD
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/IE2
Document Name Document No.
V850ES Architecture User’s Manual U15943E
V850ES/IE2 Hardware User’s Manual This manual
Documents related to development tools (user’s manuals)
Document Name Document No.
QB-V850ESIX2 (in-circuit emulator) U17909E
QB-MINI2 (On-Chip Debug Emulator with Programming Function) U18371E
CA850 (Ver. 3.00) (C compiler package)
PM+ (Ver. 6.30) (Project manager) U18416E
ID850QB (Ver. 3.40) (Integrated debugger) Operation U18604E
TW850 (Ver. 2.00) (Performance analysis tuning tool) U17241E
RX850 (Ver. 3.20) (Real-time OS)
RX850 Pro (Ver. 3.21) (Real-time OS)
AZ850 (Ver. 3.30) (System performance analyzer) U17423E
PG-FP4 Flash Memory Programmer U15260E
PG-FP5 Flash Memory Programmer U18865E
Operation U17293E
C Language U17291E
Assembly Language U17292E
Link Directive U17294E
Basics U13430E
Installation U17419E
Technical U13431E
Task Debugger U17420E
Basics U18165E
Installation U17421E
Technical U13772E
Task Debugger U17422E
User’s Manual U17716EJ2V0UD
7
CONTENTS
CHAPTER 1 INTRODUCTION................................................................................................................. 14
1.1 General .......................................................................................................................................14
1.2 Features .....................................................................................................................................15
1.3 Applications...............................................................................................................................16
1.4 Ordering Information ................................................................................................................16
1.5 Pin Configuration ......................................................................................................................17
1.6 Function Blocks ........................................................................................................................19
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 22
2.1 List of Pin Functions.................................................................................................................22
2.2 Pin I/O Circuits and Recommended Connection of Unused Pins........................................26
2.3 Pin I/O Circuits...........................................................................................................................28
CHAPTER 3 CPU FUNCTION ................................................................................................................ 29
3.1 Features .....................................................................................................................................29
3.2 CPU Register Set.......................................................................................................................30
3.2.1 Program register set .....................................................................................................................31
3.2.2 System register set .......................................................................................................................32
3.3 Operating Modes.......................................................................................................................38
3.4 Address Space ..........................................................................................................................39
3.4.1 CPU address space......................................................................................................................39
3.4.2 Wraparound of CPU address space .............................................................................................40
3.4.3 Memory map.................................................................................................................................41
3.4.4 Areas ............................................................................................................................................43
3.4.5 Recommended use of address space...........................................................................................47
3.4.6 On-chip peripheral I/O registers....................................................................................................50
3.4.7 Special registers ...........................................................................................................................56
3.4.8 System wait control register (VSWC)............................................................................................61
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 62
4.1 Features .....................................................................................................................................62
4.2 Basic Port Configuration..........................................................................................................62
4.3 Port Configuration.....................................................................................................................63
4.3.1 Port 0 ............................................................................................................................................67
4.3.2 Port 1 ............................................................................................................................................73
4.3.3 Port 2 ............................................................................................................................................85
4.3.4 Port 3 ............................................................................................................................................91
4.3.5 Port 4 ............................................................................................................................................98
4.3.6 Port DL........................................................................................................................................105
4.4 Output Data and Read Value of Port for Each Setting ....................................................... 108
4.5 Port Register Settings When Alternate Function Is Used.................................................. 113
4.6 Noise Eliminator ..................................................................................................................... 117
4.7 Cautions .................................................................................................................................. 119
4.7.1 Cautions on setting port pins ......................................................................................................119
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User’s Manual U17716EJ2V0UD
4.7.2 Cautions on bit manipulation instruction for port n register (Pn) .................................................120
CHAPTER 5 CLOCK GENERATOR .....................................................................................................121
5.1 Overview ..................................................................................................................................121
5.2 Configuration ..........................................................................................................................122
5.3 Control Registers....................................................................................................................124
5.4 PLL Function ...........................................................................................................................130
5.4.1 Overview.....................................................................................................................................130
5.4.2 PLL mode ...................................................................................................................................130
5.4.3 Clock-through mode ...................................................................................................................130
5.5 Operation .................................................................................................................................131
5.5.1 Operation of each clock.............................................................................................................. 131
5.5.2 Operation timing ......................................................................................................................... 132
5.6 Clock Monitor ..........................................................................................................................135
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................137
6.1 Overview ..................................................................................................................................137
6.2 Functions ................................................................................................................................. 137
6.3 Configuration ..........................................................................................................................138
6.4 Registers..................................................................................................................................143
6.5 Timer Output Operations .......................................................................................................156
6.6 Operation .................................................................................................................................157
6.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)................................................................ 165
6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001) .................................................... 177
6.6.3 External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010)...................................... 186
6.6.4 One-shot pulse output mode (TPmMD2 to TPmMD0 bits = 011) ...............................................199
6.6.5 PWM output mode (TPmMD2 to TPmMD0 bits = 100)............................................................... 206
6.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .......................................................215
6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110)............................................ 232
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................238
7.1 Overview ..................................................................................................................................238
7.2 Functions ................................................................................................................................. 239
7.3 Configuration ..........................................................................................................................239
7.4 Registers..................................................................................................................................244
7.5 Timer Output Operations .......................................................................................................260
7.6 Operation .................................................................................................................................261
7.6.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000) ............................................................... 269
7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ................................................... 281
7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) ....................................... 291
7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011).................................................305
7.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100)................................................................ 314
7.6.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ......................................................325
7.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)...........................................345
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM).............................................................................351
8.1 Overview ..................................................................................................................................351
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8.2
Configuration.......................................................................................................................... 352
8.3 Control Register ..................................................................................................................... 353
8.4 Operation ................................................................................................................................ 354
8.4.1 Interval timer mode .....................................................................................................................354
8.5 Cautions .................................................................................................................................. 358
CHAPTER 9 MOTOR CONTROL FUNCTION .................................................................................... 359
9.1 Functional Overview .............................................................................................................. 359
9.2 Configuration.......................................................................................................................... 360
9.3 Control Registers ................................................................................................................... 364
9.4 Operation ................................................................................................................................ 377
9.4.1 System outline ............................................................................................................................377
9.4.2 Dead-time control (generation of negative-phase wave signal) ..................................................382
9.4.3 Interrupt culling function..............................................................................................................389
9.4.4 Operation to rewrite register with transfer function......................................................................396
9.4.5 TMP1 tuning operation for A/D conversion start trigger signal output .........................................414
9.4.6 A/D conversion start trigger output function ................................................................................417
CHAPTER 10 WATCHDOG TIMER FUNCTIONS .............................................................................. 422
10.1 Functions ................................................................................................................................ 422
10.2 Configuration.......................................................................................................................... 423
10.3 Control Registers ................................................................................................................... 424
10.4 Operation ................................................................................................................................ 425
10.5 Caution .................................................................................................................................... 425
CHAPTER 11 A/D CONVERTERS 0 AND 1 ..................................................................................... 426
11.1 Features .................................................................................................................................. 426
11.2 Configuration.......................................................................................................................... 427
11.3 Control Registers ................................................................................................................... 431
11.4 Operation ................................................................................................................................ 438
11.4.1 Basic operation ...........................................................................................................................438
11.4.2 Operation mode and trigger mode ..............................................................................................439
11.5 Operation in Software Trigger Mode.................................................................................... 450
11.5.1 Continuous select mode operations............................................................................................450
11.5.2 Continuous scan mode operations..............................................................................................453
11.5.3 One-shot select mode operations ...............................................................................................454
11.5.4 One-shot scan mode operations.................................................................................................456
11.6 Operation in Timer Trigger Mode ......................................................................................... 457
11.6.1 Continuous select mode/one-shot select mode operations.........................................................458
11.6.2 Continuous scan mode/one-shot scan mode operations ............................................................460
11.7 Operation in External Trigger Mode..................................................................................... 461
11.7.1 Continuous select mode/one-shot select mode operations.........................................................462
11.7.2 Continuous scan mode/one-shot scan mode operations ............................................................464
11.8 Internal Equivalent Circuit..................................................................................................... 465
11.9 Notes on Operation................................................................................................................ 467
11.9.1 Stopping conversion operation....................................................................................................467
11.9.2 Timer/external trigger interval .....................................................................................................467
11.9.3 Operation in standby mode.........................................................................................................467
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User’s Manual U17716EJ2V0UD
11.9.4 Timer interrupt request signal in timer trigger mode ...................................................................468
11.9.5 Re-conversion start trigger input during stabilization time ..........................................................468
11.9.6 Variation of A/D conversion results............................................................................................. 468
11.9.7 A/D conversion result hysteresis characteristics......................................................................... 468
11.9.8 Restrictions on setting one-shot mode and software trigger mode .............................................469
11.10 How to Read A/D Converter Characteristics Table .............................................................470
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................474
12.1 Features ...................................................................................................................................474
12.2 Configuration ..........................................................................................................................475
12.3 Control Registers....................................................................................................................477
12.4 Interrupt Request Signals ......................................................................................................482
12.5 Operation .................................................................................................................................483
12.5.1 Data format................................................................................................................................. 483
12.5.2 UART transmission..................................................................................................................... 485
12.5.3 Continuous transmission procedure ...........................................................................................486
12.5.4 UART reception .......................................................................................................................... 488
12.5.5 Reception errors ......................................................................................................................... 489
12.5.6 Parity types and operations ........................................................................................................490
12.5.7 Receive data noise filter .............................................................................................................491
12.6 Dedicated Baud Rate Generator............................................................................................492
12.7 Cautions...................................................................................................................................499
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................500
13.1 Features ...................................................................................................................................500
13.2 Configuration ..........................................................................................................................501
13.3 Control Registers....................................................................................................................503
13.4 Operation .................................................................................................................................510
13.4.1 Single transfer mode (master mode, transmission mode) ..........................................................510
13.4.2 Single transfer mode (master mode, reception mode)................................................................ 512
13.4.3 Single transfer mode (master mode, transmission/reception mode)........................................... 514
13.4.4 Single transfer mode (slave mode, transmission mode) ............................................................. 516
13.4.5 Single transfer mode (slave mode, reception mode) ..................................................................518
13.4.6 Single transfer mode (slave mode, transmission/reception mode) .............................................520
13.4.7 Continuous transfer mode (master mode, transmission mode) ..................................................522
13.4.8 Continuous transfer mode (master mode, reception mode)........................................................ 524
13.4.9 Continuous transfer mode (master mode, transmission/reception mode)................................... 527
13.4.10 Continuous transfer mode (slave mode, transmission mode) .....................................................531
13.4.11 Continuous transfer mode (slave mode, reception mode) ..........................................................533
13.4.12 Continuous transfer mode (slave mode, transmission/reception mode) .....................................536
13.4.13 Reception error...........................................................................................................................540
13.4.14 Clock timing ................................................................................................................................541
13.5 Output Pins..............................................................................................................................543
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................544
14.1 Features ...................................................................................................................................544
14.2 Non-Maskable Interrupts........................................................................................................ 548
14.2.1 Operation.................................................................................................................................... 549
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14.2.2 Restore .......................................................................................................................................550
14.2.3 Non-maskable interrupt status flag (NP) .....................................................................................551
14.3 Maskable Interrupts ............................................................................................................... 552
14.3.1 Operation ....................................................................................................................................552
14.3.2 Restore .......................................................................................................................................554
14.3.3 Priorities of maskable interrupts..................................................................................................555
14.3.4 Interrupt control registers (xxICn) ...............................................................................................559
14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)...........................................................................562
14.3.6 In-service priority register (ISPR)................................................................................................564
14.3.7 Maskable interrupt status flag (ID) ..............................................................................................565
14.4 External Interrupt Request Input Pins (INTP0 to INTP6) .................................................... 566
14.4.1 Noise elimination.........................................................................................................................566
14.4.2 Edge detection............................................................................................................................567
14.5 Software Exception................................................................................................................ 568
14.5.1 Operation ....................................................................................................................................568
14.5.2 Restore .......................................................................................................................................569
14.5.3 Exception status flag (EP)...........................................................................................................570
14.6 Exception Trap ....................................................................................................................... 571
14.6.1 Illegal opcode definition ..............................................................................................................571
14.6.2 Debug trap ..................................................................................................................................573
14.7 Multiple Interrupt Servicing Control..................................................................................... 575
14.8 Interrupt Response Time of CPU.......................................................................................... 577
14.9 Periods in Which CPU Does Not Acknowledge Interrupts ................................................ 578
14.10 Caution .................................................................................................................................... 578
CHAPTER 15 STANDBY FUNCTION .................................................................................................. 579
15.1 Overview ................................................................................................................................. 579
15.2 Control Registers ................................................................................................................... 581
15.3 HALT Mode ............................................................................................................................. 583
15.3.1 Setting and operation status .......................................................................................................583
15.3.2 Releasing HALT mode................................................................................................................583
15.4 IDLE Mode............................................................................................................................... 585
15.4.1 Setting and operation status .......................................................................................................585
15.4.2 Releasing IDLE mode .................................................................................................................585
15.5 STOP Mode ............................................................................................................................. 587
15.5.1 Setting and operation status .......................................................................................................587
15.5.2 Releasing STOP mode ...............................................................................................................587
15.6 Securing Oscillation Stabilization Time............................................................................... 589
CHAPTER 16 RESET FUNCTIONS ..................................................................................................... 590
16.1 Overview ................................................................................................................................. 590
16.2 Registers to Check Reset Source ........................................................................................ 590
16.3 Operation ................................................................................................................................ 592
16.3.1 Reset operation via RESET pin ..................................................................................................592
16.3.2 Reset operation by watchdog timer (WDT) overflow (WDTRES)................................................594
16.3.3 Low-voltage detector (LVI)..........................................................................................................595
16.3.4 Power-on-clear circuit (POC) ......................................................................................................603
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User’s Manual U17716EJ2V0UD
CHAPTER 17 REGULATOR ..................................................................................................................605
17.1 Overview ..................................................................................................................................605
17.2 Operation .................................................................................................................................606
CHAPTER 18 FLASH MEMORY...........................................................................................................607
18.1 Features ...................................................................................................................................607
18.2 Memory Configuration............................................................................................................608
18.3 Functional Overview...............................................................................................................609
18.4 Rewriting by Dedicated Flash Memory Programmer ..........................................................613
18.4.1 Programming environment .........................................................................................................613
18.4.2 Communication mode................................................................................................................. 614
18.4.3 Flash memory control .................................................................................................................619
18.4.4 Selection of communication mode.............................................................................................. 620
18.4.5 Communication commands ........................................................................................................ 621
18.4.6 Pin connection ............................................................................................................................ 622
18.5 Rewriting by Self Programming (μPD70F3714 only) ........................................................... 627
18.5.1 Overview.....................................................................................................................................627
18.5.2 Features .....................................................................................................................................628
18.5.3 Standard self programming flow ................................................................................................. 629
18.5.4 Flash functions ...........................................................................................................................630
18.5.5 Pin processing ............................................................................................................................ 630
18.5.6 Internal resources used ..............................................................................................................631
<R>
<R>
CHAPTER 19 ELECTRICAL SPECIFICATIONS..................................................................................632
CHAPTER 20 PACKAGE DRAWING ...................................................................................................651
CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS ...........................................................652
APPENDIX A CAUTIONS.......................................................................................................................653
A.1 Restriction on Conflict Between sld Instruction and Interrupt Request........................... 653
A.1.1 Description..................................................................................................................................653
A.1.2 Countermeasure.........................................................................................................................653
APPENDIX B REGISTER INDEX ..........................................................................................................654
APPENDIX C INSTRUCTION SET LIST..............................................................................................659
C.1 Conventions ............................................................................................................................659
C.2 Instruction Set (in Alphabetical Order).................................................................................662
APPENDIX D REVISION HISTORY ......................................................................................................669
D.1 Major Revisions in This Edition.............................................................................................669
User’s Manual U17716EJ2V0UD
13
CHAPTER 1 INTRODUCTION
The V850ES/IE2 is one of the low-power operation products in the NEC Electronics V850 Series of single-chip
microcontrollers designed for real-time control applications.
1.1 General
The V850ES/IE2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions
such as ROM/RAM, a timer/counter, serial interfaces, a watchdog timer, and an A/D converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/IE2 features
instructions such as multiply instructions, saturated operation instructions, and bit manipulation instructions realized by
a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control
system, the V850ES/IE2 enables an extremely high cost-performance for applications such as motor inverter control.
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User’s Manual U17716EJ2V0UD
CHAPTER 1 INTRODUCTION
1.2 Features
{ Minimum instruction execution time:
50 ns (at internal 20 MHz operation)
{ General-purpose registers: 32 bits × 32
{ CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operation instructions (with overflow/underflow detection function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
{ Internal memory:
μ
PD70F3713 64 KB (flash memory) 6 KB
μ
PD70F3714 128 KB (flash memory) 6 KB
{ Interrupts/exceptions: Non-maskable interrupts: 1 source (external: none, internal: 1)
Maskable interrupts: 42 sources (external: 7, internal: 35)
Software exceptions: 32 sources
Exception traps: 2 sources
{ I/O lines: I/O ports: 39
{ Timer/counter function: 16-bit interval timer M (TMM): 1 channel
16-bit timer/event counter Q (TMQ): 2 channels
16-bit timer/event counter P (TMP): 4 channels
Motor control function (uses timer TMQ: 1 channel (TMQ1), TMP: 1 channel (TMP1))
16-bit accuracy 6-phase PWM function with dead time: 1 channel
High-impedance output control function
Timer tuning operation function
Arbitrary cycle setting function
Arbitrary dead-time setting function
Watchdog timer: 1 channel
{ Serial interfaces: Asynchronous serial interface A (UARTA)
3-wire variable length serial I/O (CSIB)
CSIB: 1 channel
UARTA: 2 channels
{ A/D converter: 10-bit resolution A/D converters (A/D converters 0 and 1): 4 channels × 2 units
Part Number Internal ROM Internal RAM
User’s Manual U17716EJ2V0UD
15
CHAPTER 1 INTRODUCTION
{ Clock generator: 2.5 MHz resonator connectable (external clock input prohibited)
Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, f
20 MHz)
CPU clock division function (f
XX, fXX/2, fXX/4, fXX/8)
{ Power-save function: HALT/IDLE/ STOP mode
{ Power-on-clear function
{ Low-voltage detection function
{ Self programming Supported only in the
μ
PD70F3714 (not supported in the μPD70F3713)
{ Package: 64-pin plastic LQFP (14 × 14)
O Operation supply voltage: V
AV
DD = EVDD = 3.5 to 5.5 V
DD0, AVDD1 = 4.5 to 5.5 V
O Operation ambient temperature:
T
A = −40 to +85°C
1.3 Applications
• Consumer appliances (such as inverter air conditioners, refrigerators, washing machines, etc.)
• Industrial equipment (such as motor control and general-purpose inverters, etc.)
1.4 Ordering Information
Part Number Package Internal ROM
μ
PD70F3713GC-8BS-A 64-pin plastic LQFP (14 × 14) Flash memory (64 KB)
μ
PD70F3714GC-8BS-A 64-pin plastic LQFP (14 × 14) Flash memory (128 KB)
Remark Products with -A at the end of the part number are lead-free products.
XX =
16
User’s Manual U17716EJ2V0UD
1.5 Pin Configuration
• 64-pin plastic LQFP (14 × 14)
μ
PD70F3713GC-8BS-A
μ
PD70F3714GC-8BS-A
CHAPTER 1 INTRODUCTION
Top View
P25/TOQ1B3
P24/TOQ1T3
P23/TOQ1B2
P22/TOQ1T2
P21/TOQ1B1
P20/TOQ1T1
ANI13
ANI12
ANI11
ANI10
AV
REF1
AV
DD1
AV
SS1
AV
SS0
AV
DD0
AV
REF0
EVSSEVDDP26/TOQ10
484746454443424140393837363534
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
P27/TOP31
3
4
P30/RXDA0
P31/TXDA0
P32/RXDA1
5
6
7
P33/TXDA1
P40/SIB0
P41/SOB0
P42/SCKB0
8
9
10111213141516
P43/TOP00/TIP00
P44/TOP01/TIP01
PDL0
PDL1
PDL2
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PDL3
PDL4
PDL5/FLMD1
PDL6
PDL7
EV
SS
EV
DD
FLMD0
P10/TOQH01/TIQ01/TOQ01
P11/TIQ02/TOQ02
P12/TOQH02/TIQ03/TOQ03
P13/TIQ00
P14/TOQH03/EVTQ0
P16(CLMER)
P17/TOP21/TIP21
P00/INTP0/TOQH0OFF
Note
/TOQ00(CLMER)
Note
/TIP20
SS
X2
DD
V
V
REGC
P06/INTP6
P05/INTP5/ADTRG1
P04/INTP4/ADTRG0
P03/INTP3/TOP3OFF
P02/INTP2/TOP2OFF
P01/INTP1/TOQ1OFF
ANI00
ANI01
ANI02
ANI03
X1
RESET
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of
TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output.
Low-level output is released by reset signal. For details, see Table 4-5 Alternate-Function Pins of
Port 1.
User’s Manual U17716EJ2V0UD
17
CHAPTER 1 INTRODUCTION
Pin Identification
ADTRG0, ADTRG1: A/D trigger input SCKB0: Serial clock
ANI00 to ANI03, SIB0: Serial input
ANI10 to ANI13: Analog input SOB0: Serial output
AV
DD0, AVDD1: Analog power supply TIP00, TIP01,
AV
REF0, AVREF1: Analog reference voltage TIP20, TIP21,
AV
SS0, AVSS1: Analog ground TIQ00 to TIQ03: Timer trigger input
EVDD: Power supply for port TOP00, TOP01,
EV
SS: Ground for port TOP21, TOP31,
EVTQ0: Timer event count input TOQ1B1 to TOQ1B3,
FLMD0, FLMD1: Flash programming mode TOQ1T1 to TOQ1T3,
INTP0 to INTP6: External interrupt input TOQ00 to TOQ03,
P00 to P06: Port 0 TOQ10,
P10 to P14, P16, P17: Port 1 TOQH01 to TOQH03: Timer output
P20 to P27: Port 2 TOP2OFF, TOP3OFF,
P30 to P33: Port 3 TOQ1OFF, TOQH0OFF: Timer output off
P40 to P44: Port 4 TXDA0, TXDA1: Transmit data
PDL0 to PDL7: Port DL V
REGC: Regulator control V
DD: Power supply
SS: Ground
RESET: Reset X1, X2: Clock oscillator pin
RXDA0, RXDA1: Receive data
18
User’s Manual U17716EJ2V0UD
1.6 Function Blocks
(1) Internal block diagram
INTP0 to INTP6
TIQ00 to TIQ03, EVTQ0,
TOQ1OFF, TOQH0OFF
TOQ00 to TOQ03, TOQ10,
TOQH01 to TOQH03,
TOQ1T1 to TOQ1T3,
TOQ1B1 to TOQ1B3
TIP00, TIP01, TIP20,TIP21,
TOP2OFF, TOP3OFF
TOP00, TOP01,
TOP21,TOP31
CHAPTER 1 INTRODUCTION
INTC
TMM
× 1 ch
TMQ
× 2 ch
TMP
× 4 ch
WDT
ROM
Note
RAM
6 KB
PC
32-bit
barrel shifter
System
registers
Generalpurpose
registers
(32 bits
×
32)
CPU
Multiplier
(16 × 16 → 32)
ALU
BCU
Instruction
queue
TXDA0, TXDA1
RXDA0, RXDA1
SOB0
SIB0
SCKB0
ANI00 to ANI03
ADTRG0
AV
REF0
AV
DD0
AV
SS0
ANI10 to ANI13
ADTRG1
AV
REF1
AV
DD1
AV
SS1
UARTA
× 2 ch
CSIB
ADC0
ADC1
Port
P00 to P06
P20 to P27
P30 to P33
P40 to P44
PDL0 to PDL7
P10 to P14, P16, P17
CG
PLL
RG
Regulator
CLM
POC/LVI
X1
X2
RESET
FLMD0
FLMD1
EV
DD
EV
SS
V
DD
V
SS
REGC
Note
μ
PD70F3713: 64 KB (flash memory)
μ
PD70F3714: 128 KB (flash memory)
User’s Manual U17716EJ2V0UD
19
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits), help accelerate complex processing.
(b) Bus control unit (BCU)
The BCU controls the internal bus.
(c) ROM
This is flash memory that is mapped from address 00000000H.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles. The
internal ROM capacity and area differ as follows depending on the product.
μ
PD70F3713 64 KB (flash memory) xn000000H to xn00FFFFH
μ
PD70F3714 128 KB (flash memory) xn000000H to xn01FFFFH
CHAPTER 1 INTRODUCTION
Part Number Internal ROM Capacity Internal ROM Area
Remark n = xx11B
(d) RAM
This is a 6 KB internal RAM that is mapped to the addresses xnFFD800H to xnFFEFFFH.
During instruction fetch or data access, data can be accessed from the CPU in 1-clock cycles.
Remark n = xx11B
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (INTP0 to INTP6) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple-interrupt servicing control can be performed.
(f) Clock generator (CG)
The clock generator includes two basic operation modes: PLL mode (fixed to multiplication by eight) and
clock-through mode. It generates four types of clocks (f
the operating clock for the CPU (f
(g) Timer/counter
This unit incorporates one 16-bit interval timer M (TMM) channel, two 16-bit timer/event counter Q (TMQ)
channels, and four 16-bit timer/event counter P (TMP) channels, and can measure pulse interval widths or
frequency, enable an inverter function for motor control, and output a programmable pulse.
(h) Watchdog timer (WDT)
A watchdog timer is equipped to detect program loops, system abnormalities, etc.
It generates a non-maskable interrupt request signal (INTWDT) or internal reset signal (WDTRES) after an
overflow occurs.
XX, fXX/2, fXX/4, fXX/8), and supplies one of them as
CPU).
20
User’s Manual U17716EJ2V0UD
CHAPTER 1 INTRODUCTION
(i) Serial interface
The V850ES/IE2 includes two asynchronous serial interface A (UARTA) channels and one 3-wire variable
length serial I/O (CSIB) channel as the serial interface.
For UARTA, data is transferred via the TXDAn and RXDAn pins (n = 0, 1).
For CSIB, data is transferred via the SOB0, SIB0, and SCKB0 pins.
(j) A/D converter (ADC)
The V850ES/IE2 includes two-channel 10-bit A/D converters (ADC0 and ADC1) with four analog input
pins.
(k) Ports
As shown below, the following ports have general-purpose port functions and control pin functions.
Port I/O Alternate Function
Port 0 7-bit I/O Timer/counter input, external interrupt input, external trigger input of A/D converter
Port 1 7-bit I/O Timer/counter I/O
Port 2 8-bit I/O Timer/counter output
Port 3 4-bit I/O Serial interface I/O
Port 4 5-bit I/O Serial interface I/O, timer/counter I/O
Port DL 8-bit I/O
−
User’s Manual U17716EJ2V0UD
21
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
The names and functions of the pins in the V850ES/IE2 are listed below. These pins can be divided into port pins
and non-port pins according to their function.
There are two power supplies for the I/O buffer of a pin: power supply for A/D converter (AV
power supply for external pin (EVDD). The relationship between each power supply and the pins is shown below.
Table 2-1. I/O Buffer Power Supplies for Each Pin
Power Supply Corresponding Pins
AVDD0, AVDD1 ANI00 to ANI03, ANI10 to ANI13
EVDD Ports 0 to 4, port DL, RESET
(1) Port pins
Pin Name Pin No. I/O Function Alternate Function
P00 17 INTP0/TOQH0OFF
P01 16 INTP1/TOQ1OFF
P02 15 INTP2/TOP2OFF
P03 14 INTP3/TOP3OFF
P04 13 INTP4/ADTRG0
P05 12 INTP5/ADTRG1
P06 11
P10 24 TOQH01/TIQ01/TOQ01
P11 23 TIQ02/TOQ02
P12 22 TOQH02/TIQ03/TOQ03
P13 21 TIQ00
P14 20 TOQH03/EVTQ0
P16
(CLMER)
P17 18
Note
19 TOQ00 (CLMER)
I/O Port 0
7-bit I/O port
Input data read/output data write is enabled in 1-bit units.
Use of an on-chip pull-up resistor can be specified in 1-bit
units (the on-chip pull-up resistor can be connected only in
the input mode of the port mode and when the alternate
function of the pin is used).
I/O Port 1
7-bit I/O port
Input data read/output data write is enabled in 1-bit units.
Use of an on-chip pull-up resistor can be specified in 1-bit
units (the on-chip pull-up resistor can be connected only in
the input mode of the port mode, when the input mode of
alternate function of the pin is used, and when TOP21 and
TOQH01 to TOQH03 pins, which function as output pins
when their alternate function is used, go into a highimpedance state).
INTP6
TOP21/TIP21
DD0 and AVDD1) and
Note
/TIP20
(1/2)
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of
TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output.
Low-level output is released by reset signal. For details, see Table 4-5 Alternate-Function Pins of Port
1.
22
User’s Manual U17716EJ2V0UD
<R>
CHAPTER 2 PIN FUNCTIONS
Pin Name Pin No. I/O Function Alternate Function
P20 54 TOQ1T1
P21 53 TOQ1B1
P22 52 TOQ1T2
P23 51 TOQ1B2
P24 50 TOQ1T3
P25 49 TOQ1B3
P26 46 TOQ10
P27 45
P30 44 RXDA0
P31 43 TXDA0
P32 42 RXDA1
P33 41
P40 40 SIB0
P41 39 SOB0
P42 38 SCKB0
P43 37 TOP00/TIP00
P44 36
PDL0 35
PDL1 34
PDL2 33
PDL3 32
PDL4 31
PDL5 30 FLMD1
PDL6 29
PDL7 28
I/O Port 2
8-bit I/O port
Input data read/output data write is enabled in 1-bit units.
Use of an on-chip pull-up resistor can be specified in 1-bit
units (the on-chip pull-up resistor can be connected only in
the input mode of the port mode, or when TOQ1T1 to
TOQ1T3 and TOQ1B1 to TOQ1B3 and TOP31 pins, which
function as output pins when their alternate function is used,
go into a high-impedance state).
I/O Port 3
4-bit I/O port
Input data read/output data write is enabled in 1-bit units.
Use of an on-chip pull-up resistor can be specified in 1-bit
units (the on-chip pull-up resistor can be connected only in
the input mode of the port mode and when the input mode of
the alternate function of the pin is used).
I/O Port 4
5-bit I/O port
Input data read/output data write is enabled in 1-bit units.
An on-chip pull-up resistor can be specified in 1-bit units (the
on-chip pull-up resistor can be connected only in the input
mode of the port mode, including the case where the SCKB0
pin in the slave mode, and when the alternate function of the
pin is used in the input mode).
I/O Port DL
8-bit I/O port
Input data read/output data write is enabled in 1-bit units.
An on-chip pull-up resistor can be specified in 1-bit units
(the on-chip pull-up resistor can be connected when the
pins are in the port mode and input mode).
TOP31
TXDA1
TOP01/TIP01
−
−
−
−
−
−
−
(2/2)
User’s Manual U17716EJ2V0UD
23
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
(1/2)
Pin Name Pin No. I/O Function Alternate Function
ADTRG0 13 Input INTP4/P04
ADTRG1 12 Input
ANI00
ANI01
ANI02
ANI03
ANI10
ANI11
ANI12
ANI13
AVDD0
AVDD1
AVREF0
AVREF1
AVSS0
AVSS1
EVDD
EVSS
1
2
3
4
58
57
56
55
63
60
64
59
62
61
26, 47
27, 48
Input
Input
Input
Input
Input
Input
Input
Input
External trigger input for A/D converters 0, 1
INTP5/P05
Analog input to A/D converters 0, 1
− −
Positive power supply for A/D converters 0, 1 (same
potential as V
−
− −
Reference voltage input for A/D converters 0, 1 (same
potential as AV
−
− −
Ground potential for A/D converters 0, 1 (same potential
SS)
as V
−
−
Positive power supply for external pin
Ground potential for external pin
−
DD)
DD0 and AVDD1)
−
−
−
−
−
−
−
−
−
−
−
−
−
EVTQ0 20 Input External event count input of TMQ0 TOQH03/P14
FLMD0 25 Input
FLMD1 30 Input
INTP0 17 TOQH0OFF/P00
Input External maskable interrupt request input
Pin for setting flash memory programming mode
−
PDL5
INTP1 16 TOQ1OFF/P01
INTP2 15 TOP2OFF/P02
INTP3 14 TOP3OFF/P03
INTP4 13 ADTRG0/P04
INTP5 12 ADTRG1/P05
INTP6 11
REGC 10 − Regulator output stabilization capacitance connection
RESET 5 Input System reset input
RXDA0 44 P30
Input Serial receive data input of UARTA0, UARTA1
RXDA1 42
P06
−
−
P32
SCKB0 38 I/O Serial clock I/O of CSIB0 P42
SIB0 40 Input Serial receive data input of CSIB0 P40
SOB0 39 Output Serial transmit data output of CSIB0 P41
24
User’s Manual U17716EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin Name Pin No. I/O Function Alternate Function
TIP00 37
Input
External event count input/external trigger input/capture
TOP00/P43
trigger input of TMP0
TIP01 36 Capture trigger input of TMP0 TOP01/P44
TIP20 19
External event count input/external trigger input/capture
trigger input of TMP2
TIP21 18
TIQ00 21 P13
Input Capture trigger input of TMQ0
Capture trigger input of TMP2 TOP21/P17
TOQ00 (CLMER)
P16 (CLMER)
Note
TIQ01 24 TOQH01/TOQ01/P10
TIQ02 23 TOQ02/P11
TIQ03 22
TOP00 37 TIP00/P43
Output Pulse signal output of TMP0, TMP2
TOQH02/TOQ03/P12
TOP01 36 TIP01/P44
TOP21 18
TIP21/P17
TOP2OFF 15 Input High-impedance output control signal input INTP2/P02
TOP31 45 Output Pulse signal output of TMP3 P27
TOP3OFF 14 Input High-impedance output control signal input INTP3/P03
TOQ00 (CLMER)
Note
19 TIP20/P16 (CLMER)
Output Pulse signal output of TMQ0
TOQ01 24 TOQH01/TIQ01/P10
TOQ02 23 TIQ02/P11
TOQ03 22
TOQH02/TIQ03/P12
TOQ10 46 Output Pulse signal output of TMQ1 P26
TOQ1B1 53 P21
Output Pulse signal output for 6-phase PWM
TOQ1B2 51 P23
TOQ1B3 49
P25
TOQ1OFF 16 Input High-impedance output control signal input INTP1/P01
TOQ1T1 54 P20
Output Pulse signal output for 6-phase PWM
TOQ1T2 52 P22
TOQ1T3 50
TOQH01 24 TIQ01/TOQ01/P10
Output
TOQH02 22 TIQ03/TOQ03/P12
High-impedance output by TMQ0 pulse signal output and
valid edge of TOQH0OFF pin input
TOQH03 20
P24
EVTQ0/P14
TOQH0OFF 17 Input High-impedance output control signal input INTP0/P00
TXDA0 43 P31
TXDA1 41
VDD 9
VSS 8
X1 6 Input
X2 7
Output Serial transmit data output of UARTA0, UARTA1
Positive power supply for internal unit
−
Ground potential for internal unit
−
Resonator connection pin for system clock
−
P33
−
−
−
−
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of
TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output.
Low-level output is released by reset signal. For details, see Table 4-5 Alternate-Function Pins of Port
1.
(2/2)
Note
/
Note
User’s Manual U17716EJ2V0UD
25
CHAPTER 2 PIN FUNCTIONS
2.2 Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name Alternate-Function Pin Name Pin No. I/O Circuit
Type
P00 INTP0/TOQH0OFF
17
8-P
Input: Independently connect to EV
P01 INTP1/TOQ1OFF 16
P02 INTP2/TOP2OFF 15
Output: Leave open.
P03 INTP3/TOP3OFF 14
P04 INTP4/ADTRG0 13
P05 INTP5/ADTRG1 12
P06 INTP6 11
P10 TOQH01/TIQ01/TOQ01 24
P11 TIQ02/TOQ02 23
P12 TOQH02/TIQ03/TOQ03 22
P13 TIQ00 21
P14 TOQH03/EVTQ0 20
P16 (CLMER)
Note
TOQ00 (CLMER)
Note
/TIP20 19
P17 TOP21/TIP21 18
P20 TOQ1T1 54
5-AG
P21 TOQ1B1 53
P22 TOQ1T2 52
P23 TOQ1B2 51
P24 TOQ1T3 50
P25 TOQ1B3 49
P26 TOQ10 46
P27 TOP31 45
P30 RXDA0 44 8-P
P31 TXDA0 43 5-AG
P32 RXDA1 42 8-P
P33 TXDA1 41 5-AG
P40 SIB0 40 8-P
P41 SOB0 39 5-AG
P42 SCKB0 38
8-P
P43 TOP00/TIP00 37
P44 TOP01/TIP01 36
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of
TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output.
Low-level output is released by reset signal. For details, see Table 4-5 Alternate-Function Pins of Port
1.
Recommended Connection
EV
SS via a resistor.
(1/2)
DD or
26
User’s Manual U17716EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Pin Name Alternate-Function Pin Name Pin No. I/O Circuit
Type
PDL0
PDL1
PDL2
PDL3
PDL4
−
−
−
−
−
35
34
33
32
31
5-AG
PDL5 FLMD1 30
PDL6
PDL7
ANI00
ANI01
ANI02
ANI03
ANI10
ANI11
ANI12
ANI13
RESET
FLMD0
−
−
−
−
−
−
−
−
−
−
−
−
29
28
58
57
56
55
25
1
7
2
3
4
5
2
Recommended Connection
Input: Independently connect to
DD or EVSS via a resistor.
EV
Output: Leave open.
Independently connect to AV
AV
DD1, AVSS0, or AVSS1 via a resistor.
DD0,
−
−
(2/2)
User’s Manual U17716EJ2V0UD
27
2.3 Pin I/O Circuits
Type 2
CHAPTER 2 PIN FUNCTIONS
Type 7
IN
Schmitt-triggered input with hysteresis characteristics
Type 5-AG
Pull-up
enable
Data
Output
EV
DD
P-ch
N
-ch
EV
P-ch
disable
EV
SS
Input
enable
DD
IN/OUT
IN
AV
Type 8-P
Pull-up
enable
Data
Output
disable
Input enable
P-ch
N
-ch
SS0
, AV
SS1
(Threshold voltage)
Comparator
+
–
V
REF
EV
DD
P-ch
DD
EV
P-ch
IN/OUT
N-ch
EV
SS
RESET
28
User’s Manual U17716EJ2V0UD
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/IE2 is based on the RISC architecture and executes most instructions in one clock cycle
by using 5-stage pipeline control.
3.1 Features
{ Minimum instruction execution time: 50 ns
(@ 20 MHz operation: 4.5 to 5.5 V (when using A/D converter),
3.5 to 5.5 V (when not using A/D converter))
{ Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
{ General-purpose registers: 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Load/store instruction with long/short format
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
User’s Manual U17716EJ2V0UD
29
CHAPTER 3 CPU FUNCTION
3.2 CPU Register Set
The CPU registers of the V850ES/IE2 can be classified into two categories: a general-purpose program register set
and a dedicated system register set. All the registers have 32-bit width.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set (2) System register set
31 0 31 0
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
(Element pointer (EP))
(Link pointer (LP))
EIPC
EIPSW
FEPC
FEPSW
ECR (Interrupt source register)
PSW (Program status word)
CTPC
CTPSW
DBPC
DBPSW
CTBP (CALLT base pointer)
(Interrupt status saving register)
(Interrupt status saving register)
(NMI status saving register)
(NMI status saving register)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
31 0
PC (Program counter)
30
User’s Manual U17716EJ2V0UD
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