NEC V850ES-FF3 User Manual
Data Sheet
V850ES/FF3
32-bit Single-Chip Microcontroller
Hardware
µPD70F3372(A) µPD70F3373(A)
µPD70F3372(A1) µPD70F3373(A1)
µPD70F3372(A2) µPD70F3373(A2)
Document No. U18565EE1V2DS00
Date Published March 2008
© NEC Electronics 2008
Printed in Germany
V850ES/FF3
Notes for CMOS Devices
1. Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2. Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3. Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
2
Data Sheet U18565EE1V2DS00
V850ES/FF3
Legal Notes
• The information in this document is current as of January 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that
may appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from the use of NEC Electronics products
listed in this document or any other liability arising from the use of such NEC Electronics products.
No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation
of these circuits, software and information in the design of customer's equipment shall be done under
the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred
by customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics
products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated
entirely. To minimize risks of damage to property or injury (including death) to persons arising from
defects in NEC Electronics products, customers must incorporate sufficient safety measures in their
design, such as redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: “Standard”, “Special”
and “Specific”.
The "Specific" quality grade applies only to NEC Electronics products developed based on a
customer-designated “quality assurance program” for a specific application. The recommended
applications of NEC Electronics product depend on its quality grade, as indicated below. Customers
must check the quality grade of each NEC Electronics product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and
measurement equipment, audio and visual equipment, home electronic
appliances, machine tools, personal electronic equipment and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control
systems, anti-disaster systems, anti-crime systems, safety equipment and
medical equipment (not specifically designed for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control
systems, life support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in
NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products
in applications not intended by NEC Electronics, they must contact NEC Electronics sales
representative in advance to determine NEC Electronics 's willingness to support a given application.
Notes: 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also
includes its majority-owned subsidiaries.
2. "NEC Electronics products" means any product developed or manufactured by or for NEC
Electronics (as defined above).
3. SuperFlash
tries including the United States and Japan. This product uses SuperFlash
licensed from Silicon Storage Technology, Inc.
®
is a registered trademark of Silicon Storage Technology, Inc. in several coun-
®
technology
Data Sheet U18565EE1V2DS00
3
V850ES/FF3
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
4
Data Sheet U18565EE1V2DS00
For further information,
please contact:
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V850ES/FF3
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Data Sheet U18565EE1V2DS00
G06.6-1A
5
V850ES/FF3
Table of Contents
1. Pin Group Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Device package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Pin Groups 1x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Pin Groups 2x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Groups 3x: Pins supplied by BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Pin Groups 4: Pins supplied by AVREF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Pin Groups 5: Pins supplied by AVREF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Pin Groups 6: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 Pin Groups 7: Pins supplied by VRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Electrical Specifications of (A)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.3 Power supply current (A-grade). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3. Electrical Specifications of (A1)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Data Sheet U18565EE1V2DS00
V850ES/FF3
Table of Contents
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.3 Power supply current (A1-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 36
3.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4. Electrical Specifications of (A2)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.3 Power supply current (A2-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 45
4.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Data Sheet U18565EE1V2DS00
7
V850ES/FF3
Table of Contents
5. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Product Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.2 Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8
Data Sheet U18565EE1V2DS00
V850ES/FF3
1. Pin Group Information
1.1 Device package information
The V850ES/Fx3 device series comprises several members. An overview with the pin and package
information is given in the following table:
Series Member # Pins Device package information
μPD70F3370A
μPD70F3371
μPD70F3372
μPD70F3373
μPD70F3374
μPD70F3375
μPD70F3376A
μPD70F3377A
μPD70F3378
μPD70F3379
μPD70F3380
μPD70F3381
μPD70F3382
μPD70F3383
μPD70F3384
μPD70F3385
64
80
100
144
176
FE3
FF3
FG3
FJ3
FK3
This document describes the specification for the V850ES/FF3.
1.2 Pin Groups 1x: Pins supplied by EVDD
1B: (SHMT1)
- P04, P30-31, P34; P40, P91, P913-915 (FE3)
- P04, P30-31, P34; P38-39, P40, P91, P913-915 (FF3)
- P04, P30-31, P34; P36-39, P40, P91, P911, P913-915 (FG3)
- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915 (FJ3)
- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915, P156-157
(FK3)
1D: (SHMT3)
- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FE3)
- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FF3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P90, P92-910, P912 (FG3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912 (FJ3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912, P150-155 (FK3)
1.3 Pin Groups 2x: Pins supplied by EVDD
2A: (CMOS)
- PCM0-1 (FE3)
- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FF3)
2D: (SHMT3)
- PDL0-7 (FE3)
- PDL0-11 (FF3)
Data Sheet U18565EE1V2DS00
9
V850ES/FF3
1.4 Pin Groups 3x: Pins supplied by BVDD
3A: (CMOS)
- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FG3)
- PCD0-3, PCM0-5, PCS0-7, PCT0-7 (FJ3 + FK3)
3D: (SHMT3)
- PDL0-13 (FG3)
- PDL0-15 (FJ3 + FK3)
1.5 Pin Groups 4: Pins supplied by AVREF0
4: (CMOS)
- P70-79 (FE3)
-P70-711 (FF3)
- P70-715 (FG3)
- P70-715, P120-127 (FJ3 + FK3)
1.6 Pin Groups 5: Pins supplied by AVREF1
- P20-P215 (FK3) (CMOS)
1.7 Pin Groups 6: Pins supplied by EVDD
- RESET (SHMT2)
-IC, FLMD0
1.8 Pin Groups 7: Pins supplied by VRO
- X1, X2, XT1, XT2
10
Data Sheet U18565EE1V2DS00
V850ES/FF3
2. Electrical Specifications of (A)-Grade
This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (Ta=25°C)
Parameter Symbol Conditions Rating Unit
VDD VDD=EVDD, -0.5 to +6.5 V
EVDD VDD=EVDD -0.5 to +6.5 V
Supply voltage
Input voltage
Analog input voltage VIAN Pin Group 4
High level output cur-
rent
Low level output current IOL
Operating ambient
temperature
Storage temperature Tstg -40 to +125
AVREF0 -0.5 to +6.5 V
VSS VSS=EVSS=AVSS -0.5 to +0.5 V
EVSS VSS=EVSS=AVSS -0.5 to +0.5 V
AVSS VSS=EVSS=AVSS -0.5 to +0.5 V
VI1 Pin Group 1x, 2x, 6
VI3 Pin Group 7
Pin Group 1x, 2x
IOH
Pin Group 4
Pin Group 1x, 2x
Pin Group 4
Ta
Normal operating mode -40 to +85
Flash programming mode -40 to +85
-0.5 to EVDD+0.5
Note1
-0.5 to VRO+0.5
Note1
-0.5 to AVREF0+0.5
1 pin -4 mA
To ta l - 50 m A
1 pin -4 mA
To ta l
1 pin 4 mA
To ta l 5 0 m A
1 pin 4 mA
To ta l
-20
20
Note1
Note2
Note2
mA
mA
V
V
V
°C
°C
Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins
unless otherwise specified
Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage.
2. Excluding ADC IAREF0 current.
2.2 Capacities
(Ta = 25°C, VDD = EVDD = AVREF0 = VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input/output capacitance CIO f=1MHz, Not measured pins is 0V. 10 pF
Data Sheet U18565EE1V2DS00
11
V850ES/FF3
2.3 Operating condition
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Internal System clock frequency (f
4.0≤f
≤32MHz
xx
Note1
32kHz≤f
12.5kHz≤fXT≤27.5kHz
f
RL
≤35kHz (Crystal)
XT
Note3
(240kHz Internal-OSC)
(RC)
VBCLK
)
Supply voltage Operating Condition
Operation of functions is usable under following
conditions:
• Peripheral clock frequency
≤ 32MHz
• f
4.0V≤VDD≤5.5V
Note2
• f
XP1
≤ 32MHz
XP2
• AC characteristics:
• Refer to chapter ’2.7 AC Characteris-
tics’ for details.
Operation of functions is usable under following
conditions:
• Peripheral clock frequency
≤ 20MHz
• f
3.5V≤VDD<4.0V
Note2
• f
XP1
≤ 20MHz
XP2
• AC characteristics:
• Refer to chapter ’2.7 AC Characteris-
tics’ for details.
Only operation of the following functions is
assured:
• CPU
• Flash (include programming)
• RAM
• IO Buffer
3.3V≤VDD<3.5V
Note2
• Port
• WT
• WDT
• INT
• CLM
• POC
• LVI
• A/D Converter
• Refer to chapter ’2.8 A/D Converter’ for
3.3V≤AVREF0 ≤5.5V
details.
• stop ADC for AVREF0 < 4.0V
(ADA0CE bit =0)
3.3V≤VDD<5.5V
3.3V≤VDD<5.5V
Note2
Note2
-
-
Notes: 1. For using SSCG please refer to ’2.5.5 SSCG Characteristics’ for details
2. VDD = EVDD
3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally.
12
Data Sheet U18565EE1V2DS00
V850ES/FF3
2.4 Voltage Regulator Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD
Output voltage VRO 2.5 V
Output voltage
stabilization time
t
REG
Note
Limited function see ’2.3 Operating condition’ 3.3 V
After VDD reaches voltage range min. 3.3V
To connect C=4.7uF on REGC terminal
Note: In case of non-POC device, be sure to start VDD in the state of RESET=VSS=0V.
For POC devices there is no need to control external RESET
function the internal RESET
signal will automatically controlled until VRO is stable.
terminal. For decives with POC
VDD
tREG
VRO
3.5 5.5 V
1ms
RESET
2.5 Clock Generator Circuit
2.5.1 Main System Clock Oscillation Circuit Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Crystal /
Ceramic resona-
tor
Refer to figure below
Oscillator fre-
quency (fx)
Oscillation stabili-
zation time
Note1
Note2
After STOP mode
After IDLE2 mode
Notes: 1. Indicates only oscillation circuit characteristics. Refer to ’2.7 AC Characteristics’ for CPU
operation clock.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage range MIN. 3.3V
3. Depends on the setting of the oscillation stabilization time select register (OSTS)
4. Minimum time required to stabilize flash. Time has to be secured by setting the oscillation
stabilization time select register (OSTS)
X1
X2
416MHz
Note4
64
54
Note4
Note3
Note3
μs
μs
Data Sheet U18565EE1V2DS00
13
V850ES/FF3
2.5.2 Sub System Clock Oscillation Circuit Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Crystal
resonator
RC
resonator
Refer to Figure 1
Refer to Figure 2
Oscillator fre-
quency (fxt)
Oscillation stabiliza-
tion time
Oscillator
frequency
Oscillation stabiliza-
tion time
Note1
Note2
Note1,4
Note2
R=390KΩ ±5%
C=47pF±10%
Note3
Note3
Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu opera-
tion clock.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC
Oscillator, internal system clock frequency (fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz.
32 32.768 35 kHz
,
25 40 55 kHz
100
10 s
μs
XT1 XT2 XT1 XT2
R
2.5.3 Internal-OSC Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output
frequency
Oscillation
stabilization
time
f
RL
f
RH
240kHz Internal-OSC 204 240 276 kHz
8MHz Internal-OSC 7.2 8.0 8.8 MHz
240kHz Internal-OSC 10 36 µs
8MHz Internal-OSC 51 92 256 µs
14
Data Sheet U18565EE1V2DS00
V850ES/FF3
2.5.4 PLL Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency
Output frequency fxx ≤256KB product 12 32 MHz
Lock time tPLL After VDD reaches voltage range min. 3.3V 800
Output period jitter
Note2
fx 4 16 MHz
f
PLLI
tpj Peak to peak 2.0 ns
Note1
36MHz
μs
Notes: 1. The input of the PLL (f
) can be set to fX, fX/2, or fX/4. The divider is set through an option
PLLI
byte in the code flash memory.
2. Not tested in production.
2.5.5 SSCG Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 16 MHz
Output frequency
Lock time
f
XX
t
SSCG
≤256KB product 12 32 MHz
After VDD reaches voltage range min. 3.3V 1000
μs
Remark: The SSCG MAX output frequency indicates the case without modulation. If modulation is
enabled the average SSCG frequency has to be set lower. The maximum achievable average operating frequency with modulation is as follows:
SSCG input clock divider selector
SFC1[6:4]
000B ± 0.5% ± 2.0% 31.4
001B ± 1.0% ± 2.5% 31.2
010B ± 2.0% ± 4.0% 30.7
011B ± 3.0% ± 6.0% 30.1
100B ± 4.0% ± 8.0% 29.4
101B ± 5.0% ± 10.0% 28.8
Percent modulation
TYP MAX ≤256KB product
Maximum average operating fre-
quency
Unit
MHz
Data Sheet U18565EE1V2DS00
15
V850ES/FF3
2.6 DC Characteristics
2.6.1 Input/Output Level
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter
High level
input voltage
Low level
input voltage
Input hysteresis
High level
output voltage
Note2
Low level output
voltage
Software pull-up
Software
pull-down resistor
Note2
resistor
Note1
Sym-
bol
VIH1 Pin Group 1B
VIH2
VIH3 Pin Group 2A
VIH4 Pin Group 4
VIH5 Pin Group 6
VIL1 Pin Group 1B EVSS
VIL2
VIL3 Pin Group 2A EVSS
VIL4 Pin Group 4 AVSS
VIL5 Pin Group 6 EVSS
VHYS1 Pin Group 1B
Pin Group 1D
VHYS2
Pin Group 2D
VHYS5 Pin Group 6
VOH1
VOH3 Pin Group 4
VOL1
VOL3 Pin Group 4 IOL=1.0mA 0 0.4 V
R1 VI=0V 10 30 100
R2 VI=VDD 10 30 100
Pin Group
Pin Group 1x,
P914, 915 IOL=3.0mA
Conditions MIN. TYP. MAX.
⋅EVDD
0.7
Pin Group 1D
Pin Group 2D
Pin Group 1D EVSS
Pin Group 2D EVSS
Center point at
0.5 x EVDD
Center point at
0.6 x EVDD
Center point at
0.6 x EVDD
Center point at
0.5 x EVDD
IOH=-1.0mA EVDD-1.0 EVDD V
1x, 2x
2x
IOH=-100uA EVDD-0.5 EVDD V
IOH=-1.0mA AVREF0-1.0 AVREF0 V
IOH=-100uA AVREF0-0.5 AVREF0 V
IOL=1.0mA
Note3
Note3
Note3
Note3
0.8
⋅EVDD
0.8
⋅EVDD
0.7⋅EVDD
0.7
⋅AVRE F0
0.8
⋅EVDD
0.267 x EVDD - 0.51V V
0.192 x EVDD - 0.31V V
0.192 x EVDD - 0.31V V
0.535 x EVDD - 0.9V
00.4V
0.3
0.4
0.4
0.3
0.3
0.2
Uni
EVDD V
EVDD V
EVDD V
EVDD V
AVR EF0 V
EVDD V
⋅EVDD
⋅EVDD
⋅EVDD
⋅EVDD
⋅AVR EF0
⋅EVDD
k
k
t
V
V
V
V
V
V
V
Ω
Ω
Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.
Notes: 1. DRST
terminal only. (Control register is OCDM)
2. Total IOH/IOL max is 20mA/-20mA each power supply line (EVDD and AVREF0).
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
3. Typical value. Not tested and guaranteed
16
Data Sheet U18565EE1V2DS00
V850ES/FF3
2.6.2 PIN leakage current
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High level input
leakage current
Low level input
leakage current
High level output
leakage current
Low level output
leakage current
ILIH1 VI=VDD
ILIL1 VI=0V
ILOH1 VO=VDD
ILOL1 VO=0V
Notes: 1. The input leakage current of FLMD0 is as follows:
High level input leakage current : 2.0uA
Low level input leakage current : -2.0uA
Analog pins 0.2
Other pins
Analog pins -0.2
Other pins
Analog pins 0.2
Other pins 0.5
Analog pins -0.2
Other pins -0.5
Note1
Note1
0.5
-0.5
uA
Data Sheet U18565EE1V2DS00
17
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