NEC V850ES-FF3 User Manual

Data Sheet

V850ES/FF3

32-bit Single-Chip Microcontroller

Hardware

µPD70F3372(A) µPD70F3373(A)
µPD70F3372(A1) µPD70F3373(A1)
µPD70F3372(A2) µPD70F3373(A2)

Document No. U18565EE1V2DS00

Date Published March 2008

© NEC Electronics 2008

Printed in Germany

V850ES/FF3

Notes for CMOS Devices

1. Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2. Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

3. Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

2

Data Sheet U18565EE1V2DS00

V850ES/FF3

Legal Notes

• The information in this document is current as of January 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that
may appear in this document.

• NEC Electronics does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from the use of NEC Electronics products
listed in this document or any other liability arising from the use of such NEC Electronics products.
No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Electronics or others.

• Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation
of these circuits, software and information in the design of customer's equipment shall be done under
the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred
by customers or third parties arising from the use of these circuits, software and information.

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics
products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated
entirely. To minimize risks of damage to property or injury (including death) to persons arising from
defects in NEC Electronics products, customers must incorporate sufficient safety measures in their
design, such as redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: “Standard”, “Special”
and “Specific”.

The "Specific" quality grade applies only to NEC Electronics products developed based on a
customer-designated “quality assurance program” for a specific application. The recommended
applications of NEC Electronics product depend on its quality grade, as indicated below. Customers
must check the quality grade of each NEC Electronics product before using it in a particular
application.

"Standard": Computers, office equipment, communications equipment, test and

measurement equipment, audio and visual equipment, home electronic
appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control

systems, anti-disaster systems, anti-crime systems, safety equipment and
medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control

systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in
NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products
in applications not intended by NEC Electronics, they must contact NEC Electronics sales
representative in advance to determine NEC Electronics 's willingness to support a given application.

Notes: 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also

includes its majority-owned subsidiaries.

2. "NEC Electronics products" means any product developed or manufactured by or for NEC
Electronics (as defined above).

3. SuperFlash

tries including the United States and Japan. This product uses SuperFlash
licensed from Silicon Storage Technology, Inc.

®

is a registered trademark of Silicon Storage Technology, Inc. in several coun-

®

technology

Data Sheet U18565EE1V2DS00

3

V850ES/FF3

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

4

Data Sheet U18565EE1V2DS00

For further information,
please contact:

NEC Electronics Corporation

1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: [phone]
http://www.necel.com/

[America]

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2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: [phone]
800-366-9782
http://www.am.necel.com/

[Europe]

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40472 Düsseldorf, Germany
Tel: [phone]
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78142 Velizy-Villacoublay Cédex
France
Tel: [phone]

Sucursal en España

Juan Esplandiu, 15
28007 Madrid, Spain
Tel: [phone]

V850ES/FF3

[Asia & Oceania]

NEC Electronics (China) Co., Ltd

7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
TEL: [phone]
http://www.cn.necel.com/

NEC Electronics Shanghai Ltd.

Room 2509-2510, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai P.R. China P.C:200120
Tel: [phone]
http://www.cn.necel.com/

NEC Electronics Hong Kong Ltd.

12/F., Cityplaza 4,
12 Taikoo Wan Road, Hong Kong
Tel: [phone]
http://www.hk.necel.com/

Seoul Branch

11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tel: [phone]

NEC Electronics Taiwan Ltd.

7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: [phone]

NEC Electronics Singapore Pte. Ltd.

238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: [phone]
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Entrance S (7th floor)
18322 Täby, Sweden
Tel: [phone]

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Via Fabio Filzi, 25/A
20124 Milano, Italy
Tel: [phone]

Branch The Netherlands

Steijgerweg 6
5616 HS Eindhoven
The Netherlands
Tel: [phone]

Data Sheet U18565EE1V2DS00

G06.6-1A

5

V850ES/FF3

Table of Contents

1. Pin Group Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Device package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Pin Groups 1x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3 Pin Groups 2x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Pin Groups 3x: Pins supplied by BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 Pin Groups 4: Pins supplied by AVREF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6 Pin Groups 5: Pins supplied by AVREF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.7 Pin Groups 6: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.8 Pin Groups 7: Pins supplied by VRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2. Electrical Specifications of (A)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.3 Power supply current (A-grade). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 18

2.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3. Electrical Specifications of (A1)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Data Sheet U18565EE1V2DS00

V850ES/FF3

Table of Contents

3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.6.3 Power supply current (A1-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 36

3.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

3.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

3.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4. Electrical Specifications of (A2)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.6.3 Power supply current (A2-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6.3.1 FF3 128KB mPD70F3372, FF3 256KB mPD70F3373. . . . . . . . . . . . . . . . . . . . . . . . 45

4.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

4.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Data Sheet U18565EE1V2DS00

7

V850ES/FF3

Table of Contents

5. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.1 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.2 Product Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2.2 Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8

Data Sheet U18565EE1V2DS00

V850ES/FF3

1. Pin Group Information

1.1 Device package information

The V850ES/Fx3 device series comprises several members. An overview with the pin and package
information is given in the following table:

Series Member # Pins Device package information

μPD70F3370A

μPD70F3371
μPD70F3372

μPD70F3373
μPD70F3374

μPD70F3375
μPD70F3376A
μPD70F3377A

μPD70F3378

μPD70F3379

μPD70F3380

μPD70F3381

μPD70F3382

μPD70F3383

μPD70F3384

μPD70F3385

64

80

100

144

176

FE3

FF3

FG3

FJ3

FK3

This document describes the specification for the V850ES/FF3.

1.2 Pin Groups 1x: Pins supplied by EVDD

1B: (SHMT1)

- P04, P30-31, P34; P40, P91, P913-915 (FE3)

- P04, P30-31, P34; P38-39, P40, P91, P913-915 (FF3)

- P04, P30-31, P34; P36-39, P40, P91, P911, P913-915 (FG3)

- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915 (FJ3)

- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915, P156-157
(FK3)

1D: (SHMT3)

- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FE3)

- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FF3)

- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P90, P92-910, P912 (FG3)

- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912 (FJ3)

- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912, P150-155 (FK3)

1.3 Pin Groups 2x: Pins supplied by EVDD

2A: (CMOS)

- PCM0-1 (FE3)

- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FF3)

2D: (SHMT3)

- PDL0-7 (FE3)

- PDL0-11 (FF3)

Data Sheet U18565EE1V2DS00

9

V850ES/FF3

1.4 Pin Groups 3x: Pins supplied by BVDD

3A: (CMOS)

- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FG3)

- PCD0-3, PCM0-5, PCS0-7, PCT0-7 (FJ3 + FK3)

3D: (SHMT3)

- PDL0-13 (FG3)

- PDL0-15 (FJ3 + FK3)

1.5 Pin Groups 4: Pins supplied by AVREF0

4: (CMOS)

- P70-79 (FE3)

-P70-711 (FF3)

- P70-715 (FG3)

- P70-715, P120-127 (FJ3 + FK3)

1.6 Pin Groups 5: Pins supplied by AVREF1

- P20-P215 (FK3) (CMOS)

1.7 Pin Groups 6: Pins supplied by EVDD

- RESET (SHMT2)

-IC, FLMD0

1.8 Pin Groups 7: Pins supplied by VRO

- X1, X2, XT1, XT2

10

Data Sheet U18565EE1V2DS00

V850ES/FF3

2. Electrical Specifications of (A)-Grade

This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (Ta=25°C)

Parameter Symbol Conditions Rating Unit

VDD VDD=EVDD, -0.5 to +6.5 V

EVDD VDD=EVDD -0.5 to +6.5 V

Supply voltage

Input voltage

Analog input voltage VIAN Pin Group 4

High level output cur-

rent

Low level output current IOL

Operating ambient

temperature

Storage temperature Tstg -40 to +125

AVREF0 -0.5 to +6.5 V

VSS VSS=EVSS=AVSS -0.5 to +0.5 V

EVSS VSS=EVSS=AVSS -0.5 to +0.5 V

AVSS VSS=EVSS=AVSS -0.5 to +0.5 V

VI1 Pin Group 1x, 2x, 6

VI3 Pin Group 7

Pin Group 1x, 2x

IOH

Pin Group 4

Pin Group 1x, 2x

Pin Group 4

Ta

Normal operating mode -40 to +85

Flash programming mode -40 to +85

-0.5 to EVDD+0.5

Note1

-0.5 to VRO+0.5

Note1

-0.5 to AVREF0+0.5

1 pin -4 mA
To ta l - 50 m A
1 pin -4 mA

To ta l

1 pin 4 mA
To ta l 5 0 m A
1 pin 4 mA

To ta l

-20

20

Note1

Note2

Note2

mA

mA

V

V

V

°C

°C

Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins

unless otherwise specified

Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage.

2. Excluding ADC IAREF0 current.

2.2 Capacities

(Ta = 25°C, VDD = EVDD = AVREF0 = VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input/output capacitance CIO f=1MHz, Not measured pins is 0V. 10 pF

Data Sheet U18565EE1V2DS00

11

V850ES/FF3

2.3 Operating condition

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Internal System clock frequency (f

4.0≤f

≤32MHz

xx
Note1

32kHz≤f

12.5kHz≤fXT≤27.5kHz

f

RL

≤35kHz (Crystal)

XT

Note3

(240kHz Internal-OSC)

(RC)

VBCLK

)

Supply voltage Operating Condition

Operation of functions is usable under following
conditions:

• Peripheral clock frequency
≤ 32MHz

• f

4.0V≤VDD≤5.5V

Note2

• f

XP1

≤ 32MHz

XP2

• AC characteristics:

• Refer to chapter ’2.7 AC Characteris-

tics’ for details.

Operation of functions is usable under following
conditions:

• Peripheral clock frequency
≤ 20MHz

• f

3.5V≤VDD<4.0V

Note2

• f

XP1

≤ 20MHz

XP2

• AC characteristics:

• Refer to chapter ’2.7 AC Characteris-

tics’ for details.

Only operation of the following functions is
assured:

• CPU

• Flash (include programming)

• RAM

• IO Buffer

3.3V≤VDD<3.5V

Note2

• Port

• WT

• WDT

• INT

• CLM

• POC

• LVI

• A/D Converter

• Refer to chapter ’2.8 A/D Converter’ for

3.3V≤AVREF0 ≤5.5V

details.

• stop ADC for AVREF0 < 4.0V
(ADA0CE bit =0)

3.3V≤VDD<5.5V

3.3V≤VDD<5.5V

Note2

Note2

-

-

Notes: 1. For using SSCG please refer to ’2.5.5 SSCG Characteristics’ for details

2. VDD = EVDD

3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally.

12

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.4 Voltage Regulator Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V))

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage VDD

Output voltage VRO 2.5 V
Output voltage

stabilization time

t

REG

Note

Limited function see ’2.3 Operating condition’ 3.3 V

After VDD reaches voltage range min. 3.3V

To connect C=4.7uF on REGC terminal

Note: In case of non-POC device, be sure to start VDD in the state of RESET=VSS=0V.

For POC devices there is no need to control external RESET
function the internal RESET

signal will automatically controlled until VRO is stable.

terminal. For decives with POC

VDD

tREG

VRO

3.5 5.5 V

1ms

RESET

2.5 Clock Generator Circuit

2.5.1 Main System Clock Oscillation Circuit Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Crystal /

Ceramic resona-

tor

Refer to figure below

Oscillator fre-

quency (fx)

Oscillation stabili-

zation time

Note1

Note2

After STOP mode

After IDLE2 mode

Notes: 1. Indicates only oscillation circuit characteristics. Refer to ’2.7 AC Characteristics’ for CPU

operation clock.

2. Time required to stabilize oscillation after VDD reaches oscillator voltage range MIN. 3.3V

3. Depends on the setting of the oscillation stabilization time select register (OSTS)

4. Minimum time required to stabilize flash. Time has to be secured by setting the oscillation

stabilization time select register (OSTS)

X1

X2

416MHz

Note4

64

54

Note4

Note3

Note3

μs
μs

Data Sheet U18565EE1V2DS00

13

V850ES/FF3

2.5.2 Sub System Clock Oscillation Circuit Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Crystal

resonator

RC

resonator

Refer to Figure 1

Refer to Figure 2

Oscillator fre-

quency (fxt)

Oscillation stabiliza-

tion time

Oscillator

frequency

Oscillation stabiliza-

tion time

Note1

Note2

Note1,4

Note2

R=390KΩ ±5%

C=47pF±10%

Note3

Note3

Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu opera-

tion clock.

2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V

3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.

4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC

Oscillator, internal system clock frequency (fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz.

32 32.768 35 kHz

,

25 40 55 kHz

100

10 s

μs

XT1 XT2 XT1 XT2

R

2.5.3 Internal-OSC Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Output

frequency

Oscillation

stabilization

time

f

RL

f

RH

240kHz Internal-OSC 204 240 276 kHz

8MHz Internal-OSC 7.2 8.0 8.8 MHz

240kHz Internal-OSC 10 36 µs

8MHz Internal-OSC 51 92 256 µs

14

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.5.4 PLL Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input frequency

Output frequency fxx ≤256KB product 12 32 MHz

Lock time tPLL After VDD reaches voltage range min. 3.3V 800

Output period jitter

Note2

fx 4 16 MHz

f

PLLI

tpj Peak to peak 2.0 ns

Note1

36MHz

μs

Notes: 1. The input of the PLL (f

) can be set to fX, fX/2, or fX/4. The divider is set through an option

PLLI

byte in the code flash memory.

2. Not tested in production.

2.5.5 SSCG Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input frequency fx 4 16 MHz

Output frequency

Lock time

f

XX

t

SSCG

≤256KB product 12 32 MHz

After VDD reaches voltage range min. 3.3V 1000

μs

Remark: The SSCG MAX output frequency indicates the case without modulation. If modulation is

enabled the average SSCG frequency has to be set lower. The maximum achievable aver­age operating frequency with modulation is as follows:

SSCG input clock divider selector

SFC1[6:4]

000B ± 0.5% ± 2.0% 31.4
001B ± 1.0% ± 2.5% 31.2
010B ± 2.0% ± 4.0% 30.7
011B ± 3.0% ± 6.0% 30.1
100B ± 4.0% ± 8.0% 29.4
101B ± 5.0% ± 10.0% 28.8

Percent modulation

TYP MAX ≤256KB product

Maximum average operating fre-

quency

Unit

MHz

Data Sheet U18565EE1V2DS00

15

V850ES/FF3

2.6 DC Characteristics

2.6.1 Input/Output Level

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter

High level

input voltage

Low level

input voltage

Input hysteresis

High level

output voltage

Note2

Low level output

voltage

Software pull-up

Software

pull-down resistor

Note2

resistor

Note1

Sym-

bol

VIH1 Pin Group 1B

VIH2

VIH3 Pin Group 2A

VIH4 Pin Group 4

VIH5 Pin Group 6

VIL1 Pin Group 1B EVSS

VIL2

VIL3 Pin Group 2A EVSS

VIL4 Pin Group 4 AVSS

VIL5 Pin Group 6 EVSS

VHYS1 Pin Group 1B

Pin Group 1D

VHYS2

Pin Group 2D

VHYS5 Pin Group 6

VOH1

VOH3 Pin Group 4

VOL1

VOL3 Pin Group 4 IOL=1.0mA 0 0.4 V

R1 VI=0V 10 30 100

R2 VI=VDD 10 30 100

Pin Group

Pin Group 1x,

P914, 915 IOL=3.0mA

Conditions MIN. TYP. MAX.

⋅EVDD

0.7

Pin Group 1D

Pin Group 2D

Pin Group 1D EVSS

Pin Group 2D EVSS

Center point at

0.5 x EVDD
Center point at

0.6 x EVDD
Center point at

0.6 x EVDD

Center point at

0.5 x EVDD

IOH=-1.0mA EVDD-1.0 EVDD V

1x, 2x

2x

IOH=-100uA EVDD-0.5 EVDD V
IOH=-1.0mA AVREF0-1.0 AVREF0 V
IOH=-100uA AVREF0-0.5 AVREF0 V

IOL=1.0mA

Note3

Note3

Note3

Note3

0.8

⋅EVDD

0.8

⋅EVDD

0.7⋅EVDD

0.7

⋅AVRE F0

0.8

⋅EVDD

0.267 x EVDD - 0.51V V

0.192 x EVDD - 0.31V V

0.192 x EVDD - 0.31V V

0.535 x EVDD - 0.9V

00.4V

0.3

0.4

0.4

0.3

0.3

0.2

Uni

EVDD V

EVDD V

EVDD V

EVDD V

AVR EF0 V

EVDD V

⋅EVDD
⋅EVDD
⋅EVDD
⋅EVDD

⋅AVR EF0

⋅EVDD

k

k

t

V

V

V

V

V

V

V

Ω

Ω

Remark: The characteristics of the dual-function pins are the same as those of the port pins unless

otherwise specified.

Notes: 1. DRST

terminal only. (Control register is OCDM)

2. Total IOH/IOL max is 20mA/-20mA each power supply line (EVDD and AVREF0).
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.

3. Typical value. Not tested and guaranteed

16

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.6.2 PIN leakage current

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High level input
leakage current

Low level input

leakage current

High level output

leakage current

Low level output

leakage current

ILIH1 VI=VDD

ILIL1 VI=0V

ILOH1 VO=VDD

ILOL1 VO=0V

Notes: 1. The input leakage current of FLMD0 is as follows:

High level input leakage current : 2.0uA
Low level input leakage current : -2.0uA

Analog pins 0.2

Other pins

Analog pins -0.2

Other pins

Analog pins 0.2

Other pins 0.5

Analog pins -0.2

Other pins -0.5

Note1

Note1

0.5

-0.5
uA

Data Sheet U18565EE1V2DS00

17

V850ES/FF3

2.6.3 Power supply current (A-grade)

2.6.3.1 FF3 128KB μPD70F3372, FF3 256KB μPD70F3373

(a) Absolute values

(Ta = -40 to +85°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition TYP. MAX. Unit

PLL: ON

12MHz≤fxx≤32MHz

All peripherals

running

Peripheral: f

PRSI option: 0

xx

PLL: OFF

4MHz≤f

Operating

mode

Note2,8

IDD1

Peripheral: f

PRSI option: 1

/2

xx

PLL: ON

12MHz≤fxx≤32MHz

PLL: ON

12MHz≤fxx≤32MHz

All peripherals

stopped

Peripheral: f

PRSI option: 0

xx

PLL: OFF

4MHz≤f

Peripheral: f

PRSI option: 1

/2

xx

PLL: ON

12MHz≤f

PLL: ON

12MHz≤f

All peripherals

running

Peripheral: f

PRSI option: 0

xx

PLL: OFF

4MHz≤f

HALT
mode

Note8

IDD2

Peripheral: f

PRSI option: 1

/2

xx

PLL: ON

12MHz≤f

PLL: ON

12MHz≤f

All peripherals

stopped

Peripheral: f

PRSI option: 0

xx

PLL: OFF

4MHz≤fxx≤16MHz

Peripheral: f

PRSI option: 1

/2

xx

PLL: ON

12MHz≤f

≤16MHz

xx

≤16MHz

xx

≤32MHz

xx

≤32MHz

xx

≤16MHz

xx

≤32MHz

xx

≤32MHz

xx

≤32MHz

xx

Note1

)

8MHz Internal-

8MHz Internal-

8MHz Internal-

8MHz Internal-

=20MHz

f

xx

fx=5MHz

fxx=32MHz

=16MHz

f

x

=8MHz

f

xx

Note3

OSC

=16MHz

f

xx

fx=16MHz

=32MHz

f

xx

=16MHz

f

x

=20MHz

f

xx

=5MHz

f

x

fxx=32MHz

fx=16MHz

f

=8MHz

xx

Note3

OSC

fxx=16MHz

=16MHz

f

x

fxx=32MHz

=16MHz

f

x

=20MHz

f

xx

=5MHz

f

x

=32MHz

f

xx

=16MHz

f

x

f

=8MHz

xx

Note3

OSC

f

=16MHz

xx

=16MHz

f

x

=32MHz

f

xx

=16MHz

f

x

fxx=20MHz

=5MHz

f

x

fxx=32MHz

=16MHz

f

x

f

=8MHz

xx

Note3

OSC

fxx=16MHz

=16MHz

f

x

=32MHz

f

xx

fx=16MHz

27 37 mA

39 51 mA

13 20 mA

21 30 mA

35 47 mA

22 mA

32 mA

12 mA

19 mA

31 mA

16 23 mA

24 34 mA

812mA

13 20 mA

20 27 mA

12 mA

18 mA

5mA

9mA

17 mA

18

Data Sheet U18565EE1V2DS00

V850ES/FF3

Mode Symbol Condition TYP. MAX. Unit

IDLE1

mode

IDLE2

mode

SUB

operating

Note5

mode

SubIDLE

mode

Note3,5

STOP

mode

Note3,4

IDD3

IDD4

IDD5

IDD6

IDD7

Peripheral (TAA, UARTD) run-

ning

All peripherals stopped

PLL: OFF

4MHz≤f

≤16MHz

xx

Note7

fxx=8MHz, 8MHz Internal-OSC

Crystal resonator (fxt = 32,768kHz) 80 400 μA

RC resonator (fxt=20kHz)

240 kHz Internal-OSC (SubOSC stopped) 220 1000 µA

Crystal resonator (fxt = 32,768kHz) 20 190 μA

RC resonator (fxt=20kHz)

240kHz Internal-OSC (SubOSC stopped) 25 180 μA

POC stop

POC work

240kHz Internal-OSC working 15.5 95 μA

240kHz Internal-OSC working 18.5 100 μA

fxx=5MHz

=5MHz

f

PLL: OFF

4MHz≤f

≤16MHz

xx

Note7

fxx=8MHz, 8MHz Internal-OSC

x

fxx=12MHz

=12MHz

f

x

=16MHz

f

xx

=16MHz

f

x

Note3

fxx=5MHz

=5MHz

f

PLL: OFF

4MHz≤f

≤16MHz

xx

Note7

fxx=8MHz, 8MHz Internal-OSC

x

fxx=12MHz

=12MHz

f

x

=16MHz

f

xx

=16MHz

f

x

Note3

fxx=5MHz

=5MHz

f

x

f

=12MHz

xx

=12MHz

f

x

=16MHz

f

xx

=16MHz

f

x

Note3

Note6

Note6

240kHz Internal-OSC stop 7.5 80 μA

240kHz Internal-OSC stop 10.5 85 μA

1.4 2.2 mA

2.0 3.1 mA

2.4 3.6 mA

1.5 2.3 mA

1.2 mA

1.4 mA

1.6 mA

1.1 mA

0.4 0.7 mA

0.7 1.0 mA

0.8 1.2 mA

0.2 0.5 mA

80 400 µA

40 220 μA

Data Sheet U18565EE1V2DS00

19

V850ES/FF3

(b) Calculation formulas

(Ta = -40 to +85°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition

PLL: ON

≤32MHz

xx

PLL: OFF

≤16MHz

xx

PLL: ON

PLL: ON

≤32MHz

xx

PLL: OFF

≤16MHz

xx

PLL: ON

≤32MHz

xx

PLL: ON

≤32MHz

xx

PLL: OFF

≤16MHz

xx

PLL: ON

PLL: ON

≤32MHz

xx

PLL: OFF

≤16MHz

xx

PLL: ON

≤32MHz

xx

PLL: OFF

≤16MHz

xx

Note7

Operating

mode

Note2,8

HALT
mode

Note8

IDLE1

mode

IDLE2

mode

IDD1

IDD2

IDD3

IDD4

Peripheral: f

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: f

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral (TAA, UARTD) run-

ning

All peripherals stopped

PLL: OFF

4MHz ≤fxx≤16MHz

12MHz≤f

xx

4MHz≤f

/2

xx

12MHz≤fxx≤32MHz

12MHz≤f

xx-

4MHz≤f

/2

xx

12MHz≤f

16MHz≤f

xx-

4MHz≤f

/2

xx

16MHz≤fxx≤32MHz

16MHz≤f

xx

4MHz≤f

/2

xx

16MHz≤f

4MHz≤f

Note7

Note1

)

)

Note9

TYP.

0.98⋅f

+7.1 1.18⋅fxx+13.6

xx

0.98⋅f

+5.5 1.18⋅fxx+10.6

xx

+6.0 1.08⋅fxx+12.2

0.90⋅f

xx

+6.2

0.81⋅f

xx

+5.7

0.83⋅f

xx

+6.2

0.79⋅f

xx

0.67⋅f

+3.0 0.90*fxx+5.4

xx

0.70⋅f

+1.9 1.00*fxx+4.0

xx

0.55⋅f

+2.8 0.64*fxx+7.0

xx

+2.8

0.46⋅f

xx

+1.6

0.44⋅f

xx

+1.8

0.46⋅f

xx

0.092⋅fxx+0.90 0.128⋅fxx+ 1.35

0.035⋅f

+1.01

xx

0.037⋅fxx+0.21 0.049⋅fxx+ 0.43

MAX.

Note9

Unit

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

Notes: 1. VDD and EVDD total current. (Ports are stopped).

AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull­down resistor) are not included.

2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program­ming mode), the current value (MAX. value) adds by the following value:

• Self-programming mode:

+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]

• Data flash programming mode:

+ 7-(0.18*fxx/4+3.0) [mA]

3. Main OSC is stopped.

4. Do not use SubOSC.

5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.

6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.

7. 8MHz Internal-OSC is stopped

8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.

9. The formulas are for reference only. Not all possible values for f

device inspection.

are tested in the outgoing

xx

20

Data Sheet U18565EE1V2DS00

2.7 AC Characteristics

AC test Input measurement points ( VDD, AVREF0, EVDD)

VDD

VSS

AC test output measurement points

VIH(min)

measure point

VIL(max)

V850ES/FF3

VIH(min)

VIL(max)

VOH(min)

measure point

VOL(max)

VOH(min)

VOL(max)

Load conditions

DUT

( Device under

test )

CL = 50 pF

Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load

capacitance of the device to 50pF or less by inserting a buffer or by some other means.

2.7.1 CLKOUT Output Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. MAX. Unit

Output cycle tCYK

High level width tWKH

Low level width tWKL

Rise time tKR

Fall time tKF

VDD = EVDD = 4.0V ~ 5.5V 31.25ns
VDD = EVDD = 3.5V ~ 5.5V 50ns

80μs

VDD = EVDD = 4.0V ~ 5.5V tCYK/2-13
VDD = EVDD = 3.5V ~ 5.5V tCYK/2-15
VDD = EVDD = 4.0V ~ 5.5V tCYK/2-13
VDD = EVDD = 3.5V ~ 5.5V tCYK/2-15
VDD = EVDD = 4.0V ~ 5.5V 13
VDD = EVDD = 3.5V ~ 5.5V 15
VDD = EVDD = 4.0V ~ 5.5V 13
VDD = EVDD = 3.5V ~ 5.5V 15

ns

ns

ns

ns

CLKOUT output timing

CLKOUT

•

t

KR

Data Sheet U18565EE1V2DS00

t

WKH

t

CYK

t

KF

t

WKL

21

V850ES/FF3

2.7.2 RESET, Interrupt, ADTRG Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

_RESET input low level width tWRSL analog filter 250 ns

NMI input high level width tWNIH analog filter 250 ns

NMI input low level width tWNIL analog filter 250 ns

INTPn

INTPn

Note1

input high level width

Note1

input low level width

tWITH

tWITL

Notes: 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST)

2. 2Tsamp+20 or 3Tsamp+20 ("Tsamp" is Noise reject sampling clock (NF macro))

Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective

edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.

2. RESET

, NMI, INTPn, ADTRG and DRST have analog noise filter. The typical filter time

is typ=60ns.

2.7.3 Key Return Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KRn input high level width tWKRH analog filter ,n=0-7 250 ns

KRn input low level width tWKRL analog filter ,n=0-7 250 ns

analog filter ,n=0-8 250 ns

digital filter ,n=3

Note2

ns

analog filter ,n=0-8 250 ns

digital filter ,n=3

Note2

ns

Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective

edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.

2. KRn inputs have analog noise filter. The typical filter time is typ=60ns.

2.7.4 Timer Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

TI input high level

width

TI input low level

width

tTIH

tTIL

TO output cycle tTCYK

TIAA00-01,10-11,20-21,30-31,40-41
TIAB00-03

Note1

TIAA00-01,10-11,20-21,30-31,40-41
TIAB00-03

Note1

TIAA00-01,10-11,20-21,30-31,

Note1

40-41
TIAB00-03

Note1

Note1

250 ns

Note1

250 ns

4.0V≤VDD≤5.5V 16 MHz

3.5V≤VDD<4.0V 10 MHz

Notes: 1. Except for the external trigger and external event function.

Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective

edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.

2. TIAAn and TIABn inputs have analog noise filter. The typical filter time is typ=60ns.

22

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.7.5 CSI Timing

(a) Master mode

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY1 125 ns
SCKBn high level width tKH1 tKCY1/2-15 ns
SCKBn low level width tKL1 tKCY1/2-15 ns
SIBn setup time ( to SCKBn ) tSIK1 30 ns
SIBn hold time ( from SCKBn ) tKSI1 25 ns
Delay time from SCKBn to SOBn tKSO1 25 ns

(b) Slave mode

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY1 200 ns
SCKBn high level width tKH1 90 ns
SCKBn low level width tKL1 90 ns
SIBn setup time ( to SCKBn ) tSIK1 50 ns
SIBn hold time ( from SCKBn ) tKSI1 50 ns
Delay time from SCKBn to SOBn tKSO1 50 ns

CSIBn n=0–2

t

KLn

SCKBn

t

SIK

SIBn

t

n

KSO

SOBn

t

KCYn

t

n

Input data

Output data

KSIn

t

KHn

2.7.6 UART Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Transfer rate 1.5 Mbps

ASCK0 frequency 10 MHz

Data Sheet U18565EE1V2DS00

23

V850ES/FF3

2.7.7 IIC Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol

SCL00 clock frequency fCLK 0 100 0 400 kHz
Bus-free time (between stop/start condi­tions)

Hold time
SCL00 clock low-level width tLOW 4.7 1.3 us
SCL00 clock high-level width tHIGH 4.0 0.6 us
Setup time for start/restart conditions tSU:STA 4.7 0.6 us

Data hold
time

Data setup time tSU:DAT 250

SDA00 and SCL00 signal rise time tR 1000

SDA00 and SCL00 signal fall time tF 300

Stop condition setup time tSU:STO 4.0 0.6 us
Pilse width with spike supporessed by

input filter
Capacitance load of each bus line Cb 400 400 pF

Note1

CBUS compatible master

IIC mode

tBUF 4.7 1.3 us

tHD:STA 4.0 0.6 us

tHD:DAT

tSP 0 50 ns

Normal mode High-speed mode

min. max. min. max.

5.0 us

0

Note2

Note2

0

Note4

100

20+0.1Cb

20+0.1Cb

Note3

0.9

300 ns

300 ns

Unit

us

ns

Notes: 1. At the start condition, the first clock pulse is generated after the hold time

2. The system requires a minimum of 300ns hold time Internally for the SDA signal ( at VIH-

min. of SCL00 signal )
In order to occupy the undefined area at the falling edge of SCL00.

3. If the system does not extend the SCL00 signal low hold time ( tlow ), only the maximum
data hold time (tHD:DAT ) needs to be satisfied.

4. The high-speed-mode IIC bus can be used In a normal-mode IIC bus system.
In this case, set the high-speed-mode IIC bus so that It meets the following conditions.

- If the system does not extend the SCL00 signal's low state hold time:
SU:DAT?250ns

- If the system extends the SCL00 signal's low state hold time:
Transmit the following data bit to the SDA00 line prior to releasing the SCL00 line
(tRmax.+tSU:DAT=1000+250=1250ns: Normal mode IIC bus specification ).

5. Cb: Total capacitance of one bus line (unit: pF)

24

Data Sheet U18565EE1V2DS00

IIC bus interface timing

V850ES/FF3

SCL00

SDA00

tBUF

Remark: P: Stop condition

S: Start condition
Sr: Restart condition

tR tLOW

tHD:DAT tHD:STA

S P

tSU:STA

tHIGH

tF

tSU:DAT

tSU:STO tSP tHD:STA

P Sr

Data Sheet U18565EE1V2DS00

25

V850ES/FF3

2.7.8 CAN Timing

(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Transfer rate 1Mbps

Internal delay time 100 ns

CAN Internal clock*

t

output

CTXDn pin

( Transfer data )

t

input

CRXDn pin

( Receive data )

Internal delay time (tNODE)= Internal Transfer Delay(t

*) CAN Internal clock (f

V850ES/Fx3

) :CAN baud rate clock

CAN

Internal Tr ansfer dela y

CTXDn pin

CAN

macro

Internal Receive delay

Image figure of Internal delay

CRXDn pin

) + Internal Receive Delay(t

output

input

)

26

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.8 A/D Converter

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall error
Conversion time tCONV 3.10 16
Stabilization time tSTA After ADA0PS bit = 0 -> 1 2
Recovery time for power down

mode

Zero-scale error

Full-scale error

Integral non-liniearity error

Differential non-liniearity error
Analog input voltage VIAN AVSS AVREF0 V
Analog input equivalent

circuit capacitance
Analog input equivalent

circuit resistance

AVREF0 current IAREF0

Conversion rusult when using
Diagnostic function

Note1

Note1

Note1

Note3

Note3,4

Note2

Note2

4.0V≤AVREF0<5.5V ±0.15 ±0.3 %FSR

tDPU 1 µs

ZSE ±0.3 %FSR

FSE ±0.3 %FSR

INL ±2.5 LSB

DNL ±1.5 LSB

CINA 6.19 pF

RINA 2.55 kΩ

A/D operating 4 7 mA
A/D operation stop 1 10 uA
AVREF0 conversion 3FC 3FF HEX
AVSS conversion 000 003 HEX

μs
μs

Notes: 1. Overall error excluding quantization error (±0.05%FSE). It is indicated as a ratio to the full-

scale value.

2. Excluding quantization error (±1/2 LSB)

3. Not tested in production.

4. Does not include input/output capacitance CIO

Data Sheet U18565EE1V2DS00

27

V850ES/FF3

2.9 POC

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Detect voltage VPOC0 3.3 3.5 3.7 V

Supply voltage rise time tPTH

Response time1

Response time2

Note1

Note2

tPTHD

tPD

VDD minimum width tPW 0.2 ms

Notes: 1. From detect voltage to release reset signal

2. From detect voltage to occurrence of reset signal

VDD

From VDD=0V to

VDD=3.3V

In case of power on.

After VDD reaches 3.7V.

In case of power off.

After VDD drop 3.3V.

0.002 ms

2.0 ms

0.2 1.0 ms

Detect voltag(MAX.)

(TYP.)
(MIN.)

tPTH tPTHD

tPD

tPW

tPTHD

T

Note: POC is available only in M2 devices. Refer to ’Ordering information’ in the V850ES/Fx3 User’s

Manual.

28

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.10 LVI

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Detect voltage

Response time

Note1

VDD minimum width tLW 0.2 ms
Reference voltage stabilization
wait time

Note2

Notes: 1. From detect voltage to occurrence interrupt/reset signal

2. If POC functionality is available, the wait time is not needed.

VDD

Detect voltag(MAX.)

(TYP.)

Operation voltage (MIN.)

(MIN.)

VLVI0 3.8 4.0 4.2 V
VLVI1 3.5 3.7 3.9 V

tLD

tLWAIT

After VDD reaches VLVI0/1(max).

After VDD drop VLVI0/1(min).

After VDD reaches 3.3V.

After LVION bit (LVIM.bit7) = 0->1

tLW

0.2 2.0 ms

0.1 0.2 ms

tLWAIT

LVION bit=0 1(LVI function work)

tLD

tLD

2.11 RAM Retention Flag

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Detect voltage VRAMH 1.9 2.0 2.1 V

Supply voltage rise time tRAMHTH From VDD=0V to VDD=3.3V 0.002 1800 ms

Response time

Note1

tRAMHD After VDD reaches 2.1V. 0.2 2.0 ms

VDD minimum width tRAMHW 0.2 ms

Notes: 1. From detect voltage to set RAMFbit (RAMS.bit0)

VDD

Operation voltage (MIN.)

Detect voltag(MAX.)

(TYP.)
(MIN.)

tRAMHTH

tRAMHD

tRAMHW

tRAMHD

T

T

Data Sheet U18565EE1V2DS00

29

V850ES/FF3

2.12 Data Retention Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V) (

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention power

supply voltage

Data retention power

supply current

VDDDR

IDDDR

Supply voltage rise time tRVD 1

Supply voltage fall time tFVD 1

Supply voltage hold time tHVD After STOP mode 0 ms

STOP release signal input

time

Data retention high-level

input voltage

Data retention low-level

input voltage

tDREL

VIHDR All input port 0.9VDDDR VDDDR V

VILDR All input port 0 0.1VDDDR V

Remark: When STOP mode is entered/released operation voltage range must be controlled.

STOP mode
(All function is stopped)
VDDDR=2.0V(
All function is stopped)

After VDD reaches operat­ing voltage range MIN.

3.3V

1.9 5.5 V

6.5 70

0ms

μA

μs
μs

Operation voltage(min.)

VDD/EVDD/BVDD

_RESET

NMI,INTPn(Input)

(When STOP mode is

released at falling edge)

NMI,INTPn(Input)

(When STOP mode is

released at rising edge)

Setting STOP mode

tHVD

tFVD tRVD

VDDDR

VIHDR

VIHDR

VILDR

tDREL

30

Data Sheet U18565EE1V2DS00

V850ES/FF3

2.13 Flash Memory Programming Characteristics

(a) Basic Characteristics

(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Operation frequency fCPU 4 32 MHz

Supply voltage VDD 3.3 5.5 V

Number of rewrites

High level input voltage VIH FLMD0 0.8EVDD EVDD V

Low level input voltage VIL FLMD0 EVSS 0.2EVDD V

Programming temperature tPRG -40 +85 °C

Data retention

CWRT1

CWRT2 10000

Notes: 1. Under the condition of CWRT1

2. Under the condition of CWRT2

Remark: The initial write when the product is shipped, any erase → write set of operations, or any

programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped → P → E → P → E → P :
Product is shipped → E → P → E → P → E → P : Rewrite count: 3

Code Flash

Data Flash

Code Flash

Data Flash

1000

Rewrite count: 3

15

5

count

Note1

year

Note2

(b) Serial Writing Operation Characteristics

(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time (from VDD) tDP 1 ms
RESET

release (from FLMD0) tPR 2 ms

FLMD0 pulse input start

(from raise edge of _RESET)

FLMD0 high level width /

low level width

FLMD0 raise time tR 50 ns

FLMD0 fall time tF 50 ns

tRP 800

tPW 10 100

μs

μs

Data Sheet U18565EE1V2DS00

31

V850ES/FF3

3. Electrical Specifications of (A1)-Grade

This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.

3.1 Absolute Maximum Ratings

Absolute Maximum Ratings (Ta=25°C)

Parameter Symbol Conditions Rating Unit

VDD VDD=EVDD, -0.5 to +6.5 V

EVDD VDD=EVDD -0.5 to +6.5 V

Supply voltage

Input voltage

Analog input voltage VIAN Pin Group 4

High level output cur-

rent

Low level output current IOL

Operating ambient

temperature

Storage temperature Tstg -40 to +125

AVREF0 -0.5 to +6.5 V

VSS VSS=EVSS=AVSS -0.5 to +0.5 V

EVSS VSS=EVSS=AVSS -0.5 to +0.5 V

AVSS VSS=EVSS=AVSS -0.5 to +0.5 V

VI1 Pin Group 1x, 2x, 6

VI3 Pin Group 7

Pin Group 1x, 2x

IOH

Pin Group 4

Pin Group 1x, 2x

Pin Group 4

Ta

Normal operating mode -40 to +110

Flash programming mode -40 to +110

1 pin -4 mA

1 pin -4 mA

1 pin 4 mA

1 pin 4 mA

-0.5 to EVDD+0.5

Note1

-0.5 to VRO+0.5

Note1

-0.5 to AVREF0+0.5

To ta l - 2 0 m A

To ta l

To ta l 2 0 m A

To ta l

-10

10

Note1

Note2

Note2

mA

mA

V

V

V

°C

°C

Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins

unless otherwise specified

Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage.

2. Excluding ADC0 IAREF0 current.

3.2 Capacities

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.3 Operating condition

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.4 Voltage Regulator Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.5 Clock Generator Circuit

3.5.1 Main System Clock Oscillation Circuit Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

32

Data Sheet U18565EE1V2DS00

V850ES/FF3

3.5.2 Sub System Clock Oscillation Circuit Characteristics

(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Note3

Note3

,

25 40 55 kHz

100

μs

RC

resonator

Refer to Figure 2

Oscillator

frequency

Oscillation stabiliza-

tion time

Note1,4

Note2

R=390KΩ ±5%

C=47pF±10%

Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu opera-

tion clock.

2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V

3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.

4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC

Oscillator, internal system clock frequency(fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz.

XT1

3.5.3 Internal-OSC Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.5.4 PLL Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.5.5 SSCG Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

XT2

R

Data Sheet U18565EE1V2DS00

33

V850ES/FF3

3.6 DC Characteristics

3.6.1 Input/Output Level

(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter

High level

input voltage

Low level

input voltage

Input hysteresis

High level

output voltage

Note2

Low level output

voltage

Software pull-up

Software

pull-down resistor

Note2

resistor

Note1

Sym-

bol

VIH1 Pin Group 1B

VIH2

VIH3 Pin Group 2A

VIH4 Pin Group 4

VIH5 Pin Group 6

VIL1 Pin Group 1B EVSS

VIL2

VIL3 Pin Group 2A EVSS

VIL4 Pin Group 4 AVSS

VIL5 Pin Group 6 EVSS

VHYS1 Pin Group 1B

Pin Group 1D

VHYS2

Pin Group 2D

VHYS5 Pin Group 6

VOH1

VOH3 Pin Group 4

VOL1

VOL3 Pin Group 4 IOL=1.0mA 0 0.4 V

R1 VI=0V 10 30 100

R2 VI=VDD 10 30 100

Pin Group

Pin Group 1x,

P914, 915 IOL=3.0mA

Conditions MIN. TYP. MAX.

⋅EVDD

0.7

Pin Group 1D

Pin Group 2D

Pin Group 1D EVSS

Pin Group 2D EVSS

1x, 2x

2x

Center point at

0.5 x EVDD
Center point at

0.6 x EVDD
Center point at

0.6 x EVDD

Center point at

0.5 x EVDD

IOH=-1.0mA EVDD-1.0 EVDD V
IOH=-100uA EVDD-0.5 EVDD V
IOH=-1.0mA AVREF0-1.0 AVREF0 V
IOH=-100uA AVREF0-0.5 AVREF0 V

IOL=1.0mA

Note3

Note3

Note3

Note3

⋅EVDD

0.8

0.8

⋅EVDD
⋅EVDD

0.7

⋅AVRE F0

0.7

0.8

⋅EVDD

0.267 x EVDD - 0.51V V

0.192 x EVDD - 0.31V V

0.192 x EVDD - 0.31V V

0.535 x EVDD - 0.9V

00.4V

0.3

0.4

0.4

0.3

0.3

0.2

Uni

EVDD V

EVDD V

EVDD V

EVDD V

AVR EF0 V

EVDD V

⋅EVDD
⋅EVDD
⋅EVDD
⋅EVDD

⋅AVR EF0

⋅EVDD

k

k

t

V

V

V

V

V

V

V

Ω

Ω

Remark: The characteristics of the dual-function pins are the same as those of the port pins unless

otherwise specified.

Notes: 1. DRST

terminal only. (Control register is OCDM)

2. Total IOH/IOL max is 20mA/-20mA for the power supply line EVDD.
Total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0.
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.

3. Typical value. Not tested and guaranteed

34

Data Sheet U18565EE1V2DS00

V850ES/FF3

3.6.2 PIN leakage current

(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High level input
leakage current

Low level input

leakage current

High level output

leakage current

Low level output

leakage current

ILIH1 VI=VDD

ILIL1 VI=0V

ILOH1 VO=VDD

ILOL1 VO=0V

Notes: 1. The input leakage current of FLMD0 is as follows:

High level input leakage current : 4.0uA
Low level input leakage current : -4.0uA

Analog pins 0.4

Other pins

Analog pins -0.4

Other pins

Analog pins 0.4

Other pins 0.8

Analog pins -0.4

Other pins -0.8

Note1

Note1

0.8

-0.8
uA

Data Sheet U18565EE1V2DS00

35

V850ES/FF3

3.6.3 Power supply current (A1-grade)

3.6.3.1 FF3 128KB μPD70F3372, FF3 256KB μPD70F3373

(a) Absolute values

(Ta = -40 to +110°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition TYP. MAX. Unit

PLL: ON

≤fxx≤32MHz

12MHz

Operating

mode

Note2,8

IDD1

All peripherals

running

Peripheral: f

PRSI option: 0

Peripheral: f

PRSI option: 1

xx

PLL: OFF

≤fxx≤16MHz

4MHz

/2

xx

PLL: ON

12MHz

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

12MHz

All peripherals

stopped

Peripheral: f

PRSI option: 0

Peripheral: f

PRSI option: 1

xx

PLL: OFF

4MHz

≤fxx≤16MHz

/2

xx

PLL: ON

12MHz

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

12MHz

HALT
mode

Note8

IDD2

All peripherals

running

Peripheral: f

PRSI option: 0

Peripheral: f

PRSI option: 1

xx

PLL: OFF

≤fxx≤16MHz

4MHz

/2

xx

PLL: ON

12MHz

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

12MHz

All peripherals

stopped

Peripheral: f

PRSI option: 0

Peripheral: f

PRSI option: 1

xx

PLL: OFF

≤fxx≤16MHz

4MHz

/2

xx

PLL: ON

12MHz

≤fxx≤32MHz

Note1

)

8MHz Internal-

8MHz Internal-

8MHz Internal-

8MHz Internal-

f

=20MHz

xx

=5MHz

f

x

f

=32MHz

xx

=16MHz

f

x

=8MHz

f

xx

OSC

=16MHz

f

xx

=16MHz

f

x

=32MHz

f

xx

=16MHz

f

x

f

=20MHz

xx

=5MHz

f

x

=32MHz

f

xx

=16MHz

f

x

=8MHz

f

xx

OSC

f

=16MHz

xx

=16MHz

f

x

f

=32MHz

xx

=16MHz

f

x

f

=20MHz

xx

=5MHz

f

x

f

=32MHz

xx

f

=16MHz

x

=8MHz

f

xx

OSC

Note3

f

=16MHz

xx

=16MHz

f

x

=32MHz

f

xx

=16MHz

f

x

f

=20MHz

xx

=5MHz

f

x

f

=32MHz

xx

=16MHz

f

x

=8MHz

f

xx

OSC

f

=16MHz

xx

f

=16MHz

x

=32MHz

f

xx

=16MHz

f

x

27 37 mA

39 51 mA

13 20 mA

Note3

21 30 mA

35 47 mA

22 mA

32 mA

12 mA

Note3

19 mA

31 mA

16 23 mA

24 34 mA

812mA

13 20 mA

20 27 mA

12 mA

18 mA

5mA

Note3

9mA

17 mA

36

Data Sheet U18565EE1V2DS00

V850ES/FF3

Mode Symbol Condition TYP. MAX. Unit

IDLE1

mode

IDLE2

mode

SUB

operating

Note5

mode

SubIDLE

Note3,

mode

STOP

mode

Note3,4

IDD3

IDD4

IDD5

IDD6

IDD7

Peripheral (TAA, UARTD) run-

ning

All peripherals stopped

PLL: OFF

≤fxx≤16MHz

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

RC resonator (fxt=20kHz)

240 kHz Internal-OSC (SubOSC stopped) 220 1200 µA

RC resonator (fxt=20kHz)

240kHz Internal-OSC (SubOSC stopped) 25 380

POC stop

POC work

240kHz Internal-OSC working 15.5 295

240kHz Internal-OSC working 18.5 300

fxx=5MHz

=5MHz

f

PLL: OFF

≤fxx≤16MHz

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

x

f

=12MHz

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

Note3

fxx=5MHz

=5MHz

f

PLL: OFF

≤fxx≤16MHz

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

x

f

=12MHz

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

Note3

fxx=5MHz

=5MHz

f

x

f

=12MHz

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

Note3

Note6

Note6

240kHz Internal-OSC stop 7.5 280

240kHz Internal-OSC stop 10.5 285

1.4 2.5 mA

2.0 3.4 mA

2.4 3.9 mA

1.5 2.6 mA

1.2 mA

1.4 mA

1.6 mA

1.1 mA

0.4 0.9 mA

0.7 1.2 mA

0.8 1.4 mA

0.2 0.7 mA

80 600 µA

40 420 μA

μA

μA
μA
μA
μA

Data Sheet U18565EE1V2DS00

37

V850ES/FF3

(b) Calculation formulas

(Ta = -40 to +110°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition

PLL: ON

12MHz

PLL: OFF

4MHz

12MHz

12MHz

PLL: OFF

4MHz≤f

12MHz

16MHz

PLL: OFF

4MHz

16MHz

16MHz

PLL: OFF

4MHz≤f

16MHz

PLL: OFF

4MHz

Note7

≤fxx≤32MHz

≤fxx≤16MHz

PLL: ON

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

≤16MHz

xx

PLL: ON

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

≤fxx≤16MHz

PLL: ON

≤fxx≤32MHz

PLL: ON

≤fxx≤32MHz

≤16MHz

xx

PLL: ON

≤fxx≤32MHz

≤fxx≤16MHz

Note7

Operating

mode

Note2,8

HALT
mode

Note8

IDLE1

mode

IDLE2

mode

IDD1

IDD2

IDD3

IDD4

Peripheral: f

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: f

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral (TAA, UARTD) run-

ning

All peripherals stopped

PLL: OFF

4MHz

≤fxx≤16MHz

xx

/2

xx

xx-

/2

xx

xx-

/2

xx

xx

/2

xx

Note1

)

Note9

TYP.

0.98

⋅f

+7.1 1.18⋅fxx+13.6

xx

⋅f

+5.5 1.18⋅fxx+10.6

0.98

xx

⋅f

+6.0 1.08⋅fxx+12.2

0.90

xx

⋅f

+6.2

0.81

xx

⋅f

+5.7

0.83

xx

⋅f

+6.2

0.79

xx

0.67

⋅f

+3.0 0.90*fxx+5.4

xx

0.70

⋅f

+1.9 1.00*fxx+4.0

xx

⋅f

+2.8 0.64*fxx+7.0

0.55

xx

⋅f

+2.8

0.46

xx

⋅f

+1.6

0.44

xx

⋅f

+1.8

0.46

xx

0.092⋅fxx+0.90 0.128⋅fxx+ 1.82

0.035

⋅f

+1.01

xx

0.037⋅fxx+0.21 0.049⋅fxx+ 0.63

MAX.

Note3

Unit

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

Notes: 1. VDD and EVDD total current. (Ports are stopped).

AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull­down resistor) are not included.

2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program­ming mode), the current value (MAX. value) adds by the following value:

• Self-programming mode:

+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]

• Data flash programming mode:

+ 7-(0.18*fxx/4+3.0) [mA]

3. Main OSC is stopped.

4. Do not use SubOSC.

5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.

6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.

7. 8MHz Internal-OSC is stopped

8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.

9. The formulas are for reference only. Not all possible values for f

device inspection.

are tested in the outgoing

xx

38

Data Sheet U18565EE1V2DS00

3.7 AC Characteristics

AC test Input measurement points ( VDD, AVREF0, EVDD)

VDD

VSS

AC test output measurement points

VIH(min)

measure point

VIL(max)

V850ES/FF3

VIH(min)

VIL(max)

VOH(min)

measure point

VOL(max)

VOH(min)

VOL(max)

Load conditions

DUT

( Device under

test )

CL = 50 pF

Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load

capacitance of the device to 50pF or less by inserting a buffer or by some other means.

3.7.1 CLKOUT Output Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.2 RESET, Interrupt, ADTRG Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.3 Key Return Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.4 Timer Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.5 CSI Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.6 UART Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.7 IIC Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.7.8 CAN Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

Data Sheet U18565EE1V2DS00

39

V850ES/FF3

3.8 A/D Converter

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.9 POC

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.10 LVI

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.11 RAM Retention Flag

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.12 Data Retention Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

3.13 Flash Memory Programming Characteristics

(a) Basic Characteristics

(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Operation frequency fCPU 4 32 MHz

Supply voltage VDD 3.3 5.5 V

Number of rewrites

High level input voltage VIH FLMD0 0.8EVDD EVDD V

Low level input voltage VIL FLMD0 EVSS 0.2EVDD V

Programming temperature tPRG -40 +110 °C

Data retention

CWRT1

CWRT2 10000

Code Flash

Data Flash

Code Flash

Data Flash

1000

15

Note2

5

Note1

count

year

Notes: 1. Under the condition of CWRT1

2. Under the condition of CWRT2

Remark: The initial write when the product is shipped, any erase → write set of operations, or any

programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped → P → E → P → E → P :

Rewrite count: 3

Product is shipped → E → P → E → P → E → P : Rewrite count: 3

(b) Serial Writing Operation Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.

40

Data Sheet U18565EE1V2DS00

V850ES/FF3

4. Electrical Specifications of (A2)-Grade

This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.

4.1 Absolute Maximum Ratings

Specification is identical to that from (A1)-Grade except

• Operating ambient temperature Ta = -40 to +125°C

•Note2: AVREF0 IOH/IOL current is including ADC0 max. current IAREF0.

4.2 Capacities

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

Data Sheet U18565EE1V2DS00

41

V850ES/FF3

4.3 Operating condition

(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Internal System clock frequency (f

4.0

≤fxx≤24MHz

Note1

12.5kHz

≤fXT≤27.5kHz

(240kHz Internal-OSC)

f

RL

Note3

(RC)

VBCLK

)

Supply voltage Operating Condition

Operation of functions is usable under following
conditions:

• Peripheral clock frequency

• f

≤ fXX

4.0V≤VDD≤5.5V

Note2

• f

XP1

XP2

≤ f

XX

• AC characteristics:

• Refer to chapter ’4.7 AC Characteris-

tics’ for details.

Operation of functions is usable under following
conditions:

• Peripheral clock frequency

• f

≤ 20MHz

≤VDD<4.0V

3.5V

Note2

• f

XP1

≤ 20MHz

XP2

• AC characteristics:

• Refer to chapter ’4.7 AC Characteris-

tics’ for details.

Only operation of the following functions is
assured:

• CPU

• Flash (include programming)

• RAM

• IO Buffer

3.3V

≤VDD<3.5V

Note2

• Port

• WT

• WDT

• INT

• CLM

• POC

• LVI

• A/D Converter

• Refer to chapter ’4.8 A/D Converter’ for

3.3V

≤AVR EF0≤5.5V

details.

• stop ADC for AVREF0 < 4.0V

(ADA0CE bit =0)

3.3V

≤VDD<5.5V

3.3V

≤VDD<5.5V

Note2

Note2

-

-

Notes: 1. For using SSCG please refer to ’4.5.5 SSCG Characteristics’ for details

2. VDD = EVDD

3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally.

4.4 Voltage Regulator Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.5 Clock Generator Circuit

4.5.1 Main System Clock Oscillation Circuit Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

42

Data Sheet U18565EE1V2DS00

V850ES/FF3

4.5.2 Sub System Clock Oscillation Circuit Characteristics

Specification is identical to that from (A1)-Grade except Ta=-40 to +125°C.

4.5.3 Internal-OSC Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.5.4 PLL Characteristics

(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input frequency

Output frequency fxx

Lock time tPLL After VDD reaches voltage range min. 3.3V 800

Output period jitter

Note2

fx 4 16 MHz

f

PLLI

tpj Peak to peak 2.0 ns

Note

≤256KB product 12 24 MHz

36MHz

μs

Notes: 1. The input of the PLL (f

) can be set to fX, fX/2, or fX/4. The divider is set through an option

PLLI

byte in the code flash memory.

2. Not tested in production.

4.5.5 SSCG Characteristics

(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input frequency fx 4 16 MHz

Output frequency fxx

Lock time

t

SSCG

After VDD reaches voltage range min. 3.3V 1000

≤256KB product 12 24 MHz

μs

Remark: The SSCG MAX output frequency indicates the case without modulation. If modulation is

enabled the average SSCG frequency has to be set lower. The maximum achievable aver­age operating frequency with modulation is as follows:

SSCG input clock divider selector

SFC1[6:4]

000B ± 0.5% ± 2.0% 23.5
001B ± 1.0% ± 2.5% 23.4
010B ± 2.0% ± 4.0% 23.0
011B ± 3.0% ± 6.0% 22.6
100B ± 4.0% ± 8.0% 22.1
101B ± 5.0% ± 10.0% 21.6

Percent modulation

TYP MAX

Maximum average operating fre-

quency

≤256KB product

Unit

MHz

Data Sheet U18565EE1V2DS00

43

V850ES/FF3

4.6 DC Characteristics

4.6.1 Input/Output Level

Specification is identical to that from (A1)-Grade except

• Ta = -40 to +125°C.

• Note 2:Total IOH/IOL max is 20mA/-20mA for the power supply lines EVDD.

Total IOH/IOL max is 3mA/-3mA for the power supply line AVREF0.
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
If ADC0 is not used total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0.

4.6.2 PIN leakage current

(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High level input
leakage current

Low level input

leakage current

High level output

leakage current

Low level output

leakage current

ILIH1 VI=VDD

ILIL1 VI=0V

ILOH1 VO=VDD

ILOL1 VO=0V

Analog pins 0.5

Other pins

Analog pins -0.5

Other pins

Analog pins 0.5

Other pins 1.0

Analog pins -0.5

Other pins -1.0

Note1

Note1

1.0

-1.0
uA

Notes: 1. The input leakage current of FLMD0 is as follows:

High level input leakage current: 5.0uA
Low level input leakage current: -5.0uA

44

Data Sheet U18565EE1V2DS00

V850ES/FF3

4.6.3 Power supply current (A2-grade)

4.6.3.1 FF3 128KB μPD70F3372, FF3 256KB μPD70F3373

(a) Absolute values

(Ta = -40 to +125°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition TYP. MAX. Unit

PLL: ON

≤fxx≤24MHz

12MHz

All peripherals

running

Peripheral: f

xx

PRSI option: 0

PLL: OFF

4MHz

≤fxx≤16MHz

Operating

mode

Note2,8

IDD1

All peripherals

stopped

Peripheral: f

xx

PRSI option: 0

PLL: ON

12MHz

PLL: OFF

4MHz

≤fxx≤24MHz

≤fxx≤16MHz

PLL: ON

≤fxx≤24MHz

12MHz

All peripherals

running

Peripheral: f

xx

PRSI option: 0

PLL: OFF

4MHz

≤fxx≤16MHz

HALT
mode

Note8

IDD2

All peripherals

stopped

Peripheral: f

xx

PRSI option: 0

PLL: ON

12MHz

PLL: OFF

4MHz

≤fxx≤24MHz

≤fxx≤16MHz

PLL: OFF

≤fxx≤16MHz

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

IDLE1

mode

Peripheral (TAA, UARTD) run-

ning

IDD3

PLL: OFF

≤fxx≤16MHz

All peripherals stopped

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

Note1

)

8MHz Internal-

8MHz Internal-

8MHz Internal-

8MHz Internal-

=20MHz

f

xx

=5MHz

f

x

=8MHz

f

xx

Note3

OSC

f

=16MHz

xx

=16MHz

f

x

=20MHz

f

xx

=5MHz

f

x

=8MHz

f

xx

Note3

OSC

f

=16MHz

xx

=16MHz

f

x

f

=20MHz

xx

=5MHz

f

x

=8MHz

f

xx

Note3

OSC

f

=16MHz

xx

=16MHz

f

x

=20MHz

f

xx

=5MHz

f

x

=8MHz

f

xx

Note3

OSC

f

=16MHz

xx

=16MHz

f

x

fxx=5MHz

=5MHz

f

x

=12MHz

f

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

fxx=5MHz

=5MHz

f

x

=12MHz

f

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

Note3

Note3

27 37 mA

13 20 mA

21 30 mA

22 mA

12 mA

19 mA

16 23 mA

812mA

13 20 mA

12 mA

5mA

9mA

1.4 2.8 mA

2.0 3.7 mA

2.4 4.2 mA

1.5 2.9 mA

1.2 mA

1.4 mA

1.6 mA

1.1 mA

Data Sheet U18565EE1V2DS00

45

V850ES/FF3

Mode Symbol Condition TYP. MAX. Unit

IDLE2

mode

SUB

operating

Note5

mode

SubIDLE

mode

Note3,5

STOP

mode

Note3,4

IDD4

IDD5

IDD6

IDD7

POC stop

POC work

fxx=5MHz

=5MHz

f

PLL: OFF

≤fxx≤16MHz

4MHz

Note7

fxx=8MHz, 8MHz Internal-OSC

RC resonator (fxt=20kHz)

Note6

Note3

x

f

=12MHz

xx

=12MHz

f

x

f

=16MHz

xx

=16MHz

f

x

240 kHz Internal-OSC (SubOSC stopped) 220 1450 µA

RC resonator (fxt=20kHz)

Note6

240kHz Internal-OSC (SubOSC stopped) 25 630

240kHz Internal-OSC stop 7.5 530

240kHz Internal-OSC working 15.5 545

240kHz Internal-OSC stop 10.5 535

240kHz Internal-OSC working 18.5 550

0.4 1.1 mA

0.7 1.5 mA

0.8 1.7 mA

0.2 1.0 mA

80 850 µA

40 670 μA

μA

μA
μA
μA
μA

46

Data Sheet U18565EE1V2DS00

(b) Calculation formulas

(Ta = -40 to +125°C, C=4.7uF,

VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V

Mode Symbol Condition

PLL: ON

12MHz

PLL: OFF

4MHz

12MHz

12MHz

PLL: OFF

4MHz≤f

12MHz

16MHz

PLL: OFF

4MHz

16MHz

16MHz

PLL: OFF

4MHz≤f

16MHz

PLL: OFF

4MHz

Note7

≤fxx≤24MHz

≤fxx≤16MHz

PLL: ON

≤fxx≤24MHz

PLL: ON

≤fxx≤24MHz

≤16MHz

xx

PLL: ON

≤fxx≤24MHz

PLL: ON

≤fxx≤24MHz

≤fxx≤16MHz

PLL: ON

≤fxx≤24MHz

PLL: ON

≤fxx≤24MHz

≤16MHz

xx

PLL: ON

≤fxx≤24MHz

≤fxx≤16MHz

Note7

Operating

mode

Note2,8

HALT
mode

Note8

IDLE1

mode

IDLE2

mode

IDD1

IDD2

IDD3

IDD4

Peripheral: f

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral: ff

All peripherals

PRSI option: 0

running

Peripheral: f

PRSI option: 1

Peripheral: f

All peripherals

PRSI option: 0

stopped

Peripheral: f

PRSI option: 1

Peripheral (TAA, UARTD) run-

ning

All peripherals stopped

PLL: OFF

4MHz

≤fxx≤16MHz

xx

/2

xx

xx-

/2

xx

xx-

/2

xx

xx

/2

xx

V850ES/FF3

Note1

)

Note9

TYP.

0.98

⋅f

+7.1 1.18⋅fxx+13.6

xx

⋅f

+5.5 1.18⋅fxx+10.6

0.98

xx

⋅f

+6.0 1.08⋅fxx+12.2

0.90

xx

⋅f

+6.2

0.81

xx

⋅f

+5.7

0.83

xx

⋅f

+6.2

0.79

xx

0.67

⋅f

+3.0 0.90*fxx+5.4

xx

0.70

⋅f

+1.9 1.00*fxx+4.0

xx

⋅f

+2.8 0.64*fxx+7.0

0.55

xx

⋅f

+2.8

0.46

xx

⋅f

+1.6

0.44

xx

⋅f

+1.8

0.46

xx

0.092⋅fxx+0.90 0.128⋅fxx+ 2.12

0.035

⋅f

+1.01

xx

0.037⋅fxx+0.21 0.049⋅fxx+ 0.88

MAX.

Note9

Unit

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

Notes: 1. VDD and EVDD total current. (Ports are stopped).

AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull­down resistor) are not included.

2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program­ming mode), the current value (MAX. value) adds by the following value:

• Self-programming mode:

+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]

• Data flash programming mode:

+ 7-(0.18*fxx/4+3.0) [mA]

3. Main OSC is stopped.

4. Do not use SubOSC.

5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.

6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.

7. 8MHz Internal-OSC is stopped

8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.

9. The formulas are for reference only. Not all possible values for f

device inspection.

are tested in the outgoing

xx

Data Sheet U18565EE1V2DS00

47

V850ES/FF3

4.7 AC Characteristics

AC test Input measurement points ( VDD, AVREF0, EVDD)

VDD

VSS

AC test output measurement points

Load conditions

VIH(min)

VIL(max)

VOH(min)

VOL(max)

DUT

( Device under

test )

measure point

measure point

VIH(min)

VIL(max)

VOH(min)

VOL(max)

CL = 50 pF

Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load

capacitance of the device to 50pF or less by inserting a buffer or by some other means.

4.7.1 CLKOUT Output Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.2 RESET, Interrupt, ADTRG Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.3 Key Return Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.4 Timer Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.5 CSI Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.6 UART Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.7 IIC Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.7.8 CAN Timing

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

48

Data Sheet U18565EE1V2DS00

V850ES/FF3

4.8 A/D Converter

(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall error
Conversion time tCONV 3.10 16
Stabilization time tSTA After ADA0PS bit = 0 -> 1 2
Recovery time for power down

mode

Zero-scale error

Full-scale error

Integral non-liniearity error

Differential non-liniearity error
Analog input voltage VIAN AVSS AVREF0 V
Analog input equivalent

circuit capacitance
Analog input equivalent

circuit resistance

AVREF0 current IAREF0

Conversion rusult when using
Diagnostic function

Note1

Note1

Note1

Note3

Note3,4

Note2

Note2

4.0V≤AVREF0<5.5V ±0.15 ±0.35 %FSR

tDPU 1 µs

ZSE ±0.35 %FSR

FSE ±0.35 %FSR

INL ±2.5 LSB

DNL ±1.5 LSB

CINA 6.19 pF

RINA 2.55 kΩ

A/D operating 4 7 mA
A/D operation stop 1 10 uA
AVREF0 conversion 3FC 3FF HEX
AVSS conversion 000 003 HEX

μs
μs

Notes: 1. Overall error excluding quantization error (±0.05%FSE). It is indicated as a ratio to the full-

scale value.

2. Excluding quantization error (±1/2 LSB)

3. Not tested in production.

4. Does not include input/output capacitance CIO

4.9 POC

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.10 LVI

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.11 RAM Retention Flag

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

4.12 Data Retention Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

Data Sheet U18565EE1V2DS00

49

V850ES/FF3

4.13 Flash Memory Programming Characteristics

(a) Basic Characteristics

(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Operation frequency fCPU 4 32 MHz

Supply voltage VDD 3.3 5.5 V

Number of rewrites

High level input voltage VIH FLMD0 0.8EVDD EVDD V

Low level input voltage VIL FLMD0 EVSS 0.2EVDD V

Programming temperature tPRG -40

Data retention

CWRT1

CWRT2

Notes: 1. Under the condition of CWRT1

2. Under the condition of CWRT2

Remark: The initial write when the product is shipped, any erase → write set of operations, or any

programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped → P → E → P → E → P :
Product is shipped → E → P → E → P → E → P : Rewrite count: 3

Code Flash

Data Flash

Code Flash

Data Flash

1000

10000

Rewrite count: 3

+125

15

5

count

°C

Note1

year

Note2

(b) Serial Writing Operation Characteristics

Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.

50

Data Sheet U18565EE1V2DS00

5. Package

5.1 Package Dimension

0-PIN PLASTIC LQFP (FINE PITCH) (12x12)

HD

D

V850ES/FF3

detail of lead end

60

61

80

1

ZE

ZD

y

S

NOTE

Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.

41

A3

c

40

θ

L

Lp

HE

E

21

20

e

M

Sxb

A

A2

S

A1

L1

(UNIT:mm)

ITEM DIMENSIONS

D

12.00 ±0.20

E

12.00 ±0.20

HD

14.00 ±0.20

HE

14.00 ±0.20

A

1.60 MAX.

A1

0.10 ±0.05

A2

1.40 ±0.05

A3

0.25

b

c

L

Lp

L1

θ

e

x

y

ZD

ZE

+0.07

0.20

−0.03
+0.075

0.125

−0.025

0.50

0.60 ±0.15

1.00 ±0.20

+5°

3°

−3°

0.50

0.08

0.08

1.25

1.25

P80GK-50-GAK

Data Sheet U18565EE1V2DS00

51

V850ES/FF3

5.2 Product Marking

5.2.1 Marking of pin 1 at a QFP (Quad Flat Package)

Example 1: The index mark for pin 1 is the beveled edge of the package
Example 2: The index mark for pin 1 is a round notch at one of the 4 edges. In this case, the shape of

all edges is identical (usually beveled).

Example 3: For production reasons, two or more similar notches may be located at the top of the pack-

age. In such a case the index marker for pin 1 is a round notch with an additional mark in it.

Note: RoHS compliant devices have an additional dot at the top side. Do not mix it up with the mark-

ing for pin 1. For details see 5.2.2 "Identification of Lead-Free Products" on page 53.

52

Data Sheet U18565EE1V2DS00

V850ES/FF3

5.2.2 Identification of Lead-Free Products

Lead-Free products are marked with a dot "•". The marking methods are the paint or the laser (It
doesn't sink in). The shape of lead-free marks is a circle.
Example:

Data Sheet U18565EE1V2DS00

53

V850ES/FF3

6. Change History

The following revision list shows all major changes of the different datasheet versions.

Version Chapter Comment

V1.0 Initial release

Removed ’Target Specification’ for (A)- and (A1)-Grade Devices in the Flash Pro­gramming specifications.

Changed specification of ’Number of rewrites’ from MAX. to MIN.

Remove Caution (Described in User’s Manual)

Changed document status from ’Preliminary Datasheet’ to ’Datasheet’.

Removed ’Target Specification’ for (A2)-Grade Devices in the Flash Programming
specifications.

V1.1

V1.2

2.13

3.13

2.8

4.8

4.13

54

Data Sheet U18565EE1V2DS00

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