NEC UPD784916B, UPD784915B Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD784915B, 784916B

16-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD784915B, 784916B are members of the NEC 78K/IV Series of microcontrollers equipped with a high-

speed 16-bit CPU and are versions with improved electrical characteristics of the

µ

PD784915 Subseries.

This series contains many peripheral hardware units ideal for VCR control, such as a multi-function timer unit

(super timer unit) suitable for software servo control and VCR analog circuits.

A one-time PROM version of the

µ

PD784916B, the µPD78P4916, is also available.

µ

PD784915A, 784916A of the

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µ

PD784915 Subseries User’s Manual - Hardware: U10444E

78K/IV Series User’s Manual - Instruction: U10905E

FEATURES

• High instruction execution speed realized by 16-bit CPU core

• Minimum instruction execution time: 250 ns (with 8-MHz internal clock)

• High internal memory capacity

Part Number ROM RAM

µ

PD784915B 49152 bytes 1280 bytes

µ

PD784916B 63488 bytes

• VCR analog circuits conforming to VHS Standard

• CTL amplifier

• RECCTL driver (rewritable)

• CFG amplifier

• DFG amplifier

• DPG comparator

• DPFG separation circuit (ternary separation circuit)

• Reel FG comparator (2 channels)

• CSYNC comparator

• Timer unit (super timer unit) for servo control

• Serial interface: 2 channels (3-wire serial I/O)

• A/D converter: 12 channels (conversion time: 10

• Low-frequency oscillation mode: main system clock frequency = internal clock frequency

• Low-power dissipation mode: CPU can operate with a subsystem clock.

• Supply voltage range: V

• Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current

DD = 2.7 to 5.5 V

µ

s)

APPLICATIONS

Control system/servo/timer of VCR

Unless mentioned otherwise, the µPD784916B is described as the representative product.

Document No. U13118EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan

The information in this document is subject to change without notice

©

1996

1998

ORDERING INFORMATION

Part Number Package

µ

PD784915BGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm)

µ

PD784916BGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm)

Remark xxx indicates ROM code suffix.

Product Development of 78K/IV Series

: Under mass production

: Under development

2

I

C bus supported

PD784038Y

µ

Standard

PD784026

µ

Enhanced A/D,
16-bit timer,
and power
management

PD784038

µ

Internal memory capacity was enhanced
Pin compatible with PD784026

µ

PD784216Y

µ

PD784216

100-pin
I/O and internal memory capacity
was enhanced

µ

µ

PD784915B, 784916B

Multimaster I2C bus supported

PD784225Y

µ

PD784225

µ

80-pin,
ROM correction was enhanced

Multimaster I2C bus supportedMultimaster I2C bus supported

PD784218Y

µ

PD784218

µ

Internal memory capacity was enhanced
ROM correction was added

ASSP

µ

PD784955

DC inverter control

PD784908

µ

On-chip IEBus
Controller

µ

PD78F4943

For CD-ROM,
56 Kbytes of flash memory

PD784915

µ

On-chip software servo control
VCR analog circuit, enhanced timer

TM

Multimaster I2C bus supported

µ

PD784054

PD784046

µ

On-chip 10-bit A/D

PD784928Y

µ

PD784928

µ

Function of the PD784915 was
enhanced

µ

2

Function List (1/2)

µ

PD784915B, 784916B

Item
Internal ROM capacity
Internal RAM capacity
Operating clock

Minimum instruction
execution time

I/O ports

Real-time output port
Super Timer/counter

timer
unit

Capture register

VCR special
circuit

General-purpose
timer

PWM output

Serial interface

A/D converter

µ

PD784915B
49152 bytes 63488 bytes
1280 bytes
16 MHz (internal clock: 8 MHz)

Low frequency oscillation mode: 8 MHz (internal clock: 8 MHz)
Low power dissipation mode: 32.768 kHz (subsystem clock)

250 ns (with 8-MHz internal system clock)

input : 8

54

I/O : 46

11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)

Timer/counter Compare register Capture register Remark

TM0 (16 bits) 3 ­TM1 (16 bits) 3 1

FRC (22 bits) - 6

TM3 (16 bits) 2 1

UDC (5 bits) 1 -

EC (8 bits) 4 - For HSW signal generation

EDV (8 bits) 1 - For CFG signal division

Input signal Number of bits Measurable cycle Operating edge

CFG 22 125 ns to 524 ms ↑↓

DFG 22 125 ns to 524 ms ↑
HSW 16 1 µs to 65.5 ms ↑↓
VSYNC 22 125 ns to 524 ms ↑

CTL 16 1 µs to 65.5 ms ↑↓
TREEL 22 125 ns to 524 ms ↑↓
SREEL 22 125 ns to 524 ms ↑↓

•VSYNC separation circuit, HSYNC separation circuit

• VISS detection, wide aspect detection circuits

• Field identification circuit

• Head amplifier switch/chroma rotation output circuit
Timer Compare register Capture register

TM2 (16 bits) 1 —
TM4 (16 bits) 1 (capture/compare) 1
TM5 (16 bits) 1 —

• 16-bit accuracy : 3 channels (carrier frequency: 62.5 kHz)

• 8-bit accuracy : 3 channels (carrier frequency: 62.5 kHz)

3-wire serial I/O: 2 channels

• BUSY/STRB control (1 channel only)

8-bit resolution × 12 channels, conversion time: 10 µs

µ

PD784916B

3

Function List (2/2)

µ

PD784915B, 784916B

Item

Analog circuit

Interrupt

External
Internal

Standby function

Watch function
Supply voltage
Package

µ

PD784915B

• CTL amplifier

• RECCTL driver (rewritable)

• DFG amplifier, DPG comparator, CFG amplifier

• DPFG separation circuit (ternary separation circuit)

• Reel FG comparator (2 channels)

• CSYNC comparator
4 levels (programmable), vector interrupt, macro service, context switching
9 (including NMI)
19 (including software interrupt)
HALT/STOP mode/low power dissipation mode/low power dissipation HALT mode
STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or

INTP1/INTP2/KEY0-KEY4 pins

0.5-second measurement, low-voltage operation (VDD = 2.7 V)
VDD = 2.7 to 5.5 V
100-pin plastic QFP (14 × 20 mm)

µ

PD784916B

4

PIN CONFIGURATION (Top View)

• 100-pin plastic QFP (14 x 20 mm)

µ

PD784915BGF-xxx-3BA

µ

PD784916BGF-xxx-3BA

100

1

P64

V
XT1
XT2

V

X2
X1

2
3
4
5
6
7
8
9
10
11
12
13

DD

14
15
16

SS

17
18
19
20

IC

21
22
23
24
25
26
27
28
29
30

3132333435363738 39 40 41 42 4344454647484950

P65/HWIN
P66/PWM4
P67/PWM5

P60/STRB/CLO

P61/SCK1/BUZ

P62/SO1

P63/SI1

PWM0
PWM1

SCK2

SO2

SI2/BUSY

RESET

PTO02
PTO01

PTO00
P87/PTO11
P86/PTO10

P85/PWM3
P84/PWM2

P83/ROTC

P82/HASW

CSYNCIN

REEL0IN/INTP3

REEL1IN

DFGIN96DPGIN95CFGCPIN

99

98

97

CFGAMPO

CFGIN92AV

94

93

DD1

SS1

AV

91

90

VREFC89CTLOUT2

CTLOUT1

CTLIN86RECCTL

88

87

-

RECTTL+

85

84

µ

PD784915B, 784916B

SS2

CTLDLY83AV

ANI1181ANI10

82

80

ANI9

79

ANI8

78

P77/ANI7

77

P76/ANI6

76

P75/ANI5

75

P74/ANI4

74

P73/ANI3

73

P72/ANI2

72

P71/ANI1

71

P70/ANI0
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

REF

AV

AV

DD2

P96

P95/KEY4

P94/KEY3

P93/KEY2

P92/KEY1

P91/KEY0

P90/ENV

NMI

INTP0

INTP1

INTP2

P00

P01

P02

P03

P04

P05

P06

SS

DD

V

P80

P57

P56

P55

P54

P53

P52

P51

P50

V

P47

P46

P45

P44

Caution Directly connect the IC (Internally Connected) pin to V

P43

P42

SS.

P41

P40

P07

5

µ

PD784915B, 784916B

ANI0-ANI11 : Analog Input P00-P07 : Port0
AVDD1, AVDD2 : Analog Power Supply P40-P47 : Port4
AV

SS1, AVSS2 : Analog Ground P50-P57 : Port5

AVREF : Analog Reference Voltage P60-P67 : Port6
BUSY : Serial Busy P70-P77 : Port7
BUZ : Buzzer Output P80, P82-P87 : Port8
CFGAMPO : Capstan FG Amplifier Output P90-P96 : Port9
CFGCPIN : Capstan FG Capacitor Input PTO00-PTO02 : Programmable Timer Output
CFGIN : Analog Unit Input PTO10, PTO11
CLO : Clock Output PWM0-PWM5 : Pulse Width Modulation Output
CSYNCIN : Analog Unit Input RECCTL+, RECCTL– : RECCTL Output/PBCLT Input
CTLDLY : Control Delay Input REEL0IN, REEL1IN : Analog Unit Input
CTLIN : CTL Amplifier Input Capacitor RESET : Reset
CTLOUT1, CTLOUT2 : CTL Amplifier Output ROTC : Chrominance Rotate Output
DFGIN : Analog Unit Input SCK1, SCK2 : Serial Clock
DPGIN : Analog Unit Input SI1, SI2 : Serial Input
ENV : Envelope Input SO1, SO2 : Serial Output
HASW : Head Amplifier Switch Output STRB : Serial Strobe
HWIN : Hardware Timer External Input V
IC : Internally Connected VREFC : Reference Amplifier Capacitor
INTP0-INTP3 : Interrupt From Peripherals V
KEY0-KEY4 : Key Return X1, X2 : Crystal (Main System Clock)
NMI : Nonmaskable Interrupt XT1, XT2 : Crystal (Subsystem Clock)

DD : Power Supply

SS : Ground

6

INTERNAL BLOCK DIAGRAM

µ

PD784915B, 784916B

NMI

INTP0 to INTP3

PWM0 to PWM5

PTO00 to PTO02

PTO10, PTO11

VREFC
REEL0IN
REEL1IN

CSYNCIN

DFGIN
DPGIN
CFGIN

CFGAMPO

CFGCPIN
CTLOUT1
CTLOUT2

CTLIN

RECCTL+

RECCTL

CTLDLY

AVDD1, AVDD2

AVSS1, AVSS2

AVREF

ANI0 to ANI1

SI1

SO1

SCK1

INTERRUPT

SUPER TIMER

­ANALOG UNIT

A/D CONVERTER

INTERFACE 1

CONTROL

UNIT

&

SERIAL

78K/IV

16-bit CPU CORE

(RAM: 512 bytes)

RAM

768 bytes

ROM

VDD
VSS

SYSTEM

CONTROL

CLOCK OUTPUT

BUZZER OUTPUT

KEY INPUT

REAL-TIME

OUTPUT PORT

PORT0 P00 to P07

PORT4 P40 to P47

PORT5 P50 to P57

PORT6 P60 to P67

PORT7 P70 to P77

X1
X2
XT1
XT2
RESET

CLO

BUZ

KEY0 to KEY4

P00 to P07

P80, P82, P83

SI2/BUSY

SO2
SCK2
STRB

SERIAL

INTERFACE 2

Remark Internal ROM capacity depends on the product.

PORT8 P80, P82 to P87

PORT9 P90 to P96

7

SYSTEM CONFIGURATION EXAMPLE

• Camera-contained VCR

Drum motor M

Capstan motor M

CTL head

Loading motor M

Driver

Driver

Driver

DFG

DPG

CFG

DFGIN
DPGIN

PWM0

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

µ

PD784916B

-

PORT

PORT

PORT

SCK1

SI1

SO1

INTP0

PORT

SCK2

SO2

BUSY

µ

PD784915B, 784916B

Key matrix

INTP0

Camera-

SCK

controlling

SO

microcontroller

SI

PD784036

µ

PORT

Camera block

CS
CLK

LCD C/D

µ

PD7225

DATA
BUSY

Audio/video

signal

processing

circuit

Remote
controller
signal

Composite sync signal
Video head switch
Audio head switch
Pseudo vertical sync signal

Remote controller
reception signal

µ

PC2800A

PORT
CSYNCIN

PTO00
PTO01
P80

INTP2

XT1 XT2X1 X2

16 MHz 32.768 kHz

PORT

STRB

PORT

LCD display panel

CS
CLK

OSD

DATA

µ

PD6461

BUSY
STB

Mechanical block

8

• Stationary VCR

Drum motor M

Capstan motor M

CTL head

Loading motor M

Reel motor

µ

PD784915B, 784916B

µ

PD784916B

DFG

DFGIN
DPGIN

DPG

Driver

Driver

Driver

Reel FG0

M

M

Driver

Driver

Reel FG1

PWM0

CFG

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

REEL0IN

PWM3

PWM4

REEL1IN

Low frequency
oscillation mode

-

CSYNCIN

PTO00
PTO01

PWM5

XT1 XT2X1 X2

PORT

SCK1

SI1

SO1

PORT

SCK2

SO2

PORT

Composite sync signal
Video head switch
Audio head switch
Pseudo vertical sync signal

P80

PORT

PORT

Remote controller

INTP2

reception signal

STB
CLK
DOUT
DIN

FIP

CS
CLK
DATA

TM

C/D

FIP

µ

PD16311

Key matrix

OSD

µ

PD6464

Audio/video signal

processing circuit

Mechanical block

µ

PC2800A

Tuner

Remote controller
signal

8 MHz 32.768 kHz

9

µ

PD784915B, 784916B

CONTENTS

1. DIFFERENCES AMONG µPD784915 SUBSERIES PRODUCTS .................................................. 11

2. PIN FUNCTIONS.............................................................................................................................. 12

2.1 Port Pins ................................................................................................................................................ 12

2.2 Non-Port Pins ........................................................................................................................................ 13

2.3 I/O Circuits and Connection of Unused Pins...................................................................................... 15

3. INTERNAL BLOCK FUNCTIONS.................................................................................................... 19

3.1 CPU Registers ....................................................................................................................................... 19

3.1.1 General-purpose registers ......................................................................................................... 19

3.1.2 Other CPU registers.................................................................................................................... 20

3.2 Memory Space....................................................................................................................................... 20

3.3 Special Function Registers (SFRs) ..................................................................................................... 23

3.4 Ports ....................................................................................................................................................... 28

3.5 Real-time Output Port ........................................................................................................................... 29

3.6 Super Timer Unit ................................................................................................................................... 33

3.7 Serial Interface ...................................................................................................................................... 38

3.8 A/D Converter ........................................................................................................................................ 40

3.9 VCR Analog Circuits ............................................................................................................................. 41

3.10 Watch Function ..................................................................................................................................... 47

3.11 Clock Output Function ......................................................................................................................... 48

4. INTERNAL/EXTERNAL CONTROL FUNCTION............................................................................ 49

4.1 Interrupt Function ................................................................................................................................. 49

4.1.1 Vector interrupt ........................................................................................................................... 51

4.1.2 Context switching ....................................................................................................................... 51

4.1.3 Macro service .............................................................................................................................. 52

4.1.4 Application example of macro service .....................................................................................54

4.2 Standby Function.................................................................................................................................. 57

4.3 Clock Generator Circuit........................................................................................................................ 59

4.4 Reset Function ...................................................................................................................................... 60

5. INSTRUCTION SETS....................................................................................................................... 61

6. ELECTRICAL CHARACTERISTICS ............................................................................................... 65

7. PACKAGE DRAWING ..................................................................................................................... 77

8. RECOMMENDED SOLDERING CONDITIONS............................................................................... 78

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 79

APPENDIX B. RELATED DOCUMENTS ............................................................................................... 81

10

µ

PD784915B, 784916B

1. DIFFERENCES AMONG µPD784915 SUBSERIES PRODUCTS

The µPD784915 Subseries consists of the six products listed in Table 1-1. The µPD784915A is a low-cost process-

shrinked version of the µPD784915. The µPD784916A expands the internal ROM capacity of the µPD784915 to 62

µ

Kbytes. The
and 784916A.

The µPD78P4916 features writable one-time PROM instead of the mask ROM of the µPD784915, 784915A,
784916A, 784915B, and 784916B. Except for this substitution of PROM for ROM and the fact that PROM capacity
differs from the ROM capacities offered in the other products, the
products.

In switching from the PROM product, used for debugging and testing application systems, to the mask ROM
products for mass production, be careful to check the differences among these products.

For details on the CPU functions and the internal hardware, refer to
Hardware (U10444E).

PD784915B and 784916B feature improved electrical characteristics compared to the µPD784915A

µ

PD78P4916 has the same functions as those

µ

PD784915 Subseries User’s Manual —

µ

Table 1-1. Differences among

PD784915 Subseries Products

Item

Internal ROM Mask ROM

Internal RAM 1280 bytes 2048 bytes
Internal memory capacity Not provided Provided

selection register (IMS)
Electrical characteristics The electrical characteristics of the µPD784915A/784916A, the µPD784915B/784916B,

Pin connections In the µPD78P4916, pin function for PROM read/write has been added.

µ

PD784915,

784915A

49152 bytes 63488 bytes 49152 bytes 63488 bytes 63232 bytes

and the µPD78P4916 differ with respect to the items listed below.

• P40 to P47, P50 to P57: Low-level input voltage

• VDD supply current

• Data hold current

• CTL amplifier: Phase signal elimination ratio

• CFG amplifier: CFGAMPO low-level output current
For details, refer to the data sheet of each product.

• µPD784915A/784916A Data Sheet (U11022J)

• µPD784915B/784916B Data Sheet (This document)

• µPD78P4916 Data Sheet (U11045J)

µ

PD784916A

µ

PD784915B

µ

PD784916B

µ

PD78P4916

Note

Note

Note The internal PROM and internal RAM capacities can be changed using the internal memory selection register

(IMS).

Caution The PROM version and mask ROM version differ in noise immunity and noise radiation, etc. When

considering replacing a PROM version with a mask ROM version when switching from preproduction
to volume production, perform sufficient evaluation using a CS version (not ES version) of the
mask ROM version.

11

2. PIN FUNCTIONS

2.1 Port Pins

µ

PD784915B, 784916B

Pin Name I/O

P00 to P07 I/O Real-time 8-bit I/O port (port 0).

P40 to P47 I/O

P50 to P57 I/O

P60 I/O STRB/CLO 8-bit I/O port (port 6).
P61 SCK1/BUZ • Can be set in input or output mode in 1-bit units.
P62 SO1 • Can be connected with software pull-up resistors.
P63 SI1
P64
P65 HWIN
P66 PWM4
P67 PWM5
P70 to P77 Input ANI0 to ANI7 8-bit input port (port 7)
P80 I/O Real-time Pseudo VSYNC output 7-bit I/O port (port 8).
P82 output port HASW output • Can be set in input or output mode in

P83 ROTC output • Can be connected with software pull-

P84 PWM2
P85 PWM3
P86 PTO10
P87 PTO11
P90 I/O ENV 7-bit I/O port (port 9).
P91 to P95 KEY0 to KEY4 • Can be set in input or output mode in 1-bit units.
P96

Alternate Function

output port • Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

-

-

-

-

8-bit I/O port (port 4).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

8-bit I/O port (port 5).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

• Can be connected with software pull-up resistors.

Function

1-bit units.

up resistors.

12

2.2 Non-Port Pins (1/2)

µ

PD784915B, 784916B

Pin Name I/O
REEL0IN Input INTP3 Reel FG input
REEL1IN
DFGIN
DPGIN
CFGIN
CSYNCIN
CFGCPIN
CFGAMPO Output
PTO00 Output
PTO01
PTO02
PTO10 P86
PTO11 P87
PWM0 Output
PWM1
PWM2 P84
PWM3 P85
PWM4 P66
PWM5 P67
HASW Output P82 Head amplifier switch signal output
ROTC Output P83 Chroma rotation signal output
ENV Input P90 Envelope signal input
SI1 Input P63 Serial data input (serial interface channel 1)
SO1 Output P62 Serial data output (serial interface channel 1)
SCK1 I/O P61/BUZ Serial clock I/O (serial interface channel 1)
SI2 Input BUSY Serial data input (serial interface channel 2)
SO2 Output
SCK2 I/O
BUSY Input SI2 Serial busy signal input (serial interface channel 2)
STRB Output P60/CLO Serial strobe signal output (serial interface channel 2)
ANI0 to ANI7 Analog input P70 to P77 Analog signal input of A/D converter
ANI8 to ANI11
CTLIN
CTLOUT1 Output
CTLOUT2 I/O
RECCTL+, RECCTL– I/O
CTLDLY
VREFC
NMI Input
INTP0 to INTP2 Input
INTP3 Input REEL0IN
KEY0 to KEY4 Input P91 to P95 Key input signal input
CLO Output P60/STRB Clock output
BUZ Output P61/SCK1 Buzzer output

--

--

--

Alternate Function

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Function

Drum FG, PFG input (ternary)
Drum PG input
Capstan FG input
Composite SYNC input
CFG comparator input
CFG amplifier output
Programmable timer output of super timer unit

PWM output of super timer unit

Serial data output (serial interface channel 2)
Serial clock I/O (serial interface channel 2)

CTL amplifier input capacitor connection
CTL amplifier output
Logic signal input/CTL amplifier output
RECCTL signal output/PBCTL signal input
External time constant connection (for RECCTL rewriting)
VREF amplifier AC connection
Non-maskable interrupt request input
External interrupt request input

13

2.2 Non-Port Pins (2/2)

µ

PD784915B, 784916B

Pin Name I/O
HWIN Input P65 External input of hardware watch counter
RESET Input
X1 Input
X2
XT1 Input
XT2
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
VDD
VSS
IC

-

-

--

--

--

--

--

--

Alternate Function

-

-

-

Function

Reset input
Crystal connection for main system clock oscillation

Crystal connection for subsystem clock oscillation.
Crystal connection for watch clock oscillation
Positive power supply to analog circuits
GND of analog circuits
Reference voltage input to A/D converter
Positive power supply to digital circuits
GND of digital circuits
Internally connected. Directly connect to VSS.

14

µ

PD784915B, 784916B

2.3 I/O Circuits and Connection of Unused Pins

Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins. For the

configuration of each type of I/O circuit, refer to Figure 2-1.

Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (1/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins
P00 to P07 5-A I/O Input: Connect to VDD
P40 to P47
P50 to P57
P60/STRB/CLO
P61/SCK1/BUZ 8-A
P62/SO1 5-A
P63/SI1 8-A
P64 5-A
P65/HWIN 8-A
P66/PWM4 5-A
P67/PWM5
P70/ANI0 to P77/ANI7 9 Input Connect to VSS
P80 5-A I/O Input: Connect to VDD
P82/HASW
P83/ROTC
P84/PWM2
P85/PWM3
P86/PTO10
P87/PTO11
P90/ENV
P91/KEY0 to P95/KEY4 8-A
P96 5-A
SI2/BUSY 2-A Input Connect to VDD
SO2 4 Output Hi-Z: Connect to VSS via a pull-down resistor

SCK2 8-A I/O Input: Connect to VDD

ANI8 to ANI11 7 Input Connect to VSS
RECCTL+, RECCTL– — I/O When ENCTL = 0 and ENREC = 0: Connect to VSS

Output: Leave open

Output: Leave open

Others: Leave open

Output: Leave open

Remark ENCTL : bit 1 of amplifier control register (AMPC)

ENREC: bit 7 of amplifier mode register 0 (AMPM0)

15

µ

PD784915B, 784916B

Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (2/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins
DFGIN — Input When ENDRUM = 0: Connect to VSS
DPGIN When ENDRUM = 0 or ENDRUM = 1 and SELPGSEPA

= 0: Connect to VSS
CFGIN, CFGCPIN When ENCAP = 0: Connect to VSS
CSYNCIN When ENCSYN = 0: Connect to VSS
REEL0IN/INTP3, REEL1IN When ENREEL = 0: Connect to VSS
CTLOUT1 — Output Leave open
CTLOUT2 — I/O When ENCTL = 0 and ENCOMP = 0: Connect to VSS

When ENCTL = 1: Leave open
CFGAMPO — Output Leave open
CTLIN — — When ENCTL = 0: Leave open
VREFC When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0:

Leave open
CTLDLY Leave open
PWM0, PWM1 3 Output Leave open
PTO00 to PTO02
NMI 2 Input Connect to VDD
INTP0 Connect to VDD or VSS
INTP1, INTP2 2-A Input Connect to VDD
AVDD1, AVDD2 — — Connect to VDD
AVREF, AVSS1, AVSS2 Connect to VSS
RESET 2 — —
XT1 — — Connect to VSS
XT2 Leave open
IC Directly connect to VSS

Remark ENDRUM : bit 2 of amplifier control register (AMPC)

SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0)
ENCAP : bit 3 of amplifier control register (AMPC)
ENCSYN : bit 5 of amplifier control register (AMPC)
ENREEL : bit 6 of amplifier control register (AMPC)
ENCTL : bit 1 of amplifier control register (AMPC)
ENCOMP : bit 4 of amplifier control register (AMPC)

16

Figure 2-1. I/O Circuits of Pins (1/2)

µ

PD784915B, 784916B

Type 2

IN

Schmitt trigger input with hysteresis characteristics

Type 2-A

V

DD

P-ch

pullup
enable

IN

Schmitt trigger input with hysteresis characteristics

Type 3

DD

V

P-ch

data

N-ch

OUT

Type 5-A

pullup

enable

data

output

disable

input

enable

Type 7

IN

P-ch
N-ch

DD

V

P-ch

N-ch

Comparator

+

-

V

P-ch

DD

IN/
OUT

Type 4

DD

data

output

disable

Push-pull output that can make output high
impedance (both P-ch and N-ch are off)

V

P-ch

N-ch

OUT

Type 8-A

pullup

enable

data

output

disable

V

REF

(threshold voltage)

DD

V

P-ch

N-ch

V

P-ch

DD

IN/
OUT

17

Type 9

Figure 2-1. I/O Circuits of Pins (2/2)

µ

PD784915B, 784916B

P-ch

IN

N-ch

V

Comparator

+

-

REF

(threshold voltage)

input enable

18

µ

PD784915B, 784916B

3. INTERNAL BLOCK FUNCTIONS

3.1 CPU Registers

3.1.1 General-purpose registers

µ

PD784916B has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-

The
purpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general­purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register.

These eight banks of general-purpose registers can be selected by software or context switching function.

The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the
internal RAM.

Figure 3-1. Configuration of General-Purpose Registers

A (R1) X (R0)

AX (RP0)

B (R3) C (R2)

BC (RP1)

R5 R4

RP2

R7 R6

RP3

R9 R8V

VP (RP4)

VVP (RG4)

R11 R10U

UP (RP5)

UUP (RG5)

D (R13) E (R12)T

DE (RP6)

TDE (RG6)

H (R15) L (R14)W

HL (RP7)

WHL (RG7)

( ): absolute name

8 banks

Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the
RSS bit is planned to be deleted from the future models in the 78K/IV Series.

19

µ

PD784915B, 784916B

3.1.2 Other CPU registers

(1) Program counter

µ

The program counter of the

PD784916B is 20 bits wide. The value of the program counter is automatically

updated as the program is executed.

19 0

PC

(2) Program status word

This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program
is executed.

12 11 10 9 8

PSWH UF15RBS214RBS113RBS0

PSW

PSWL S7Z

6

RSS

5AC4IE3

Note

0

P/V201CY

Note The RSS flag is provided to maintain compatibility with the microcontrollers in the 78K/III Series. Always

set this flag to 0 except when the software of the 78K/III Series is used.

(3) Stack pointer

This is a 24-bit pointer that holds the first address of the stack.
Be sure to write 0 to the high-order 4 bits.

23 0

SP

000200

3.2 Memory Space

The µPD784916B can access a 64 Kbyte memory space.
Table 3-1 shows the addresses of the internal ROM and internal data areas.

Table 3-1. Memory Space

Part Number Internal ROM Area Internal Data Area

µ

PD784915B 0000H-BFFFH FA00H-FFFFH

µ

PD784916B 0000H-F7FFH

Caution Some products in the 78K/IV Series can access up to 1 Mbyte of memory space in an address

expansion mode which is set by the LOCATION instruction. However, the memory space of the

µ

PD784916B is 64 Kbytes (0000H to FFFFH). Therefore, be sure to execute the LOCATION 0
instruction immediately after reset to set the memory space to 64 Kbytes (the LOCATION
instruction cannot be used more than twice).

20

µ

Figure 3-2. Memory Map of µPD784915B

FEFFH

FE80H

FE7FH

PD784915B, 784916B

General-purpose

registers (128 bytes)

FFFFH

FF00H

FEFFH

Data

memory

FA00H
F9FFH

Memory space (64 Kbytes)

C000H

BFFFH

data memory

Program memory/

Special function register

(SFR) (256 bytes)

Internal RAM

(1280 bytes)

Cannot be used

Internal ROM

(49152 bytes)

0000H

FE3BH

FE06H

FD00H
FCFFH

FA00H

BFFFH

1000H

0FFFH

0800H

07FFH

0080H
007FH

0040H
003FH

0000H

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(768 bytes)

Program/data area

(49152 bytes)

CALLF entry area

(2048 bytes)

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

21

Figure 3-3. Memory Map of µPD784916B

FEFFH

FE80H

FE7FH

µ

PD784915B, 784916B

General-purpose

registers (128 bytes)

FFFFH

FEFFH

Data

memory

FA00H
F9FFH

F7FFH

Memory space (64 Kbytes)

data memory

Program memory/

Special function register

FF00H

F800H

0000H

(SFR) (256 bytes)

Internal RAM

(1280 bytes)

Cannot be used

Internal ROM

(63488 bytes)

FE3BH

FE06H

FD00H
FCFFH

FA00H

F7FFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(768 bytes)

Program/data area

(63488 bytes)

CALLF entry area

(2048 bytes)

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

22

µ

PD784915B, 784916B

3.3 Special Function Registers (SFRs)

Special function registers are assigned special functions and mapped to a 256-byte space from addresses FF00H
through FFFFH. These registers include mode registers and control registers that control the internal peripheral
hardware units.

Caution Do not access an address to which no SFR is assigned. If such an address is accessed by

µ

mistake, the

Table 3-2 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Abbreviation............................ Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler

• R/W ......................................... Indicates whether the SFR in question can be read or written.

PD784916B may be deadlocked. This deadlock can be cleared only by reset input.

(RA78K4). With a C compiler (CC78K4), the abbreviation can be used as an sfr
variable by the #pragma sfr instruction.

R/W : Read/write
R : Read only
W : Write only

• Bit length ................................. Indicates the bit length (word length) of the SFR.

• Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that

can be manipulated in 16-bit units can be described as the operand sfrp of an
instruction. Specify an even address to manipulate this SFR.
An SFR that can be manipulated in 1-bit units can be described for a bit
manipulation instruction.

• After reset ............................... Indicates the status of each register after the RESET signal has been input.

23

µ

PD784915B, 784916B

Table 3-2. Special Function Registers (1/4)

Bit Bit Units for After

Address Special Function Register (SFR) Name Symbol R/W Length Manipulation Releasing

1 bit 8 bits 16 bits Reset
FF00H Port 0 P0 R/W 8 √√
FF04H Port 4 P4 8 √√
FF05H Port 5 P5 8 √√
FF06H Port 6 P6 8 √√
FF07H Port 7 P7 R 8 √√
FF08H Port 8 P8 R/W 8 √√
FF09H Port 9 P9 8 √√
FF0EH Port 0 buffer register L P0L 8 √√
FF0FH Port 0 buffer register H P0H 8 √√
FF10H Timer 0 compare register 0 CR00 16
FF11H Event counter compare register 0 ECC0 W 8
FF12H Timer 0 compare register 1 CR01 R/W 16
FF13H Event counter compare register 1 ECC1 W 8
FF14H Timer 0 compare register 2 CR02 R/W 16
FF15H Event counter compare register 2 ECC2 W 8
FF16H Timer 1 compare register 0 CR10 R/W 16
FF17H Event counter compare register 3 ECC3 W 8
FF18H Timer 1 compare register 1 CR11 R/W 16
FF1AH Timer 1 compare register 2 CR12 R 16
FF1CH Timer 1 compare register 3 CR13 R/W 16
FF1EH Timer 2 compare register 0 CR20 16
FF20H Port 0 mode register PM0 W 8
FF24H Port 4 mode register PM4 8
FF25H Port 5 mode register PM5 8
FF26H Port 6 mode register PM6 8
FF28H Port 8 mode register PM8 8
FF29H Port 9 mode register PM9 8
FF2EH Real-time output port 0 control register RTPC R/W 8 √√
FF30H Timer register 0 TM0 R 16
FF31H Event counter EC R/W 8
FF32H Timer register 1 TM1 R 16
FF34H Free running counter (bits 0 to 15) FRCL 16
FF35H Free running counter (bits 16 to 21) FRCH 8
FF36H Timer register 2 TM2 16
FF38H Timer control register 0 TMC0 R/W 8 √√
FF39H Timer control register 1 TMC1 8 √√
FF3AH Timer control register 2 TMC2 8 √√
FF3BH Timer control register 3 TMC3 8 √√

--

-

--

-

--

-

--

-

--

--

--

--

-

-

-

-

-

-

--

-

--

--

-

--

√

√

√

√

√
√
√
√
√
√

√

√

-

Undefined

-

-

-

-

-

-

-

­√ Cleared to 0

-

√

-

√

-

√

-

√
√
√
√

-

-

-

-

-

-

­√ Cleared to 0

-

√
√ 0000H

­√ Cleared to 0

-

-

-

-

FFH

FDH
7FH
00H

00H

00H

00×00000

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the

contents before initialization are undefined).

24

µ

PD784915B, 784916B

Table 3-2. Special Function Registers (2/4)

Bit Bit Units for After

Address Special Function Register (SFR) Name Symbol R/W Length Manipulation Releasing

1 bit 8 bits 16 bits Reset
FF3CH Timer register 3 TM3 R 16
FF3DH Timer control register 4 TMC4 R/W 8 √√
FF3EH Timer register 4 TM4 R 16

FF48H Port 8 mode control register PMC8 R/W 8 √√
FF4DH Trigger source select register TRGS0 8 √√
FF4EH Pull-up resistor option register L PUOL 8 √√
FF4FH Pull-up resistor option register H PUOH 8 √√

FF50H Input control register ICR 8 √√

FF51H Up/down counter count register UDC 8

FF52H Event divider counter EDV R 8

FF53H Capture mode register CPTM R/W 8 √√

FF54H Timer register 5 TM5 R 16

FF56H Timer 3 capture register 0 CPT30 16

FF58H Timer 0 output mode register TOM0 W 8

FF59H Timer 0 output control register TOC0 8

ADML

Note 1

Note 2

R/W 8

8 √√

FF5AH Timer 1 output mode register TOM1
FF5BH Timer 1 output control register TOC1 W 8
FF5CH Timer 3 compare register 0 CR30 R/W 16
FF5EH Timer 3 compare register 1 CR31 16

FF60H Port 8 buffer register L P8L 8 √√

FF63H Up/down counter compare register UDCC W 8

FF65H Trigger source select register 1 TRGS1 R/W 8 √√

FF66H Port 6 mode control register PMC6 8 √√

FF68H A/D converter mode register ADM 16

FF6AH A/D conversion result register ADCR R 8
FF6CH Hardware watch counter 0 HW0 R/W 16
FF6EH Hardware watch counter 1 HW1 R 16
FF6FH Watch mode register WM R/W 8 √√

FF70H PWM control register 0 PWMC0 R/W 8 √√

FF71H PWM control register 1 PWMC1 8 √√

FF72H PWM0 modulo register PWM0 16

FF73H PWM2 modulo register PWM2 8

FF74H PWM1 modulo register PWM1 16

FF75H PWM3 modulo register PWM3 8

--

--

-

-

--

--

-

-

-

-

--

--

-

--

-

--

--

--

-

--

-

√ Cleared to 0

-

××000000

√ Cleared to 0

-

-

-

-

-

√
√

√
√
√
√

√

√

√

√

-

-

-

√ Cleared to 0
√

-

-

-

-

√ Cleared to 0
√

-

-

-

­√ 0000H

-

-

√ Not affected
√ by reset

-

-

­√ 0000H

­√ 0000H

-

00H

10H

Undefined

Cleared to 0

00H

××000000

00H
80H
00H

000×0×0×
Undefined

00H

Undefined

00××0×00

05H
15H

00H

00H

Notes 1. When the timer 1 output mode register (TOM1) is read, the write sequence of the REC driver is read

(bits 0 and 1).

2. ADML is the low-order 8 bits of the A/D converter mode register (ADM) and can be manipulated in 1­or 8-bit units.

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the

contents before initialization are undefined).

25

µ

PD784915B, 784916B

Table 3-2. Special Function Registers (3/4)

Bit Bit Units for After

Address Special Function Register (SFR) Name Symbol R/W Length Manipulation Releasing

1 bit 8 bits 16 bits Reset
FF76H PWM5 modulo register PWM5 R/W 16
FF77H PWM4 modulo register PWM4 8
FF78H Event divider control register EDVC W 8
FF79H Clock output mode register CLOM R/W 8 √√
FF7AH Timer 4 capture/compare register 0 CR40 16
FF7BH Clock control register CC 8 √√
FF7CH Timer 4 capture register 1 CR41 R 16
FF7DH Capture/compare control register CRC W 8
FF7EH Timer 5 compare register CR50 R/W 16
FF84H Serial mode register 1 CSIM1 8 √√
FF85H Serial shift register 1 SIO1 8
FF88H Serial mode register 2 CSIM2 8 √√
FF89H Serial shift register 2 SIO2 8
FF8AH Serial control register 2 CSIC2 8
FF91H Head amplifier switch output control register HAPC 8 √√
FF94H Amplifier control register AMPC 8 √√
FF95H Amplifier mode register 0 AMPM0 8 √√
FF96H Amplifier mode register 1 AMPM1 8 √√
FF97H Gain control register CTLM 8 √√
FFA0H External interrupt mode register INTM0 8 √√
FFA1H External capture mode register 1 INTM1 8 √√
FFA2H External capture mode register 2 INTM2 8 √√
FFA6H Key interrupt control register KEYC 8 √√
FFA8H In-service priority register ISPR R 8 √√
FFAAH Interrupt mode control register IMC R/W 8 √√

FFACH Interrupt mask flag register MK0L 8 √√√ FFH
FFADH MK0H 8 √√
FFAEH MK1L 8 √√√
FFAFH MK1H 8 √√

FFB0H FRC capture register 0L CPT0L R 16
FFB1H FRC capture register 0H CPT0H 8
FFB2H FRC capture register 1L CPT1L 16
FFB3H FRC capture register 1H CPT1H 8
FFB4H FRC capture register 2L CPT2L 16
FFB5H FRC capture register 2H CPT2H 8
FFB6H FRC capture register 3L CPT3L 16
FFB7H FRC capture register 3H CPT3H 8
FFB8H FRC capture register 4L CPT4L 16

MK0

MK1

--

-

-

--

--

-

--

-

-

-

--

-

--

-

--

-

--

-

--

√ 0000H
√
√

√

√

√
√

√

√

√

√

-

-

­√ Cleared to 0

­√ Cleared to 0

­√ Cleared to 0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

√ Cleared to 0

-

√

-

√

-

√

-

√

00H
00H
00H

00H

00H

00H

Undefined

00H

Undefined

00H

000000×0

00H

70H
00H
80H

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the

contents before initialization are undefined).

26