NEC UPD75P3116GC-AB8, UPD75P3116GK-8A8 Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3116 replaces the µPD753108’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
µ
Because the
development stage using the
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
µ
PD753104, 753106, or 753108, and for use in small-scale production.
µ
PD753108 User’s Manual : U10890E
FEATURES
Compatible with µPD753108
Memory capacity:
• PROM : 16384 x 8 bits
• RAM : 512 x 4 bits
Can be operated in same power supply voltage range as the mask version µPD753108
DD = 1.8 to 5.5 V
• V
On-chip LCD controller/driver
QTOPTM microcontroller
Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
The support include writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number Package
µ
PD75P3116GC-AB8 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
µ
PD75P3116GK-8A8 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
Document No. U11369EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised points.
©
1994
µ
PD75P3116
FUNCTION OUTLINE
Item Function
Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µs (main system clock: @ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7 µs (main system clock: @ 6.0 MHz)
• 122 µs (subsystem clock: @ 32.768 kHz)
Internal memory PROM 16384 x 8 bits
RAM 512 x 4 bits
General-purpose register • 4-bit manipulation: 8 x 4 banks
• 8-bit manipulation: 4 x 4 banks
I/O ports CMOS input 8 Internal pull-up resistor connection can be specified by software: 7
CMOS I/O 20 Internal pull-up resistor connection can be specified by software: 12
Shared by segment pin: 8
N-ch open-drain I/O 4 13-V withstand voltage
Total 32
LCD controller/driver • Segment number selection: 16/20/24 segments (Switchable to CMOS I/O
ports in a batch of 4 pins, max. 8 pins)
• Display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
Timers 5 channels: • 8-bit timer/event counter : 3 channels
(Can be used as 16-bit timer/event counter, carrier generator,
and timer with gate)
• Basic interval timer/watchdog timer : 1 channel
• Watch timer : 1 channel
Serial interface • 3-wire serial I/O mode ··· MSB/LSB first switchable
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB) 16 bits
Clock output (PCL) Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)
Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)
Buzzer output (BUZ) • 2, 4, and 32 kHz (
• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)
Vectored interrupts • External : 3
• Internal : 5
Test inputs • External : 1
• Internal : 1
System clock oscillation circuit • Ceramic/crystal oscillation circuit for main system clock
• Crystal oscillation circuit for subsystem clock
Standby function STOP/HALT mode
Power supply voltage V
Package • 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
DD = 1.8 to 5.5 V
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz
)
2
µ
PD75P3116
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................. 4
2. BLOCK DIAGRAM ............................................................................................................................ 5
3. PIN FUNCTIONS ............................................................................................................................... 6
3.1 Port Pins ................................................................................................................................................... 6
3.2 Non-port Pins ........................................................................................................................................... 8
3.3 Equivalent Circuits for Pins .................................................................................................................... 10
3.4 Recommended Connection of Unused Pins ......................................................................................... 12
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 13
4.1 Differences between Mk I Mode and Mk II Mode ................................................................................... 13
4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 14
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, AND 753108 ...................... 15
6. MEMORY CONFIGURATION ........................................................................................................... 16
7. INSTRUCTION SET .......................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 27
8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 27
8.2 Program Memory Write Procedure ......................................................................................................... 28
8.3 Program Memory Read Procedure ......................................................................................................... 29
8.4 One-time PROM Screening ..................................................................................................................... 30
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 31
10. CHARACTERISTIC CURVES (REFERENCE VALUES) .................................................................. 46
11. PACKAGE DRAWINGS ................................................................................................................... 48
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50
APPENDIX A. FUNCTION LIST OF µPD75308B, 753108, AND 75P3116 ........................................... 51
APPENDIX B. DEVELOPMENT TOOLS................................................................................................ 53
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 57
3
1. PIN CONFIGURATION (Top View)
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) :µPD75P3116GC-AB8
µ
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch):
COM363COM262COM161COM060S059S158S257S356S455S554S653S752S851S950S1049S11
PD75P3116GK-8A8
µ
PD75P3116
64
BIAS
V
LC0
V
LC1
V
P30/LCDCL/MD0
P31/SYNC/MD1
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
LC2
P32/MD2
P33/MD3
Vss
P50/D4
P51/D5
P52/D6
P53/D7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note Always connect the V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
18
19
21
22X123X224
Note
XT120XT2
RESET
P63/KR3/D3
PP pin directly to VDD during normal operation.
VPP
25
26
VDD
P00/INT4
27
28
29
P01/SCK
P03/SI/SB1
P02/SO/SB0
33
30
31
32
P13/TI0
P10/INT0
P11/INT1
P12/INT2/TI1/TI2
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
PIN IDENTIFICATIONS
P00-P03 : Port0 COM0 to COM3 : Common Output 0 to 3
P10-P13 : Port1 V
LC0 to VLC2 : LCD Power Supply 0 to 2
P20-P23 : Port2 BIAS : LCD Power Supply Bias Control
P30-P33 : Port3 LCDCL : LCD Clock
P50-P53 : Port5 SYNC : LCD Synchronization
P60-P63 : Port6 TI0 to TI2 : Timer Input 0 to 2
P80-P83 : Port8 PTO0 to PTO2 : Programmable Timer Output 0 to 2
P90-P93 : Port9 BUZ : Buzzer Clock
KR0-KR3 : Key Return 0 to 3 PCL : Programmable Clock
SCK : Serial Clock INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
SI : Serial Input INT2 : External Test Input 2
SO : Serial Output X1, X2 : Main System Clock Oscillation 1, 2
SB0, SB1 : Serial Data Bus 0, 1 XT1, XT2 : Subsystem Clock Oscillation 1, 2
RESET : Reset V
MD0 to MD3 : Mode Selection 0 to 3 V
PP : Programming Power Supply
DD : Positive Power Supply
D0 to D7 : Data Bus 0 to 7 Vss : Ground
S0 to S23 : Segment Output 0 to 23
4
2. BLOCK DIAGRAM
µ
PD75P3116
BUZ/P23
PTO0/P20
TI1/TI2/
P12/INT2
PTO1/P21
PTO2/
PCL/P22
TOUT0
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
TI0/P13
TIMER/EVENT
COUNTER #1
TIMER/EVENT
COUNTER #2
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
TIMER/EVENT
COUNTER #0
INTT1
8-BIT
8-BIT
INTT2
CLOCKED
SERIAL
INTERFACE
INTERRUPT
CONTROL
4
BIT SEQ.
BUFFER (16)
WATCH
TIMER
INTW f
LCD
INTBT
8-BIT
INTT0 TOUT0
CASCADED
16-BIT
TIMER/
EVENT
COUNTER
INTCSI
TOUT0
INT1
PROGRAM
COUNTER (14)
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
CLOCK
OUTPUT
CONTROL
PCL/PTO2/P22
fx/2
CLOCK
DIVIDER
ALU
DECODE
AND
CONTROL
N
CPU CLOCK Φ
SYSTEM CLOCK
GENERATOR
MAIN SUB
X2X1 XT2XT1
CY
GENERAL
REG.
DATA
MEMORY
(RAM)
512 x 4 BITS
STAND BY
CONTROL
SP (8)
SBS
BANK
V
DD
PORT0 P00 to P03
PORT1 P10 to P13
PORT2
PORT3
PORT5
PORT6
PORT8 P80 to P83
PORT9 P90 to P93
f
LCD
V
PP
RESETVss
4
4
4
4
4
4
4
4
4
4
LCD
DRIVER
CONTROLLER/
P20 to P23
P30/MD0 to
P33/MD3
P50/D4 to
P53/D7
P60/D0 to
P63/D3
S0 to S1516
S16/P93 to
S19/P90
S20/P83 to
S23/P80
COM0 to COM34
BIAS
V
LC0
V
LC1
V
LC2
SYNC/P31
LCDCL/P30
5
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
µ
PD75P3116
Pin name I/O Alternate function Function 8-bit Status I/O circuit
I/O after reset type
P00 Input INT4 4-bit input port (PORT0) X Input <B>
P01 to P03 are 3-bit pins for which connection of
P01 I/O SCK an internal pull-up resistor can be specified by <F>-A
software.
P02 I/O SO/SB0 <F>-B
P03 I/O SI/SB1 <M>-C
P10 Input INT0 4-bit input port (PORT1) X Input <B>-C
Connection of an internal pull-up resistor can be
P11 INT1 specified by software in 4-bit units.
P10/INT0 can select noise elimination circuit.
P12 TI1/TI2/INT2
P13 TI0
P20 I/O PTO0 4-bit I/O port (PORT2) X Input E-B
Connection of an internal pull-up resistor
P21 PTO1 can be specified by software in 4-bit units.
P22 PCL/PTO2
P23 BUZ
P30 I/O LCDCL/MD0 Programmable 4-bit I/O port (PORT3) X Input E-B
Input and output in single-bit units can be specified.
P31 SYNC/MD1 When set for 4-bit units, connection of an internal
pull-up resistor can be specified by software.
P32 MD2
Note 1
P33 MD3
Note 2
P50
P51
P52
P53
Note 2
Note 2
Note 2
I/O D4 N-ch open-drain 4-bit I/O port (PORT5) X High M-E
When set to open-drain, voltage is 13 V. impedance
D5
D6
D7
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
3.1 Port Pins (2/2)
µ
PD75P3116
Pin name I/O Alternate function Function 8-bit Status I/O circuit
I/O after reset type
P60 I/O KR0/D0 Programmable 4-bit I/O port (PORT6) X Input <F>-A
Input and output in single-bit units can be specified.
P61 KR1/D1 When set for 4-bit units, connection of an internal
pull-up resistor can be specified by software.
P62 KR2/D2
P63 KR3/D3
P80 I/O S23 4-bit I/O port (PORT8) Input H
When set for 4-bit units, connection of an internal
P81 S22 pull-up resistor can be specified by software
P82 S21
P83 S20
P90 I/O S19 Programmable 4-bit I/O port (PORT9) Input H
When set for 4-bit units, connection of an internal
P91 S18 pull-up resistor can be specified by software
P92 S17
P93 S16
Note 3
Note 3
.
.
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low-level leak current increases when an input instruction or a bit manipulation instruction is performed.
3. Do not connect an internal pull-up resistor by software when used as the segment signal output.
Note 1
7
3.2 Non-port Pins (1/2)
µ
PD75P3116
Pin name I/O Alternate function Function Status I/O circuit
after reset type
TI0 Input P13 External event pulse input to timer/event counter Input <B>-C
TI1 P12/INT2/TI2
TI2 P12/INT2/TI1
PTO0 Output P20 Timer/event counter output Input E-B
PTO1 P21
PTO2 P22/PCL
PCL P22/PTO2 Clock output
BUZ P23 Frequency output (for buzzer or system clock trimming)
SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 P02 Serial data output <F>-B
Serial data bus I/O
SI/SB1 P03 Serial data input <M>-C
Serial data bus I/O
INT4 Input P00 Edge detection vectored interrupt input <B>
(valid for detecting both rising and falling edges)
INT0 Input P10 Edge detection vectored interrupt input
(detection edge is selectable)
INT1 P11
INT2 Input P12/TI1/TI2 Rising edge detection testable input Asynch
KR0 to KR3 I/O P60 to P63 Parallel falling edge detection testable input Input <F>-A
X1 Input — Ceramic/crystal resonator connection for main system — —
X2 — and input inverted phase to X2.
XT1 Input — Crystal resonator connection for subsystem clock oscillation. — —
XT2 — phase to XT2. XT1 can be used as a 1-bit (test) input.
RESET Input — System reset input (low-level active) — <B>
MD0 to MD3 Input P30 to P33 Mode selection for program memory (PROM) write/verify Input E-B
D0 to D3 I/O
D4 to D7 P50 to P53 M-E
Note 2
V
PP
VDD — — Positive power supply — —
Vss — — Ground potential — —
P60/KR0 to P63/KR3
— — Programmable power supply voltage applied for program — —
INT0/P10 can select noise elimination circuit.
clock oscillation. If using an external clock, input signal to X1
If using an external clock, input signal to XT1 and input inverted
Data bus for program memory (PROM) write/verify Input <F>-A
memory (PROM) write/verify.
For normal operation, connect directly to VDD.
Apply +12.5 V for PROM write/verify.
With noise elimination
circuit/asynch is selectable
Asynch
Input <B>-C
Note 1
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. The V
PP pin does not operate correctly when it is not connected to the VDD pin during normal operation.
8
µ
PD75P3116
3.2 Non-port Pins (2/2)
Pin name I/O Alternate function Function Status I/O circuit
after reset type
S0 to S15
S16 to S19
S20 to S23
COM0 to COM3
VLC0 to VLC2 — — Power supply for driving LCD — —
BIAS Output — Output for external split resistor cut Note 2 —
LCDCL
Note 3
SYNC
Note 3
Output — Segment signal output Note 1 G-A
Output P93 to P90 Segment signal output Input H
Output P83 to P80 Segment signal output Input H
Output — Common signal output Note 1 G-B
I/O P30/MD0 Clock output for driving external expansion driver Input E-B
I/O P31/MD1 Clock output for synchronization of external expansion driver Input E-B
Notes 1. The VPP pin does not operate normally if it is not connected with VDD pin when normal operation.
2. The V
LCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S0 to S23: V
LC1, COM0 to COM2: VLC2, COM3: VLC0
3. When the split resistor is incorporated : Low level
When the split resistor is not incorporated : High impedance
4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
9
3.3 Equivalent Circuits for Pins
µ
The equivalent circuits for the
TYPE A TYPE D
PD75P3116’s pins are shown in abbreviated form below.
µ
PD75P3116
VDD
P-ch
IN
N-ch
CMOS standard input buffer
IN
VDD
Data
Output
disable
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-BTYPE B
P.U.R.
enable
Data
Type D
Output
disable
P-ch
N-ch
VDD
P.U.R.
P-ch
IN/OUT
OUT
Schmitt trigger input with hysteresis characteristics.
TYPE B-C TYPE F-A
VDD
P.U.R.
P-ch
IN
P.U.R. : Pull-Up Resistor
P.U.R.
enable
Output
disable
Data
Type A
P.U.R. : Pull-Up Resistor
P.U.R.
enable
Type D
Type B
P.U.R. : Pull-Up Resistor
VDD
P.U.R.
P-ch
IN/OUT
(Continued)
10
TYPE F-B TYPE H
VDD
P.U.R.
µ
PD75P3116
(Continued)
Output
disable
(P)
Data
Output
disable
Output
disable
(N)
P.U.R. : Pull-Up Resistor
LC0
V
VLC1
SEG
data
V
LC2
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
P.U.R.
enable
VDD
P-ch
N-ch
N-chP-ch
N-ch
P-ch
IN/OUT
OUT
Output
disable
TYPE M-CTYPE G-A
SEG
data
Data
Output
disable
Data
Type G-A
Type E-B
P.U.R.
enable
N-ch
P-ch
N-ch
IN/OUT
VDD
P.U.R.
P-ch
IN/OUT
N-ch
TYPE G-B TYPE M-E
LC0
V
VLC1
COM
data
VLC2
P-ch
N-ch
N-ch
P-ch
N-ch
P-ch
N-ch
N-chP-ch
P-chN-ch
Input instruction
OUT
Data
Output
disable
Pull-up resistor that operates only when an input
Note
instruction is executed. (The current flows from
V
P.U.R. : Pull-Up Resistor
N-ch
(+13-V
withstand
Note
Voltage
controller
voltage)
(+13-V
withstand
voltage)
VDD
P-ch
P.U.R.
DD to a pin when the pin is at low level.)
IN/OUT
11
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Unused Pin Connection
Pin Recommended connection
P00/INT4 Connect to Vss or VDD
P01/SCK Individually connect to Vss or VDD through a resistor.
P02/SO/SB0
P03/SI/SB1 Connect to Vss
P10/INT0 and P11/INT1 Connect to Vss or V
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0 Input status : Individually connect to Vss or V
P21/PTO1 through a resistor
P22/PTO2/PCL Output status : Leave open
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
P50/D4 to P53/D7 Connect to Vss
P60/KR0/D0 to P63/KR3/D3 Input status :
Output status : Leave open
S0 to S15 Leave open
COM0 to COM3
S16/P93 to S19/P90 Input status :
S20/P83 to S23/P80 Output status : Leave open
V
LC0 to VLC2 Connect to Vss
BIAS Connect to Vss only when neither of V
VLC2 is used. In other cases, leave open.
Note
XT1
Note
XT2
V
PP Always connect to VDD directly
Connect to Vss or VDD
Leave open
DD
DD
Individually connect to Vss or VDD through a resistor
Individually connect to Vss or VDD through a resistor
LC0, VLC1 and
µ
PD75P3116
12
Note In case the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback
resistor not used).
µ
PD75P3116
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3116 enables the program memory to be switched between
µ
the Mk I mode and Mk II mode. This function is applicable when using the
753106, or 753108.
When the SBS bit 3 is set to 1 : sets the Mk I mode (supports the Mk I mode for the
When the SBS bit 3 is set to 0 : sets the Mk II mode (supports the Mk II mode for the
4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists differences between the Mk I mode and the Mk II mode for the
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item Mk I mode Mk II mode
Program counter PC
Program memory (bytes) 16384
Data memory (bits) 512 x 4
Stack Stack bank Selectable via memory banks 0, 1
No. of stack bytes 2 bytes 3 bytes
Instruction BRA !addr1 instruction Not available Available
CALLA !addr1 instruction
Instruction CALL !addr instruction 3 machine cycles 4 machine cycles
execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles
Supported mask ROMs When set to Mk I mode: When set to Mk II mode:
13-0
µ
PD753104, 753106, and 753108
PD75P3116 to evaluate the µPD753104,
µ
PD753104, 753106, and 753108)
µ
PD753104, 753106, and 753108)
µ
PD75P3116.
µ
PD753104, 753106, and 753108
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore,
this mode is effective for enhancing software compatibility with products that have a program area of
more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.
13
µ
PD75P3116
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of
the stack bank selection register.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
Note
sure to initialize the stack bank selection register to 100XB
Note
be sure to initialize it to 000XB
.
at the beginning of the program. When using the Mk II mode,
Note Set the desired value for X.
Figure 4-1. Format of Stack Bank Selection Register
Address 3 2 1 0
SBS3 SBS2 SBS1 SBS0F84H
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
Setting prohibited
1
1
0 Be sure to enter “0” for bit 2.
Mode selection specification
01Mk II mode
Mk I mode
Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to “0” and set the Mk II mode before using the instructions.
14
µ
PD75P3116
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108
The µPD75P3116 replaces the internal mask ROM in the µPD753104, 753106, and 753108 with a one-time PROM and
features expanded ROM capacity. The µPD75P3116’s Mk I mode supports the Mk I mode in the µPD753104, 753106,
and 753108 and the µPD75P3116’s Mk II mode supports the Mk II mode in the µPD753104, 753106, and 753108.
µ
Table 5-1 lists differences among the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details on the CPU functions and internal hardware, refer to the User’s Manual.
Table 5-1. Differences between
PD75P3116 and the µPD753104, 753106, and 753108. Be sure to check the
µ
PD75P3116 and µPD753104, 753106, and 753108
Item
Program counter 12 bits 13 bits 14 bits
Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM
Data memory (x 4 bits) 512
Mask options Pull-up resistor for Available Not available
PORT5 (On chip/not on chip can be specified.) (Not on chip)
Split resistor for
LCD driving power supply
Wait time after Available Not available
RESET (Selectable between 217/fX and 215/fX) (fixed to 215/fX)
Feedback resistor Available Not available
of subsystem clock (Use/not use can be selected.) (Enable)
Pin configuration Pin Nos. 5 to 8 P30 to P33
Pin Nos. 10 to 13 P50 to P53 P50/D4 to P53/D7
Pin Nos. 14 to 17 P60/KR0 to P63/KR3
Pin No. 21 IC VPP
Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask
µ
PD753104
4096 6144 8192 16384
layouts.
µ
PD753106
µ
PD753108
µ
P30/MD0 to P33/MD3
P60/KR0/D0 to P63/KR3/D3
PD75P3116
Note 217/fX : 21.8 ms at 6.0-MHz operation, 31.3 ms at 4.19-MHz operation
215/fX : 5.46 ms at 6.0-MHz operation, 7.81 ms at 4.19-MHz operation
Note
Caution Noise resistance and noise radiation are different in PROM and mask ROMs. When changing from
PROM versions to mask ROM versions when switching from prototype development to full production,
be sure to fully evaluate the mask ROM version’s CS (not ES).
15
6. MEMORY CONFIGURATION
765 0
MBE
RBE
0000H
0002H
0004H
0006H
0008H
000AH
000CH
MBE
MBE
MBE
MBE
MBE
MBE
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
RBE
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
RBE
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
RBE
INTT1/INTT2 start address (upper 6 bits)
INTT1/INTT2 start address (lower 8 bits)
Figure 6-1. Program Memory Map
CALLF
!faddr instruction
entry address
BRCB
!caddr instruction
branch address
µ
PD75P3116
Branch addresses for
the following instructions
• BR !addr
• CALL !addr
• BRA !addr1
• CALLA !addr1
• BR BCDE
• BR BCXA
Note
Note
Branch/call
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
Reference table for GETI instruction
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
address
by GETI
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
Note Can be used only in the Mk II mode
Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC’s lower 8 bits only.
16
Figure 6-2. Data Memory Map
µ
PD75P3116
Data area
static RAM
(512 x 4)
Stack area
Note
Display data memory
General-purpose register area
000H
01FH
020H
0FFH
100H
1DFH
1E0H
1F7H
1F8H
1FFH
Data memory
(32 x 4)
256 x 4
(224 x 4)
256 x 4
(224 x 4)
(24 x 4)
(8 x 4)
Not incorporated
Memory bank
0
1
F80H
Peripheral hardware area
FFFH
Note Memory bank 0 or 1 can be selected as the stack area.
128 x 4
15
17
µ
PD75P3116
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, refer to the RA75X Assembler Package User’s Manual Language
(EEU-1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or
– symbols are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer to the
User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation Coding format
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’
rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H to FBFH, FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label
addr 0000H to 3FFFH immediate data or label
addr1 0000H to 3FFFH immediate data or label (Mk II mode only)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H to 7FH immediate data (however, bit0 = 0) or label
PORTn PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9
IEXXX IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW
RBn RB0 to RB3
MBn MB0, MB1, MB15
Note
18
Note When processing 8-bit data, only even-numbered addresses can be specified.
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