NEC UPD75P036KG, UPD75P036CW, UPD75P036GC-AB8 Datasheet
DATA SHEET
MOS Integrated Circuit
µ
PD75P036
4-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD75P036 is a 4-bit signgle-chip microcontroller that replaced the µPD75028's on-chip ROM with
one-time PROM or EPROM. Because this device can operate at the same supply voltage as its mask
version, it is suited for preproduction in development stage or small-scale production.
The one-time PROM version is programmable only once and is useful for small-scale production of many
different products and time-to-market of a new product. The EPROM version is programmable, erasable,
and reprogrammable, and is suited for the evaluation of application systems.
Detailed functions are described in the followig user's manual. Be sure to read it for designing.
µ
PD75028 User's Manual: IEU-1280
★
FEATURES
•
µ
PD75028 compatible
µ
• At full production, the
PD75P036 can be replaced with the µPD75028 which incorporates mask ROM
• Memory capacity
• Program memory (PROM): 16256 x 8 bits
• Data memory (RAM): 1024 x 4 bits
• Internal pull-up resistors can be specified by software: Ports 0-3, 6-8
• Internal pull-down resistors can be specified by software: Port 9
• Open-drain input/output: Ports 4, 5, 10
• Can operate at low voltage: VDD = 2.7 to 6.0 V
ORDERING INFORMATION
Part Number Package Internal ROM Quality Grade
µ
PD75P036CW 64-pin plastic shrink DIP (750 mils) One-time PROM Standard
µ
PD75P036GC-AB8 64-pin plastic QFP (14 x 14 mm) One-time PROM Standard
µ
PD75P036KG 64-pin ceramic WQFN EPROM Not applicable
Caution Internal pull-up/pull-down resistors cannot be specified by mask option as for this device.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation
to know the specification of quality grade on e devices and its recommended applications.
★
The reliability of the EPROM version, µPD75P036KG, is not guaranteed when used in mass-produced application
sets. Please use this device only experimentally or for evaluation during trial manufacture.
The function common to the one-time PROM and EPROM versions is referred to as PROM throughout this document.
Document No. U10051EJ3V0DS00 (3rd edition)
(Previous No. IC-2967
Date Published September 1995 P
Printed in Japan
The information in this document is subject to change without notice.
The mark ★ shows revised points.
NEC Corporation
1991
PIN CONFIGURATIONS (Top View)
• 64-pin plastic shrink DIP (750 mils)
µ
PD75P036
SB1/SI/P03
SB0/SO/P02
SCK/P01
INT4/P00
BUZ/P23
PCL/P22
PPO/P21
PTO0/P20
MAT/P103
MAZ/P102
MAI/P101
MAR/P100
RESET
X1
X2
V
XT1
XT2
V
AV
AV
REF+
AV
REF-
AN7
AN6
AN5
AN4
AN3/P113
AN2/P112
AN1/P111
AN0/P110
AV
TIO/P13
PP
DD
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
µ
PD75P036CW
• 64-pin plastic QFP (14 x 14 mm)
• 64-pin ceramic WQFN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SS
P30/MD0
P31/MD1
P32/MD2
P33/MD3
P40
P41
P42
P43
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P80
P81
P82
P83
P90
P91
P92
P93
P10/INT0
P11/INT1
P12/INT2
P43
P42
P41
P40
MD3/P33
MD2/P32
MD1/P31
MD0/P30
V
SB1/SI/P03
SB0/SO/P02
SCK/P01
INT4/P00
BUZ/P23
PCL/P22
PPO/P21
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
1
2
3
4
5
6
7
8
SS
9
10
11
12
13
14
15
16
171819
µ
PD75P036KG
X1
RESET
MAI/P101
PTO0/P20
MAT/P103
MAZ/P102
MAR/P100
P73/KR7
P80
P81
P72/KR6
52535455565758596061626364
51 50 49
DDAVDD
V
XT2
REF+
AV
P82
32313029282726252423222120
REF-
AV
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P70/KR4
P63/KR3
P71/KR5
µ
PD75P036GC-AB8
PP
X2
V
XT1
P83
AN7
P90
P91
P92
P93
P10/INT0
P11/INT1
P12/INT2
TI0/P13
SS
AV
AN0/P110
AN1/P111
AN2/P112
AN3/P113
AN4
AN5
AN6
2
µ
PD75P036
PIN IDENTIFICATION
P00-P03 : Port 0 INT0, INT1, INT4: External Vectored Interrupt
P10-P13 : Port 1 INT2 : External Test Input
P20-P23 : Port 2 X1, X2 : Main System Clock Oscillation
P30-P33 : Port 3 XT1, XT2 : Subsystem Clock Oscillation
P40-P43 : Port 4 MAR : Reference Integration
P50-P53 : Port 5 Control
P60-P63 : Port 6 MAI : Integration Control
P70-P73 : Port 7 MAZ : Autozero Control
P80-P83 : Port 8 MAT : External Comparate
P90-P93 : Port 9 Timing Input
P100-P103 : Port 10 PPO : Programmable Pulse Output
P110-P113 : Port 11 ··· MFT timer mode
KR0-KR7 : Key Return AN0-AN7 : Analog Input
SCK : Serial Clock AV
SI : Serial Input AB
SO : Serial Output AV
REF+ : Analog Reference (+)
REF– : Analog Reference (–)
DD : Analog VDD
SB0, SB1 : Serial Bus AVSS : Analog VSS
RESET : Reset Input VDD : Positive Power Supply
TI0 : Timer Input V
SS : Ground
PTO0 : Programmable Timer Output MD0-MD3 : Mode Selection
BUZ : Buzzer Clock VPP : Programming/Verifying Power Supply
PCL : Programmable Clock
MFT A/D mode
★
Remark MFT: Multifunction Timer
3
4
BLOCK DIAGRAM
TI0/P13
PTO0/P20
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0-KR3/P60-P63
KR4-KR7/P70-P73
BUZ/P23
AV
AV
REF+
AV
REF–
AV
AN0-AN3/P110-P113
AN4-AN7
MAR/P100
MAI/P101
MAZ/P102
MAT/P103
PPO/P21
BASIC
INTERVAL
TIMER
INTBT
TIMER
/COUNTER
#0
INTT0
SERIAL
INTERFACE
INTCSI
INTERRUPT
CONTROL
WATCH
TIMER
INTW
DD
A/D
CON-
SS
VERTER
MULTIFUNCTION
TIMER
INTMFT
PROGRAM
COUNTER
PROM
PROGRAM
MEMORY
16256 x 4 BITS
CLOCK
OUTPUT
CONTROL
PCL/P22
fx/2
CLOCK
DIVIDER
ALU
DECODE
AND
CONTROL
N
CLOCK GENERATOR
SUB
XT1 XT2 X1 X2
MAIN
CY
GENERAL
REG.
RAM
DATA
MEMORY
1024 x 4 BITS
STAND BY
CONTROL
V
PPVDDVSS
SP
BANK
CPU CLOCK
Φ
RESET
BIT SEQ.
BUFFER
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
PORT 10
PORT 11
P00–P03
P10–P13
P20–P23
P30/MD0-P33/MD3
P40–P43
P50–P53
P60–P63
P70–P73
P80–P83
P90–P93
P100–P103
P110–P113
µ
PD75P036
CONTENTS
1. PIN FUNCTIONS ... 6
1.1 Port Pins ... 6
1.2 Non-Port Pins ... 8
1.3 Pin Input/Output Circuits ... 10
1.4 Recommended Connection of Unused Pins ... 13
2. MEMORY ... 14
2.1 Differences between µPD75P036 and µPD75028/75036 ... 14
2.2 Program Memory (ROM) ... 15
2.3 Data Memory (RAM) ... 17
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ... 19
3.1 Operation Modes For Writing/Verifying Program Memory ... 19
3.2 Program Memory Write Procedure ... 20
3.3 Program Memory Read Procedure ... 21
3.4 Erasure (µPD75P036KG only) ... 22
µ
PD75P036
★
★
4. ELECTRICAL SPECIFICATIONS ... 23
5. CHARACTERISTIC CURVES ... 38
6. PACKAGE DRAWINGS ... 44
7. RECOMMENDED SOLDERING CONDITIONS ... 47
APPENDIX A. DEVELOPMENT TOOLS ... 48
APPENDIX B. RELATED DOCUMENTS ... 49
★
★
5
µ
PD75P036
1. PIN FUNCTIONS
1.1 Port Pins (1/2)
Pin Name Input/Output Alternate Function 8-Bit I/O When Reset Input/Output
Function Circuit
P00 Input INT4 4-bit input port (PORT0). No Input B
P01 Input/Output SCK Internal pull-up resistors can be specified in F - A
P02 Input/Output SO/SB0 3-bit units for the P01 to P03 pins by F - B
P03 Input/Output SI/SBI software. M - C
P10 Input INT0 With noise elimination function No Input B - C
P11 INT1 4-bit input port (PORT1).
P12 INT2 Internal pull-up resistors can be specified in
P13 TI0 4-bit units by software.
P20 Input/Output PTO0 4-bit input/output port (PORT2). No Input E - B
P21 PPO Internal pull-up resistors can be specified in
P22 PCL 4-bit units by software.
P23 BUZ
Note 2
P30
P31
P32
P33
Input/Output MD0 Programmable 4-bit input/output port No Input E - B
Note 2
Note 2
Note 2
MD1 (PORT3).
MD2 This port can be specified for input/output
MD3 in bit units.
Internal pull-up resistors can be specified in
4-bit units by software.
Note 2
N-ch open-drain 4-bit input/output port Yes Input M - A
P40-P43 Input/Output (PORT4).
Withstands up to 10 V.
Data input/output pin for writing and verifying
of program memory (PROM) (lower 4 bits).
Note 2
Input/Output N-ch open-drain 4-bit input/output port Input M - A
P50-P53 (PORT5).
Withstands up to 10 V.
Data input/output pin for writing and verifying
of program memory (PROM) (upper 4 bits).
Type
Note 1
Notes 1. Circles indicate Schmitt-triggerred inputs.
2. Can directly drive LEDs.
6
µ
PD75P036
1.1 Port Pins (2/2)
Pin Name Input/Output Alternate Function 8-Bit I/O When Reset Input/Output
Function Circuit
P60 Input/Output KR0 Programmable 4-bit input/output port Yes Input F - A
P61 KR1 (PORT6).
P62 KR2 Internal pull-up resistors can be specified in
P63 KR3 4-bit units by software.
P70 Input/Output KR4 4-bit input/output port (PORT7). Input F - A
P71 KR5 Internal pull-up resistors can be specified in
P72 KR6 4-bit units by software.
P73 KR7
P80-P83 Input/Output — 4-bit input/output port (PORT8). No Input E - B
Internal pull-up resistors can be specified in
4-bit units by software.
P90-P93 Input/Output — 4-bit input/output port (PORT9). Input E - D
Internal pull-up resistors can be specified in
4-bit units by software.
P100 Input/Output MAR N-ch open-drain 4-bit input/output port No Input M -A
P101 MAI (PORT10).
P102 MAZ Withstands up to 10 V in open-drain mode.
P103 MAT
P110 Input AN0 4-bit input/output port (PORT11). Input Y
P111 AN1
P112 AN2
P113 AN3
Type
Note 1
Note Circles indicate schmitt-triggerred inputs.
7
µ
PD75P036
1.2 Non-Port Pins (1/2)
Pin Name Input/Output Alternate Function 8-Bit I/O When Reset Input/Output
Function Circuit
TI0 Input P13 External event pulse input pin to timer/event counter Input B - C
PTO0 Input/Output P20 Timer/event counter output pin Input E - B
PCL Input/Output P22 Clock output pin Input E - B
BUZ Input/Output P23 Fixed frequency output pin (for buzzer or for trimming Input E - B
the system clock)
SCK Input/Output P01 Serial clock input/output pin Input F - A
SO/SB0 Input/Output P02 Serial data output pin Input F - B
Serial bus input/output pin
SI/SB1 Input/Output P03 Serial data output pin Input M - C
Serial bus input/output pin
INT4 Input P00 Edge detection vectored interrupt input pin (Either Input B
rising or falling edge detection is effective)
INT0 Input P10 Edge detection vectored interrupt input pin (Detection Input B - C
INT1 P11 edge can be selected)
INT2 Input P12 Edge detection testable input pin (rising edge detection) Input B - C
KR0-KR3 Input/Output P60-P63 Testable input/output pin (parallel falling edge detection) Input F - A
KR4-KR7 Input/Output P70-P73 Testable input/output pin (parallel falling edge detection) Input F - A
MAR Input/Output P100 In integral A/D Reverse integration signal output pin Input M - A
MAI Input/Output P101 converter mode Integration signal output pin Input M - A
MAZ Input/Output P102 of MFT Auto zero signal output pin Input M - A
MAT Input/Output P103 Comparator input pin Input M - A
PPO Input/Output P21 In timer mode Timer pulse output pin Input E - B
of MFT
Type
Note 1
Note Circles indicate Schmitt-triggerred inputs.
Remark MFT: Multifunction timer
8
µ
PD75P036
1.2 Non-Port Pins (2/2)
Pin Name Input/Output Alternate Function When Reset Input/Output
Function Circuit
AN0-AN3 Input P110-P113 Pins only for A/D 8-bit analog input pin. — Y
AN4-AN7 — converter Y - A
AVREF+ Input — Reference voltage input — Z - A
pin (AVDD side).
AVREF– Input — Reference voltage input — Z - A
pin (AVSS side).
AVDD — — Positive power supply pin. — —
AVSS — — GND potential pin. — —
X1, X2 Input — Crystal or ceramic resonator connection for main — —
system clock generation. To use external clock, input
the external clock to X1 and its reverse phase to X2.
XT1, XT2 Input — Crystal or ceramic resonator connection for subsystem — —
clock generation. To use external clock, input the
external clock to XT1 and its reverse phase to XT2.
XT1 can be used as a 1-bit input (test) pin.
RESET Input — System reset input pin. — B
MD0/MD3 Input/Output P30-P33 Mode selection pins in program memory (PROM) Input E - B
Note 2
VPP
VDD — — Positive power supply pin. — —
VSS — — GND potential pin. — —
— — Program voltage application pin in program memory — —
write/verify mode.
(PROM) write/verify mode.
At normal operation, connect the pin to VDD directly.
In the PROM write/verify mode, apply +12.5 V.
Type
Note 1
Notes 1. Circles indicate schmitt trigger inputs.
2. If the V
PP pin is not connected directly to the VDD pin at normal operation, the
normally.
µ
PD75P036 does not operate
9
1.3 Pin Input/Output Circuits
The following shows a simplified input/output circuit diagram for each pin of the
µ
PD75P036.
µ
PD75P036
TYPE A (for TYPE E - B)
V
DD
P-ch
IN
N-ch
CMOS-level input buffer
TYPE B
IN
Schmitt-triggerred input with hysteresis characteristics
TYPE D (for TYPE E - B, F - A)
V
DD
data
output
disable
Push-pull output that can be set in an output
high-impedance state (both P-ch and N-ch are off)
TYPE E - B
P.U.R.
enable
data
output
disable
P.U.R. : Pull-Up Resistor
Type D
Type A
P-ch
N-ch
V
DD
OUT
P.U.R.
P-ch
IN/OUT
10
TYPE B - C
P-ch
IN
V
DD
P.U.R.
P.U.R.
enable
P.U.R. : Pull-Up Resistor
TYPE E - D
data
output
disable
P.D.R. : Pull-Down Resistor
Type D
Type A
P.D.R.
enable
IN/OUT
N-ch
P.D.R.
µ
PD75P036
TYPE F - A
output
disable
TYPE F - B
output
disable
(P)
data
output
disable
P.U.R.
enable
data
P.U.R. : Pull-Up Resistor
output
disable
(N)
Type D
P.U.R.
enable
Type B
TYPE M - C
V
DD
P.U.R. P.U.R.
P-ch P-ch
IN/OUT
data
P.U.R.
enable
N-ch
output
disable
P.U.R. : PullUp Resistor
TYPE Y
V
DD
P.U.R.
V
DD
P-ch
N-ch
P-ch
IN/OUT
IN
AV
P-ch
N-ch
DD
Sam-
pling
C
AV
SS
Reference voltage
(from serial resistor
input
string voltage tap)
enable
V
+
–
DD
AV
AV
IN/OUT
DD
SS
TYPE M - A
data
output
disable
P.U.R. : Pull-Up Resistor
N-ch
(+10-V
voltage)
Middle-voltage input buffer
(withstands up to + 10 V)
P.U.R. : Pull-Up Resistor
IN/OUT
TYPE Y - A
IN
AV
DD
P-ch
N-ch
AV
IN instruction
Input buffer
AV
DD
+
Sam-
pling
–
C
AV
SS
SS
Reference voltage
(from serial resistor
string voltage tap)
11
TYPE Z - A
AVREF+
AVREF-
Reference voltage
µ
PD75P036
12
µ
PD75P036
1.4 Recommended Connection of Unused Pins
Pin Name Recomended Connecting Method
P00/INT4 Connect to VSS.
P01/SCK Connect to VSS or VDD.
P02/SO/SB0
P03/SI/SB1
P10/INT0-P12/INT2 Connect to VSS.
P13/TI0
P20/PTO0 Input state: Independently connect to VSS or VDD via a
P21/PPO resistor.
P22/PCL Output state: Leave Open.
P23/BUZ
P30/MD0-P33/MD3
P40-P43
P50-P53
P60/KR0-P63/KR3
P70/KR4-P73/KR7
P80-P83
P90-P93
P100/MAR
P101/MAI
P102/MAZ
P103/MAT
P110/AN0-P113/AN3 Connect to VSS or VDD.
AN4-AN7
AVREF+ Connect to VSS.
AVREF–
AVSS
AVDD Connect to VDD.
XT1 Connect to VSS or VDD.
XT2 Leave Open.
VPP Connect directly to VDD.
★
13
µ
PD75P036
2. MEMORY
2.1 Differences between µPD75P036 and µPD75028/75036
µ
PD75P036 is a microcontroller provided by replacing the µPD75028's on-chip mask ROM with one-time
The
PROM or EPROM. Capacity of program memory and data memory are different, but CPU function and internal
hardware are identical. Table 2-1 shows the differences between the µPD75P036 and µPD75028/75036. Users
should fully consider these differences especially when debugging or producing an application system on an
experimental basis by using the PROM version and then mass-producing the system using the mask ROM version.
µ
For details about the CPU function and the internal hardware, refer to
PD75028 User's Manual (IEM-1280).
★
Item
Program memory One-time PROM/EPROM Mask ROM
Data memory 000H-3FFH 000H-1FFH 000H-3FFH
Pull-up resistor Ports 0-3, 6-8 Can be specified by software.
Pull-down resistor Port 9 Can be specified by software.
XT1 feedback resistor Provided on-chip Can be disconnected by mask option
Supply voltage VDD = 2.7 to 6.0 V
Pin connection Pin 16 (SDIP) VPP Internally connected
Electrical specifications Supply current and operating temperature ranges differ between µPD75P036 and
Others Noise immunity and noise radiation differ because circuit complexity and mask layout are
Table 2-1. Differences between µPD75P036 and µPD75028/75036
µ
PD75P036
0000H-3F7FH 0000H-1F7FH 0000H-3F7FH
(16256 x 8 bits) (8064 x 8 bits) (16256 x 8 bits)
(1024 x 4 bits) (512 x 4 bits) (1024 x 4 bits)
Ports 4, 5, 10 Not provided Can be connected by mask option
Pin 25 (QFP)
Pins 60-63 P33/MD3-P30/MD0 P33-P30
(SDIP)
Pins 5-8 (QFP)
µ
PD75028/75036. For details, refer to the electrical specifications described in Data Sheet
of each model.
different.
µ
PD75028
µ
PD75036
Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To
replace the PROM version with the mask ROM version in the course of experimental production
to mass production, evaluate your system by using the CS version (not ES) of the mask ROM
version.
14
µ
PD75P036
2.2 Program Memory (ROM) ··· 16256 words x 8 bits
The program memory is a 16256-word x 8-bit PROM and stores programs, table data, etc.
The program memory is accessed by referencing the program counter contents. Table data can be referenced
by executing a table look-up instruction (MOVT).
Figure 2-1 shows the address range in which a branch can be taken by branch instructions and subroutine call
instructions. A relative branch instruction (BR $addr) enables a branch to addresses [PC value –15 to –1, +2 to
+16] regardless of block boundaries.
Program memory addresses are 0000H-3F7FH and the following addresses are assigned to special purposes:
(All areas except 0000H or 0001H can be used as normal program memory.)
• Addresses 0000H-0001H
Vector table into which the program start address and MBE setting value when the RESET signal is generated
are written.
Processing at reset is started at any desired address.
• Addresses 0002H-000DH
Vector table into which the program start address and MBE setting value when each vectored interrupt is
generated are written.
Interrupt servicing can be started at any desired address.
• Addresses 0020H-007FH
Table area referenced by the GETI instruction
Note
.
Note The GETI instruction is provided to execute any 2-byte or 3-byte instruction or two 1-byte instructions as a 1-
byte instruction; it is used to reduce the number of program steps.
15
µ
PD75P036
Address
0000H
0002H
0004H
0006H
0008H
000AH
000CH
7
MBE
MBE
MBE
MBE
MBE
MBE
MBE
Figure 2-1. Program Memory Map
6
0
Internal reset start address (high-order six bits)
Internal reset start address (low-order eight bits)
INTBT/INT4 start address (high-order six bits)
0
INTBT/INT4 start address (low-order eight bits)
INT0 start address (high-order six bits)
0
INT0 start address (low-order eight bits)
INT1 start address (high-order six bits)
0
INT1 start address (low-order eight bits)
INTCSI start address (high-order six bits)
0
INTCSI start address (low-order eight bits)
INT0 start address (high-order six bits)
0
INT0 start address (low-order eight bits)
INTMFT start address (high-order six bits)
0
INTMFT start address (low-order eight bits)
0
CALLF
! faddr
instruction
address
entry
BRCB
! caddr
instruction
branch
address
CALL ! addr
instruction
subroutine
entry addres
BR ! addr
Instruction
branch
address
BR $ addr
instruction
relative
branch Address
(–15 to –1 and
+2 to +16)
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3F7FH
GETI instruction reference table
BRCB ! caddr
instruction
branch addresses
BRCB ! caddr
instruction
branch addresses
BRCB ! caddr
instruction
branch addresses
Branch destination
address and
subroutine entry
address to be set
by GETI instruction
16
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