NEC UPD75P0076GT, UPD75P0076CU Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75P0076

4-BIT SINGLE-CHIP MICROCONTROLLER

The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM capacity.

Because the development using the µPD750064, 750066, and 750068 products, and for use in small-lot production.

PD75P0076 supports programming by users, it is suitable for use in prototype testing for system

Detailed information about function is provided in the following user’s manual.

Be sure to read it before designing:

PD750068 User’s Manual: U10670E

FEATURES

Compatible with µPD750068 Memory capacity:

• PROM : 16384 x 8 bits

• RAM : 512 x 4 bits Can operate with same power supply voltage as the mask ROM version µPD750068 VDD = 1.8 to 5.5 V On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V) 8-bit resolution x 8 channels

Small shrink SOP package

ORDERING INFORMATION

Part Number Package

PD75P0076CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD75P0076GT 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

Caution On-chip pull-up resistors by mask option cannot be provided.

Document No. U10232EJ1V0DS00 (1st edition) Date Published December 1996 N Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1995

PD75P0076

Functional Outline

Parameter Function

Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock)

• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock)

• 122 µs (@ 32.768 kHz with subsystem clock)

On-chip memory PROM 16384 x 8 bits

RAM 512 x 4 bits

General-purpose register • 4-bit operation: 8 x 4 banks

• 8-bit operation: 4 x 4 banks

Input/ CMOS input 12 Connections of on-chip pull-up resistors can be specified by software: 7 output Also used for analog input pins: 4 port

Timer 4 channels

Serial interface • 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit

A/D converter 8-bit resolution x 8 channels (1.8 V ≤ AVREF ≤ VDD) Bit sequential buffer 16 bits Clock output (PCL) • Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock)

Buzzer output (BUZ) • 2, 4, 32 kHz (@ 4.19 MHz with main system clock or

Vectored interrupts External: 3, Internal: 4 Test input External: 1, Internal: 1 System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation

Standby function STOP/HALT mode Operating ambient temperature Power supply voltage VDD = 1.8 to 5.5 V Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

CMOS input/output 12 Connections of on-chip pull-up resistors can be specified by software: 12

Also used for analog input pins: 4

N-ch open-drain 8 13-V withstand voltage input/output pins

Total 32

•

8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter)

• 8-bit basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

• 2-wire serial I/O mode

• Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock)

@ 32.768 kHz with subsystem clock)

• 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)

• Crystal oscillator for subsystem clock oscillation

TA = –40 to +85 ˚C

• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

PD75P0076

CONTENTS

1. PIN CONFIGURATION (Top View) ................................................................................................... 4

2. BLOCK DIAGRAM ............................................................................................................................ 5

3. PIN FUNCTIONS ............................................................................................................................... 6

3.1 Port Pins ................................................................................................................................................... 6

3.2 Non-port Pins ........................................................................................................................................... 7

3.3 Equivalent Circuits for Pins .................................................................................................................... 9

3.4 Handling of Unused Pins......................................................................................................................... 12

4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13

4.1 Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13

4.2 Setting of Stack Bank Selection (SBS) Register .................................................................................... 14

5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068........................ 15

6. MEMORY CONFIGURATION ............................................................................................................ 16

7. INSTRUCTION SET ........................................................................................................................... 18

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29

8.1 Operation Modes for Program Memory Write/Verify ............................................................................. 29

8.2 Steps in Program Memory Write Operation............................................................................................ 30

8.3 Steps in Program Memory Read Operation............................................................................................ 31

8.4 One-time PROM Screening ..................................................................................................................... 32

9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33

10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49

11. PACKAGE DRAWINGS .................................................................................................................... 51

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53

APPENDIX A DIFFERENCES AMONG µPD75068, 750068 AND 75P0076......................................... 54

APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55

APPENDIX C RELATED DOCUMENTS ................................................................................................. 58

1. PIN CONFIGURATION (Top View)

• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD75P0076CU

• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

PD75P0076GT

PD75P0076

XT1 XT2

RESET

X2 P33/MD3 P32/MD2 P31/MD1 P30/MD0

AV P63/KR3/AN7 P62/KR2/AN6 P61/KR1/AN5 P60/KR0/AN4

P113/AN3 P112/AN2 P111/AN1 P110/AN0

REF

V V

1 2 3 4 5 6 7 8 9

PP DD

10 11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

P40/D0 P41/D1 P42/D2 P43/D3 P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ

In normal operation mode, make sure to connect VPP directly to VDD.

Pin Identification

AN0 to AN7 : Analog Input 0 to 7 P110 to P113 : Port 11 AVREF : Analog Reference PCL : Programmable Clock AV

SS : Analog Ground PTO0, PTO1 : Programmable Timer Output 0, 1

BUZ : Buzzer Clock RESET : Reset Input D0 to D7 : Data Bus 0 to 7 SB0, SB1 : Serial Data Bus 0, 1 INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 SCK : Serial Clock INT2 : External Test Input 2 SI : Serial Input KR0 to KR3 : Key Return SO : Serial Output MD0 to MD3 : Mode Selection 0 to 3 TI0, TI1 : Timer Input 0, 1 P00 to P03 : Port 0 V P10 to P13 : Port 1 VPP : Programmable Power Supply P20 to P23 : Port 2 V P30 to P33 : Port 3 X1, X2 : Main System Clock Oscillation 1, 2 P40 to P43 : Port 4 XT1, XT2 : Subsystem Clock Oscillation 1, 2 P50 to P53 : Port 5 P60 to P63 : Port 6

DD : Positive Power Supply

SS : Ground

2. BLOCK DIAGRAM

PD75P0076

BUZ/P23

TI0/P13

PTO0/P20

TI1/P12/INT2

PTO1/P21

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10 INT1/P11 INT4/P00

INT2/P12/TI1

KR0/P60 to KR3/P63

AN0/P110 to AN3/P113

AN4/P60 to AN7/P63

BASIC INTERVAL TIMER/WATCHDOG TIMER

WATCH TIMER

INTW

8-BIT TIMER/ EVENT COUNTER#0

8-BIT TIMER/ EVENT COUNTER#1

CLOCKED SERIAL

INTERFACE

INTERRUPT

CONTROL

A/D CONVERTER

INTBT

INTW

INTT0

CASCADED 16-BIT TIMER/ EVENT COUNTER

INTT1

TOUT0INTCSI

SP (8)

ALU

PROGRAM COUNTER

SBS

BANK

GENERAL REG.

PROGRAM

MEMORY

(PROM)

16384 x 8 BITS

DECODE

AND

CONTROL

CLOCK OUTPUT CONTROL

CLOCK DIVIDER

DATA MEMORY

(RAM)

512 x 4BITS

fx/2

SYSTEM CLOCK GENERATOR

SUB MAIN

CPU CLOCK Φ

PCL/P22 XT1 XT2 X1 X2

STAND BY CONTROL

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT11

P00 to P034

P10 to P13

P20 to P23

P30/MD0 to

P33/MD3

P40/D0 to

P43/D3

P50/D4 to

P53/D7

P60 to P63

P110 to P113

BIT SEQ. BUFFER (16)

PP VDD VSS RESET

AVSS

REF

3. PIN FUNCTIONS

3.1 Port Pins

PD75P0076

Pin name I/O Alternate function Function

8-bit After I/O circuit

accessible reset type

Note 1

P00 I INT4 This is a 4-bit input port (PORT0). Not Input

For P01 to P03, on-chip pull-up resistors are available

P01 I/O SCK software-specifiable in 3-bit units. <F>-A P02 I/O SO/SB0 <F>-B P03 I/O SI/SB1 <M>-C P10 I INT0 This is a 4-bit input port (PORT1). Not Input -C

Connections of on-chip pull-up resistors are available

P11 INT1 software-specifiable in 4-bit units. P10/INT0

can select a noise elimination circuit.

P12 TI1/INT2 P13 TI0 P20 I/O PTO0 This is a 4-bit I/O port (PORT2). Not Input E-B

Connections of on-chip pull-up resistors are available

P21 PTO1 software-specifiable in 4-bit units. P22 PCL P23 BUZ P30 I/O MD0 This is a programmable 4-bit I/O port (PORT3). Not Input E-B

Input and output can be specified in single-bit available

P31 MD1 units. Connections of on-chip pull-up resistors

are software-specifiable in 4-bit units.

P32 MD2 P33 MD3

Note 2

P40 P41 P42 P43 P50 P51 P52 P53

Note 2

I/O D0 This is an N-ch open-drain 4-bit I/O port Available High

(PORT4). In the open-drain mode, withstands impedance M-E

D1 up to 13 V. Also used as data I/O pin

(lower 4 bits) for program memory (PROM)

D2 write/verify. D3

I/O D4 This is an N-ch open-drain 4-bit I/O port High

(PORT5). In the open-drain mode, withstands impedance M-E

D5 up to 13 V. Also used as data I/O pin

(upper 4 bits) for program memory (PROM)

D6 write/verify. D7

P60 I/O KR0/AN4 This is a programmable 4-bit I/O port (PORT6). Not Input <Y>-D

Input and output can be specified in single-bit available

P61 KR1/AN5 units. Connections of on-chip pull-up resistors

are software-specifiable in 4-bit units.

P62 KR2/AN6 P63 KR3/AN7 P110 I AN0 This is a 4-bit input port (PORT11). Not Input Y-A

available

P111 AN1 P112 AN2 P113 AN3

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.

3.2 Non-port Pins (1/2)

PD75P0076

Pin name I/O

TI0 I P13 Inputs external event pulses to the timer/event Input -C TI1 P12/INT2 PTO0 O P20 Timer/event counter output Input E-B PTO1 P21 PCL P22 Clock output BUZ P23 Optional frequency output (for buzzer output or

SCK I/O P01 Serial clock I/O Input <F>-A SO/SB0 P02 Serial data output <F>-B

SI/SB1 P03 Serial data input <M>-C

INT4 I P00 Edge detection vectored interrupt input (both rising

INT0 I P10 Edge detection vectored Noise eliminator/ Input -C

INT1 P11 edge can be selected). Asynchronous

INT2 P12/TI1 Rising edge detection Asynchronous

KR0 to KR3 I P60/AN4 to Falling edge detection testable input Input <Y>-D

AN0 to AN3 I AN4 to AN7 P60/KR0 to <Y>-D

AVREF — — A/D converter reference voltage — Z-N AVSS — — A/D converter reference GND potential — Z-N X1 I — Crystal/ceramic connection pin for the main system — —

X2 — clock oscillator. When inputting the external clock,

XT1 I — Crystal connection pin for the subsystem clock — — XT2 — oscillator. When the external clock is used, input the

RESET I — System reset input (low-level active) —

Alternate function

P63/AN7 P110 to P113

P63/KR3

Function

counter.

system clock trimming)

Serial data bus I/O

edge and falling edge detection)

interrupt input (detection asynchronous selection

INT0/P10 can select a noise eliminator.

testable input

Analog signal input Input Y-A

input the external clock to pin X1, and the inverted phase of the external clock to pin X2.

external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin.

After Circuit reset type

Note

Note Circuit types enclosed in brackets indicate Schmitt triggered inputs.

3.2 Non-port Pins (2/2)

PD75P0076

Pin name I/O

MD0 to MD3 I P30 to 33 Mode selection for program memory (PROM) Input E-B

D0 to D3 I/O P40 to 43 D4 to D7 P50 to 53

Note

VPP

VDD — — Positive power supply — — VSS — — Ground — —

Alternate function

write/verify. Data bus pin for program memory (PROM) write/verify.

— — Programmable voltage supply in program memory — —

(PROM) write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode.

Function

After Circuit reset type

Input M-E

Note During normal operation, the VPP pin will not operate normally unless connected to VDD pin.

3.3 Equivalent Circuits for Pins

The equivalent circuits for the µPD75P0076’s pin are shown in schematic diagrams below.

TYPE A TYPE D

Data

CMOS standard input buffer

P-ch

N-ch

Output

disable

Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF).

PD75P0076

P-ch

OUT

N-ch

(1/3)

TYPE E-BTYPE B

Schmitt trigger input with hysteresis characteristics.

TYPE B-C TYPE F-A

P.U.R.

P-ch

P.U.R. enable

Data

Output

disable

P.U.R. enable

Type D

Type A

P.U.R. : Pull-Up Resistor

P.U.R.

enable

P-ch

IN/OUT

P.U.R.

P-ch

P.U.R. : Pull-Up Resistor

Schmitt trigger input with hysteresis characteristics.

Data

Output

disable

Type D

IN/OUT

Type B

P.U.R. : Pull-Up Resistor

TYPE F-B TYPE Y

PD75P0076

(2/3)

Output disable (P)

Data Output disable

TYPE M-C

Output disable

Output disable (N)

P.U.R. : Pull-Up Resistor

P.U.R. enable

Data

P.U.R. enable

N-ch

P-ch

N-ch

P.U.R.

P-ch

IN/OUT

P.U.R.

IN/OUT

TYPE Y-A

P-ch N-ch

Input

enable

Type Y

Sampling C

Reference voltage (from the voltage tap of the serial resistor string)

Type A

–

IN instruction

Input butfer

P.U.R. : Pull-Up Resistor

TYPE M-E*

Data

Output disable

Input instruction

P-ch

P.U.R.

Note

Voltage control circuit

Note This is a pull-up resistor which only

operates when an input instruction is executed (when the pin is low a current flows from V

N-ch

(+13 V withstand voltage)

to the pin).

IN/OUT

PD75P0076

(3/3)

TYPE Y-D

Data

Output disable

P.U.R. enable

Type D

Type B

Type Y

P.U.R.: Pull-Up Resistor

P.U.R.

P-ch

IN/OUT

TYPE Z-N

ADEN

REF

N-ch

Reference voltage

3.4 Handling of Unused Pins

P00/INT4 Connect to VSS or VDD P01/SCK Independently connect to VSS or VDD through P02/SO/SB0 P03/SI/SB1 Connected to VSS P10/INT0, P11/INT1 Connect to VSS or VDD P12/TI1/INT2 P13/TI0 P20/PTO0 Input mode : independently connected to VSS P21/PTO1 or VDD through resistor P22/PCL Output mode : open P23/BUZ P30/MD0 to P33/MD3 P40/D0 to P43/D3 Connected to VSS P50/D4 to P53/D7 P60/KR0/AN4 to P63/KR3/AN7 Input mode : independently connected to VSS

P110/AN0 to P113/AN3 Connected to VSS or VDD

Note

XT1

Note

XT2 VPP Make sure to connect directly to VDD AVREF Connect to VSS AVSS

Pin Recommended connection

resistor

or VDD through resistor

Output mode : open

Connect to VSS or VDD Open

PD75P0076

Note When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).

PD75P0076

4. SWITCHING BETWEEN Mk I AND Mk II MODES

Setting a stack bank selection (SBS) register for the µPD75P0076 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750064, 750066, and 750068 using the µPD75P0076.

When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750064, 750066, and 750068)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the

Table 4-1. Differences between Mk I Mode and Mk II Mode

Item Mk I Mode Mk II Mode Program counter PC13 to 0 Program memory (bytes) 16384 Data memory (bits) 512 x 4 Stack Stack bank Selectable from memory banks 0 and 1

Stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 Not provided Provided

CALLA !addr1 Instruction CALL !addr 3 machine cycles 4 machine cycles execution time CALLF !faddr 2 machine cycles 3 machine cycles Supported mask ROM versions and Mk I mode of µPD750064, 750066, Mk II mode of µPD750064, 750066,

mode and 750068 and 750068

PD750064, 750066, and 750068)

PD75P0076.

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This

mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode.

PD75P0076

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

Note

sure to initialize the stack bank selection register to 100xB

Note

be sure to initialize it to 000xB

at the beginning of the program. When using the Mk II mode,

Note Set the desired value for x.

Figure 4-1. Format of Stack Bank Selection Register

Address 3 2 1 0

SBS3 SBS2 SBS1 SBS0F84H

Symbol

SBS

Stack area specification

0 0 1 1

0 Be sure to enter “0” for bit 2.

Memory bank 0

Memory bank 1

1 0

Setting prohibited

Mode selection specification

01Mk II mode

Mk I mode

Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When

using instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions.

2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register.

PD75P0076

5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068

The µPD75P0076 replaces the internal mask ROM in the µPD750064, 750066, and 750068 with a one-time PROM and features expanded ROM capacity. The µPD75P0076’s Mk I mode supports the Mk I mode in the µPD750064, 750066, and 750068 and the µPD75P0076’s Mk II mode supports the Mk II mode in the µPD750064, 750066, and 750068.

Table 5-1 lists differences among the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. For further description of CPU functions and internal hardware, see the

Information (U10165E).

Table 5-1. Differences between

PD75P0076 and the µPD750064, 750066, 750068. Be sure to check the

PD750064 and 750068 Preliminary Product

PD75P0076 and µPD750064, 750066, 750068

Item Program counter 12-bit 13-bit 14-bit Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

Data memory (x 4 bits) 512 Mask options Pull-up resistor for Yes (on-chip specifiable) No (off chip)

ports 4 and 5 Wait time when Yes (217/fX, 215/fX selectable)

RESET Feedback resistor of Yes (Use/not use selectable) No (Use)

subsystem clock

Pin configuration Pins 6 to 9 P33 to P30 P33/MD3 to P30/MD0

Pin 20 IC VPP Pins 34 to 37 P53 to P50 P53/D7 to P53/D4 Pins 38 to 41 P43 to P40 P43/D3 to P40/D0

Other Noise resistance and noise radiation may differ due to different circuit complexities

PD750064

4096 6144 8192 16384

and mask layouts.

PD750066

Note

PD750068

No (fixed at 215/fX)

PD75P0076

Note

Note 217/fX is 21.8 ms in 6.0 MHz operation and 31.3 ms in 4.19 MHz operation.

215/fX is 5.46 ms in 6.0 MHz operation and 7.81 ms in 4.19 MHz operation.

Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using

a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES).

6. MEMORY CONFIGURATION

76 0

MBE

RBE

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE

Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits)

RBE

INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits)

RBE

INT0 start address (upper 6 bits) INT0 start address (lower 8 bits)

RBE

INT1 start address (upper 6 bits) INT1 start address (lower 8 bits)

RBE

INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits)

RBE

INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits)

RBE

INTT1 start address (upper 6 bits) INTT1 start address (lower 8 bits)

Figure 6-1. Program Memory Map

CALLF

!faddr instruction

entry address

BRCB

!caddr instruction

branch address

the following instructions

Branch address for

• BR BCDE

• BR BCXA

• BR !addr

• BRA !addr1

• CALLA !addr1

PD75P0076

Note

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

Reference table for GETI instruction

!caddr instruction

branch address

!caddr instruction

branch address

!caddr instruction

branch address

CALL !addr instruction

subroutine

entry address

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

BRCB

Branch destination

address specified by

GETI instruction,

subroutine entry

address

Note Can be used only in Mk II mode.

Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to

branch to addresses with changes in the PC’s lower 8 bits only.

Figure 6-2. Data Memory Map

PD75P0076

Data area

static RAM

(512 x 4)

General register

area

Stack area

Note

000H

01FH 020H

0FFH

100H

1FFH

Data memory

(32 x 4)

256 x 4

(224 x 4)

256 x 4

Memory bank

Peripheral hardware area

Note Either memory bank 0 or 1 can be selected as the stack area.

F80H

FFFH

Unimplemented

128 x 4

PD75P0076

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, see the RA75X Assembler Package User’s Manual–Language (EEU-

1363)). When there are several codes, select and use just one. Uppercase letters, and + and – symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description,

see the

PD750068 User’s Manual (U10670E)). Labels that can be entered for fmem and pmem are restricted.

Representation Coding format reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’ rp’1 BC, DE, HL, XA’, BC’, DE’, HL’ rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label bit 2-bit immediate data or label fmem FB0H to FBFH, FF0H to FFFH immediate data or label pmem FC0H to FFFH immediate data or label addr 0000H to 3FFFH immediate data or label addr1 000H to 3FFFH immediate data or label (in Mk II mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (however, bit0 = 0) or label PORTn PORT0 to PORT6, PORT11 IEXXX IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW RBn RB0 to RB3 MBn MB0, MB1, MB15

Note

Note When processing 8-bit data, only even addresses can be specified.

(2) Operation legend

A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA’ : Expansion register pair (XA’) BC’ : Expansion register pair (BC’) DE’ : Expansion register pair (DE’) HL’ : Expansion register pair (HL’) PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 6, 11) IME : Interrupt master enable flag IPS : Interrupt priority select register IExxx : Interrupt enable flag RBS : Register bank select register MBS : Memory bank select register PCC : Processor clock control register . : Delimiter for address and bit (xx) : Contents of address xx xxH : Hexadecimal data

PD75P0076

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