NEC UPD75402AGB-A-XXX-3B4, UPD75402AGB-XXX-3B4, UPD75402ACT-XXX, UPD75402ACT-A-XXX, UPD75402AC-XXX Datasheet

...

Printed in Japan

MOS INTEGRATED CIRCUIT

DATA SHEET

PD75402A(A)

4 BIT SINGLE-CHIP MICROCOMPUTER

The µPD75402A(A) is a CMOS single-chip microcomputer which uses the 75X series architecture. It operates

at high speed with a minimum instruction execution time of 0.95

The

PD75P402 is also available for system development evaluation. It contains one-time PROM instead

of mask ROM used in the

PD75402A(A).

The following user's manual describes the details of the functions of the µPD75402A(A). Be sure to read

it before designing an application system.

PD75402A User's Manual: IEU-644

FEATURES

• More reliable than the

PD75402A

• High-speed operation with a minimum instruction execution time of 0.95

s (when the microcomputer

operates at 4.19 MHz)

• Low voltage and low-speed instruction execution time of 15.3

s (when the microcomputer operates at

4.19 MHz)

• Memory mapping by on-chip peripheral hardware

• NEC standard serial bus interface (SBI)

• 8-bit basic interval timer (watchdog timer applicable)

• Interrupt function

• Three vectored interrupts (one external and two internal interrupts)

• One external test input

• Clock output function (remote controller output applicable)

• Capable of specifying the incorporation of 16 pull-up resistors by software

APPLICATIONS

Electronic units for automobiles, and suchlike

ORDERING INFORMATION

Part number Package Quality grade

PD75402AC(A)-××× 28-pin plastic DIP (600 mil) Special

PD75402ACT(A)-××× 28-pin plastic shrink DIP (400 mil) Special

PD75402AGB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Special

Remark ××× indicates the ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

Major changes in this revision are indicated by stars (

) in the margins.

Document No. IC-2841B (O.D.No. IC-8273B) Date Published November 1993 P

1990

NEC CORPORATION 1991

PD75402A(A)

DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75402A

FUNCTIONAL OVERVIEW

Special Standard

Item

Quality grade

Product

PD75402A(A)

PD75402A

Function

• 0.95, 1.91, or 15.3 µs (when operating at 4.19 MHz)

• Switchable among three speeds 1920 × 8 bits 64 × 4 bits 4 bits × 4 or 8 bits × 2 (memory mapping)

• CMOS input ports : 6 lines

• CMOS I/O ports : 12 lines (8 lines can drive the LED directly.)

• N-ch open-drain I/O ports : 4 lines (All lines can drive the LED directly.)

• Capable of controlling the incorporation of 16 pull-up resistors by software

• Capable of controlling the incorporation of 4 pull-up resistors by mask option

• 1.05 MHz, 524 kHz, or 65.5 kHz (when operating at 4.19 MHz)

• Applicable to remote controller output

8-bit basic interval timer (watchdog timer applicable)

• 8 bits

• Two transfer modes (three-wire synchronous mode and SBI mode)

One external and two internal interrupts One external input (See Chapter 6 for details.)

STOP/HALT mode

• Bit manipulation instructions (set, clear, test, and Boolean operation)

• 1-byte relative branch instructions

• 4-bit operation instructions (add, Boolean operation, and compare)

• 4- and 8-bit transfer instructions

• 28-pin plastic DIP (600 mil)

• 28-pin plastic shrink DIP (400 mil)

• 44-pin plastic QFP (10 × 10 mm)

Item

Number of basic instructions

Minimum instruction execution time

ROM

RAM

General register

I/O line

Pull-up resistor

Clock output

Timer/counter

Serial interface

Vectored interrupt

Test input

Standby

Instruction set

Package

Built-in memory

PD75402A(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ...................................................................................... 4

2. BLOCK DIAGRAM ...................................................................................................................... 6

3. PIN FUNCTIONS ....................................................................................................................... 7

3.1 PORT PINS ..................................................................................................................................... 7

3.2 NON-PORT PINS ........................................................................................................................... 8

3.3 PIN INPUT/OUTPUT CIRCUITS .................................................................................................. 8

3.4 SELECTION OF A MASK OPTION ........................................................................................... 10

3.5 HANDLING UNUSED PINS ......................................................................................................... 11

3.6 NOTES ON USING THE P00 AND RESET PINS ................................................................. 11

4. MEMORY CONFIGURATION ................................................................................................... 12

5. PERIPHERAL HARDWARE FUNCTIONS................................................................................ 14

5.1 PORTS.............................................................................................................................................. 14

5.2 CLOCK GENERATOR .................................................................................................................... 15

5.3 CLOCK OUTPUT CIRCUIT ........................................................................................................... 16

5.4 BASIC INTERVAL TIMER ............................................................................................................ 17

5.5 SERIAL INTERFACE ...................................................................................................................... 18

6. INTERRUPT FUNCTION ........................................................................................................... 20

7. STANDBY FUNCTION .............................................................................................................. 22

8. RESET FUNCTION .................................................................................................................... 23

9. INSTRUCTION SET ................................................................................................................... 25

10. ELECTRICAL CHARACTERISTICS ........................................................................................... 29

11. PACKAGE DIMENSIONS .......................................................................................................... 38

12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 42

APPENDIX A DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75P402 ................... 43

APPENDIX B DEVELOPMENT TOOLS......................................................................................... 44

APPENDIX C RELATED DOCUMENTS ........................................................................................ 45

★

PD75402A(A)

1. PIN CONFIGURATION (TOP VIEW)

28-pin plastic DIP (600 mil), 28-pin plastic shrink DIP (400 mil)

Note

NC 1 28 V

RESET 2 27 X1

P00 3 26 X2

P01/SCK 4 25 P12/INT2

P02/SO/SB0 5 24 P10/INT0

P03/SI 6 23 P23

P50 7 22 P22/PCL

P51 8 21 P21

P52 9 20 P20

P53 10 19 P63

P30 11 18 P62

P31 12 17 P61

P32 13 16 P60

14 15 P33

PD75402AC(A)/CT(A)-

×××

P00 - P03 : Port 0 SCK : Serial clock I/O P10 and P12: Port 1 SO/SB0 : Serial output/input-output P20 - P23 : Port 2 SI : Serial input P30 - P33 : Port 3 PCL : Clock output P50 - P53 : Port 5 INT0 : External vectored interrupt input P60 - P63 : Port 6 INT2 : External test input

X1 and X2: Oscillating pins RESET : Reset input V

DD : Power supply

SS : Ground

NC : No connection

Note When the

PD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

directly to the V

SS pin.

PD75402A(A)

44-pin plastic QFP (10 × 10 mm)

P30 P01/SCK133

P31 P00232

P32 RESET331

NC NC

Note

430

NC529

NC NC628

NC NC727

P33 V

826

P60 X1925

P61 X210 24

NC NC11 23

124413431442154116401739183819372036213522

P53

P52

P51

P50

P03/SI

P02/SO/SB0

P62

P63

P20

P21

P22/PCL

P23

P10/INT0

P12/INT2

PD75402AGB(A)-×××-3B4

Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

(pin 30) directly to the V

SS pin.

PD75402A(A)

2. BLOCK DIAGRAM

Port 3

P30 - P33

Port 5

P50 - P53

Port 6

P60 - P63

Port 0

P00 - P03

Port 1

P10, P12

Port 2

P20 - P23

SPCY

ALU

ROM Program memory

Program counter (11)

1920 × 8 bits

Decode and control

General register

RAM Data memory

64 × 4 bits

Basic interval timer

Serial interface

Interrupt control

INTBT

INTCSI

Clock output control

Clock divider

Clock generator

Standby control

CPU Clock

PCL X1 X2 VDDVSSRESET

SO/SB0

SCK

INT0 INT2

fXX/2

PD75402A(A)

3. PIN FUNCTIONS

3.1 PORT PINS

Remarks 1. The µPD75402A(A) cannot perform 8-bit I/O with two ports as a pair.

2. See Chapter 8 for each pin status during resetting.

P00

P01

P02

P03

P10

P12

P20

P21

P22

P23

P30 - P33

P50 - P53

P60 - P63

I/O

Input

I/O

Input

I/O

Dualfunction pin

–

SCK

SO/SB0

INT0

INT2

–

PCL

–

Function

4-bit input port (port 0) P01 to P03 allow the connection of built-in pull-up resistors to be specified in units of three bits by software.

2-bit input port (port 1) P10 connects with the built-in noise eliminator using a sampling clock. P12 connects with the built-in noise eliminator using an analog delay. P12 allows the connection of built-in pull-up resistor to be specified by software.

4-bit I/O port (port 2) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software.

Programmable 4-bit I/O port (port 3) Allow I/O specification bit by bit. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED.

4-bit N-ch open-drain I/O port (port 5) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified bit by bit by mask option. Can directly drive LED.

4-bit I/O port (port 6) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED.

PD75402A(A)

3.2 NON-PORT PINS

Remark See Chapter 8 for each pin status during resetting.

Note Connect the NC pin directly to the VSS pin when the µPD75402A(A) shares the printed circuit board

with the

PD75P402 in emulation.

3.3 PIN INPUT/OUTPUT CIRCUITS

The I/O circuits of the

PD75402A(A) are roughly shown on the next and subsequent pages.

Table 1-1 I/O Circuit Type of Pin

Remark The types in circles have a Schmitt-triggered input.

INT0

INT2

SCK

SB0

PCL

X1, X2

RESET

VDD

VSS

Note

I/O

Input

I/O

Input

–

Dualfunction pin

P10

P12

P03

P02/SB0

P01

P02/SO

P22

–

Function

Edge detection vectored interrupt request input pin (A detected edge can be selected by the mode register.) Connects with the built-in noise eliminator using a sampling clock.

Edge detection external test input pin (A rising edge is detected.)

Serial data input pin

Serial data output pin

Serial clock I/O pin

Serial bus I/O pin

Clock output pin

Pin for connection to a crystal/ceramic resonator for system clock generation. An external clock is applied to X1, and its reverse phase to X2.

System reset input pin, which connects with the built-in noise eliminator using an analog delay.

Positive power supply pin

Ground potential pin

No connection

P00

P01/SCK

P02/SO/SB0

P03 / SI

P10 / INT0

P12/INT2

P20, P21, and P23

P22/PCL

P30 - P33

P50 - P53

P60 - P63

RESET

I/O type

E-B

I/O type

-A

-B

-C

PD75402A(A)

Type A (For type E-B)

CMOS input buffer

Schmitt trigger input with hysteresis

Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch)

P.U.R.: Pull-Up Resistor

Type B Type E-B

Type B-C

Type D (For type E-B, F-A)

P-ch

N-ch

P-ch

P.U.R. enable

P.U.R.

P-ch

N-ch

OUT

Data

Output disable

P.U.R.

P.U.R.

enable

P-ch

IN/OUT

Data

Output disable

Type D

Type A

(1/2)

Type F-A

P.U.R.: Pull-Up Resistor

P.U.R.

P.U.R.

enable

P-ch

IN/OUT

Data

Output disable

Type D

Type B

PD75402A(A)

3.4 SELECTION OF A MASK OPTION

The following mask options are provided for pins:

Pull-up resistors connected 2 No pull-up resistors connected

(Either can be specified bit by bit.)

P50 - P53

Type F-B

Type M

P.U.R.: Pull-Up Resistor

VDD

P-ch

N-ch

IN/OUT

VDD

P-ch

P.U.R.

P.U.R.

enable Output disable (P)

Data

Output disable

Output disable (N)

N-ch (Withstand  voltage: +10 V)

IN/OUT

Data

VDD

Output disable

P.U.R.

enable

(Mask option)

Input buffer with an intermediate  withstand voltage of +10 V 

(2/2)

PD75402A(A)

3.5 HANDLING UNUSED PINS

Recommended connection method

Connected to the VSS pin

• When a pull-up resistor is contained Connected to the VDD pin

• When a pull-up resistor is not contained Connected to the VSS or VDD pin

• When a pull-up resistor is contained Input mode : Connected to the VDD pin Output mode : Open

• When a pull-up resistor is not contained Input mode : Connected to the VSS or VDD pin Output mode : Open

Open or directly connected to the VSS pin

Note

P00

P01 - P03

P10, P12

P20 - P23

P30 - P33

P50 - P53

P60 - P63

• Connect a capacitor between the pin and VDD.

Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

directly to V

SS pin.

3.6 NOTES ON USING THE P00 AND RESET PINS

The P00 and RESET pins have the test mode selecting function for testing the internal operation of the

PD75402A(A) (IC test), besides the functions shown in Sections 3.1 and 3.2.

Applying a voltage exceeding V

DD to the P00 and/or RESET pin causes the

PD75402A(A) to enter the test

mode. When noise exceeding V

DD comes in during normal operation, the device is switched to the test mode.

For example, when the wiring from the P00 or RESET pin is too long, noise voltage induced on the wiring

is applied to the pin, driving the voltage at the pin above VDD, which may cause malfunction.

When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If

noise yet arises, use an external part to suppress it as shown below.

• Connect a diode with low VF (0.3 V or lower) between the pin and V

DD.

P00, RESET

Diode with low V

PD75402A(A)

4. MEMORY CONFIGURATION

• Program memory (ROM): 1920 × 8 bits (000H to 77FH)

• 000H and 001H : Vector table which contains the program start address after reset

• 002H to 009H : Vector table which contains the program start addresses when interrupts occur

• Data memory

• Data area : 64 × 4 bits (000H to 03FH)

• Peripheral hardware area: 128 × 4 bits (F80H to FFFH)

Fig. 4-1 Program Memory Map

00000

76543

Reset start address (three high-order bits)

INTBT start address (three high-order bits)

INT0 start address (three high-order bits)

Reset start address (eight low-order bits)

INTBT start address (eight low-order bits)

INT0 start address (eight low-order bits)

INTCSI start address (three high-order bits)

INTCSI start address (eight low-order bits)

Address

000H

001H

002H

003H

004H

005H

008H

009H

77FH

Entry address specified in  CALLF !faddr instruction       Branch address specified in  BRCB !caddr instruction       Relative branch address specified in BR $addr instruction 

–15 to –1, +2 to +16

PD75402A(A)

Fig. 4-2 Data Memory Map

General register area

Stack area

Data area Static RAM (64 × 4)

Peripheral hardware area

000H 003H 004H

020H

03FH

F80H

FFFH

(4 × 4)

(32 × 4)

No memory

128 × 4

Bank 0 (64 × 4)

Bank 15

PD75402A(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

The µPD75402A(A) has the following three types of I/O port:

• 6 CMOS input pins (PORT0 and PORT1)

• 12 CMOS I/O pins (PORT2, PORT3, and PORT6)

• 4 N-ch open-drain I/O pins (PORT5)

Total: 22 pins

Table 5-1 Functions of Ports

Note PORT3, PORT5, and PORT6 can directly drive the LED.

Port name

PORT0 PORT1

PORT3

Note

PORT2 PORT6

Note

PORT5

Note

Function

4-bit Input

4-bit I/O

4-bit I/O (N-ch open-drain I/O with a withstand voltage of 10 V)

Remarks

Also used for SO/SB0, SI, SCK, INT0, and INT2.

—

Port 2 is also used for PCL.

This port can incorporate a pull-up resistor as a mask option bit by bit.

Operation and feature

Allows read and test at any time regardless of the operation modes of dual function pins.

Allows input or output mode setting bit by bit.

Allows input or output mode setting in units of 4 bits.

PD75402A(A)

5.2 CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC). The instruction execution time is variable.

• 0.95

s, 1.91 µs, 15.3 µs (when fXX is 4.19 MHz.)

Fig. 5-1 Block Diagram of the Clock Generator

System clock oscillator

or f

Oscillation stops.

1/16 to 1/512

Frequency divider

1/2 1/16

Selector

    

Frequency divider

HALT flip- flop

RESET input rising edge detection signal

RESET input falling edge detection signal

Standby release signal from interrupt control circuit

STOP flip- flop

All bits are cleared.

PCC2 is cleared.

HALT*

STOP*

PCC0

PCC1

PCC2

PCC3

Internal bus

PCC

· Basic interval timer (BT)

· Clock output circuit

· Serial interface

1/4

· INT0 noise eliminator

      

· CPU

· INT0 noise 

eliminator

· Clock output circuit

Remarks 1. fXX = Crystal/ceramic oscillated frequency

2. f

X = External clock frequency

3. Φ = CPU clock

4. An asterisk (*) indicates instruction execution.

5. PCC: Processor clock control register

6. One clock cycle (t

CY) of Φ is equal to one machine cycle of an instruction. See AC

characteristics of Chapter 10 for details of t

CY.

+ 33 hidden pages