NEC UPD750004CU-A-XXX, UPD750008GB-XXX-3BS-MTX, UPD750008GB-XXX-3B4, UPD750008CU-A-XXX, UPD750008CU-XXX Datasheet

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD750004,750006,750008,750004(A),750006(A),750008(A)

4 BIT SINGLE-CHIP MICROCONTROLLER

The µPD750008 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing

capability equal to that of an 8-bit microcontroller.

The µPD750008 is an advanced model of the µPD75008. It features an enhanced CPU function and enables high-

speed operation at a low voltage of 2.2 V. It can be substituted for the

PD75008. In addition, it is best suited to

applications using batteries. The

PD750008(A) has a higher reliability than the µPD750008.

A built-in one-time PROM product,

PD75P0016, is also available. It is suitable for small-scale production and

evaluation of application systems.

The following user’s manual describes the details of the functions of the

PD750008. Be sure to read it

before designing application systems.

PD750008 User’s Manual: U10740E

FEATURES

• Capable of low-voltage operation: VDD = 2.2 to 5.5 V

• Internal memory Program memory (ROM) : 4096 × 8 bits (

PD750004 and µPD750004(A))

: 6144 × 8 bits (

PD750006 and µPD750006(A))

: 8192 × 8 bits (

PD750008 and µPD750008(A)) Data memory (RAM) : 512 × 4 bits

APPLICATIONS

•µPD750004, µPD750006, and µPD750008 Cordless telephones, radio devices, audio products, and home electric appliances

•

PD750004(A), µPD750006(A), and µPD750008(A)

Electrical equipment for automobiles

The

PD750004, µPD750006, µPD750008, µPD750004(A), µPD750006(A), and µPD750008(A) differ only in

quality grade. In this manual, the

PD750008 is described unless otherwise specified. Users of other than the

PD750008 should read µPD750008 as referring to the pertinent product.

When the description differs among

PD750004, µPD750006, and µPD750008, they also refer to the pertinent

(A) products.

PD750004 → µPD750004(A), µPD750006 → µPD750006(A), µPD750008 → µPD750008(A)

The information in this document is subject to change without notice.

1990

The mark shows major revised points.

•

Function for specifying the instruction execution time (useful for high-speed operation and saving power)

0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (when operating at

4.19 MHz)

0.67

s, 1.33 µs, 2.67 µs, 10.7 µs (when operating at

6.0 MHz) 122 µs (when operating at 32.768 kHz)

• Enhanced timer function (4 channels)

• Can be easily substituted for the µPD75008 because this product succeeds to the functions and instructions of the

PD75008.

1994

Document No. U10738EJ3V0DS00 (3rd edition) Date Published February 1997 J Printed in Japan

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

ORDERING INFORMATION

Part number Package Quality grade

PD750004CU-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Standard

PD750004GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Standard

PD750006CU-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Standard

PD750006GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Standard

PD750008CU-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Standard

PD750008GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Standard

PD750004CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Special

PD750004GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Special

PD750006CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Special

PD750006GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Special

PD750008CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Special

PD750008GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Special

Remark ××× is a mask ROM code number.

DIFFERENCES BETWEEN µPD75000× AND µPD75000×(A)

Product number

Item

Quality grade Standard Special

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

PD750004

PD750006

PD750008

PD750004(A)

PD750006(A)

PD750008(A)

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

ROM

RAM

FUNCTIONS

CMOS input CMOS I/O

N-ch open drain I/O

Total

Can incorporate 7 pull-up resistors that are specified with the software. Can directly drive the LED.

Can incorporate 18 pull-up resistors that are specified with the software. Can directly drive the LED.

Can withstand 13 V. Can incorporate pull-up resistors that are specified with the mask option.

Serial interface

Clock output (PCL)

Buzzer output (BUZ)

Vectored interrupt

Test input

System clock oscillator

Standby Operating ambient

temperature range Supply voltage Package

Item

Command execution time

Internal memory

General-purpose register

I/O port

Timer

Bit sequential buffer (BSB)

4 channels

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 1 channel

• Basic interval timer/watchdog timer: 1 channel

• lock timer: 1 channel

• Three-wire serial I/O mode ... switchable between the start LSB and the start MSB

• Two-wire serial I/O mode

• SBI mode

16 bits

• Φ, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz)

• Φ, 750 kHz, 375 kHz, 93.8 kHz (when the main system clock operates at 6.0 MHz)

• 2 kHz, 4 kHz, 32 kHz (when the main system clock operates at 4.19 MHz or when the

subsystem clock operates at 32.768 kHz)

• 2.93 kHz, 5.86 kHz, 46.9 kHz (when the main system clock operates at 6.0 MHz)

External : 3 Internal : 4

External : 1 Internal : 1

• Ceramic or crystal oscillator for main system clock

• Crystal oscillator for subsystem clock

STOP/HALT mode TA = -40 to +85 °C

VDD = 2.2 to 5.5 V 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Function

• 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz)

• 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz)

• 122 µs (when the subsystem clock operates at 32.768 kHz) 4096 × 8 bits (µPD750004) 6144 × 8 bits (µPD750006) 8192 × 8 bits (µPD750008) 512 × 4 bits

• When operating in 4 bits: 8 × 4 banks

• When operating in 8 bits: 4 × 4 banks

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 6

2. BLOCK DIAGRAM ...................................................................................................................... 8

3. PIN FUNCTIONS ......................................................................................................................... 9

3.1 PORT PINS ...................................................................................................................................... 9

3.2 NON-PORT PINS ............................................................................................................................ 10

3.3 PIN INPUT/OUTPUT CIRCUITS ..................................................................................................... 11

3.4 CONNECTION OF UNUSED PINS ................................................................................................ 13

4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION ........................................................................ 14

4.1 DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE ........................................................ 14

4.2 SETTING OF THE STACK BANK SELECTION REGISTER (SBS) ............................................ 15

5. MEMORY CONFIGURATION..................................................................................................... 16

6. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 21

6.1 DIGITAL I/O PORTS....................................................................................................................... 21

6.2 CLOCK GENERATOR .................................................................................................................... 21

6.3 CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR............................................ 23

6.4 CLOCK OUTPUT CIRCUIT ............................................................................................................ 24

6.5 BASIC INTERVAL TIMER/WATCHDOG TIMER........................................................................... 25

6.6 CLOCK TIMER ................................................................................................................................ 26

6.7 TIMER/EVENT COUNTER .............................................................................................................. 27

6.8 SERIAL INTERFACE...................................................................................................................... 30

6.9 BIT SEQUENTIAL BUFFER........................................................................................................... 32

7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS................................................................ 3 3

8. STANDBY FUNCTION ................................................................................................................ 35

9. RESET FUNCTION ..................................................................................................................... 36

10. MASK OPTION ........................................................................................................................... 39

11. INSTRUCTION SET .................................................................................................................... 40

12. ELECTRICAL CHARACTERISTICS .......................................................................................... 53

13. CHARACTERISTIC CURVE (REFERENCE VALUES)............................................................. 67

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

14. PACKAGE DRAWINGS .............................................................................................................. 7 0

15. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 73

APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ...................... 74

APPENDIX B DEVELOPMENT TOOLS .......................................................................................... 7 6

APPENDIX C RELATED DOCUMENTS.......................................................................................... 80

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

1. PIN CONFIGURATION (TOP VIEW)

• 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

PD750004CU-×××, µPD750004CU(A)-×××

PD750006CU-×××, µPD750006CU(A)-×××

PD750008CU-×××, µPD750008CU(A)-×××

IC : Internally connected (Connect directly to V

DD.)

SS

P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ

XT1 XT2

RESET

X1

X2 P33 P32 P31 P30 P81 P80

P03/SI/SB1

P02/SO/SB0

P01/SCK

P00/INT4

P13/TI0 P12/INT2 P11/INT1 P10/INT0

IC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

• 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

PD750004GB-×××-3BS-MTX, µPD750004GB(A)-×××-3BS-MTX

PD750006GB-×××-3BS-MTX, µPD750006GB(A)-×××-3BS-MTX

PD750008GB-×××-3BS-MTX, µPD750008GB(A)-×××-3BS-MTX

IC : Internally connected (Connect directly to V

DD.)

PIN NAMES

P00 - 03 : Port 0 SO : Serial Output P10 - 13 : Port 1 SB0, SB1 : Serial Data Bus 0, 1 P20 - 23 : Port 2 RESET : Reset P30 - 33 : Port 3 TI0 : Timer Input 0 P40 - 43 : Port 4 PTO0, PTO1 : Programmable Timer Output 0, 1 P50 - 53 : Port 5 BUZ : Buzzer Clock P60 - 63 : Port 6 PCL : Programmable Clock P70 - 73 : Port 7 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 P80, 81 : Port 8 INT2 : External Test Input 2 KR0 - KR7 : Key Return 0 - 7 X1, X2 : Main System Clock Oscillation 1, 2 SCK : Serial Clock XT1, XT2 : Subsystem Clock Oscillation 1, 2 SI : Serial Input NC : No Connection

IC : Internally Connected

P13/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30 P31 P32 P33

P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0

P53 P52 P51 P50

33 32 31 30 29 28 27 26 25 24 23

1 2 3 4 5 6 7 8 9 10 11

NC

P43

P42

P41

P40

SS

XT1

XT2

RESET

X1

P73/KR7

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

DD

IC

P10/INT0

P11/INT1

P12/INT2

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

2. BLOCK DIAGRAM

Note The ROM capacity depends on the product.

BIT SEQ.

BUFFER (16)

PORT 0 P00 - P034

PORT 1

PORT 2 4

PORT 3 P30 - P334

PORT 4 P40 - P434

PORT 5 P50 - P534

PORT 6 P60 - P634

VSSVDDRESET

CPU CLOCK

STAND BY CONTROL

X2X1XT2XT1

SYSTEM CLOCK  GENERATOR

MAINSUB

CLOCK

DIVIDER

CLOCK OUTPUT CONTROL

fx/2

PCL/P22

GENERAL  REGISTER

DATA

MEMORY

(RAM)

512 × 4 BITS

BANK

SBS

SP (8)

ALU

PROGRAM COUNTER

PROGRAM

MEMORY

Note

(ROM)



DECODE

AND

CONTROL

BASIC INTERVAL TIMER/ WATCHDOG TIMER

TI0/P13

INTBT

8-BIT  TIMER/EVENT COUNTER #0

PTO0/P20

INTT0 TOUT0

8-BIT TIMER COUNTER #1

INTT1

TOUT0

CLOCKED SERIAL INTERFACE

SI/SB1/P03

INTERRUPT

CONTROL

INT0/P10

SO/SB0/P02

SCK/P01

INT1/P11 INT2/P12

INT4/P00 KR0/P60-

KR7/P73

WATCH

TIMER

PORT 7 P70 - P734

PORT 8 P80, P812

P10 - P134

P20 - P23

PTO1/P21

INTCSI

INTW

BUZ/P23

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3. PIN FUNCTIONS

3.1 PORT PINS

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are used as N-ch open-drain input ports), the input leak low current increases when an input instruction or bit operation instruction is executed.

I/O circuit type

Note 1

-A

-B

-C

E-B

M-D

-A

E-B

When reset

Input

High level (when pull-up resistors are provided) or high impedance

Input

8-bit I/O

Function

4-bit input port (PORT0). For P01 - P03, built-in pull-up resistors can be connected by software in units of 3 bits.

4-bit input port (PORT1). Built-in pull-up resistors can be connected by software in units of 4 bits. A noise eliminator can be selected only when the P10/INT0 pin is used.

4-bit I/O port (PORT2). Built-in pull-up resistors can be connected by software in units of 4 bits.

Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits.

N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode.

N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode.

Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits.

4-bit I/O port (PORT7). Built-in pull-up resistors can be connected by software in units of 4 bits.

2-bit I/O port (PORT8). Built-in pull-up resistors can be connected by software in units of 2 bits.

B F

Pin name

P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 - P33

P40 - P43

Notes 2

P50 - P53

Notes 2

P60 P61 P62 P63 P70 P71 P72 P73 P80 P81

Input/

output

Input

I/O I/O I/O

Input

I/O

Shared

pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 PTO1 PCL BUZ

KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.2 NON-PORT PINS

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. With a noise eliminator/asynchronously selectable

3. Asynchronous

Function

Inputs external event pulse to the timer/event counter

Timer/event counter output Timer counter output Clock output Arbitrary frequency output (for buzzer output or

system clock trimming) Serial clock I/O Serial data output

Serial data bus I/O Serial data input

Serial data bus I/O Edge detection vectored interrupt input (both

rising and falling edges are detected)

Rising edge detection testable input Falling edge detection testable input Falling edge detection testable input Crystal/ceramic connection pin for main system

clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2.

Crystal connection pin for subsystem clock generation. When external clock signal is used, it is applied to XT1, and it reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test).

System reset input (active low) Internally connected. (To be connected directly to

VDD) Positive power supply Ground potential

Input/

output

Input

Output

I/O

Input

I/O I/O

Input

When reset

Input

Input Input

Edge detection vectored interrupt input (detection edge selectable). A noise eliminator can be selected when INT0/P10 is used.

Shared pin

P13

P20 P21 P22 P23

P01 P02

P03

P00

P10

P11 P12 P60 - P63 P70 - P73

Note 3

Note 2

Note 3

I/O circuit type

Note 1

-C

E-B

-A

-B

-C

-A

Pin name

TI0

PTO0 PTO1 PCL BUZ

SCK SO/SB0

SI/SB1

INT4

INT0

INT1 INT2 KR0 - KR3 KR4 - KR7 X1

XT1

XT2

RESET IC

VDD VSS

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuit of each

PD750008 pin is shown below in a simplified manner.

Type A

Type D

Type B Type E-B

Type B-C Type F-A

Schmitt trigger input with hysteresis

P.U.R.: Pull-Up Resistor

P-ch

P.U.R. enable

P.U.R.

P.U.R.: Pull-Up Resistor

P.U.R.

P.U.R. enable

P-ch

IN/OUT

Data

Output disable

Type D

Type A

P.U.R.

P.U.R. enable

P-ch

IN/OUT

Data

Output disable

Type D

Type B

P.U.R.: Pull-Up Resistor

Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch)

P-ch

N-ch

OUT

Data

Output

disable

CMOS input buffer

P-ch

N-ch

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Type F-B

Type M-C

Type M-D

P.U.R.: Pull-Up Resistor

P-ch

N-ch

IN/OUT

P-ch

P.U.R.

P.U.R.

enable Output disable (P)

Data

Output disable

Output disable (N)

P.U.R.: Pull-Up Resistor

N-ch

P.U.R.

Data

Output disable

P.U.R.

enable

P-ch

IN/OUT

P.U.R.: Pull-Up Resistor

N-ch (Withstand voltage:  +13 V)

IN/OUT

Data

Output disable

P.U.R.

(Mask option)

Note

P.U.R

Note

P-ch

Input 

instruction

Pull-up resistor that operates only when pull-up resistors  that can be specified with the mask option are not  incorporated and an input instruction is executed. (When the pin is low, the current flows from V

to the pin.)

Voltage  restriction circuit

(Withstand voltage: +13 V)

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Input state : To be connected to VSS or VDD

through a separate resistor

Output state : To be left open

Input state : To be connected to VSS or VDD

through a separate resistor

Output state : To be left open

Input state : To be connected to VSS Output state : To be connected to V SS

(Do not connect to a pull-up resistor specified with a mask option.)

3.4 CONNECTION OF UNUSED PINS

Table 3-1 Connection of Unused Pins

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-

in feedback resistor).

Pin name Recommended connection P00/INT4 To be connected to VSS or VDD P01/SCK

P02/SO/SB0

P03/SI/SB1 To be connected to VSS P10/INT0 - P12/INT2 To be connected to VSS or VDD P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ

P30 - P33 P40 - P43

P50 - P53

P60/KR0 - P63/KR3 P70/KR4 - P73/KR7 P80, P81 XT1

Note

To be connected to VSS

XT2

Note

To be left open

IC To be connected directly to VDD

To be connected to VSS or VDD through a separate resistor

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION

4.1 DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE

The CPU of the

PD750008 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable.

Bit 3 of the stack bank selection register (SBS) determines the mode.

• Mk Ι mode: This mode has the upward compatibility with the

PD75008.

It can be used in the 75XL CPUs having a ROM of up to 16 KB.

• Mk ΙΙ mode: This mode is not compatible with the

PD75008.

It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.

Table 4-1 shows the differences between Mk Ι mode and Mk ΙΙ mode.

Table 4-1 Differences between Mk Ι Mode and Mk ΙΙ Mode

Caution Mk ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL

series. This mode enhances a software compatibility with products whose program area is larger than 16K bytes. In Mk ΙΙ mode, one more stack byte is required for execution of subroutine call instructions per stack compared with Mk Ι mode. When a CALL !addr or CALLF !faddr instruction is executed, it takes one more machine cycle. Therefore, Mk Ι mode should be used for applications for which RAM efficiency or processing capabilities is more critical than a software compatibility.

Number of stack bytes in a subroutine instruction

BRA !addr1 instruction CALLA !addr1 instruction

CALL !addr instruction CALLF !faddr instruction

2 bytes

None

3 machine cycles 2 machine cycles

3 bytes

Available

4 machine cycles 3 machine cycles

Mk Ι mode Mk ΙΙ mode

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

4.2 SETTING OF THE STACK BANK SELECTION REGISTER (SBS)

The Mk Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Fig. 4-1 shows the register

configuration.

The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk Ι mode,

initialize the register to 100×B

Note

at the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to

000×B

Note

Note Specify the desired value in ×.

Fig. 4-1 Stack Bank Selection Register Format

Caution The CPU operates in Mk Ι mode after the RESET signal is issued, because bit 3 of SBS is set to 1.

Set bit 3 of SBS to 0 (Mk ΙΙ mode) to use the CPU in Mk ΙΙ mode.

SBS0SBS1SBS2SBS3

0123

F84H

Address

SBS

Symbol

0001Memory bank 0

Memory bank 1

Other settings are inhibited.

01Mk ΙΙ mode

Mk Ι mode

Mode switching designation

Bit 2 must be set to 0.

Stack area designation

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

5. MEMORY CONFIGURATION

• Program memory (ROM) : 4096 × 8 bits (0000H-0FFFH): µPD750004 6144 × 8 bits (0000H-17FFH):

PD750006

8192 × 8 bits (0000H-1FFFH):

PD750008

• 0000H to 0001H

Vector address table for holding the RBE and MBE values and program start address when a RESET signal is issued (allowing a reset start at an arbitrary address)

• 0002H to 000DH

Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt (allowing interrupt processing to be started at an arbitrary address)

• 0020H to 007FH

Table area referenced by the GETI instruction

• Data memory (RAM)

• Data area : 512 × 4 bits (000H to 1FFH)

• Peripheral hardware area : 128 × 4 bits (F80H to FFFH)

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-1 Program Memory Map (in µPD750004)

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

000H

Address

7654

MBE RBE 0 0 Internal reset start address (high-order 4 bits)

002H MBE RBE 0 0 INTBT/INT4 (high-order 4 bits)start address

004H MBE RBE 0 0 INT0 (high-order 4 bits)start address

006H MBE RBE 0 0 INT1 (high-order 4 bits)start address

008H MBE RBE 0 0 INTCSI (high-order 4 bits)start address

00AH MBE RBE 0 0 INTT0 (high-order 4 bits)start address

00CH MBE RBE 0 0 INTT1 (high-order 4 bits)start address

020H

07FH 080H

7FFH

800H

FFFH

GETI instruction reference table

(low-order 8 bits)

CALLF ! faddr instruction entry address

Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1

Note

or

CALLA !addr1

Note



instruction

CALL !addr instruction subroutine entry address

BR $addr instruction relative branch address

BRCB !caddr instruction branch address

-15 to -1, +2 to +16

Branch destination

 address and subroutine entry address when GETI instruction is executed

Internal reset start address

INTBT/INT4 start address

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-2 Program Memory Map (in µPD750006)

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

0000H

Address

0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address

0004H MBE RBE 0 INT0 (high-order 5 bits)start address

0006H MBE RBE 0 INT1 (high-order 5 bits)start address

0008H MBE RBE 0 INTCSI (high-order 5 bits)start address

000AH MBE RBE 0 INTT0 (high-order 5 bits)start address

0020H

007FH 0080H

07FFH 0800H

MBE RBE 0

Internal reset start address (high-order 5 bits)

0FFFH

1000H

17FFH

GETI instruction reference table

000CH MBE RBE 0 INTT1 (high-order 5 bits)start address

(low-order 8 bits)

CALLF !faddr instruction entry address

BRCB !caddr instruction branch address

Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1

Note

or

CALLA !addr1

Note

instruction

CALL !addr instruction subroutine entry address

BR $addr instruction relative branch address

-15 to -1, +2 to +16

Branch destination address and subroutine entry address when GETI instruction is executed

BRCB !caddr instruction branch address

765 0



Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1

start address

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-3 Program Memory Map (in µPD750008)

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

0000H

Address

0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address

0004H MBE RBE 0 INT0 (high-order 5 bits)start address

0006H MBE RBE 0 INT1 (high-order 5 bits)start address

0008H MBE RBE 0 INTCSI (high-order 5 bits)start address

000AH MBE RBE 0 INTT0 (high-order 5 bits)start address

0020H

007FH

0080H

07FFH

0800H

MBE RBE 0

Internal reset start address (high-order 5 bits)

0FFFH

1000H

1FFFH

GETI instruction reference table

000CH MBE RBE 0 INTT1 (high-order 5 bits)start address

(low-order 8 bits)

CALLF !faddr instruction entry address

BRCB !caddr  instruction  branch  address

Branch address  of BR BCXA, BR  BCDE, BR !addr,  BRA !addr1

or 

CALLA !addr1

Note



instruction

CALL !addr  instruction subroutine entry  address

BR $addr  instruction relative  branch address

-15 to -1, +2 to +16

Branch destination address and subroutine entry address when GETI instruction is executed

BRCB !caddr  instruction  branch  address

765 0



Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1

start address

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-4 Data Memory Map

Note Memory bank 0 or 1 can be selected as the stack area.

(32 × 4)

Data memory

000H

01FH 020H

0FFH

100H

1FFH

F80H

FFFH

256 × 4



(224 × 4)

256 × 4

128 × 4

Stack area

Note

Area for  general-purpose  register

Data area

Static RAM 

(512 × 4)

Peripheral  hardware area

Not contained

Memory bank

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

When the serial interface function is used, dual-function pins function as output pins in some operation modes.

4-bit input port

Allows input or output mode setting in units of 4 bits.

Allows input or output mode setting in units of 1 bit.

Operation and feature

Port name PORT0

PORT1

PORT2

PORT3 PORT4

PORT5

PORT6

PORT7

PORT8

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 DIGITAL I/O PORTS

The

PD750008 has the following three types of I/O port:

• 8 CMOS input pins (PORT0 and PORT1)

• 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8)

• 8 N-ch open-drain I/O pins (PORT4 and PORT5) Total: 34 pins

Table 6-1 Digital Ports and Their Features

6.2 CLOCK GENERATOR

The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Fig. 6-1 shows

the configuration of the clock generator.

Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control

The main system clock and subsystem clock are used. The instruction execution time can be made variable.

• 0.95

s, 1.91 µs, 3.81 µs, 15.3 µs (when the main system clock is at 4.19 MHz)

• 0.67

s, 1.33 µs, 2.67 µs, 10.7 µs (when the main system clock is at 6.0 MHz)

• 122

s (when the subsystem clock is at 32.768 kHz)

Allows input or output mode setting in units of 4 bits. Whether to use pull-up resistors can be specified bit by bit with the mask option.

Allows input or output mode setting in units of 1 bit.

Allows input or output mode setting in units of 4 bits.

Ports 4 and 5 can be paired, allowing data I/O in units of 8 bits.

Ports 6 and 7 can be paired, allowing data I/O in units of 8 bits.

4-bit input

4-bit I/O

4-bit I/O (N-ch open-drain can withstand 13 V)

4-bit I/O

2-bit I/O

Also used as INT4, SCK, SO/SB0, or SI/SB1.

Also used as INT0, INTI, INT2 or TI0.

Also used as PTO0, PTO1, PCL, or BUZ.

Also used as one of KR0 to KR3.

Also used as one of KR4 to KR7.

Allows input or output mode setting in units of 2 bits.

Function

Remarks

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 6-1 Clock Generator Block Diagram

Note Instruction execution

Remarks 1. fX = Main system clock frequency

2. f

XT = Subsystem clock frequency

3. Φ = CPU clock

4. PCC: Processor clock control register

5. SCC: System clock control register

6. One clock cycle (t

CY) of the CPU clock (Φ) is equal to one machine cycle of an instruction.

Subsystem clock generator

Main system clock generator

Clock timer

•

Basic interval timer (BT)

•

Timer/event counter

•

Timer counter

•

Serial interface

•

Clock timer

•

INT0 noise eliminator

•

Clock output circuit



1/1 to 1/4096

Frequency divider

Selec- tor

Frequency  divider

Oscillator disable signal

Internal bus

HALT

Note

STOP

Note

PCC2, PCC3  clear signal

Wait release signal from BT

Standby release signal from  interrupt control circuit

RESET signal

XT1

XT2

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

STOP flip-flop

HALT flip-flop

1/2 1/16

1/4

WM.3

•

CPU

•

INT0 noise

eliminator

•

Clock output circuit 

      

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.3 CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR

The subsystem clock oscillator of the

PD750008 subseries has two control functions to decrease the supply

current.

• The function to select with the software whether to use the built-in feedback resistor

Note

• The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply voltage is high (V

DD ≥ 2.7 V)

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect

XT1 to V

SS, and open XT2. This makes it possible to reduce the supply current required by the subsystem

clock oscillator.

Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Fig. 6-2.)

Fig. 6-2 Subsystem Clock Oscillator

SOS.0

SOS.1

XT1 XT2

Inverter

Feedback resistor

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.4 CLOCK OUTPUT CIRCUIT

The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control

waveform output, peripheral LSIs, etc.

• Clock output (PCL): Φ, 524, 262, or 65.5 kHz (at 4.19 MHz) Φ, 750, 375, or 93.8 kHz (at 6.0 MHz)

Fig. 6-3 Clock Output Circuit Configuration

Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable.

From the clock generator 

CLOM

Selector

Output buffer

Port 2 input/ output mode  specification bit

P22 output latch

PCL/P22

Internal bus

PORT2.2 Bit 2 of PMGB

CLOM0CLOM10CLOM3

fX/2

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.5 BASIC INTERVAL TIMER/WATCHDOG TIMER

The basic interval timer/watchdog timer has these functions:

• Interval timer operation which generates a reference timer interrupt

• Operation as a watchdog timer for detecting program crashes and resetting the CPU

• Selection of wait time for releasing the standby mode and counting the wait time

• Reading out the count value

Fig. 6-4 Block Diagram of the Basic Interval Timer/Watchdog Timer

Note Instruction execution

From the clock generator

Internal bus

/25

/27

/29

/212

MPX 

Basic interval timer

(8-bit frequency divider)



Clear signal 

BT interrupt  request flag 

Vectored interrupt request signal

IRQBT 

Wait release signal for standby release 

Set  signal

BT 

BTM3BTM2BTM1BTM0BTM



SET1

Note

WDTM



Internal reset signal

SET1

Note

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.6 CLOCK TIMER

The

PD750008 contains one channel for a clock timer. The clock timer provides the following functions:

• Sets the test flag (IRQW) with a 0.5 sec interval. The standby mode can be released by IRQW.

• The 0.5 second interval can be generated from either the main system clock (4.194304 MHz) or subsystem clock

(32.768 kHz).

• The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for

program debugging, testing, etc.

• Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be

used for beep and system clock frequency trimming.

• The frequency divider circuit can be cleared so that a zero-second start of the clock can be made.

Fig. 6-5 Clock Timer Block Diagram

( ) is for f

X = 4.194304 MHz, fXT = 32.768 kHz.

P23/BUZ

Internal bus

Selector

From the clock generator

X



128

(32.768 kHz)  f

XT

(32.768 kHz)

Selector Frequency divider

Selector

INTW IRQW set signal

2 Hz

0.5 sec

WM7 0 WM5 WM4 WM3 WM2 WM1 WM0

P23 output  latch

Bit 2 of PMGBPORT2.3

Output buffer

Clear

fW (32.768 kHz)

Bit test instruction

Port 2 input/ output mode

(4 kHz) (2 kHz)

fw 2

(256 Hz: 3.91 ms)

fw

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