NEC UPD7225GB-3B7, UPD7225GC-AB6, UPD7225G01, UPD7225G00 Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD7225

PROGRAMMABLE LCD CONTROLLER/DRIVER

The

PD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The µPD7225 can be

µ

serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The µPD7225 contains a segment decoder which can generate specific segment patterns. In addition, the µPD7225 can be used to control on/off (blinking) operation of a display.

FEATURES

•Can directly drive LCD

•Programmable time-division multiplexing

•

Static drive

•

Divide-by-2, 3, or -4 time division multiplexing

•Number of digits displayed

•

7-segment

Divide-by-4 time division...............16 digits

Divide-by-3 time division...............10 2/3 digits

Divide-by-2 time division...............8 digits

Static.................................................4 digits

•

14-segment

Divide-by-4 time division...............8 digits

•Bias method Static, 1/2, 1/3

•Segment decoder output

•

7-segment: Numeric characters 0 to 9, six symbols

•

14-segment: 36 alphanumeric characters, 13 symbols

•Blinking operation

•Multi-chip configuration possible

•8-bit serials interface 75X series and 78K series compatible

•CMOS

•Single power supply

ORDERING INFORMATION

Part Number Package

µ

PD7225G00 52-pin plastic QFP (14 × 14 mm)

µ

PD7225G01 52-pin plastic QFP (straight) ( 14 m m )

µ

PD7225GB-3B7 56-pin plastic QFP (10 × 10 mm)

µ

PD7225GC-AB6 52-pin plastic QFP (14 × 14 mm)

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S14308EJ6V0DS00 (6th edition)

(O.D. No. IC-1555) Date Published June 1999 N CP (K) Printed in Japan

The mark shows major revised points.

©

1986, 1999

PIN CONFIGURATION: (Top View)

µµµµ

PD7225

PD7225G00 52-pin plastic QFP (14

µµµµ

PD7225G01 52-pin plastic QFP (straight) ( 14 mm)

µµµµ

PD7225GC-AB6 52-pin plastic QFP (14

µµµµ

CL1

S31

S30

51 50 49 48 47 46 45 44 43 42 41 40

CL2

/SYNC

V

LC1

VLC2 VLC3

VSS VDD

/SCK

/CS

/BUSY

SI

1 2 3 4 5 6 7 8 9 10 11

52

S29

14 mm)

××××

14 mm)

××××

S28

S27

S26

S25

S24

S23

S22

S21

S20

39 38 37 36 35 34 33 32 31 30 29

S19 S18 S17 S16 S15 S14 V

DD

S13 S12 S11 S10

C, /D

/RESET

12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

S0

S1

S2

S3

S4

NC

COM0

COM1

COM2

COM3

S5

S6

28 27

S7

SI : Serial Input CL1 : External Resistor 1 (External Clock) /SCK : Serial Clock CL2 : External Resistor 2 C, /D : Command/Data RESET : Reset /CS : Chip Select V /BUSY : Busy V SYNC : Sync V

LC1-VLC3 DD SS

: Power Supply For LCD Drive : Power Supply

: Ground S0-S31 : Segment IC : Internally Connected COM0-COM3 : Common NC : Non-connection

/

Remark

indicates active low signal.

×××

S9 S8

2

Data Sheet S14308EJ6V0DS00

µµµµ

PD7225

PD7225GB-3B7 56-pin plastic QFP (10

µµµµ

IC

S19

S18

S17

56 55 54 53 52 51 50 49 48 47 46 45 44 43

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

1

2

3

4

5

6

7

8

9

10

11

10 mm)

××××

S16

S15

S14

VDDS13

S12

S11

S10

S9

S8

42

41

40

39

38

37

36

35

34

33

32

IC

S7

S6

S5

S4

S3

S2

S1

S0

COM3

COM2

Note

S31

CL1

IC

12

13

14

15 16 17 18 19 20 21 22 23 24 25 26 27 28

CL2

/SYNC

IC Pin must be connected to V

LC1VLC2VLC3

V

DD

or left unconnected.

31

30

29

SS

DD

V

/SCK

SI

/CS

/BUSY

C, /D

IC

/RESET

COM1

COM0

NC

Data Sheet S14308EJ6V0DS00

3

BLOCK DIAGRAM

V

LC1

LCD DRIVER

COM

3S1S29S30S31

COM

2S0

µµµµ

PD7225

COM

1

0

VLC2

VLC3

/SYNC

CL1

CL2

V

VSS

/RESET

/CS

C, /D

/BUSY

LCD

TIMING

CONTROL

OSC

DD

WRITE

CONTROL

SEGMENT

DECODER

DISPLAY DATA LATCH

DATA

MEMORY

COMMAND/DATA REGISTER

SERIAL INTERFACE

DATA

POINTER

BLINKING

DATA

MEMORY

COMMAND

DECODER

/SCKSI

4

Data Sheet S14308EJ6V0DS00

1. PIN FUNCTIONS

µµµµ

PD7225

1.1 SI (Serial Input)

This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet

commands for controlling the operation of the µPD7225 can be input to this pin.

1.2 /SCK (Serial Clock)

This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1. If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.

1.3 C, /D (Command/Data)

This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a high level indicates a command.

1.4 /BUSY

This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.

Tri-state output

……

…………

……

…………

Input

……

…………

Input

……

…………

Input

1.5 /CS (Chip Select)

When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.

1.6 /SYNC (SYNChronous)

The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking operation is synchronized in a multi-chip configuration.

When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to

Figure 1-1

display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.

), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the

f

CL

/SYNC

Input

……

…………

Input/Output

……

…………

Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)

Data Sheet S14308EJ6V0DS00

5

Figure 1-2. /SYNC Pin Status after Reset (/RESET = 1)

µµµµ

PD7225

Static

COM0

/SYNC

Divie-by-2 time division

COM0

/SYNC

Divie-by-3 time division

COM0

/SYNC

Divie-by-4 time division

1 frame

COM0

/SYNC

1.7 /RESET

……

…………

Input

This is an active low reset input pin.

1.8 S0-S31 (Segment)

……

…………

Output

These pins output segment drive signals.

1.9 COM0-COM3 (COMmon)

……

…………

Output

These pins output common drive signals.

1.10 CL1, CL2 (Clock)

A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the

CL1 pin for input.

LC1

LC2

1.11 V

, V

LC3

LCD driver power supply pin.

6

Data Sheet S14308EJ6V0DS00

DD

1.12 V

Positive power supply pin. Either pin 7 or pin 33 can be used.

SS

1.13 V

GND pin.

µµµµ

PD7225

Data Sheet S14308EJ6V0DS00

7

µµµµ

PD7225

2. INTERNAL SYSTEM CONFIGURATION

2.1 Serial Interface

The serial interface consists of an 8-bit serial register and a 3-bit SCK counter.

The serial register clocks in the serial data from the SI pin at the rising edge of /SCK. At the same time, the SCK counter increments (+1) the serial clock. As a result, if an overflow occurs (when eight pulses are counted), input from the SI pin is disabled (/BUSY = 0), and the contents of the serial register is output to the command/data register.

The /SCK should be set to high before serial data is input and after the data has been input (after eight clocks are input to /SCK).

Serial data must be input to the SI pin beginning with MSB first.

LSB

µ

PD7225

SI pin

MSB

D7

D6 D5 D4 D3 D2 D1 D0

2.2 Command/Data Register

The command/data register latches the contents of the serial register in order to process the serial data clocked into the serial register. After the serial data is latched, if the clocked in data is specified as command, the command/data register transfers its contents to the command decoder. If specified as data the command/data register transfers its contents to data memory or the segment decoder.

2.3 Command Decoder

When the contents of the command/data register are specified as a command (C, /D was high when data was input), the command decoder, clocks in the contents of the command/data register and controls the µPD7225.

2.4 Segment Decoders

The µPD7225 has a 7-segment decoder for use with divide-by-3 and divide-by-4 time division, and a 14-segment decoder for use divide-by-4 time division.

The 7-segment decoder can generate signals for numeric characters 0 to 9 and six different symbols. The 14segment decoder can generate signals for 36 alphanumeric characters and 13 different symbols. When the WITH SEGMENT DECODER command is executed, if the contents of the command/data register are specified as data, the contents will be input to the segment decoder, and converted to display codes, and then automatically written to the data memory. Whether to select the 7-segment decoder or 14-segment decoder is determined by the most significant bit (bit 7) of the data input to the segment decoder. It the most significant bit is 0, the 7-segment decoder will be selected. If it is 1, the 14-segment decoder will be selected. If the 7-segment decoder is selected (however, divide-by-3 and divide-by-4 time division), the lower 4 bits (bit 3 to bit 0) of the input data (C, /D = 0) will be decoded and written to the data memory.

If the 14- segment decoder is selected (however, divide-by-4 time division), the lower 7 bits of the input data (C, /D = 0) will be decoded and written to the data memory.

8

Data Sheet S14308EJ6V0DS00

µµµµ

PD7225

703 0

Decode data

Specifies 7-segment decoder

706 1

Decode data

Specifies 14-segment decoder

When displaying the output of the segment decoder (display data) on the LCD, use an LCD configured as shown

in Figure 2-1 or Figure 2-2.

If another type of LCD is used, the displayed pattern will be different.

Figure 2-1. 7-Segment Type LCD

When configuring the LCD for divide-by-3 time division mode, connect as follows:

SEGn + 1

SEGn + 2

SEGn

COM0

COM1

COM2

a

b

f

g

e

c

DP

d

SEGn SEGn +1 SEGn + 2 COM0 COM1 COM2

: b, c, DP : a, d, g : e, f : a, b, f : c, e, g : d, DP

Data Sheet S14308EJ6V0DS00

9

When configuring the LCD for divide-by-4 time division mode, connect as follows:

SEGn

µµµµ

PD7225

SEGn + 1

f

e

d

COM0

COM2

a

b

g

c

DP

SEGn SEGn + 1 COM0 COM1 COM2 COM3

: a, b, c, DP : d, e, f, g : a, f : b, g : c, e : d, DP

COM1

COM3

10

Data Sheet S14308EJ6V0DS00

µµµµ

PD7225

Figure 2-2. 14-Segment LCD

The 14-segment type LCD can be used only in the divide-by-4 time division mode. For the 14-segment LCD type,

connect segments and commons as follows:

SEGn + 3 SEGn + 2

COM0

COM1

COM2

SEGn + 1 SEGn

e

a

bihgf

kj

cnml

d

DP

SEGn SEGn + 1 SEGn + 2 SEGn + 3 COM0 COM1 COM2 COM3

: h, i, k, n : d, e, f : a, b, c, DP : g, j, l, m : a, g, h : b, i, j, f : c, e, k, l : d, m, n, DP

COM3

The following shows the input data and display pattern, and the configuration of the display data which is automatically written into the data memory. For the 7-segment type, the lower 4 bits (D3 to D0) are decoded. For the 14-segment type, the input data and display pattern correspond to 8-bit ASCII code. The first address to which the display data is written is indicated as address N.

Data Sheet S14308EJ6V0DS00

11

Figure 2-3. 7-Segment LCD

µµµµ

PD7225

Data

(HEX)

00

01

02

03

04

Display

pattern

Data memory

Divide-by-3

time division

5

3

0

7

2

7

0

2

1

time division

NN +1 NN +1N +2

3

1

3

Divide-by-4

7

D

6

0

3

E

7

A

6

3

Data

(HEX)

08

09

0A

0B

0C

Display pattern

Data memory

Divide-by-3

time division

7

3

7

1

2

0

7

3

5

3

time division

NN +1 NN +1N +2

3

0

Divide-by-4

7

F

7

B

0

2

1

F

1

D

05

06

07

2

7

1

2

7

3

1

0

5

B

5

F

7

0

0D

0E

0F

0

2

0

6

2

6

0

A

4

E

0

12

Data Sheet S14308EJ6V0DS00

Figure 2-4. 14-Segment LCD

Upper bit

µµµµ

PD7225

Data

(HEX)

0

1

2

3

4

5

6

Display pattern

A

Data memory

N+2N+1 N

N+3

0

B

Display

pattern

0

Data memory

N+3N+2N+1 N

E

7

4

0

6

0

C

3

2

8

7

2

6

2

A

5

2

5

2

E

Display pattern

2

0

4

C

Data memory

N+3N+2N+1 N

C

7

A

6

7

2

8

7

8

E

1

0

8

7

8

E

1

2

6

1

2

Display

pattern

0

4

5

0

1

4

D

Data memory

N+3N+2N+1 N

6

3

2

E

7

0

6

3

2

8

5

1

0

1

8

E

6

0

4

6

4

8

C

4

1

0

2

7

Lower bits

8

9

A

B

C

D

E

F

6

7

0

5

0

F

0

A

0

2

0

4

2

0

A

0

F

0

5

0

4

0

2

0

7

2

7

2

0

4

0

2

0

1

0

4

E

4

A

2

8

4

8

0

4

6

2

1

8

1

8

0

C

6

0

A

6

0

2

0

E

0

6

1

6

1

7

0

2

6

8

6

0

E

4

E

5

4

0

5

0

9

1

4

0

1

8

6

A

0

2

0

2

8

0

Data Sheet S14308EJ6V0DS00

13

µµµµ

PD7225

2.5 Data Memory/Data Pointer

The data memory is a memory which stores display data (32 × 4 bits). Data input by serial transfer, command

immediate data, etc., is written to the data memory.

Specified by data pointer

Address

012345678910 293031

0

Bit

In the data memory, either data from the serial register (when the segment decoder is not used) or data from the

segment decoder (when the segment decoder is used) is written as display data.

When the segment decoder is not used, all bits or the lower 4 bits of the serial data (C, /D = 0) input to the serial register are assigned and written to the specific bits in location 2 to location 4 in the data memory according to the specified time division. When the segment decoder is used, the contents of the serial register (C, /D = 0) are decoded by the segment decoder, and the corresponding display data are allocated to the location specified in data memory by the time division specification (devide-by-3, -4 time division) and the MSB (Most Significant Bit) of the serial data. (1) to (4) below describe these operations.

The contents of the data memory can be modified in 4-bit units or in bit units using a command.

1 2 3

(1) Static

The lower 4 bits of the contents of the serial register are written to bit 0 in each address (the upper 4 bits are ignored).

bit3 bit0

D3 D2 D1 D0

n + 3 n + 2 n + 1 Address n

Only the content of bit 0 in each address are effective as display data. After the data is written, the data pointer points to address n + 4.

(2) Divide-by-2 time division

The contents of the 4 even bits of the serial register are written to bit 0 in the four addresses, and the contents of 4 odd bits of the serial register are written to bit 1.

bit3 bit0

D7 D6 D5 D4 D3 D2 D1 D0

n + 3 n + 2 n + 1 Address n

The contents of bits 0 and 1 of each address are effective as display data. After the data is written, the data pointer points to address n + 4.

14

Data Sheet S14308EJ6V0DS00

µµµµ

PD7225

(3) Divide-by-3 time division

The contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and 2 of each address. In this case, 0 will be automatically written to bit 2 of address n + 2. For segment decoder output, 0 will also be automatically written to bit 2 (D2) of address n.

bit3 bit0

0D7D6 D5D4D3

n + 2 n + 1 Address n

D2

D1 D0

0

The contents of bits 0, 1, and 2 of each address are effective as display data. After the data is written, the data pointer points to address n + 3. The segment decoder output written to the data memory corresponds to segments (a to g, DP) shown in Figure 2-1 as follows:

bit3 bit0

ef dga DPcb

n + 2 n + 1 Address n

(4) Divide-by-4 time division

The contents of the 8 bits of the serial register or the segment decoder output (8 bits) are written to bits 0, 1, 2, and 3 of each address. For segment decoder output, 0 is automatically written to bit 3 (D3) of address n.

bit3 bit0

D7 D6 D5 D4

n + 1 Address n

D3

D2 D1 D0

0

The contents of all bits of each address are effective as display data. After the data is written, the data pointer points to address n + 2. When 7 segments are used, the segment decoder output written to the data memory corresponds to segments (a to g, DP) shown in Figure 2-1 as follows:

bit3 bit0

degf DPcba

n + 1 Address n

When 14 segments are used, the segment decoder output is written to bits 0, 1, 2, and 3 of each address. In this case, 0s are automatically written to bit 3 of address n + 2, and bit 0 of address n+ 1.

D15 D14 D13 D12

n + 3 n + 2 n + 1 Address n

D11

D10 D9 D8 D7 D6 D5

0

Data Sheet S14308EJ6V0DS00

D4

0

bit3 bit0

D3 D2 D1 D0

15

µµµµ

PD7225

All bits of each address are effective. After the data is written, the data pointer points to address n + 4. The segment decoder output written to the data memory corresponds to segments (a to n, DP) shown in Figure 2-2 as follows:

ml jg DPcba def0 nki h

n + 3 n + 2 n + 1 Address n

All contents of the 32 × 4-bit data memory are transferred to the 32 × 4-bit display data latch when the /CS is set to high. In this case, if the DISPLAY ON command has been set, the contents of the display data latch are converted to the segment drive signal in 32-bit units in synchronization with COM0-COM3 signals, and output from the segment pins. The figure below shows the relationship of the data memory, segment pins, and common signal selection timing.

Figure 2-5. Data Memory, Segment Pins, and Common Signal Selection Timing

COM 0 COM 1 COM 2 COM 3

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

012345678

9 10 28293031

Address

S28S29 S30S31

0 1

Bit

2 3

The data pointer (5 bits) specifies the address (0-31) of the data memory to which the display data will be written (at the same time, the data pointer specifies the blinking data memory address (0-31)). The LOAD DATA POINTER command is used to set the address to the data pointer (the data pointer can be initialized by setting the /CS to low). When the data pointer is counted up to 31, it then becomes 0 at the next count, and thus it repeats the operation shown below.

031

It should be noted that, if display data is written sequentially from address 0 in the divide-by-3 time division mode, addresses 30 and 31 will not be written. However, if the data is written in the divide-by-3 time division mode again, data will be written from addresses 30, 31, followed by 0 so that the display data previously written to address 0 will be modified.

16

Data Sheet S14308EJ6V0DS00