NEC UPD16878 DATA SHEET
µµµµ
查询UPD16878供应商
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
DESCRIPTION
The µPD16878 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET
output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional
driver ICs that use bipolar transistors.
Because the µPD16878 controls a motor by inputting serial data, its package has been shrunk and the number of
pins reduced. As a result, the performance of the application set can be improved and the size of the set has been
reduced.
The µPD16878 employs a current-controlled 64-step micro step driving method that drives stepper motor with low
vibration.
The µPD16878 is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set.
The µPD16878 can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16878
FEATURES
• Four H bridge circuits employing power MOS FETs
• Current-controlled 64-step micro step driving
• Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input)
Data is input with the LSB first.
EVR reference setting voltage: 100 to 250 mV (@VREF
Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)
Original oscillation division or internal oscillation selectable
Number of pulses in 1 VD: 0 to 126 pulses ... 6 bits + 2-bit data input (2 pulses/step)
Step cycle: 0.25 to 8191.75 µs ... 15-bit data input (0.25- µs step)
• 3-V power supply. Minimum operating voltage: 2.7 V (MIN.)
• Low current consumption IDD: 3.0 mA (MAX.), IDD
• 38-pin plastic shrink SOP (7.62 mm (300))
ORDERING INFORMATION
Part number Package
PD16878GS-BGG 38-pin plastic shrink SOP (7.62 mm (300))
µ
= 250 mV) ... 4-bit data input (10-mV step)
: 100 µA (MAX.), I
(RESET)
MO(RESET)
: 1.0 µA (MAX.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15974EJ1V0DS00 (1st edition)
Date Published February 2002 N CP(K)
Printed in Japan
©
2002
BLOCK DIAGRAM
EXP0 EXP1 EXP2 EXP3
α
β
EXT
EXT
31
22
EXTOUT SELECTOR
β
µµµµ
PD16878
D
FILTERFILTERFILTERFILTER
+
2ch
–+
M
V
β
H BRIDGE
10125141643028326
FIL
2
D
1
D
D
FB
C
FIL
2
+
–+
M
V
1ch
β
H BRIDGE
C
1
C
SCLK SDATA LATCH
REF
V
D
V
OUT
OSC
IN
OSC
SERIAL-PARARELLE DECODER
EVR1 EVR2
CURRENT SET
C
FB
x 2
α
PULSE GENERATER
EVR2
EVR1
CURRENT SET
+
–+
M
V
2ch
α
H BRIDGE
B
FIL
2
B
1
B
B
FB
A
FIL
2
A
OSC
1/N
37 36 32 7 35 34 33 17 18 19 21
SELECTOR
+
–+
M
V
1ch
α
H BRIDGE
1
A
25 24 29 15 11 6
A
FB
38
8
23
27
9
13
2
DD
VM1VM2VM3V
V
M4
OSC
C
RESET
2
Data Sheet S15974EJ1V0DS
1
LGND
20
PGND
PIN CONFIGURATION
38-pin plastic shrink SOP (7.62 mm (300))
10
11
12
13
14
15
16
17
18
19
µµµµ
PD16878
1
LGND
2
C
OSC
3
FIL
A
4
FIL
B
5
FIL
C
6
FIL
D
7
V
REF
8
V
DD
V
M3
9
D
2
FB
D
D
1
V
M4
C
2
FB
C
C
1
EXP0
EXP1
EXP2
RESET
OSC
OSC
SCLK
SDATA
LATCH
EXT
FB
FB
EXT
EXP3
PGND
V
V
OUT
V
B
B
A
A
38
37
IN
36
35
34
33
D
32
β
31
2
30
B
29
1
28
M2
27
2
26
A
25
1
24
M1
23
α
22
21
20
Data Sheet S15974EJ1V0DS
3
1. PIN FUNCTIONS
Pin No. Symbol Function
1 LGND Control circuit GND pin
2C
3FIL
4FIL
5FIL
6FIL
7V
8V
9V
10 D
11 FB
12 D
13 V
14 C
15 FB
16 C
OSC
A
B
C
D
REF
DD
M3
2
D
1
M4
2
C
1
17 EXP0 Output monitor pin (open drain)
18 EXP1 Output monitor pin (open drain)
19 EXP2 Output monitor pin (open drain)
20 PGND Power circuit GND pin
21 EXP3 Output monitor pin (open drain)
22 EXT
23 V
24 A
25 FB
26 A
27 V
28 B
29 FB
30 B
31 EXT
32 V
α
M1
1
A
2
M2
1
B
2
β
D
33 LATCH Latch signal input pin
34 SDATA Serial data input pin
35 SCLK Serial clock input pin
36 OSC
37 OSC
IN
OUT
38 RESET Reset signal output pin
Chopping capacitor connection pin
α
1-ch filter capacitor connection pin (1000 pF TYP.)
α
2-ch filter capacitor connection pin (1000 pF TYP.)
β
1-ch filter capacitor connection pin (1000 pF TYP.)
β
2-ch filter capacitor connection pin (1000 pF TYP.)
Reference voltage input pin (250 mV TYP.)
Control circuit supply voltage input pin
Output circuit supply voltage input pin
β
2-ch output pin
β
2-ch sense resistor connection pin
β
2-ch output pin
Output circuit supply voltage connection pin
β
1-ch output pin
β
1-ch sense resistor connection pin
β
1-ch output pin
Logic circuit monitor pin
Output circuit supply voltage input pin
α
1-ch output pin
α
1-ch sense resistor connection pin
α
1-ch output pin
Output circuit supply voltage input pin
α
2-ch output pin
α
2-ch sense resistor connection pin
α
2-ch output pin
Logic circuit monitor pin
Video sync signal input pin
Original oscillation input pin (4 MHz TYP.)
Original oscillation output pin
µµµµ
PD16878
4
Data Sheet S15974EJ1V0DS
2. I/O PIN EQUIVALENT CIRCUIT
Pin Name Equivalent Circuit Pin Name Equivalent Circuit
DD
V
DD
LATCH
SDATA
SCLK
Pad
V
OSC
IN
Pad
RESET
Pull-down
resistor (125 Ω)
V
DD
V
DD
DD
V
µµµµ
PD16878
OSC
EXT
EXT
V
REF
α
β
OUT
Pad
Pad
EXP0
EXP1
Pad
EXP2
EXP3
V
DD
FIL
A
FIL
FIL
FIL
B
C
D
Pad
V
M
DD
V
Buffer
A1, A
B1, B
C1, C
D1, D
2
2
2
2
Parasitic diodes
Pad
FB
Data Sheet S15974EJ1V0DS
5
3. EXAMPLE OF STANDARD CONNECTION
α
EXT
100 kΩ x 4
EXTOUT SELECTOR
: 64 kHz
OSC
250 mV
EVR : 1010
f
CPU
EXP0 EXP1EXP2 EXP3
SCLK SDATA LATCH
REF
V
D
V
OUT
OSC
EVR1 EVR2
SERIAL-PARARELLE DECODER
EVR2
PULSE GENERATER
EVR1
x2
1/N
β
EXT
+
+
β
CURRENT SET
α
+
CURRENT SET
OSC
+
FILTERFILTERFILTERFILTER
– +
M
V
– +
M
V
– +
M
V
– +
M
V
2ch
β
H BRIDGE
1ch
β
H BRIDGE
2ch
α
H BRIDGE
1ch
α
H BRIDGE
D
FIL
2
D
1
D
D
FB
C
FIL
2
C
1
C
C
FB
B
FIL
2
B
1
B
B
FB
A
FIL
2
A
1
A
1000 pF
6.8 Ω
6.8 Ω
1000 pF
µµµµ
PD16878
MOTOR 1 MOTOR 2
IN
OSC
SELECTOR
A
FB
4 MHz
M4
OSC
C
LGND
PGND
RESET
DD
VM1VM2VM3V
V
33 pF
3.3 V
6.8 Ω x 2
REGULATOR
6
Data Sheet S15974EJ1V0DS
BATTERY
4.8 to 11 V
1000 pF x 2
4. STANDARD CHARACTERISTICS CURVES
µµµµ
PD16878
1.4
PT vs. TA Characteristics I
1.2
(W)
T
1.0
125°C/W
0.8
0.6
0.4
Total Power Dissipation P
0.2
0
20 40 60–10 0
Ambient Temperature T
5
IDD vs. VDD Characteristics
4
(mA)
DD
3
2
pin Current I
DD
V
1
0
234
Control Circuit Supply Volage V
80 100 120
A
(°C)
TA = 25°C,
operating,
output open
56
DD
(V)
1
µ
0.8
( A)
MO (RESET)
0.6
MO (RESET)
vs. VM Characteristics
0.4
pin Current I
M
0.2
OFF V
0
468
Output Circuit Supply Voltage V
200
µ
( A)
150
DD (RESET)
DD (RESET)
vs. VDD Characteristics
I
100
50
pin Current at Reset State I
DD
V
0
234
Control Circuit Supply Volage V
TA = 25°C,
no load,
after reset
10 12
M
(V)
TA = 25°C,
after reset
56
DD
(V)
VIH/VDD, VIL/VDD vs. VDD Characteristics
1
(V)
0.8
DD
/V
IL
, V
0.6
DD
/V
IH
0.4
0.2
Input Voltage V
0
234
Control Circuit Supply Volage V
TA = 25°C
V
IH
IL
V
56
DD
(V)
60
µ
( A)
IL
/I
IH
40
20
0
High-level/Low-level Input Current I
Data Sheet S15974EJ1V0DS
IIH/IIL vs. VIN Characteristics
I
IH
I
IL
234
IN
Input Voltage V
(V)
TA = 25°C,
IIH: VIN = VDD,
I
IL
:
VIN = 0 V
56
7
f
OSC
150
vs. VDD Characteristics f
140
(kHz)
130
OSC
120
110
Chopping Frequency f
100
TA = 25°C,
C
OSC
= 100 pF,
DATA: all high
6
STEP vs. VDD Characteristics
5
(kHz)
STEP
4
3
Step Frequency f
TA = 25°C,
C
OSC
= 100 pF
µµµµ
PD16878
90
23456
Control Circuit Supply Voltage V
V
REFVER
40
vs. VDD Characteristics
DD
(V)
TA = 25°C,
V
REF
= 250 mV
(mV)
30
REFVER
20
10
EVR Variable Voltage V
0
234
Control Circuit Supply Voltage V
tON, t
OFF
500
vs. VM Characteristics
56
DD
(V)
TA = 25°C,
IM = 100 mA,
C
FIL
(ns)
400
OFF
/t
ON
300
t
ON
: none
2
234
Control Circuit Supply Voltage V
I
M (MAX)
80
vs. EVR Characteristics
56
DD
(V)
TA = 25°C, VM = 6 V
(mA)
70
M (MAX)
Rs = 6.8 Ω, f
L = 25 mH/R = 100 Ω at 1 kHz
OSC
= 64 kHz,
60
50
40
30
Sine Wave Peak Output Current I
20
50 100 150 200 250 300
Reference Setting Voltage EVR (mV)
200
100
Turn-on Time, Turn-off Time t
0
468
Output Circuit Supply Voltage V
8
t
OFF
10 12
M
(V)
Data Sheet S15974EJ1V0DS
µµµµ
PD16878
5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (f
= 4-MHz EXTERNAL CLOCK INPUT)
CLK
Input data consists of serial data (8 bytes x 8 bits).
Input serial data with the LSB first, from the 1st byte to 8th byte.
(1) Initial data (2) Standard data
<1st byte> <1st byte>
Bit Data Function Setting Bit Data Function Setting
D7 1
D6 1
D5 1
D4 0 −− D4 0 −−
D3 1 or 0 EXP3 Hi-Z or L D3 1 or 0 EXP3 Hi-Z or L
D2 1 or 0 EXP2 Hi-Z or L D2 1 or 0 EXP2 Hi-Z or L
D1 1 or 0 EXP1 Hi-Z or L D1 1 or 0 EXP1 Hi-Z or L
D0 1 or 0 EXP0 Hi-Z or L D0 1 or 0 EXP0 Hi-Z or L
HEADER DATA2
HEADER DATA1
HEADER DATA0
DATA selection
Remark Hi-Z : High impedance,
L : Low level (current sink)
D7 0
D6 0
D5 0
HEADER DATA2
HEADER DATA1
HEADER DATA0
Remark Hi-Z : High impedance,
L : Low level (current sink)
DATA selection
<2nd byte> <2nd byte>
Bit Data Function Setting Bit Data Function Setting
D7 D7 1 or 0
D6 D6 1 or 0
D5 D5
D4 D4
8-bit data
input
D3 D3
D2 D2
D1 D1
D0
Note
First Point Wait
Start point wait
s to 2.04 ms
8
µ
Setting
(1 to 255)
s
µ
∆t = 8
6-bit data
input
D0
ROTATION
α
ENABLE
α
Pulse Number
α
ch CCW/CW
α
ch ON/OFF
α
ch
α
Number of
pulses in 1 VD
Setting (0 to 63)
∆n = 2 pulses
Note Input other than “0”. Note The number of pulses can be varied in 2-pulse
steps.
Note
<3rd byte> <3rd byte>
Bit Data Function Setting Bit Data Function Setting
D7 D7
D6 D6
D5 D5
D4 D4
8-bit data
input
D3 D3
D2 D2
D1 D1
D0
Note
First Point
Magnetize Wait
Start point drive
wait
s to 2.04 ms
µ
8
Setting
(1 to 255)
s
µ
∆t = 8
D0
15-bit data
Low-order
8-bit data
input
Pulse Width
α
ch pulse
α
cycle
0.25 to 8191.75 µs
Setting
(1 to 32767)
∆t = 0.25
Note Input other than “0”.
Data Sheet S15974EJ1V0DS
s
µ
9
<4th byte> <4th byte>
Bit Data Function Setting Bit Data Function Setting
D7 1 or 0 OSCSEL
Internal/external
D6 0 - - D6
D7 1 or 0 Current Set
15-bit data
α
D5 0 - - D5
D4 D4
D3 D3
5-bit data
D2 D2
input
D1 D1
Chopping
Frequency
D0
Chopping
frequency :
32 to 124 kHz
Setting
(8 to 31)
∆f = 4 kHz
Note
D0
High-order
7-bit data
input
Pulse Width
α
Note The frequency is 0 kHz if 0 to 7 is input.
<5th byte> <5th byte>
Bit Data EXT
α
D7 0 - - D7 1 or 0
D6
D5
D4
D3
D2
D1
D0
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ENABLE
ROTATION
Pulse Out
FF7
FF3
Checksum
Chopping
Note1
α
Note2
α
α
α
α
Note3
Note4
Notes 1. H level : Conducts, L level : Stops
2. H level : Reverse (CCW),
EXT
ENABLE
β
ROTATION
Pulse Out
FF7
β
FF3
β
FF2
β
FF1
β
β
Note1
Bit Data Function Setting
ROTATION
β
D6 1 or 0
Note2
β
β
D5
D4
D3
D2
6-bit data
input
ENABLE
β
Pulse Number
β
D1
D0
Note The number of pulses can be varied in 2-pulse
steps.
L level : Forward (CW)
3. H level : Normal data input,
L level : Abnormal data input
4. Not output in internal oscillation mode.
5. Select one of D0 to D6 and input “1”.
If two or more of D0 to D6 are selected,
they are positively ORed for output.
µµµµ
PD16878
set2/set1
α
ch
pulse cycle :
0.25 to 8191.75 µs
Setting
(1 to 32767)
∆t = 0.25
ch CCW/CW
β
ch ON/OFF
β
β
ch
s
µ
Number of
pulses in 1 VD
Setting (1 to 63)
∆n = 2 pulses
Note
<6th byte> <6th byte>
Bit Data Function Setting Bit Data Function Setting
D7 D7
D6 D6
4-bit data
input
D5 D5
ch
α
Current Set2
D4
D3 D3
D2 D2
4-bit data
input
D1 D1
ch
α
Current Set1
D0
α
ch Output current
setting 2
EVR : 100
to 250 mV
Setting (0 to 15)
α
ch Output current
setting 1
EVR : 100
to 250 mV
Setting (0 to 15)
Note
Note
D4
D0
15-bit data
Low-order
8-bit data
input
Pulse Width
β
Note A voltage of about double EVR is output to
the FIL pin.
10
Data Sheet S15974EJ1V0DS
β
ch pulse
cycle:
0.25 to 8191.75 µs
Setting
(1 to 32767)
∆t = 0.25
s
µ
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