NEC PD78F0058Y User Manual

PRELIMINARY PRODUCT INFORMATION

MOS INTEGRATED CIRCUIT

PD78F0058Y

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD78F0058Y is a product of the µPD780058Y Subseries in the 78K/0 Series and equivalent to the

PD780058Y with a flash memory in place of internal ROM. This device is incorporated with a flash memory which

can be programmed without being removed from the substrate.

Functions are described in detail in the following user’s manuals, which should be read when carrying out

design work.

PD780058, 780058Y Subseries User’s Manual : U12013E

78K/0 Series User’s Manual Instruction : U12326E

FEATURES

• Pin-compatible with mask ROM versions (except VPP pin)

• Flash memory : 60 Kbytes

• Internal high-speed RAM : 1024 bytes

• Internal expansion RAM : 1024 bytes

• Buffer RAM : 32 bytes

• Operable with the same power supply voltage as that of mask ROM version (V

Notes 1. The flash memory capacity can be changed with the memory size switching register (IMS).

2. The internal expansion RAM capacity can be changed with the internal expansion RAM size

switching register (IXS).

Remark For the differences between the flash memory versions and the mask ROM versions, refer to

1. DIFFERENCES BETWEEN

Note 1

Note 2

PD78F0058Y AND MASK ROM VERSIONS.

DD = 1.8 to 5.5 V)

ORDERING INFORMATION

Part Number Package Internal ROM

PD78F0058YGC-3B9

PD78F0058YGC-8BT

PD78F0058YGK-BE9

Note Note Note

80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) Flash memory 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) Flash memory 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Flash memory

Note Under planning

Caution Two types of packages are available for

For the suppliable package, consult an NEC sales representative.

The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production.

Document No. U12324EJ1V0PM00 (1st edition) Date Published April 1997 N Printed in Japan

PD78F0058YGC (refer to 6. PACKAGE DRAWINGS).

1997

PD78F0058Y

78K/0 SERIES DEVELOPMENT

The products in the 78K/0 series are listed below. The names enclosed in boxes are subseries names.

Under mass production Under development

78K/0 series

For Control

Note

µ µ µµ

µµ

PD780018Y

PD780058Y

µ µ µ µ

µ µ

Note

100 pins Low EMI noise model of the PD78078PD78075BµPD78075BY 100 pins 100 pins 100 pins 80 pins Enhanced serial I/O of the PD78054, low EMI noise model 80 pins 80 pins 64 pins 64 pins

64 pins

80 pins Basic subseries for driving FIP; Total number of display outputs: 34

PD78078µPD78078Y PD78070A PD78070AY PD780018

PD780058

PD78058F PD78058FY PD78054 PD78054Y

µ µ

PD780034 PD780034Y

PD780024 PD780024Y PD78014H64 pins Low EMI noise model of the PD78018F

PD78018F64 pins PD78018FY

µ µ

PD7801464 pins PD78014Y

PD78000164 pins

PD7800264 pins PD78002Y

PD78083

For Inverter Control

PD78096464 pins

PD780924

For Driving FIP

PD780208100 pins

PD780228100 pins PD78044H80 pins

PD78044F

Y subseries supports I

Adds timer to the PD78054 with enhanced external interface function ROM-less model of the PD78078 Enhanced serial I/O of the PD78078 with limited function

Low EMI noise model of the PD78054 Adds UART and D/A to the PD78014 with enhanced I/O Enhanced A/D of the PD780024 Enhanced serial I/O of the PD78018F, low EMI noise model

Low-voltage model (1.8 V) of the PD78014 with increased choice of ROM and RAM capacities Adds A/D and 16-bit timer to the PD78002 Adds A/D to the PD78002 Basic subseries for control applications UART provided, low-voltage (1.8 V) operation42/44 pins

Enhanced A/D of the PD780924 Inverter control circuit and UART provided, low EMI noise model

Enhanced l/O, FIP C/D of the PD78044F; Total number of display outputs: 53 Enhanced I/O, FIP C/D of the PD78044H; Total number of display outputs: 48 Adds N-ch open drain I/O to the PD78044; Total number of display outputs: 34

C bus.

µ µ

100 pins

Note Under planning

For Driving LCD

PD780308100 pins

PD78064B100 pins

PD78064 PD78064Y

Supporting IEBus

PD7809880 pins

For LV

PD78P091464 pins

PD780308Y

Enhanced SIO of the PD78064 with extended ROM and RAM Low EMI noise model of the PD78064 Subseries for driving LCD with UART provided

Adds IEBus controller to the PD78054

PWM output, LV digital code decoder, and Hsync counter provided

PD78F0058Y

Major functional differences among the Y subseries are shown below.

Function ROM Capacity Serial Interface I/O VDD MIN.

Subseries Value

Control

LCD control 3-wire/time division UART : 1ch

PD78075BY 32 K to 40 K 3-wire/2-wire/I2C : 1ch 88 1.8 V

PD78078Y 48 K to 60 K

PD78070AY – 61 2.7 V

PD780018Y 48 K to 60 K

PD780058Y 24 K to 60 K 3-wire/2-wire/I2C : 1ch 68 1.8 V

PD78058FY 48 K to 60 K 3-wire/2-wire/I2C : 1ch 69 2.7 V

PD78054Y 16 K to 60 K 3-wire/UART : 1ch 2.0 V

PD780034Y 8 K to 32 K UART : 1ch 51 1.8 V

PD780024Y I2C bus (supports multimaster) : 1ch

PD78018FY 8 K to 60 K 3-wire/2-wire/I2C : 1ch 53

PD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C : 1ch 2.7 V

PD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1ch

PD780308Y 48 K to 60 K 3-wire/2-wire/I2C : 1ch 57 2.0 V

PD78064Y 16 K to 32 K 3-wire/2-wire/I2C : 1ch

3-wire with automatic send/receive function 3-wire/UART : 1ch

3-wire with automatic send/receive function Time division UART : 1ch

C bus (supports multimaster) : 1ch

3-wire with automatic send/receive function 3-wire/time division UART : 1ch

3-wire with automatic send/receive function

3-wire : 1ch

3-wire with automatic send/receive function

3-wire : 1ch

3-wire/UART : 1ch

: 1ch

: 1ch 88

: 1ch

Remark The functions, except for the serial interface are the same as those of subseries without Y.

OVERVIEW OF FUNCTION

Item Function

Internal Flash memory 60 Kbytes memory

Memory space 64 Kbytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle On-chip instruction execution time cycle modification function

Instruction set • 16-bit operation

I/O ports Total : 68

A/D converter • 8-bit resolution × 8 channels D/A converter • 8-bit resolution × 2 channels

Serial interface • 3-wired serial I/O/2-wire serial I/O/I

Timer • 16-bit timer/event counter : 1 channel

Timer output 3 (14-bit PWM output capable: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (main system clock: at 5.0-MHz operation) Vectored-interrupt Maskable Internal : 13, External : 7 source Non-maskable Internal : 1

Test input Internal : 1, External : 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

High-speed RAM 1024 bytes Expansion RAM 1024 bytes Buffer RAM 32 bytes

When main system 0.4 clock selected

When subsystem 122 clock selected

• Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, boolean operation)

• BCD correction, etc.

• CMOS input : 2

• CMOS I/O : 62

• N-ch open drain I/O : 4

• 3-wired serial I/O mode (MAX. 32-byte on-chip automatic send/receive function) : 1 channel

• 3-wired serial I/O/UART mode (on-chip time division transfer function) selectable : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel

5.0 MHz (main system clock: at 5.0-MHz operation)

32.768 kHz (subsystem clock: at 32.768-kHz operation)

Software 1

• 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

Notes 1. The flash memory capacity can be changed with the memory size switching register (IMS).

2. The internal expansion RAM capacity can be changed with the internal expansion RAM size

switching register (IXS).

3. Under planning

Note 1

Note 2

s/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0-MHz operation)

s (at 32.768-kHz operation)

C bus mode selectable : 1 channel

Note 3

PD78F0058Y

PIN CONFIGURATION (Top View)

• 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

PD78F0058YGC-3B9

• 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

PD78F0058YGC-8BT

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD78F0058YGK-BE9

Note

PD78F0058Y

P15/ANI5 P16/ANI6 P17/ANI7

AV P130/ANO0 P131/ANO1

REF1

P70/SI2/RxD0

P71/SO2/TxD0

P72/SCK2/ASCK

P20/SI1

P21/SO1

P22/SCK1

P23/STB/TxD1

P24/BUSY/RxD1

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

P40/AD0 P41/AD1

P14/ANI4

P13/ANI3

P12/ANI2

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1 2 3

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P11/ANI1

P10/ANI0

REF0

VDD0

XT1/P07

XT2

VPPX1X2V

DD1

VSS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1/TI01

P00/INTP0/TI00

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR

P42/AD2

Note Under planning

Cautions 1. Connect the V

2. Connect the AV

Remark When the

PD78F0058Y is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to V

DD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is

recommended.

SS1

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

PP pin directly to VSS0 in normal operation mode

SS pin to VSS0.

P55/A13

P56/A14

P57/A15

P60

P61

P62

P63

P64/RD

PD78F0058Y

A8 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe

REF0, 1 : Analog Reference Voltage

SS : Analog Ground

AV BUSY : Busy BUZ : Buzzer Clock INTP0 to INTP6

: Interrupt from Peripherals P00 to P05, P07: Port0 P10 to P17 : Port1 P20 to P27 : Port2 P30 to P37 : Port3 P40 to P47 : Port4 P50 to P57 : Port5 P60 to P67 : Port6 P70 to P72 : Port7 P120 to P127 : Port12 P130, P131 : Port13 PCL : Programmable Clock

RD : Read Strobe RESET : Reset RTP0 to RTP7 : Real-Time Output Port RxD0, RxD1 : Receive Data SB0, SB1 : Serial Bus SCK0 to SCK2 : Serial Clock SCL : Serial Clock SDA0, SDA1 : Serial Data SI0 to SI2 : Serial Input SO0 to SO2 : Serial Output STB : Strobe TI00, TI01 : Timer Input TI1, TI2 : Timer Input TO0 to TO2 : Timer Output TxD0, TxD1 : Transmit Data

DD0, VDD1 : Power Supply

PP : Programming Power Supply

SS0, VSS1 : Ground

V WAIT : Wait WR : Write Strobe X1, X2 : Crystal (Main system Clock) XT1, XT2 : Crystal (Subsystem Clock)

BLOCK DIAGRAM

PD78F0058Y

TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/TxD1/P23

BUSY/RxD1/P24

STB/TxD1/P23

SI2/RxD0/P70

SO2/TxD0/P71

SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

REF0

ANO0/P130,

ANO1/P131

REF1

INTP0/P00 to

INTP5/P05

16-bit TIMER/ EVENT COUNTER

8-bit TIMER/ EVENT COUNTER 1

8-bit TIMER/ EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL INTERFACE 0

SERIAL INTERFACE 1

SERIAL INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

78K/0

CPU CORE

RAM

2048 Bytes

FLASH MEMORY 60 K Bytes

PORT0

P01 to P05 P07

P00

PORT1

P10 to P17

PORT2 P20 to P27

PORT3

PORT4

P30 to P37

P40 to P47

PORT5 P50 to P57

PORT6 P60 to P67

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

P70 to P72

P120 to P127

P130,P131

RTP0/P120 to RTP7/P127

AD0/P40 to AD7/P47 A8/P50 to

EXTERNAL

ACCESS

A15/P57 RD/P64

WR/P65 WAIT/P66 ASTB/P67

BUZ/P36

PCL/P35

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

RESET

SYSTEM

CONTROL

DD0

SS0

V V

DD1

SS1

X1 X2 XT1/P07 XT2

PD78F0058Y

CONTENTS

1. DIFFERENCES BETWEEN µPD78F0058Y AND MASK ROM VERSIONS .................................... 9

2. PIN FUNCTIONS............................................................................................................................... 10

2.1 Port Pins................................................................................................................................................... 10

2.2 Non-Port Pins .......................................................................................................................................... 12

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 14

3. MEMORY SIZE SWITCHING REGISTER (IMS)............................................................................... 18

4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) .............................................. 19

5. FLASH MEMORY PROGRAMMING ................................................................................................ 20

5.1 Selection of Transmission Method ........................................................................................................ 20

5.2 Function of Flash Memory Programming ............................................................................................. 21

5.3 Connection of Flashpro II....................................................................................................................... 22

6. PACKAGE DRAWINGS .................................................................................................................... 24

APPENDIX A. DEVELOPMENT TOOLS................................................................................................ 27

APPENDIX B. RELATED DOCUMENTS ............................................................................................... 29

PD78F0058Y

1. DIFFERENCES BETWEEN µPD78F0058Y AND MASK ROM VERSIONS

The µPD78F0058Y is a product provided with a flash memory which enables on-board reading, erasing, and

rewriting of programs with device mounted on target system. The functions of the functions specified for flash memory and mask option of P60 to P63 pins) can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS) and internal expansion RAM size switching register (IXS).

Table 1-1 shows the differences between the flash memory version (

versions (

PD780053Y, 780054Y, 780055Y, 780056Y, and 780058Y).

PD78F0058Y) and the mask ROM

PD78F0058 (except the

Table 1-1. Differences between

Item Internal ROM structure Flash memory Mask ROM Internal ROM capacity 60 Kbytes

Internal expansion RAM capacity 1024 bytes

Internal ROM capacity changeable/not Changeable changeable with memory size switching register (IMS)

Internal expansion RAM capacity Changeable changeable/not changeable with internal expansion RAM size switching register (IXS)

IC pin Not provided Provided VPP pin Provided Not provided P60 to P63 pin mask option with internal Not provided Provided

pull-up resistors

PD78F0058Y and Mask ROM Versions

PD78F0058Y Mask ROM Versions

PD780053Y : 24 Kbytes

PD780054Y : 32 Kbytes

PD780055Y : 40 Kbytes

PD780056Y : 48 Kbytes

PD780058Y : 60 Kbytes

PD780053Y : None

PD780054Y : None

PD780055Y : None

PD780056Y : None

PD780058Y : 1024 bytes

Note 1

Note 2

Not changeable

Notes 1. Flash memory is set to 60 Kbytes by RESET input

2. Internal expansion RAM is set to 1024 bytes by RESET input.

Caution The noise resistance and noise radiation differ between flash memory versions and mask

ROM versions. When considering the replacement of flash memory versions with mask ROM versions in the process from trial manufacturing to mass production, adequate evaluation should be carried out using CS products (not ES products) of mask ROM versions.

Remark Only the

PD780058Y and 78F0058Y are provided with IXS.

PD78F0058Y

2. PIN FUNCTIONS

2.1 Port Pins (1/2)

Pin Name I/O Funciton After Reset Alternate Function

P00 P01 P02 P03 P04 P05

Note 1

P07 P10 to P17

P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37

Input I/O

I/O

Port 0 7-bit input/output port

Port 1 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Port 2 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Port 3 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Input only Input/output can be specified bit-wise.

When used as an input port, an internal pull-up resistor can be connected by software.

Input only

Note 2

Input Input

Input

INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7

SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL TO0 TO1 TO2 TI1 TI2 PCL BUZ –

Notes 1. When using P07/XT1 pin as an input port, set 1 to the bit 6 (FRC) of the processor clock control

2. When using P10/ANI0 to P17/ANI7 pins as analog inputs of A/D converter, the internal pull-up resistor is automatically set unused.

PD78F0058Y

2.1 Port Pins (2/2)

Pin Name I/O Funciton After Reset Alternate Function

P40 to P47

P50 to P57

P60 P61 P62 P63 P64 P65 P66 P67 P70

P71

P72

P120 to P127

P130, P131

I/O

Port 4 8-bit input/output port Input/output can be specified in 8-bit units. When used as an input port, an internal pull-up resistor can be connected by software. Test input flag (KRIF) is set to 1 by the falling edge detection.

Port 5 8-bit input/output port LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Port 6 8-bit input/output port Input/output can be specified bit-wise.

Port 7 3-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Port 12 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

Port 13 2-bit input/output port Input/output can be specified bit-wise. When used as an input port, an internal pull-up resistor can be connected by software.

N-ch open drain input/output port. LED can be driven directly.

When used as an input port, an internal pull-up resistor can be connected by software.

Input

AD0 to AD7

A8 to A15

–

RD WR WAIT ASTB SI2/RxD0

SO2/TxD0

SCK2/ASCK

RTP0 to RTP7

ANO0, ANO1

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