2.2.9P90 to P97 (Port 9).......................................................................................................................42
2.2.10S0 to S14......................................................................................................................................42
2.2.11COM0 to COM3............................................................................................................................42
4-3Block Diagram of P00 to P03........................................................................................................................81
4-4Block Diagram of P10 and P11.....................................................................................................................82
4-5Block Diagram of P20....................................................................................................................................83
4-6Block Diagram of P21 and P26.....................................................................................................................84
4-7Block Diagram of P22....................................................................................................................................85
4-8Block Diagram of P23....................................................................................................................................86
4-9Block Diagram of P24....................................................................................................................................87
4-10Block Diagram of P25....................................................................................................................................88
4-11Block Diagram of P30....................................................................................................................................89
4-12Block Diagram of P31 to P33........................................................................................................................90
4-13Block Diagram of P50 to P53........................................................................................................................91
4-14Block Diagram of Port 6................................................................................................................................92
4-15Block Diagram of P70 to P72........................................................................................................................93
4-16Block Diagram of P80, P81...........................................................................................................................94
4-17Block Diagram of P90 to P97........................................................................................................................95
4-18Format of Port Mode Register.......................................................................................................................97
4-19Format of Pull-Up Resistor Option Register 0...............................................................................................98
4-20Format of Pull-Up Resistor Option Register B2.............................................................................................99
4-21Format of Pull-Up Resistor Option Register B3.............................................................................................99
18User’s Manual U15075EJ1V0UM00
LIST OF FIGURES (2/5)
Figure No.TitlePage
4-22Format of Pull-Up Resistor Option Register B7...........................................................................................100
4-23Format of Pull-Up Resistor Option Register B8...........................................................................................100
4-24Format of Pull-Up Resistor Option Register B9...........................................................................................101
5-1Block Diagram of Clock Generator..............................................................................................................104
5-2Format of Processor Clock Control Register...............................................................................................105
5-3Format of Suboscillation Mode Register.....................................................................................................106
5-4Format of Subclock Control Register..........................................................................................................107
5-5External Circuit of Main System Clock Oscillator........................................................................................108
5-6External Circuit of Subsystem Clock Oscillator...........................................................................................109
5-7Examples of Incorrect Resonator Connection.............................................................................................110
5-8Switching Between System Clock and CPU Clock......................................................................................114
6-1Block Diagram of 16-Bit Timer.....................................................................................................................117
6-2Format of 16-Bit Timer Mode Control Register 90.......................................................................................120
6-3Format of Buzzer Output Control Register 90.............................................................................................121
6-4Format of Port Mode Register 2..................................................................................................................122
6-5Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation......................................123
6-6Timing of Timer Interrupt Operation............................................................................................................124
6-7Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation.........................................125
6-12Settings of Buzzer Output Control Register 90 for Buzzer Output Operation..............................................128
7-1Block Diagram of Timer 50..........................................................................................................................133
7-2Block Diagram of Timer 60..........................................................................................................................134
7-3Block Diagram of Output Controller (Timer 60)...........................................................................................135
7-4Format of 8-Bit Timer Mode Control Register 50.........................................................................................139
7-5Format of 8-Bit Timer Mode Control Register 60.........................................................................................141
7-6Format of Carrier Generator Output Control Register 60............................................................................142
7-7Format of Port Mode Register 3..................................................................................................................142
7-8Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)...............................................145
7-9Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H)...............................145
7-10Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)...............................146
7-11Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N
<
M)).....146
7-12Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N
>
M)).....147
7-13Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is
Selected for Timer 50 Count Clock)............................................................................................................148
7-14Timing of Operation of External Event Counter with 8-Bit Resolution........................................................150
7-15Timing of Square-Wave Output with 8-Bit Resolution.................................................................................152
User’s Manual U15075EJ1V0UM0019
LIST OF FIGURES (3/5)
Figure No.TitlePage
7-16Timing of Interval Timer Operation with 16-Bit Resolution..........................................................................155
7-17Timing of External Event Counter Operation with 16-Bit Resolution...........................................................157
7-18Timing of Square-Wave Output with 16-Bit Resolution...............................................................................159
7-19Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M
>
N))........................................161
7-20Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M
<
N),
Phases of Carrier Clock and NRZ60 Are Asynchronous)...........................................................................162
12-113-Wire Serial I/O Mode Timing....................................................................................................................240
13-1Block Diagram of LCD Controller/Driver......................................................................................................248
13-2Format of LCD Display Mode Register 0.....................................................................................................250
13-3Format of LCD Clock Control Register 0.....................................................................................................251
13-4Format of LCD Voltage Amplification Control Register 0............................................................................252
13-5Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
14-12Interrupt Request Acknowledgment Program Algorithm.............................................................................274
14-13Interrupt Request Acknowledgment Timing (Example: MOV A, r)..............................................................275
14-14Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is
Generated in Final Clock Under Execution)................................................................................................275
14-15Example of Multiple Interrupts.....................................................................................................................276
15-1Format of Oscillation Stabilization Time Select Register.............................................................................280
15-2Releasing HALT Mode by Interrupt.............................................................................................................282
15-3Releasing HALT Mode by RESET Input.....................................................................................................283
15-4Releasing STOP Mode by Interrupt............................................................................................................285
15-5Releasing STOP Mode by RESET Input.....................................................................................................286
16-1Block Diagram of Reset Function................................................................................................................287
16-2Reset Timing by RESET Input....................................................................................................................288
16-3Reset Timing by Overflow in Watchdog Timer............................................................................................288
16-4Reset Timing by RESET Input in STOP Mode............................................................................................288
2-1Types of Pin Input/Output Circuits.................................................................................................................44
3-1Internal ROM Capacity..................................................................................................................................53
3-4Special Function Register List.......................................................................................................................66
4-2Configuration of Port.....................................................................................................................................80
4-3Port Mode Register and Output Latch Settings When Using Alternate Functions........................................98
5-1Configuration of Clock Generator................................................................................................................103
5-2Maximum Time Required for Switching CPU Clock....................................................................................113
6-2Interval Time of 16-Bit Timer.......................................................................................................................123
6-3Settings of Capture Edge............................................................................................................................126
6-4Buzzer Frequency of 16-Bit Timer...............................................................................................................128
7-3Interval Time of Timer 50............................................................................................................................144
7-4Interval Time of Timer 60............................................................................................................................144
8-3Interval Time of Interval Timer.....................................................................................................................174
9-5Interval Time of Interval Timer.....................................................................................................................182
10-1Configuration of 8-Bit A/D Converter...........................................................................................................183
11-1Configuration of 10-Bit A/D Converter.........................................................................................................197
User’s Manual U15075EJ1V0UM0023
LIST OF TABLES (2/2)
Table No.TitlePage
12-1Configuration of Serial Interface 20.............................................................................................................211
15-4Operation After Releasing STOP Mode......................................................................................................286
16-1Hardware Status After Reset.......................................................................................................................289
17-1Differences Between
µ
PD78F9436, 78F9456 and Mask ROM Versions....................................................291
17-3Functions of Flash Memory Programming..................................................................................................293
17-4Example of Settings for PG-FP3.................................................................................................................295
18-1Selection of Mask Option for Pins...............................................................................................................297
19-1Operand Identifiers and Description Methods.............................................................................................299
24User’s Manual U15075EJ1V0UM00
[MEMO]
User’s Manual U15075EJ1V0UM0025
CHAPTER 1 GENERAL
1.1 Features
•ROM and RAM capacities
ItemData Memory
Part Number
Program Memory
(ROM)
Internal High-Speed
RAM
LCD Display RAM
µ
PD789425, 7894358 KB
µ
PD789426, 789436
Mask ROM
16 KB
µ
PD78F9436Flash memory16 KB
5 bytes
µ
PD789445, 78945512 KB
µ
PD789446, 789456
Mask ROM
µ
PD78F9456Flash memory
16 KB
512 bytes
15 bytes
•Minimum instruction execution time can be changed from high-speed (0.4
µ
s: @ 5.0 MHz operation with main
system clock) to ultra-low-speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
•I/O ports:40 (
µ
PD789426, 789436 Subseries)
30 (
µ
PD789446, 789456 Subseries)
•Timer: 5 channels
•
16-bit timer:1 channel
•
8-bit timer:2 channels
•
Watch timer:1 channel
•
Watchdog timer: 1 channel
•A/D converter:
8-bit resolution: 6 channels (
µ
PD789426, 789446 Subseries)
10-bit resolution: 6 channels (
µ
PD789436, 789456 Subseries)
•Serial interface: 1 channel
•LCD controller/driver
Segment signals: 5, common signals: 4 (
µ
PD789426, 789436 Subseries)
Segment signals: 15, common signals: 4 (
µ
PD789446, 789456 Subseries)
•Vectored interrupt sources: 15
•Power supply voltage: V
DD
= 1.8 to 5.5 V
•Operating ambient temperature: T
A
= –40 to +85
°
C
1.2 Applications
Portable audio, cameras, healthcare equipment, etc.
CHAPTER 1 GENERAL
26User’s Manual U15075EJ1V0UM00
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD789425GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789426GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789435GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789436GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789445GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789446GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789455GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD789456GK-
×××
-9ET64-pin plastic TQFP (12
×
12 mm)Mask ROM
µ
PD78F9436GK-9ET64-pin plastic TQFP (12
×
12 mm)Flash memory
µ
PD78F9456GK-9ET64-pin plastic TQFP (12
×
12 mm)Flash memory
Remark
×××
indicates ROM code suffix.
CHAPTER 1 GENERAL
User’s Manual U15075EJ1V0UM00
27
1.4 Pin Configuration (Top View)
1.4.1 Pin configuration of
µ
µµ
µ
PD789426, 789436 Subseries (Top view)
64-pin plastic TQFP (fine pitch) (12
×
12)
µ
PD789425GK-
×××
-9ET
µ
PD789426GK-
×××
-9ET
µ
PD789435GK-
×××
-9ET
µ
PD789436GK-
×××
-9ET
µ
PD78F9436GK-9ET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
646362616059585756555453525150
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
IC(V
PP
)
XT1
XT2
V
DD
V
SS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3
32
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
P90
P91
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
AV
DD
P72
P71
P70
P81
P80
P97
P96
P95
P94
P93
P92
P20
P21/BZO90
P22/SS20
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO90
P30/INTP0/CPT90
P31/INTP1/TO50/TMI60
P32/INTP2/TO60
P33/INTP3/TO61
P10
P11
AV
SS
P60/ANI0
P61/ANI1
Cautions1.Connect the IC (Internally Connected) pin directly to V
SS
.
2.Connect the AV
DD
pin to V
DD
.
3.Connect the AV
SS
pin to V
SS
.
Remark
The parenthesized values apply to the
µ
PD78F9436.
CHAPTER 1 GENERAL
28
User’s Manual U15075EJ1V0UM00
1.4.2 Pin configuration of
µ
µµ
µ
PD789446, 789456 Subseries (Top view)
64-pin plastic TQFP (fine pitch) (12
×
12)
µ
PD789445GK-
×××
-9ET
µ
PD789446GK-
×××
-9ET
µ
PD789455GK-
×××
-9ET
µ
PD789456GK-
×××
-9ET
µ
PD78F9456GK-9ET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
646362616059585756555453525150
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
IC(V
PP
)
XT1
XT2
V
DD
V
SS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3
32
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
AV
DD
P72
P71
P70
S14
S13
S12
S11
S10
S9
S8
S7
P20
P21/BZO90
P22/SS20
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO90
P30/INTP0/CPT90
P31/INTP1/TO50/TMI60
P32/INTP2/TO60
P33/INTP3/TO61
P10
P11
AV
SS
P60/ANI0
P61/ANI1
Cautions1.Connect the IC (Internally Connected) pin directly to V
SS
.
2.Connect the AV
DD
pin to V
DD
.
3.Connect the AV
SS
pin to V
SS
.
Remark
The parenthesized values apply to the
µ
PD78F9456.
CHAPTER 1 GENERAL
User’s Manual U15075EJ1V0UM00
29
ANI0 to ANI5:Analog inputP90 to P97
Note 1
:Port 9
ASCK20:Asynchronous serial inputRESET:Reset
AV
DD
:Analog power supplyRxD20:Receive data
AV
SS
:Analog groundSS20:Serial chip select
BZO90:Buzzer outputS0 to S4, S5 to S14
Note 2
:Segment output
CAPH, CAPL:LCD power supply capacitance controlSCK20:Serial clock
COM0 to COM3:Common outputSI20:Serial input
CPT90:Capture trigger inputSO20:Serial output
IC:Internally connectedTMI60:Timer input
INTP0 to INTP3:External interrupt inputTO90, TO50, TO60,
KR0 to KR3:Key returnTO61:Timer output
P00 to P03:Port 0TxD20:Transmit data
P10, P11:Port 1V
DD
:Power supply
P20 to P26:Port 2V
LC0
to V
LC2
:LCD power supply
P30 to P33:Port 3V
PP
:Programming power supply
P50 to P53:Port 5V
SS
:Ground
P60 to P65:Port 6X1, X2:Crystal (main system clock)
P70 to P72:Port 7XT1, XT2:Crystal (subsystem clock)
P80, P81
Note 1
:Port 8
Notes1.
µ
PD789426, 789436 Subseries only
2.
µ
PD789446, 789456 Subseries only
CHAPTER 1 GENERAL
30
User’s Manual U15075EJ1V0UM00
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under development
Products in mass production
PD789014
Small-scale package, general-purpose applications
78K/0S
Series
28-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
LCD drive
Inverter control
44-pin
PD789842
On-chip inverter controller and UART
ASSP
80-pin
80-pin
PD789446
PD789456
PD789436
PD789417A
PD789407A
PD789426
PD789306
PD789316
PD789426 with enhanced A/D
PD789446 with enhanced A/D converter
A/D converter and resistance division type LCD (28 × 4)
A/D converter and on-chip voltage booster type LCD (15 × 4)
PD789407A with enhanced A/D converter
A/D converter and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
On-chip voltage booster type LCD (24 × 4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789146
PD789156
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789167 with enhanced A/D converter
PD789104A with enhanced timer
PD789124A with enhanced A/D converter
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter
PD789026 with added A/D converter and multiplier
PD789104A with added EEPROM
TM
PD789146 with enhanced A/D converter
PD789177Y
PD789167Y
Y Subseries products support SMB.
Dot LCD drive
20-pin
PD789860
PD789840
44-pin
44-pin
PD789800
20-pin
PD789861
For keyless entry, on-chip POC and key return circuit
For keypad, on-chip POC
For PC keyboard, on-chip USB function
RC oscillation version of the PD789860
52-pin
52-pin
For remote controller, with SIO and resistance division type LCD
For remote controller, with A/D converter and on-chip voltage booster type LCD
88-pin
PD789830
PD789835
144-pin
Segments: 40, commons: 16
Segment/common outputs: 96
42-/44-pin
44-pin
PD789046
PD789074
PD789026
30-pin
PD789026 with enhanced timer
VFD drive
52-pin
PD789871
Total display outputs: 25
PD789488
A/D converter and on-chip voltage booster type LCD (28 × 4)
80-pin
PD789488 with added remote control receiver and resistance division type LCD
80-pin
PD789327
PD78980364-pin
PD789467
PD789477
For PC keyboard, on-chip USB HUB function
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
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