Watch timerInterrupt requests are generated at 0.5-second intervals. (A watch clock oscillator is
Clock outputSelectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
PWM outputs12-bit resolution × 2 channels
Serial interfaceUART/IOE (3-wire serial I/O):2 channels (on-chip baud rate generator)
APPENDIX A DEVELOPMENT TOOLS ..........................................................................................91
APPENDIX B RELATED DOCUMENTS .........................................................................................94
7Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
1. DIFFERENCES BETWEEN µPD784908 SUBSERIES PRODUCTS
The only difference between the µPD784907 and µPD784908 is their internal memory capacities.
The µPD78P4908 is produced by replacing the mask ROM in the µPD784907 or µPD784908 with 128-Kbyte one-
time PROM. Table 1-1 shows the differences between these products.
µ
Table 1-1. Differences between the
PD784908 Subseries Products
Part Number
Item
Internal ROM96 K (mask ROM)128 K (mask ROM)128 K (one-time PROM)
Internal RAM3,584 bytes4,352 bytes
RegulatorProvidedNone
Power supply voltageVDD = 4.0 to 5.5 VVDD = 4.5 to 5.5 V
(Main clock: fXX = 12.58 MHz, internal system clock = fXX,(Main clock: fXX = 12.58 MHz,
fCYK = 79 ns)internal system clock = fXX,
VDD = 3.5 to 5.5 VfCYK = 79 ns)
(other than above, fCYK = 159 ns)VDD = 4.0 to 5.5 V
Electrical specificationsRefer to the data sheet of each product.
µ
PD784907
µ
PD784908
µ
PD78P4908
(other than above,
fCYK = 159 ns)
8
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
2. MAJOR DIFFERENCES BETWEEN µPD784908 AND µPD78098 SUBSERIES
External77
External extended functionProvided (up to 1 Mbyte)None
IEBus controllerIncorporated (simplified)Incorporated (complete hardware)
Power supply voltage• Mask ROM versionVDD = 2.7 to 6.0 V
VDD = 4.0 to 5.5 V
(Main clock: fXX = 12.58 MHz,
internal system clock = fXX, fCYK = 79 ns)
VDD = 3.5 to 5.5 V
(other than above, fCYK = 159 ns)
• PROM version
VDD = 4.5 to 5.5 V
(Main clock: fXX = 12.58 MHz,
internal system clock = fXX, fCYK = 79 ns)
VDD = 4.0 to 5.5 V
(other than above, fCYK = 159 ns)
2. Connect the REGOFF pin directly to VSS (select regulator operation).
3. Connect the REGC pin to V
10
SS
V
VDD
P51/A9
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
SS.
SS via a capacitor of the order of 1
Data Sheet U11680EJ2V0DS00
P53/A11
P52/A10
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
µ
F.
P43/AD3
µ
PD784907, 784908
A8 to A19:Address bus
AD0 to AD7:Address/data bus
ANI0 to ANI7:Analog input
ASCK, ASCK2: Asynchronous serial clock
ASTB:Address strobe
DD:Analog power supply
AV
AVREF1:Reference voltage
AVSS:Analog ground
CI:Clock input
CLKOUT:Clock output
HLDAK:Hold acknowledge
HLDRQ:Hold request
INTP0 to INTP5: Interrupt from peripherals
NMI:Non-maskable interrupt
P00 to P07:Port 0
P10 to P17:Port 1
P20 to P27:Port 2
P30 to P37:Port 3
P40 to P47:Port 4
P50 to P57:Port 5
P60 to P67:Port 6
P70 to P77:Port 7
P90 to P97:Port 9
P100 to P107:Port 10
PWM0, PWM1: Pulse width modulation output
RD:Read strobe
REFRQ:Refresh request
REGC:Regulator capacitance
REGOFF:Regulator off
RESET:Reset
RX:IEBus receive data
XD, RXD2:Receive data
R
SCK0 to SCK3: Serial clock
SI0 to SI3:Serial input
SO0 to SO3:Serial output
TEST:Test
TO0 to TO3:Timer output
TX:IEBus transmit data
XD, TXD2:Transmit data
T
VDD:Power supply
VSS:Ground
WAIT:Wait
WR:Write strobe
X1, X2:Crystal (main system clock)
XT1, XT2:Crystal (watch)
11Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK))
Front panelPD784908
Remote-controll
FIP
µ
TM
FIP
controller/driver
µ
signal reception
circuit
PC2800A, etc.
Key
matrix
PD16312, etc.
Interrupt input
SIO with automatic
transmission/reception
function
LED
display
Audio control
circuit
Electronic
volume
EEPROM
TM
3-wire serial I/O
µ
General-purpose
port
3-wire serial I/O
IEBus controller
REGOFF
REGC
Cassette deck
unit
Tuner pack
IEBus
driver/
receiver
IEBus
CD unit
CD changer,
one CD, etc.
DSP unit
TV unit
12
Data Sheet U11680EJ2V0DS00
5. BLOCK DIAGRAM
µ
PD784907, 784908
NMI
INTP0 to INTP5
INTP3
TO0
TO1
INTP0
INTP1
INTP2/CI
TO2
TO3
P00 to P03
P04 to P07
PWM0
PWM1
Programmable
interrupt controller
Timer/counter 0
(16 bits)
Timer/counter 1
(16 bits)
Timer/counter 2
(16 bits)
Timer 3
(16 bits)
Real-time output
port
PWM
78K/IV
CPU core
RAM
ROM
UART/IOE2
Baud-rate
generator
UART/IOE1
Baud-rate
generator
Clocked serial
interface
Clocked serial
interface 3
Clock output
Bus interface
RxD/SI1
TxD/SO1
ASCK/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SCK0
SO0
SI0
SCK3
SO3
SI3
ASTB/CLKOUT
AD0 to AD7
A8 to A15
A16 to A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
ANI0 to ANI7
AV
DD
AV
REF1
AV
INTP5
TX
RX
RESET
TEST
X1
X2
REGC
REGOFF
V
V
XT1
XT2
SS
DD
SS
A/D converter
IEBus controller
System control
(regulator)
Watch timer
Watchdog timer
Remark The internal ROM and RAM capacities differ depending on the product.
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 9
Port 10
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P90 to P97
P100 to P107
13Data Sheet U11680EJ2V0DS00
6. PIN FUNCTIONS
6.1 Port Pins (1/2)
Pin NameI/OAlternate FunctionFunction
P00 to P07I/O—Port 0 (P0):
• 8-bit I/O port.
• Can be used as a real-time output port (4 bits × 2).
• Input and output can be specified by 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• Can drive transistors.
P10I/O—
P11—
P12ASCK2/SCK2
P13RxD2/SI2
P14TxD2/SO2
P15 to P17—
P20InputNMI
P21INTP0
P22INTP1
P23INTP2/CI
P24INTP3
P25INTP4/ASCK/SCK1
P26INTP5
P27SI0
P30I/ORxD/SI1
P31TxD/SO1
P32SCK0
P33SO0
P34 to P37TO0 to TO3
P40 to P47I/OAD0 to AD7Port 4 (P4):
P50 to P57I/OA8 to A15Port 5 (P5):
Port 1 (P1):
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• Can drive LEDs.
Port 2 (P2):
• 8-bit input port.
• P20 does not function as a general-purpose port (non-maskable interrupt).
However, the input level can be checked by an interrupt service routine.
• The use of on-chip pull-up resistors can be specified by software for pins
P22 to P27 (in 6-bit units).
• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by a
CSIM1 specification.
Port 3 (P3):
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• The use of the N-ch open drain can be specified for pins P32 and P33.
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• Can drive LEDs.
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• Can drive LEDs.
µ
PD784907, 784908
14
Data Sheet U11680EJ2V0DS00
6.1 Port Pins (2/2)
Pin NameI/OAlternate FunctionFunction
P60 to P63I/OA16 to A19
P64RD
P65WR
P66WAIT/HLDRQ
P67REFRQ/HLDAK
P70 to P77I/OANI0 to ANI7Port 7 (P7):
P90 to P97I/O—Port 9 (P9):
P100 toI/O—
P104
P105SCK3
P106SI3
P107SO3
Port 6 (P6):
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Port 10 (P10):
• 8-bit I/O port.
• Input and output can be specified in 1-bit units.
• The use of on-chip pull-up resistors can be simultaneously specified by
software for all pins in input mode.
• The use of the N-ch open drain can be specified for pins P105 and P107.
µ
PD784907, 784908
15Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
6.2 Non-Port Pins (1/2)
Pin NameI/OAlternate FunctionFunction
TO0 to TO3OutputP34 to P37Timer output
CIInputP23/INTP2Input of a count clock for timer/counter 2
RxDInputP30/SI1Serial data input (UART0)
RxD2P13/SI2Serial data input (UART2)
TxDOutputP31/SO1Serial data output (UART0)
TxD2P14/SO2Serial data output (UART2)
ASCKInputP25/INTP4/SCK1Baud rate clock input (UART0)
ASCK2P12/SCK2Baud rate clock input (UART2)
SI0InputP27Serial data input (3-wire serial I/O 0)
SI1P30/RxDSerial data input (3-wire serial I/O 1)
SI2P13/RxD2Serial data input (3-wire serial I/O 2)
SI3P106Serial data input (3-wire serial I/O 3)
SO0OutputP33Serial data output (3-wire serial I/O 0)
SO1P31/TxDSerial data output (3-wire serial I/O 1)
SO2P14/TxD2Serial data output (3-wire serial I/O 2)
SO3P107Serial data output (3-wire serial I/O 3)
SCK0I/OP32Serial clock I/O (3-wire serial I/O 0)
SCK1P25/INTP4/ASCKSerial clock I/O (3-wire serial I/O 1)
SCK2P12/ASCK2Serial clock I/O (3-wire serial I/O 2)
SCK3P105Serial clock I/O (3-wire serial I/O 3)
NMIInputP20External interrupt—
INTP0P21request• Input of a count clock for timer/counter 1
• Capture/trigger signal for CR11 or CR12
INTP1P22• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR22
INTP2P23/CI• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR21
INTP3P24• Input of a count clock for timer/counter 0
• Capture/trigger signal for CR02
INTP4P25/ASCK/SCK1—
INTP5P26
AD0 to AD7I/OP40 to P47Time multiplexing address/data bus (for connecting external memory)
A8 to A15OutputP50 to P57High-order address bus (for connecting external memory)
A16 to A19OutputP60 to P63High-order address bus during address expansion (for connecting external
memory)
RDOutputP64Strobe signal output for reading the contents of external memory
WROutputP65Strobe signal output for writing on external memory
WAITInputP66/HLDRQWait insertion
REFRQOutputP67/HLDAKRefresh pulse output to external pseudo static memory
HLDRQInputP66/WAITInput of bus hold request
HLDAKOutputP67/REFRQOutput of bus hold response
ASTBOutputCLKOUTLatch timing output of time multiplexing address (A0 to A7) (for connecting
external memory)
Input of a conversion start trigger for A/D converter
when the regulator is stopped. Connect to VSS via a capacitor of order of 1µF.
REGOFF——Signal for specifying regulator operation
RESETInput—Chip reset
X1Input—Crystal input for system clock oscillation (A clock pulse can also be input
X2—
XT1Input—Watch clock connection
XT2——
ANI0 to ANI7InputP70 to P77Analog voltage input for A/D converter
AVREF1——To apply the reference voltage for A/D converter
AVDDPositive power supply for A/D converter
AVSSGND for A/D converter
VDDPositive power supply
VSSGND
TESTInputConnect directly to V
to the X1 pin.)
SS. (This pin is for IC test.)
Data Sheet U11680EJ2V0DS00
17
µ
PD784907, 784908
6.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-1.
For each type of input/output circuit, refer to Figure 6-1.
Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)
Pin NameI/O Circuit TypeI/ORecommended Connections of Unused Pins
P00 to P075-AI/OInput: Connect to VDD
P10, P11
P12/ASCK2/SCK28-A
P13/RxD2/SI25-A
P14/TxD2/SO2
P15 to P17
P20/NMI2InputConnect to VDD or VSS
P21/INTP0
P22/INTP12-AConnect to VDD
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK18-AI/OInput: Connect to VDD
P26/INTP52-AInputConnect to VDD
P27/SI0
P30/RxD/SI15-AI/OInput: Connect to VDD
P31/TxD/SO1
P32/SCK010-A
P33/SO0
P34/TO0 to P37/TO35-A
P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60/A16 to P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0 to P77/ANI720I/OInput: Connect to VDD or VSS
P90 to P975-A
P100 to P104
P105/SCK310-A
P106/SI38-A
P107/SO310-A
ASTB/CLKOUT4OutputLeave open
Output:Leave open
Output:Leave open
Output:Leave open
Output:Leave open
18
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (2/2)
Pin NameI/O Circuit TypeI/ORecommended Connections of Unused Pins
RESET2Input—
TEST1Connect directly to VSS
XT2——Leave open
XT1—InputConnect to V SS
PWM0, PWM13OutputLeave open
RX1InputConnect to VDD or VSS
TX3OutputLeave open
AVREF1——Connect to VSS
AVSS
AVDDConnect to VDD
CautionConnect an I/O pin, whose input/output mode is undefined, to VDD via a resistor of several
10 kΩ (especially if the voltage on the reset input pin rises higher than the low level input at power
on or when the mode is being switched between input and output by software).
Remark Since type numbers are commonly used in the 78K Series, these numbers are not always serial in each
product (some circuits are not included).
Data Sheet U11680EJ2V0DS00
19
Figure 6-1. I/O Circuits for Pins
Type 1Type 4
DD
V
P
Data
µ
PD784907, 784908
V
DD
P
OUT
IN
N
Push-pull output which can output high impedance
(both the positive and negative channels are off.)
Type 2
Type 5-A
Pull-up
enable
IN
Schmitt trigger input with hysteresis characteristics
Data
Output
disable
Input
enable
Type 2-AType 8-A
V
DD
Output
disable
N
V
DD
P
DD
V
P
IN/OUT
N
V
DD
Pull-up
P
Pull-up
enable
enable
Data
IN
Output
disable
Schmitt trigger input with hysteresis characteristics
Type 3Type 10-A
DD
V
Pull-up
enable
P-ch
Data
DataOUT
Open
N-ch
drain
Output
disable
V
DD
P
IN/OUT
N
P
V
DD
P
V
DD
P
IN/OUT
N
20
Data Sheet U11680EJ2V0DS00
Type 20
µ
PD784907, 784908
V
DD
Output
disable
Input
enable
Data
Comparator
(Threshold voltage)
P
IN/OUT
N
+
–
V
REF
P
N
Data Sheet U11680EJ2V0DS00
21
µ
PD784907, 784908
7. CPU ARCHITECTURE
7.1 Memory Space
A memory space of 1 Mbyte can be accessed. By using a LOCATION instruction, the mode for mapping internal
data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be
executed after a reset, and can be used only once.
(1) When the LOCATION 0 instruction is executed
• Internal memory
The internal data area and internal ROM area are mapped as follows:
Part NumberInternal Data AreaInternal ROM Area
µ
PD7849070F100H to 0FFFFH00000H to 0F0FFH
10000H to 17FFFH
µ
PD7849080EE00H to 0FFFFH00000H to 0FDFFH
10000H to 1FFFFH
CautionThe following internal ROM areas, existing at the same addresses as the internal data areas,
cannot be used when the LOCATION 0 instruction is executed:
Part NumberUnusable Area
µ
PD7849070F100H to 0FFFFH (3,840 bytes)
µ
PD7849080EE00H to 0FFFFH (4,608 bytes)
• External memory
The external memory is accessed in external memory expansion mode.
(2) When the LOCATION 0FH instruction is executed
• Internal memory
The internal data area and internal ROM area are mapped as follows:
Part NumberInternal Data AreaInternal ROM Area
µ
PD784907FF100H to FFFFFH00000H to 17FFFH
µ
PD784908FEE00H to FFFFFH00000H to 1FFFFH
• External memory
The external memory is accessed in external memory expansion mode.
22
Data Sheet U11680EJ2V0DS00
Figure 7-1.
µ
PD784907 Memory Map
Data Sheet U11680EJ2V0DS00
FFFFFH
18000H
1 7FFFH
10000H
0FFFFH
0 FFDFH
0 FFD0H
0FF00H
0FEFFH
0F100H
0F0FFH
00000H
When the LOCATION 0
instruction is executed
External memory
(928 Kbytes)
Note 1
Internal ROM
(32,768 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Internal RAM
(3,584 bytes)
Internal ROM
(61,696 bytes)
Note 4
0FEFFH
0FE80H
0FE7FH
0FE39H
0FE06H
0 FD0 0H
0 FCFFH
0F100H
17FFFH
10000H
0F0FFH
01000H
0 0FFFH
00800H
007FFH
00080H
0007FH
00040H
0003FH
00000H
General-purpose
registers (128 bytes)
Macro service control
word area (42 bytes)
Data area (512 bytes)
Program/data area
(3,072 bytes)
Note 2
Program/data area
CALLF entry area
(2 Kbytes)
CALLT table area
(64 bytes)
Vector table area
(64 bytes)
Note 3
FFEFFH
FFE80H
FFE7FH
FFE39H
FFE06H
FFD00H
F FCFFH
FF100H
1 7FFFH
FFFFFH
FFFDFH
FFFD0H
FFF00H
FFEFFH
FF100H
FF0FFH
18000H
1 7FFFH
00000H
When the LOCATION 0FH
instruction is executed
Special function registers (SFRs)
Note 1
(256 bytes)
Internal RAM
(3,584 bytes)
External memory
(946,432 bytes)
Internal ROM
(96 Kbytes)
Note 1
Note 4
µ
PD784907, 784908
23
Notes 1. Accessed in external memory expansion mode.
2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed:94,464 bytes
When the LOCATION 0FH instruction is executed: 98,304 bytes
4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.
24
Figure 7-2.
µ
PD784908 Memory Map
Data Sheet U11680EJ2V0DS00
FFFFFH
20000H
1FFFFH
10000H
0FFFFH
0FFDFH
0FFD0H
0FF 00H
0FEFFH
0EE00H
0EDFFH
00000H
When the LOCATION 0
instruction is executed
External memory
(896 Kbytes)
Note 1
Internal ROM
(65,536 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Internal RAM
(4,352 bytes)
Internal ROM
(60,928 bytes)
Note 4
0FEFFH
0FE8 0H
0FE7 FH
0FE3 9H
0FE0 6H
0FD00H
0FCFFH
0EE00H
1FFFFH
10000H
0EDFFH
01000H
00FFFH
00800H
007 FFH
00080H
0007FH
00040H
0003FH
00000H
General-purpose
registers (128 bytes)
Macro service control
word area (42 bytes)
Data area (512 bytes)
Program/data area
(3,840 bytes)
Note 2
Program/data area
CALLF entry area
(2 Kbytes)
CALLT table area
(64 bytes)
Vector table area
(64 bytes)
Note 3
FFEFFH
FFE 8 0H
FFE 7 FH
FFE 3 9H
FFE 0 6H
FFD00H
FFCFFH
FEE 0 0 H
1FFFFH
FFFFFH
FFFDFH
FFFD0H
FFF00H
FFEFFH
FEE 0 0 H
FEDFFH
20000H
1FFFFH
00000H
When the LOCATION 0FH
instruction is executed
Special function registers (SFRs)
Note 1
(256 bytes)
Internal RAM
(4,352 bytes)
External memory
(912,896 bytes)
Internal ROM
(128 Kbytes)
Note 1
Note 4
µ
PD784907, 784908
Notes 1. Accessed in external memory expansion mode.
2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed:126,464 bytes
When the LOCATION 0FH instruction is executed: 131,072 bytes
4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.
µ
PD784907, 784908
7.2 CPU Registers
7.2.1 General-purpose registers
A set of general-purpose registers consists of sixteen 8-bit general-purpose registers. Two 8-bit general-purpose
registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers,
when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.
Eight banks of this register set are provided. The user can switch between banks by software or the context switching
function.
General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto
internal RAM.
Figure 7-3. General-Purpose Register Format
A (R1)X (R0)
AX (RP0)
B (R3)C (R2)
BC (RP1)
R5R4
RP2
R7R6
RP3
V
VVP (RG4)
U
UUP (RG5)
T
TDE (RG6)
WL (R14)
WHL (RG7)
The character strings enclosed in
parentheses represent absolute names.
R9R8
VP (RP4)
R11R10
UP (RP5)
D (R13)E (R12)
DE (RP6)
H (R15)
HL (RP7)
8 banks
CautionBy setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C,
B, AX, and BC registers, respectively. However, this function must be used only when using
programs for the 78K/III series.
Data Sheet U11680EJ2V0DS00
25
µ
PD784907, 784908
7.2.2 Control registers
(1) Program counter (PC)
This register is a 20-bit program counter. The program counter is automatically updated by program execution.
Figure 7-4. Format of Program Counter (PC)
190
PC
(2) Program Status Word (PSW)
This register holds the CPU state. The program status word is automatically updated by program execution.
Figure 7-5. Format of Program Status Word (PSW)
PSW
PSWH
PSWL
15141312
UFRBS2RBS1RBS0
76543210
SZRSS
Note
ACIEP/V0CY
111098
Note This flag is used to maintain compatibility with the 78K/III Series. This flag must be set to 0 when
programs for the 78K/III Series are not being used.
(3) Stack pointer (SP)
This register is a 24-bit pointer for holding the start address of the stack.
The higher 4 bits must be set to 0.
Figure 7-6. Format of Stack Pointer (SP)
23200
SP0000
26
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
7.2.3 Special function registers (SFRs)
The special function registers are registers with special functions such as mode registers and control registers for
built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H
Note
and 0FFFFH
Note On execution of the LOCATION 0 instruction. FFF00H to FFFFFH when the LOCATION 0FH instruction
CautionDo not access an address in this area where no SFR is allocated, as the
Table 7-1 lists the special function registers (SFRs). The symbols of the table columns are explained below.
• Symbol.................................... Symbol indicating an on-chip SFR. The symbols listed in the table are reserved
• R/W ......................................... Indicates whether the SFR is read-only, write-only, or read/write.
• Bit units for manipulation ....... Indicates the maximum number of bits that can be manipulated whenever an SFR
• After reset............................... Indicates the state of the register when the RESET signal has been input.
.
is executed.
in the deadlock state. The deadlock state can be cleared only by a reset.
words for the NEC assembler (RA78K4). In the C compiler (CC78K4), the
symbols can be used as sfr variables with the #pragma sfr command.
R/W: Read/write
R:Read-only.
W:Write-only.
is manipulated. An SFR that supports 16-bit manipulation can be described in
the sfrp operand. For address specification, an even-numbered address must
be specified.
An SFR that can be manipulated in 1-bit units can be described as the operand
of a bit manipulation instruction.
µ
PD784908 may be placed
Data Sheet U11680EJ2V0DS00
27
Table 7-1. Special Function Registers (SFRs) (1/5)
0FF14HCompare register L (timer/counter 1)CR10
0FF15HCompare register H (timer/counter 1) ———
0FF16HCapture/compare register L (timer/counter 1)CR11
0FF17HCapture/compare register H (timer/counter 1) ———
0FF18HCompare register L (timer/counter 2)CR20
0FF19HCompare register H (timer/counter 2) ———
0FF1AHCapture/compare register L (timer/counter 2)CR21
0FF1BHCapture/compare register H (timer/counter 2) ———
0FF1CHCompare register L (timer 3)CR30
0FF1DHCompare register H (timer 3) ———
0FF20HPort 0 mode registerPM0—FFH
0FF21HPort 1 mode registerPM1—
0FF23HPort 3 mode registerPM3—
0FF24HPort 4 mode registerPM4—
0FF25HPort 5 mode registerPM5—
0FF26HPort 6 mode registerPM6—
0FF27HPort 7 mode registerPM7—
0FF29HPort 9 mode registerPM9—
0FF2AHPort 10 mode registerPM10—
0FF2EHReal-time output port control registerRTPC—00H
0FF30HCapture/compare control register 0CRC0——10H
0FF31HTimer output control registerTOC—00H
0FF32HCapture/compare control register 1CRC1——
0FF33HCapture/compare control register 2CRC2—
Note
Special Function Register (SFR) NameSymbolR/W
CR10W
CR11W
CR20W
CR21W
CR30W
Bit Units for Manipulation
1 bit 8 bits 16 bits
—
—
—
—
—
—10H
After Reset
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H
is added to each address.
28
Data Sheet U11680EJ2V0DS00
µ
Table 7-1. Special Function Registers (SFRs) (2/5)
PD784907, 784908
Address
0FF36HCapture register (timer/counter 0)CR02R——0000H
0FF38HCapture register L (timer/counter 1)CR12
0FF39HCapture register H (timer/counter 1) ———
0FF3AHCapture register L (timer/counter 2)CR22
0FF3BHCapture register H (timer/counter 2) ———
0FF41HPort 1 mode control registerPMC1R/W—00H
0FF43HPort 3 mode control registerPMC3—
0FF4AHPort 10 mode control registerPMC10—
0FF4EHRegister L for optional pull-up resistorPUOL—
0FF4FHRegister H for optional pull-up resistorPUOH—
0FF50HTimer register 0TM0R——0000H
0FF51H——
0FF52HTimer register 1TM1TM1W—
0FF53H ———
0FF54HTimer register 2TM2TM2W—
0FF55H ———
0FF56HTimer register 3TM3TM3W—
0FF57H ———
0FF5CHPrescaler mode register 0PRM0R/W——11H
0FF5DHTimer control register 0TMC0—00H
0FF5EHPrescaler mode register 1PRM1——11H
0FF5FHTimer control register 1TMC1—00H
0FF68HA/D converter mode registerADM—00H
0FF6AHA/D conversion result registerADCRR——Undefined
0FF6CHA/D current cut selection registerIEADR/W—00H
0FF6FHClock timer mode registerWM—
0FF70HPWM control registerPWMC—05H
0FF71HPWM prescaler registerPWPR——00H
0FF72HPWM modulo register 0PWM0——Undefined
0FF74HPWM modulo register 1PWM1——
0FF7DHOne-shot pulse output control registerOSPC—00H
0FF80HClocked serial interface mode register 3CSIM3—
0FF82HClocked serial interface mode registerCSIM
Note
Special Function Register (SFR) NameSymbolR/W
CR12W
CR22W
Bit Units for Manipulation
1 bit 8 bits 16 bits
—
—
—
After Reset
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H
is added to each address.
Data Sheet U11680EJ2V0DS00
29
Table 7-1. Special Function Registers (SFRs) (3/5)
µ
PD784907, 784908
Address
0FF84HClocked serial interface mode register 1CSIM1R/W—00H
0FF85HClocked serial interface mode register 2CSIM2—
0FF86HSerial shift registerSIO——Undefined
0FF88HAsynchronous serial interface mode registerASIM—00H
0FF89HAsynchronous serial interface mode register 2ASIM2—
0FF8AHAsynchronous serial interface status registerASISR—
0FF8BHAsynchronous serial interface status register 2 ASIS2—
0FF8CHSerial receive buffer: UART0RXB——Undefined
0FFB8HControl data registerCDRR/W——01H
0FFB9HTelegraph length registerDLR——
Note
Special Function Register (SFR) NameSymbolR/W
Serial transmission shift register: UART0TXSW——
Serial shift register: IOE1SIO1R/W——
Serial transmission shift register: UART2TXS2W——
Serial shift register: IOE2SIO2R/W——
Bit Units for Manipulation
1 bit 8 bits 16 bits
After Reset
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,
F0000H is added to each address.
30
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
Table 7-1. Special Function Registers (SFRs) (4/5)
Note
Address
0FFBAHData registerDRR/W——00H
0FFBBHUnit status registerUSRR—
0FFBCHInterrupt status registerISRR/W—
0FFBDHSlave status registerSSRR—41H
0FFBEHSuccess count registerSCR——01H
0FFBFHCommunication count registerCCR——20H
0FFC0HStandby control registerSTBCR/W—
0FFC2HWatchdog timer mode registerWDM—
0FFC4HMemory expansion mode registerMM—20H
0FFC5HHold mode registerHLDM—00H
0FFC6HClock output mode registerCLOM—
0FFC7HProgrammable wait control register 1PWC1——AAH
0FFC8HProgrammable wait control register 2PWC2——AAAAH
0FFCCHRefresh mode registerRFM—00H
0FFCDHRefresh area specification registerRFA—
0FFCFHOscillation stabilization time specification register OSTS——
0FFD0H toExternal SFR area —— —
0FFDFH
0FFE0HInterrupt control register (INTP0)PIC0—43H
0FFE1HInterrupt control register (INTP1)PIC1—
0FFE2HInterrupt control register (INTP2)PIC2—
0FFE3HInterrupt control register (INTP3)PIC3—
0FFE4HInterrupt control register (INTC00)CIC00—
0FFE5HInterrupt control register (INTC01)CIC01—
0FFE6HInterrupt control register (INTC10)CIC10—
0FFE7HInterrupt control register (INTC11)CIC11—
0FFE8HInterrupt control register (INTC20)CIC20—
0FFE9HInterrupt control register (INTC21)CIC21—
0FFEAHInterrupt control register (INTC30)CIC30—
0FFEBHInterrupt control register (INTP4)PIC4—
0FFECHInterrupt control register (INTP5)PIC5—
0FFEDHInterrupt control register (INTAD)ADIC—
0FFEEHInterrupt control register (INTSER)SERIC—
Special Function Register (SFR) NameSymbolR/W
Bit Units for Manipulation
1 bit 8 bits 16 bits
Note 2
Note 2
—30H
—00H
After Reset
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,
F0000H is added to each address.
2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV
WDM,#byte. Other instructions cannot perform a write operation.
Data Sheet U11680EJ2V0DS00
31
µ
PD784907, 784908
Table 7-1. Special Function Registers (SFRs) (5/5)
Note
Address
0FFEFHInterrupt control register (INTSR)SRICR/W—43H
0FFF0HInterrupt control register (INTST)STIC—
0FFF1HInterrupt control register (INTCSI)CSIIC—
0FFF2HInterrupt control register (INTSER2)SERIC2—
0FFF3HInterrupt control register (INTSR2)SRIC2—
0FFF4HInterrupt control register (INTST2)STIC2—
0FFF6HInterrupt control register (INTIE1)IEIC1—
0FFF7HInterrupt control register (INTIE2)IEIC2—
0FFF8HInterrupt control register (INTW)WIC—
0FFF9HInterrupt control register (INTCSI3)CSIIC3—
0FFFCHInternal memory size switching register
Special Function Register (SFR) NameSymbolR/W
Interrupt control register (INTCSI1)CSIIC1—
Interrupt control register (INTCSI2)CSIIC2—
Note 2
IMS——FFH
Bit Units for Manipulation
1 bit 8 bits 16 bits
After Reset
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,
F0000H is added to each address.
2. A write to this register is meaningful only for the µPD78P4908.
32
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8. PERIPHERAL HARDWARE FUNCTIONS
8.1 Ports
The ports shown in Figure 8-1 are provided to make various control operations possible. Table 8-1 shows the
functions of the ports. When inputting to port 0 to port 6, port 9, and port 10, an on-chip pull-up resistor can be specified
by software.
Figure 8-1. Port Configuration
P00
Port 0
P07
P10
Port 1
P17
Port 9
Port 10
P90
P97
P30
P37
P40
P47
P50
P57
P60
P67
P70P100
Port 2P20 to P27
8
Port 3
Port 4
Port 5
Port 6
Port 7
P107
Data Sheet U11680EJ2V0DS00
P77
33
µ
PD784907, 784908
Table 8-1. Port Functions
Port NamePin NameFunctionSpecification of Pull-up Resistor Connection by Software
Port 0P00 to P07• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Operable as 4-bit real-time outputs
(P00 to P03, P04 to P07)
• Can drive transistors
Port 1P10 to P17• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Can drive LEDs
Port 2P20 to P27• Input portIn 6-bit units (P22 through P27)
Port 3P30 to P37• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Either pin P32/SCK0 or P33/SO0 can be
set as the N-ch open drain.
Port 4P40 to P47• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Can drive LEDs
Port 5P50 to P57• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Can drive LEDs
Port 6P60 to P67• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
Port 7P70 to P77• Input or output mode can be specified—
in 1-bit units
Port 9P90 to P97• Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
Port 10P100 to P107 • Input or output mode can be specifiedAll port pins in input mode
in 1-bit units
• Either pin P105/SCK3 or P107/SO3 can
be set as the N-ch open drain.
34
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.2 Clock Generator
A circuit for generating the clock signal required for operation is provided. The clock generator has a frequency
divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency
divider to reduce the current consumption.
Figure 8-2. Block Diagram of Clock Generator
Clock-synchronized 3-wire serial I/O (CSI)
Asynchronous serial I/O (UART/IOE)
INTP0 noise eliminator
X1
X2
Oscillator
Oscillation settling timer
Timer/counter
XX
f
1/21/21/2
STBC.7
XX
/8
f
XX
/4
f
f
XX
/2
STBC.4, 5
Selector
f
CLK
CPU
Peripheral circuits
1
0
Selector
Watch clock
Main clock
Watch timer
Note Set bit 7 of the standby control register (STBC) to 1.
Remark f
XX: Oscillator frequency or external clock input frequency
fCLK: Internal operating frequency
Operation clock of the IEBus controller
INTW interrupt signal
Note
Data Sheet U11680EJ2V0DS00
35
µ
PD784907, 784908
Figure 8-3. Examples of Using Oscillator
(1) Crystal/ceramic oscillation
µ
PD784908
V
SS
X1
X2
(2) External clock
• When EXTC bit of OSTS = 1 • When EXTC bit of OSTS = 0
PD784908
µ
X1
X1
µ
PD784908
PD74HC04, etc.
µ
X2
Open
X2
CautionWhen using the clock generator, wire in the area enclosed by the broken lines to avoid adverse
influence from capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Make the ground point of the oscillator capacitor the same potential as V
SS. Do not ground
the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
36
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
Compared with the main system clock oscillator, the watch clock oscillator, which is a low-gain circuit designed
to reduce current consumption, is more likely to cause noise-induced malfunctions. Therefore, special care should
be taken when using the watch clock oscillator.
The microcontroller can operate normally only when the oscillation is normal and stable. If a high-precision oscillator
frequency is required, consult with the oscillator manufacturer.
Figure 8-4. Notes on Connecting the Oscillator
PD784908
µ
X2
Cautions1. Place the oscillator as close as possible to pins X1 and X2 (XT1 and XT2).
2. Do not let other signal lines cross that part of the circuit enclosed in broken lines.
X1V
SS
Data Sheet U11680EJ2V0DS00
37
µ
PD784907, 784908
8.3 Real-Time Output Port
The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or
external interrupt. Thus, pulse output that is free of jitter can be obtained.
Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors)
where an arbitrary pattern is output at arbitrary intervals.
As shown in Figure 8-5, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L).
Figure 8-5. Block Diagram of Real-Time Output Port
Three timer/counter units and one timer unit are incorporated.
Moreover, because seven interrupt requests are supported, these timers/counters can be used as seven timer/
counter units.
Table 8-2. Timers/Counters Operation
Name Timer/Counter 0 Timer/Counter 1 Timer/Counter 2Timer 3
Item
Count width8 bits—
16 bits
Operating modeInterval timer2 ch2 ch2 ch1 ch
External event counter—
One-shot timer———
FunctionTimer output2 ch—2 ch—
Toggle output——
PWM/PPG output——
One-shot pulse output
Real-time output———
Pulse width measurement1 input1 input2 inputs—
Number of interrupt requests2221
Note
———
Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the level
of a pulse output inactive by hardware (interrupt request signal).
Note that this function differs from the one-shot timer function of timer/counter 2.
Data Sheet U11680EJ2V0DS00
39
Timer/counter 0
Figure 8-6. Timer/Counter Block Diagram
Clear control
µ
PD784907, 784908
Software trigger
fXX/4
INTP3
Timer/counter 1
fXX/4
INTP0
Prescaler
Edge
detection
Prescaler
Event input
Edge
detection
INTP3
INTP0
Timer register 0
Selector
Compare register
Compare register
Capture register
Clear control
Timer register 1
(TM1/TM1W)
Selector
Compare register
(CR10/CR10W)
Capture/compare register
(CR11/CR11W)
Capture register
(CR12/CR12W)
(TM0)
(CR00)
(CR01)
(CR02)
Match
Match
Match
Match
OVF
TO0
TO1
Pulse output control
INTC00
INTC01
OVF
INTC10
To real-time
output port
INTC11
Timer/counter 2
fXX/4
INTP2/CI
INTP1
Edge
detection
Edge
detection
Timer 3
fXX/4
Remark OVF: Overflow flag
Prescaler
INTP2
Prescaler
Selector
INTP1
Clear control
Timer register 2
(TM2/TM2W)
Compare register
(CR20/CR20W)
Capture/compare register
(CR21/CR21W)
Capture register
(CR22/CR22W)
Timer register 3
(TM3/TM3W)
Compare register
(CR30/CR30W)
Match
Match
Clear
Match
OVF
TO2
TO3
Pulse output control
INTC20
INTC21
UART, CSI
INTC30
40
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.5 Watch Timer
As the count clock, either of two types of clock can be input to the watch timer: the main clock (6.29 MHz/12.58
MHz) or the watch clock (32.768 kHz). They can be selected using the control register. The watch clock is input to
the watch timer only. It is not input to the CPU or other peripheral circuits. Therefore, the speed of CPU operation
cannot be slowed by the watch clock.
Note
The watch timer generates interrupt signals (INTW), at 0.5-second intervals
, by dividing the count clock. At
the same time, the watch timer sets the interrupt request flag (WIF) (where WIF refers to bit 7 of the interrupt control
register (WIC)).
By switching modes, the INTW generation interval can be changed to about 1 ms (fast-forward mode: normal
operation speed × 512).
When the main clock is selected as the count clock, the watch timer stops if in STOP or IDLE standby mode, but
continues operating if in HALT standby mode. When the watch clock is selected as the count clock, the watch timer
continues operating regardless of the standby mode. The operation of the watch clock oscillator is controlled by means
of the watch timer mode register (WM).
µ
The watch timer of the
PD784908 does not have a buzzer output function.
Note After the operation is enabled, the time until first INTW generation is not 0.5 s.
Table 8-3. Relationship between Count Clock and Watch Timer Operation
Count Clock Selection Normal Operation ModeStandby Modes
HALT modeSTOP modeIDLE mode
Main clockOperableOperableStoppedStopped
Watch clockOperableOperableOperableOperable
The watch timer consists of a frequency divider which divides the count clock by 3 and a counter which divides
the frequency output from the frequency divider by 214. As the count clock, select the signal obtained by dividing the
internal system clock by 128 or that output by the watch clock oscillator.
Figure 8-7. Watch Timer Block Diagram
WM.3
Reset
Main clock
f
XX
/128
Division
by 3
Watch
clock
oscillator
ON/OFF
0
1
1234567891011121314
CounterCounter
0
SEL
SELSEL
1
WM.2
1
INTW
0
WM.7
WM.6
Data Sheet U11680EJ2V0DS00
Main clock selection: 6.29 MHz
STBC.7
12.58 MHz
41
µ
PD784907, 784908
8.6 PWM Output (PWM0, PWM1)
Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency
of 24.57 kHz (fCLK = 6.29 MHz) are incorporated. Low or high active level can be selected for the PWM output
channels, independently of each other. This output is best suited to DC motor speed control.
Figure 8-8. Block Diagram of PWM Output Unit
Internal bus
CLK
f
Prescaler
Remark n = 0, 1
(Modulo register)
150
PWMn
8-bit
down-counter
1/256
16
8 74 3
84
Pulse control
circuit
4-bit counter
8
PWM control register
(PWMC)
Reload
control
Output
control
PWMn (output pin)
42
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.7 A/D Converter
An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0 through ANI7) is incorporated.
The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D
conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved.
A/D conversion can be started in the following two ways:
• Hardware start: Conversion is started by trigger input (INTP5).
• Software start: Conversion is started by setting the bit of the A/D converter mode register (ADM).
After conversion has started, one of the following modes can be selected:
• Scan mode: Multiple analog inputs are selected sequentially to convert multiple pins.
• Select mode: A single analog input is selected at all times to enable conversion data to be obtained continuously.
ADM is used to specify the above modes, as well as the termination of conversion.
When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,
the results of conversion can be continuously transferred to memory by the macro service.
Cautions1. For this product, apply the same voltage as the power supply voltage (AV
voltage input pin (AVREF1).
2. When port 7 is used as both an output port and A/D input line, do not manipulate the output
port while A/D conversion is in progress.
Figure 8-9. Block Diagram of A/D Converter
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
INTP5
Input selector
Edge
detection
circuit
A/D converter mode
register (ADM)
Sample and hold circuit
Conversion
trigger
Trigger enable
Voltage comparator
Successive
approximation
register (SAR)
Control
circuit
A/D conversion
result register (ADCR)
INTAD
8
Series resistor string
R/2
R
Tap selector
R/2
AV
DD
Connection
control
AV
REF1
AV
SS
DD) to the reference
A/D current cut selection
register (IEAD)
8
Internal bus
Data Sheet U11680EJ2V0DS00
8
43
µ
PD784907, 784908
8.8 Serial Interface
Four independent serial interface channels are incorporated.
•
Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2
•
Synchronous serial interface (CSI) × 2
• 3-wire serial I/O (IOE)
This makes it possible for communication with an external system and local communication within the system to
be simultaneously executed (see Figure 8-10).
Figure 8-10. Example of Serial Interface
UART + 3-wire serial I/O + 2-wire serial I/O
PD4711A
µ
RS-232-C
driver/receiver
Note Handshake line
PD784908 (master)
µ
[UART]
RxD
TxD
Port
SO1
SI1
SCK1
INTPm
Port
SI0
SO0
SCK0
INTPn
Port
[3-wire serial I/O]
Note
V
DD
Note
[2-wire serial I/O]
Slave
SI
SO
SCK
Port
INT
V
DD
Slave
SB0
SCK0
Port
INT
44
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
Two serial interface channels, from which asynchronous serial interface mode and 3-wire serial I/O mode can be
selected, are provided.
(1) Asynchronous serial interface mode
In this mode, 1-byte data is transferred or received after a start bit.
A baud rate generator is incorporated to enable communication at a wide range of baud rates.
A baud rate can be defined by dividing the frequency of a clock signal input to the ASCK pin.
By using the baud rate generator, a baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.
Figure 8-11. Block Diagram of Asynchronous Serial Interface Mode
Internal bus
RxD, RxD2
TxD, TxD2
Baud rate generator
XX
f
ASCK, ASCK2
Selector
1/2
n+1
Receive buffer
Receive
shift register
Reception
control parity
check
1/2m
1/2m
RXB, RXB2
INTSR,
INTSR2
INTSER,
INTSER2
Transmission
shift register
Transmission
control parity
bit addition
TXS, TXS2
INTST, INTST2
Remark f
XX: Oscillating frequency or external clock input frequency
n = 0 to 11
m = 16 to 30
Data Sheet U11680EJ2V0DS00
45
µ
PD784907, 784908
(2) 3-wire serial I/O mode
In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in synchronization with this clock.
This mode is designed for communication with a device incorporating a conventional synchronous serial interface.
Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI
and SO). In general, a handshake line is required to check the state of communication.
Figure 8-12. Block Diagram of 3-Wire Serial I/O Mode
Internal bus
Direction control
circuit
SIO1, SIO2
SI1, SI2
Shift register Output latch
SO1, SO2
SCK1, SCK2
Remark f
Serial clock counter
Serial clock
control circuit
XX: Oscillating frequency or external clock input frequency
n = 0 to 11
m = 1, 16 to 30
Interrupt
generator
Selector
1/m1/2
INTCSI1,
INTCSI2
n+1
f
XX
46
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.8.2 Clocked serial interface (CSI)
With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in synchronization with this clock.
Figure 8-13. Block Diagram of Clocked Serial Interface
Internal bus
SIn
SIOn registerCSIMn register
Selector
SOn
SCKn
Remark f
Serial clock counter
XX: Oscillating frequency or external clock input frequency
n = 0, 3
Selector
INTCSIn
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
Data Sheet U11680EJ2V0DS00
47
µ
PD784907, 784908
• 3-wire serial I/O mode
This mode is designed for communication with a device incorporating a conventional clocked serial interface.
Basically, three lines are used for communication: the serial clock line (SCKn) and serial data lines (SIn and SOn)
(n = 0, 3).
In general, a handshake line is required to check the state of communication.
8.9 Clock Output Function
The frequency of the CPU clock signal can be divided and output from the system. Moreover, the port can be used
as a 1-bit port.
The ASTB pin is also used as the CLKOUT pin, so that when this function is used, the local bus interface cannot
be used.
Figure 8-14. Block Diagram of Clock Output Function
f
CLK
f
CLK
/2
CLK
/4
f
Selector
CLK
/8
f
f
CLK
/16
Output control
Enable output Output level
CLKOUT
48
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
8.10 Edge Detection Function
The interrupt input pins (NMI, INTP0 through INTP5) are used not only to input interrupt requests but also to input
trigger signals to the internal hardware units. Because these pins operate at the edge of the input signal, they have
an edge-detection function incorporated. Moreover, a noise elimination function is also provided to prevent erroneous
edge detection caused by noise.
Table 8-4. Noise Elimination Method of Interrupt Input Pins
Pin NameDetectable EdgeNoise Elimination Method
NMIRising edge or falling edgeAnalog delay
INTP0 to INTP3Rising edge or falling edge, or both edges Clock sampling
Note
INTP4, INTP5Analog delay
Note INTP0 is used for sampling clock selection.
8.11 Watchdog Timer
A watchdog timer is incorporated to detect a CPU runaway. The watchdog timer, if not cleared by software within
a specified interval, generates a non-maskable interrupt request. Furthermore, once watchdog timer operation is
enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt request
based on the watchdog timer or on an interrupt request based on the NMI pin.
Figure 8-15. Block Diagram of Watchdog Timer
f
CLK
Clear signal
Timer
21
f
CLK
/2
20
CLK
/2
f
19
f
CLK
/2
17
f
CLK
/2
Selector
INTWDT
Data Sheet U11680EJ2V0DS00
49
µ
PD784907, 784908
8.12 Simplified IEBus Controller
µ
A newly developed IEBus controller is incorporated into the
PD784908. This IEBus controller has fewer functions
than the IEBus interface function of previous product (incorporated into the 78K/0).
Table 8-5 compares the previous product and the new, simplified IEBus interface.
Table 8-5. Comparisons between Previous Product and Simplified IEBus Interface
ItemPrevious Product (IEBus Incorporated into 78K/0)Simplified IEBus
Communication modeModes 0 to 2Fixed to mode 1
Internal system clock6.0 (6.29) MHz
Internal buffer sizeTransmission buffer 33 bytes (FIFO)Transmission/reception data register 1 byte
Reception buffer 40 bytes (FIFO)
Up to four frames can be received
CPU processingProcessing before transmission start (data setting)Processing before transmission start (data setting)
Setting and control of each communication statusSetting and control of each communication status
Data write to the transmission bufferData write processing for every byte
Data read from the reception bufferData read processing for every byte
Transmission control such as slave status
Control of multiple frames, remastering request
Hardware processingBit processingBit processing
(modulation/demodulation, error detection)(modulation/demodulation, error detection)
Field processing (generation, control)Field processing (generation, control)
Detection of arbitration resultsDetection of arbitration results
Parity processing (generation, error detection)Parity processing (generation, error detection)
ACK/NACK automatic responseACK/NACK automatic response
Automatic data retransmittingAutomatic data retransmitting
Automatic remastering
Transmission such as automatic slave status
Reception of multiple frames
50
Data Sheet U11680EJ2V0DS00
Figure 8-16. IEBus Controller
CPU interface section
µ
PD784907, 784908
Internal register section
RX
TX
CLK
88
121212
BCR(8)DLR(8)USR(8) ISR(8) SSR(8) SCR(8) CCR(8)
UAR(12) SAR(12) PAR(12) CDR(8)
8
121212
NF
MPX
IEBus interface section
MPX
TX/RX
Parity error
detector
PSR (8 bits)
8888888
DR(8)
888
Internal bus
8
Conflict
detector
12
8
12-bit latch
Comparator
ACK
generator
Interrupt
control
circuit
Interrupt control
section
88888
INT request
(vector, macro service)
5
Internal bus R/W
Bit processing sectionField processing section
Data Sheet U11680EJ2V0DS00
51
•
Hardware configuration and functions
The internal configuration of the IEBus consists mainly of the following six sections:
• CPU interface section
• Interrupt control section
• Internal register section
• Bit processing section
• Field processing section
• IEBus interface section
<CPU interface section>
Interfaces between the CPU (78K/IV) and the IEBus.
<Interrupt control section>
Passes interrupt request signals from the IEBus to the CPU.
<Internal register section>
Control register which stores the data in each field to control the IEBus.
µ
PD784907, 784908
<Bit processing section>
Generates and resolves the bit timing. Mainly consists of the bit sequence ROM, 8-bit preset timer, and
discriminator.
<Field processing section>
Generates each field in the communication frame. Mainly consists of the field sequence ROM, 4-bit down counter,
and discriminator.
<IEBus interface section>
Interface section of the external driver/receiver. Mainly consists of the noise filter, shift register, conflict detector,
parity detector, parity generator, and ACK/NACK generator.
52
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
9. INTERRUPT FUNCTION
The three types of interrupt request-response servicing, as shown in Table 9-1 below, can be selected by program.
Table 9-1. Servicing of Interrupt Request
Servicing ModeServicing AgentServicingPC and PSW Contents
Vectored interruptSoftwareBranches and executes a servicing routineSaves to and restores from the stack.
(servicing is arbitrary).
Context switchingAutomatically switches register banks, andSaves to or restores from fixed area in
branches and executes a servicing routinethe register bank.
(servicing is arbitrary).
Macro serviceFirmwareExecutes data transfer between memory and Maintained
I/O (servicing is fixed).
9.1 Interrupt Source
Table 9-2 shows the interrupt sources available. As shown, interrupts are generated by 27 types of sources,
execution of the BRK and BRKCS instructions, or an operand error.
Four levels of interrupt servicing priority can be set. Priority levels can be set to nest control during interrupt servicing
or to simultaneously generate interrupt requests. However, nested macro services are performed without suspension.
When interrupt requests having the same priority level are generated, they are serviced according to the default
priority (fixed) (see Table 9-2).
Data Sheet U11680EJ2V0DS00
53
µ
PD784907, 784908
Table 9-2. Interrupt Source
TypeDefaultSourceInternal/ Macro
Priority
Software—BRK instructionInstruction execution——
Non-maskable—NMIDetection of edge input on the pinExternal—
Maskable0 (highest) INTP0Detection of edge input on the pin (TM1/TM1W capture trigger) External√
1INTP1Detection of edge input on the pin (TM2/TM2W capture trigger)
2INTP2Detection of edge input on the pin (TM2/TM2W event counter
3INTP3Detection of edge input on the pin (TM0 capture trigger)
4INTC00TM0-CR00 match signal issuedInternal√
5INTC01TM0-CR01 match signal issued
6INTC10TM1-CR10 match signal issued (in 8-bit operation mode)
7INTC11TM1-CR11 match signal issued (in 8-bit operation mode)
8INTC20TM2-CR20 match signal issued (in 8-bit operation mode)
9INTC21TM2-CR21 match signal issued (in 8-bit operation mode)
10INTC30TM3-CR30 match signal issued (in 8-bit operation mode)
11INTP4Detection of edge input on the pinExternal√
12INTP5Detection of edge input on the pin
13INTADA/D converter processing completed (ADCR transfer)Internal√
14INTSERASI0 reception error—
15INTSRASI0 reception completed or CSI1 transfer completed√
16INTSTASI0 transmission completed
17INTCSICSI0 transfer completed
18INTSER2ASI2 reception error—
19INTSR2ASI2 reception completed or CSI2 transfer completed√
20INTST2ASI2 transmission completed
21INTIE1IEBus data access request
22INTIE2IEBus communication error and communication start/end
23INTWClock timer output
24 (lowest) INTCSI3CSI3 transfer completed
NameTrigger
BRKCS instruction Instruction execution
Operand errorWhen the MOV STBC,#byte, MOV WDM,#byte, or LOCATION
instruction is executed, exclusive OR of the byte operand and
byte does not produce FFH.
WDTWatchdog timer overflowInternal
input)
TM1W-CR10W match signal issued (in 16-bit operation mode)
TM1W-CR11W match signal issued (in 16-bit operation mode)
TM2W-CR20W match signal issued (in 16-bit operation mode)
TM2W-CR21W match signal issued (in 16-bit operation mode)
TM3W-CR30W match signal issued (in 16-bit operation mode)
(A/D converter start conversion trigger)
INTCSI1
INTCSI2
External Service
Remark ASI: Asynchronous serial interface
CSI: Clocked serial interface
54
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
9.2 Vectored Interrupt
When a branch to an interrupt servicing routine occurs, the vector table address corresponding to the interrupt
source is used as the branch address.
Interrupt servicing by the CPU consists of the following operations :
• When branching: Saves the CPU status (PC and PSW contents) to the stack.
• When returning: Restores the CPU status (PC and PSW contents) from the stack.
To return control from the servicing routine to the main routine, the RETI instruction is used.
The branch destination addresses must be within the range of 0 to FFFFH.
When an interrupt request is generated, or when the BRKCS instruction is executed, a predetermined register bank
is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same
time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register
bank.
The branch address must be within the range of 0 to FFFFH.
Figure 9-1. Context Switching Operation When Interrupt Request Is Generated
0000B
<7>
PC19-16
<2>
Save
(Bits 8 to 11 of
temporary register)
Temporary register
<1>
Save
Transfer
PC15-0
<6>
Exchange
<5>
Save
Register bank n (n = 0-7)
AX
BC
R5R4
R7
V
U
T
WL
DE
H
VP
UP
R6
Switching between register banks
<3>
(RBS0-RBS2 ← n)
<4>
RSS ← 0
IE ← 0
Register bank (0 to 7)
PSW
9.4 Macro Service
The macro service function enables data transfer between memory and special function registers (SFRs) without
requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same
transfer cycle to directly transfer data without having to perform data fetch.
Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible.
Figure 9-2. Macro Service
CPUSFRMemory
Internal bus
Read
Write
Macro service
controller
Write
Read
56
Data Sheet U11680EJ2V0DS00
9.5 Examples of Macro Service Applications
(1) Serial interface transmission
Transmit data storage buffer (memory)
Data n
Data n - 1
Data 2
Data 1
Internal bus
µ
PD784907, 784908
TxD
Transmit
shift register
Transmit control
TXS (SFR)
INTST
Each time macro service request (INTST) is generated, the next transmit data is transferred from memory to TXS.
When data n (last byte) has been transferred to TXS (that is, once the transmit data storage buffer becomes
empty), vectored interrupt request (INTST) is generated.
(2) Serial interface reception
Receive data storage buffer (memory)
Data n
Data n - 1
Data 2
Data 1
Internal bus
RxD
Receive buffer
Receive
shift register
Receive control
RXB (SFR)
INTSR
Each time macro service request (INTSR) is generated, receive data is transferred from RXB to memory. When
data n (last byte) has been transferred to memory (that is, once the receive data storage buffer becomes full),
vectored interrupt request (INTSR) is generated.
Data Sheet U11680EJ2V0DS00
57
µ
PD784907, 784908
(3) Real-time output port
INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro
service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used
to independently control two stepping motors. They can also be applied to PWM and DC motor control.
Each time macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer
register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10
match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last
byte) is transferred to CR10, vectored interrupt request (INTC10) is generated.
For INTC11, the same operation as that performed for INTC10 is performed.
58
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
10. LOCAL BUS INTERFACE
The local bus interface enables the connection of external memory and I/O devices (memory mapped I/O) and
supports a 1-Mbyte memory space (see Figure 10-1).
Figure 10-1. Example of Local Bus Interface
PD784908
µ
A16 to A19
Decoder
RD
WR
REFRQ
Pseudo SRAM
PROM
PD27C1001A
µ
Kanji character
generator
PD24C1000
µ
AD0 to AD7
ASTB
A8 to A15
Latch
Data bus
Address bus
Gate array for I/O
expansion including
Centronics interface
circuit, etc.
10.1 Memory Expansion
By adding external memory, program memory or data memory can be expanded, 256 bytes at a time, to
approximately 1 Mbyte (seven steps).
Data Sheet U11680EJ2V0DS00
59
µ
PD784907, 784908
10.2 Memory Space
The 1-Mbyte memory space is divided into eight spaces, each having a logical address. Each of these spaces
can be controlled using the programmable wait and pseudo-static RAM refresh functions.
Figure 10-2. Memory Space
FFFFFH
512 Kbytes
80000H
7FFFFH
256 Kbytes
40000H
3FFFFH
20000H
1FFFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
128 Kbytes
64 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
60
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
10.3 Programmable Wait
When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space
while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when
memory devices having different access times are connected.
In addition, an address wait function that extends the ASTB signal active period is provided to ensure the lapse
of the address decode time. (This function is set for the entire space.)
10.4 Pseudo-Static RAM Refresh Function
Refresh is performed as follows:
• Pulse refresh
A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory
space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the
REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal
memory access.
• Power-down self-refresh
In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM.
10.5 Bus Hold Function
A bus hold function is provided to facilitate connection to devices such as a DMA controller. When a bus hold request
signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and
WR pins enter the high-impedance state, the bus hold acknowledge signal (HLDAK) is made active, and the bus is
released to the external bus master as soon as the current bus cycle is completed.
While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.
Data Sheet U11680EJ2V0DS00
61
µ
PD784907, 784908
11. STANDBY FUNCTION
This function is to reduce the power consumption of the chip, and can be used in the following modes:
• HALT mode: Stops the operating clock of the CPU. This mode is used in combination with the normal operation
mode for intermittent operation to reduce the average power consumption.
• IDLE mode: Stops the entire system with the oscillator continuing operation. The power consumption in this
mode is close to that in the STOP mode. However, the time required to restore the normal program
operation from this mode is almost the same as that from the HALT mode.
• STOP mode: Stops the oscillator and thereby stops all the internal operations of the chip. Consequently, the
power consumption is minimized with only leakage current flowing.
These modes are programmable.
The macro service can be started from the HALT mode.
Figure 11-1. Standby Mode Status Transition
Macro service request
End of one operation
End of macro service
Interrupt request
RESET input
Set HALT
Note 2
Macro service request
End of one operation
HALT
(standby)
Macro
service
Notes 1, 3
INTW
NMI, INTP4, INTP5 input
STOP
(standby)
Wait for
oscillation
settling
Note 1
Set STOP
RESET input
Oscillation settling
time elapses
Set IDLE
INTW
IDLE
(standby)
Program
operation
Note 1
RESET input
Notes 1, 3
NMI, INTP4, INTP5 input
Request for masked interrupt
Notes 1. INTW, INTP4, and INTP5 are applied when not masked.
2. Only unmasked interrupt request
3. When the watch clock is operating
Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby
(STOP, HALT, or IDLE mode).
62
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
12. RESET FUNCTION
When a low-level signal is input to the RESET pin, the internal hardware becomes initialize status (reset status).
When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):
• Low-order 8 bits of the PC:Contents of address 0000H
• Intermediate 8 bits of the PC: Contents of address 0001H
• High-order 4 bits of the PC:0
The PC contents are used as a branch destination address, and program execution starts from that address.
Therefore, a reset start can be performed from an arbitrary address.
The contents of each register can be set by software, as necessary.
The RESET input circuit incorporates a noise eliminator to prevent malfunctions caused by noise. This noise
eliminator is an analog delay sampling circuit.
Figure 12-1. Accepting Reset
Execute instruction
of reset start address
RESET
(input)
Internal reset signal
Delay
Delay
Start reset
Delay
End reset
Initialize PC
For power-on reset, the RESET signal must be held active until the oscillation stabilization time (approximately 40
ms) has elapsed.
Figure 12-2. Power-On Reset
Oscillation stabilization timeDelay
V
DD
Initialize PC
Execute instruction of
reset start address
RESET
(input)
Internal reset signal
End reset
Data Sheet U11680EJ2V0DS00
63
µ
PD784907, 784908
13. REGULATOR
The µPD784908 incorporates a regulator (a circuit which enables low-voltage operation) to reduce the current
consumption of the device. To enable or disable the operation of this regulator, specify the input level of the REGOFF
pin. To disable the operation of the regulator, input a high level signal to the REGOFF pin. To enable operation, input
a low level signal to the REGOFF pin.
When the regulator is turned on, the CPU enters low-power mode. It is recommended to operate this product using
this regulator.
µ
To stabilize the regulator output voltage, connect a capacitor (of about 1
connection pin).
When the regulator is stopped, apply the same level as V
DD to the REGC pin. Figure 13-1 is a block diagram of
the regulator's peripheral circuits.
Figure 13-1. Regulator Peripheral Circuits
REGOFF
Low level: Regulator is turned on.
High level: Regulator is turned off.
F) to the REGC pin (stabilizing capacitor
DD
V
REGC
1 F
µ
Regulator
Stops oscillation.
STBC.7
• Processing for the REGC pin
When the regulator is operatingConnect a capacitor to stabilize the regulator.
When the regulator is stoppedSupply the power supply voltage.
Internal power supply voltage
(Supplies to the CPU and
peripheral circuits.)
64
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
14. INSTRUCTION SET
(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are
the same as BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS
Data Sheet U11680EJ2V0DS00
69
µ
PD784907, 784908
15. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
ParameterSymbolConditionsRatingsUnit
Supply voltageVDD–0.3 to +6.5V
AVDD–0.3 to VDD + 0.3V
AVSS–0.3 to +0.3V
Input voltageVI1–0.3 to VDD + 0.3V
Analog input voltageVANAVSS – 0.3 to AVREF1 + 0.3V
Output voltageVO–0.3 to VDD + 0.3V
Output current, lowIOLPer pin10mA
Total of P00 to P07, P30 to50mA
P37, P54 to P57, P60 to P67,
and P100 to P107 pins
Total of P10 to P17, P40 to50mA
P47, P50 to P53, P70 to P77,
P90 to P97, PWM0, PWM1,
and TX pins
Output current, highIOHPer pin–6mA
Total of P00 to P07, P30 to–30mA
P37, P54 to P57, P60 to P67,
and P100 to P107 pins
Total of P10 to P17, P40 to–30mA
P47, P50 to P53, P70 to P77,
P90 to P97, PWM0, PWM1,
and TX pins
A/D converter reference inputAVREF1–0.3 to VDD + 0.3V
voltage
Operating ambient temperatureTA–40 to +85°C
Storage temperatureTstg–65 to +150°C
CautionProduct quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of a alternate-function pin are the same as those of a port
pin.
70
Data Sheet U11680EJ2V0DS00
Operating Conditions
• Operating ambient temperature (T
A): –40°C to +85°C
• Power supply voltage and clock cycle time: see Figure 15-1 .
• Selection of internal regulator (REGOFF pin: low-level input)
Figure 15-1. Power Supply Voltage and Clock Cycle Time
2. P40/AD0 to P47/AD7, P50/A8 to P57/A15, P60/A16 to P67/REFRQ/HLDAK, P00 to P07
3. P00 to P07
4. P10 to P17, P40/AD0 to P47/AD7, P50/A8 to P57/A15
5. Other than pull-up resistors
Data Sheet U11680EJ2V0DS00
73
µ
PD784907, 784908
DC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, VSS = AVSS = 0 V) (2/2)
ParameterSymbolConditionsMIN.TYP.MAX.Unit
Input leakage currentILI10 V ≤ VI≤ VDDFor pins other than±10
X1 and XT1
ILI2X1 and XT1±20
Output leakage currentI LO0 V ≤ VO≤ VDD±10
VDD supply current
Pull-up resistorRLVI = 0 VX1 and XT11580kΩ
Note
IDD1Operation modefXX = 12.58 MHz1020mA
VDD = 4.0 to 5.5 V
fXX = 6.29 MHz510mA
VDD = 3.5 to 5.5 V
IDD2HALT modefXX = 12.58 MHz2.04.0mA
VDD = 4.0 to 5.5 V
fCLK = fXX/8
(STBC = B1H)
Peripheral operation
stops.
f
XX = 6.29 MHz1.22.4mA
VDD = 3.5 to 5.5 V
fCLK = fXX/8
(STBC = 31H)
Peripheral operation
stops.
IDD3IDLE modefXX = 12.58 MHz0.61.2mA
VDD = 4.0 to 5.5 V
fXX = 6.29 MHz0.30.6mA
VDD = 3.5 to 5.5 V
µ
A
µ
A
µ
A
Note These values are valid when the internal regulator is ON (REGOFF pin = L level). They do not include the
DD and AVREF1 currents.
AV
74
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
(1) Read/write operation
ParameterSymbolConditionsMIN.MAX.Unit
Address setup time (to ASTB↓)tSASTVDD = 5.0 V(0.5 + a)T – 1129ns
ASTB high-level widthtWSTHVDD = 5.0 V(0.5 + a)T – 1723ns
Address hold time (from ASTB↓)tHSTLAVDD = 5.0 V0.5T – 1921ns
Address hold time (from RD↑)tHRAVDD = 5.0 V0.5T – 1426ns
Delay from address to RD↓t DARVDD = 5.0 V(1 + a)T – 574ns
Address float time (from RD↓)tFRA0ns
Data input time from addresstDAIDVDD = 5.0 V(2.5 + a + n)T – 37400ns
Data input time from
Data input time from RD↓tDRIDVDD = 5.0 V(1.5 + n)T – 40238ns
Delay from ASTB↓ to RD↓tDSTRVDD = 5.0 V0.5T – 931ns
Data hold time (from RD↑)tHRID0ns
Address active time from RD↑tDRAVDD = 5.0 V0.5T – 238ns
Delay from RD↑ to ASTB↑tDRSTVDD = 5.0 V0.5T – 931ns
RD low-level widthtWRLVDD = 5.0 V(1.5 + n)T – 2594ns
Delay from address↓ to WR↓tDAWVDD = 5.0 V(1 + a)T – 574ns
Address hold time (from WR↑)tHWAVDD = 5.0 V0.5T – 1426ns
Delay from ASTB↓ to data outputtDSTODVDD = 5.0 V0.5T + 1555ns
Delay from WR↓ to data outputtDWOD15ns
Delay from ASTB↓ to WR↓t DSTWVDD = 5.0 V0.5T – 931ns
Data setup time (to WR↑)tSODWRVDD = 5.0 V(1.5 + n)T – 2099ns
Data hold time (from WR↑)tHWODVDD = 5.0 V0.5T – 1426ns
Delay from WR↑ to ASTB↑tDWSTVDD = 5.0 V0.5T – 931ns
WR low-level widthtWWLVDD = 5.0 V(1.5 + n)T – 2594ns
ASTB↓
tDSTIDVDD = 5.0 V(2 + n)T – 35283ns
Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)
a: 1 during address wait, otherwise, 0
n: number of wait states (n ≥ 0)
Data Sheet U11680EJ2V0DS00
75
µ
PD784907, 784908
(2) External wait timing
ParameterSymbolConditionsMIN.MAX.Unit
WAIT↓ input time from addresstDAWTVDD = 5.0 V(2 + a)T – 40198ns
WAIT↓ input time from ASTB↓tDSTWTVDD = 5.0 V1.5T – 4079ns
WAIT hold time from ASTB↓t HSTWTVDD = 5.0 V(0.5 + n)T + 5124ns
Delay from ASTB↓ to WAIT↑t DSTWTHVDD = 5.0 V(1.5 + n)T – 40238ns
WAIT↓ input time from RD↓tDRWTLVDD = 5.0 VT – 4039ns
WAIT hold time from RD↓t HRWTVDD = 5.0 VnT + 584ns
Delay from RD↓ to WAIT↑tDRWTHVDD = 5.0 V(1 + n)T – 40198ns
Data input time from WAIT↑tDWTIDVDD = 5.0 V0.5T – 535ns
Delay from WAIT↑ to RD↑tDWTRVDD = 5.0 V0.5T40ns
Delay from WAIT↑ to WR↑tDWTWVDD = 5.0 V0.5T40ns
WAIT↓ input time from WR↓tDWWTLVDD = 5.0 VT – 4039ns
WAIT hold time from WR↓tHWWTVDD = 5.0 VnT + 584ns
Delay from WR↓ to WAIT↑tDWWTHVDD = 5.0 V(1 + n)T – 40198ns
Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)
a: 1 during address wait, otherwise, 0
n: number of wait states (n ≥ 0)
76
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
(3) Bus hold timing
ParameterSymbolConditionsMIN.MAX.Unit
Delay from HLDRQ↑ to floattFQHCVDD = 5.0 V(2 + 4 + a + n)T + 50765ns
Delay from HLDRQ↑ to HLDAK↑t DHQHHAHVDD = 5.0 V(3 + 4 + a + n)T + 30825ns
Delay from float to HLDAK↑tDCFHAVDD = 5.0 VT + 30109ns
Delay from HLDRQ↓ to HLDAK↓t DHQLHALVDD = 5.0 V2T + 40199ns
Delay from HLDRQ↓ to activetDHACVDD = 5.0 VT – 2059ns
Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)
a: 1 during address wait, otherwise, 0
n: number of wait states (n ≥ 0)
(4) Refresh timing
ParameterSymbolConditionsMIN.MAX.Unit
Random read/write cycle timetRCVDD = 5.0 V3T238ns
REFRQ low-level pulse widthtWRFQLVDD = 5.0 V1.5T – 2594ns
Delay from ASTB↓ to REFRQtDSTRFQVDD = 5.0 V0.5T – 931ns
Delay from RD↑ to REFRQtDRRFQV DD = 5.0 V1.5T – 9110ns
Delay from WR↑ to REFRQtDWRFQVDD = 5.0 V1.5T – 9110ns
Delay from REFRQ↑ to ASTBtDRFQSTVDD = 5.0 V0.5T – 931ns
REFRQ high-level pulse widthtWRFQHVDD = 5.0 V1.5T – 2594ns
Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)
Data Sheet U11680EJ2V0DS0077
µ
PD784907, 784908
Serial Operation (TA = –40 to +85°C, VDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI, CSI3
ParameterSymbolConditionsMIN.MAX.Unit
Serial clock cycle timetCYSK0Input f CLK = fXX8/fXXns
(SCK0, SCK3)
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and
P107/SO3 pins
AC Timing Test Points
V
DD
– 1 V
0.45 V
0.8 VDD or 2.2 V
0.8 V
0.8 VDD or 2.2 V
Test points
0.8 V
82
Data Sheet U11680EJ2V0DS00
Timing Waveform
(1) Read operation
ASTB
A8 to A19
AD0 to AD7
t
WSTH
t
SAST
t
DAR
t
DSTR
t
HSTLA
t
DAID
t
DSTID
µ
PD784907, 784908
t
DRST
t
HRA
t
FRA
t
DRID
t
HRID
t
DRA
RD
(2) Write operation
ASTB
A8 to A19
AD0 to AD7
WR
t
WSTH
t
SAST
t
DAW
t
DSTW
t
HSTLA
t
DSTOD
t
DWOD
t
WRL
t
SODWR
t
DWST
t
HWA
t
HWOD
t
WWL
Data Sheet U11680EJ2V0DS0083
Hold Timing
ASTB, A8 to A19,
AD0 to AD7, RD, WR
t
FHQC
HLDRQ
t
DHQHHAH
HLDAK
External Wait Signal Input Timing
(1) Read operation
ASTB
t
DCFHA
t
DSTWT
t
DSTWTH
t
HSTWTH
t
DHQLHAL
t
DHAC
µ
PD784907, 784908
A8 to A19
AD0 to AD7
RD
WAIT
(2) Write operation
ASTB
A8 to A19
AD0 to AD7
t
DAWT
t
DSTWT
t
DRWTL
t
DSTWTH
t
HSTWTH
t
HRWT
t
DRWTH
t
DWTID
t
DWTR
84
WR
WAIT
t
DAWT
t
DWWTL
t
HWWT
t
DWWTH
Data Sheet U11680EJ2V0DS00
t
DWTW
Refresh Timing Waveform
(1) Random read/write cycle
t
RC
ASTB
WR
t
RC
t
RC
t
RC
RD
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR
µ
PD784907, 784908
t
RC
REFRQ
(3) Refresh after a read
ASTB
RD
REFRQ
(4) Refresh after a write
ASTB
t
DSTRFQ
t
WRFQL
t
t
WRFQH
t
DRRFQ
DRFQST
t
WRFQL
t
DRFQST
WR
REFRQ
tDRFQST
tDWRFQ
tWRFQL
Data Sheet U11680EJ2V0DS0085
Serial Operation (CSI, CSI3)
SCK0, SCK3
t
WSKL0
t
CYSK0
t
WSKH0
µ
PD784907, 784908
SSSK0tHSSK0
t
SI0, SI3
SO0, SO3
Serial Operation (IOE1, IOE2)
SCK1, SCK2
SI1, SI2
SO1, SO2
Serial Operation (UART, UART2)
t
WSKL1
t
CYSK1
t
WASKH
t
WSKH1
t
DSBSK1
Output data
t
DSOSK
Output data
t
WASKL
t
HSBSK1
t
HSOSK
Input data
SSSK1tHSSK1
t
Input data
ASCK,
ASCK2
Clock Output Timing
CLKOUT
86
t
CLR
t
CYASK
t
CLH
t
CLF
t
CYCL
Data Sheet U11680EJ2V0DS00
t
CLL
Interrupt Request Input Timing
NMI
INTP0
t
WNIH
t
WIT0H
t
WIT1H
t
WNIL
t
WIT0L
t
WIT1L
µ
PD784907, 784908
INTP1 to INTP3
INTP4, INTP5
Reset Input Timing
RESET
CI,
t
WIT2H
t
WRSH
t
WIT2L
t
WRSL
Data Sheet U11680EJ2V0DS0087
External Clock Timing
X1
Data Retention Characteristics
STOP mode setting
V
DD
t
HVD
t
FVD
µ
PD784907, 784908
t
WXH
t
XR
t
CYX
V
DDDR
t
RVD
t
WXL
t
XF
t
DREL
t
WAIT
RESET
NMI
(Clearing by falling edge)
NMI
(Clearing by rising edge)
88
Data Sheet U11680EJ2V0DS00
16. PACKAGE DRAWING
100 PIN PLASTIC QFP (14×20)
A
B
µ
PD784907, 784908
81
80
51
50
CD
100
1
30
31
F
G
H
M
I
P
N
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
RemarkThe shape and material of the ES version are the same
as those of the corresponding mass-produced product.
J
K
L
detail of lead end
S
Q
R
M
ITEM MILLIMETERSINCHES
A23.6±0.40.929±0.016
B20.0±0.20.795
C14.0±0.20.551
D17.6±0.40.693±0.016
F0.80.031
G0.60.024
H0.30±0.100.012
I0.150.006
J0.65 (T.P.)0.026 (T.P.)
K1.8±0.20.071
L0.8±0.20.031
M0.150.006
N0.100.004
P2.7±0.10.106
Q0.1±0.10.004±0.004
R5°±5°5°±5°
S3.0 MAX.0.119 MAX.
+0.10
–0.05
P100GF-65-3BA1-3
+0.009
–0.008
+0.009
–0.008
+0.004
–0.005
+0.008
–0.009
+0.009
–0.008
+0.004
–0.003
+0.005
–0.004
Data Sheet U11680EJ2V0DS0089
µ
PD784907, 784908
17. RECOMMENDED SOLDERING CONDITIONS
The µPD784908 should be soldered under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual(C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales represen-
tative.
Table 17-1. Soldering Conditions for Surface Mount Type
CautionDo not use different soldering methods together (except for partial heating).
90
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD784908.
Also refer to (5) Cautions on using development tools.
(1) Language processing software
RA78K4Assembler package common to 78K/IV Series
CC78K4C compiler package common to 78K/IV Series
DF784908Device file for µPD784908 Subseries
CC78K4-LC compiler library source file common to 78K/IV Series
(2) PROM write tools
PG-1500PROM programmer
PA-78P4908GFProgrammer adapter, connects to PG-1500
PG-1500 controllerControl program for PG-1500
(3) Debugging tools
• When using the in-circuit emulator IE-78K4-NS
IE-78K4-NSIn-circuit emulator common to 78K/IV Series
IE-70000-MC-PS-BPower supply unit for IE-78K4-NS
IE-70000-98-IF-CInterface adapter when a PC-9800 Series computer (except notebook type)
is used as the host machine (C bus supported)
IE-70000-CD-IF-AP C card and interface cable when a notebook type is used as the
host machine (PCMCIA socket supported)
IE-70000-PC-IF-CInterface adapter when an IBM PC/ATTM or compatible is used as the host
machine (ISA bus supported)
IE-70000-PCI-IFAdapter when a PC that incorporates a PCI bus is used as the host machine
IE-784908-NS-EM1Emulation board to emulate µPD784908 Subseries
NP-100GF
EV-9200GF-100Socket to be mounted on target system board made for 100-pin plastic QFP
ID78K4-NSIntegrated debugger for IE-78K4-NS
SM78K4System simulator common to 78K/IV Series
DF784908Device file for µPD784908 Subseries
Note
Emulation probe for 100-pin plastic QFP (GF-3BA type)
(GF-3BA type). Used in LCC mode.
Note Under development
Data Sheet U11680EJ2V0DS0091
µ
PD784907, 784908
• When using the in-circuit emulator IE-784000-R
IE-784000-RIn-circuit emulator common to 78K/IV Series
IE-70000-98-IF-CInterface adapter when a PC-9800 Series computer (except notebook type)
is used as the host machine (C bus supported)
IE-70000-PC-IF-CInterface adapter when an IBM PC/AT or compatible is used as the host
machine (ISA bus supported)
IE-70000-PCI-IFAdapter when a PC that incorporates a PCI bus is used as the host machine
IE-78000-R-SV3Interface adapter and cable when the EWS is used as the host machine
IE-784908-NS-EM1Emulation board to emulate µPD784908 Subseries
IE-784908-R-EM1
IE-784000-R-EMEmulation board common to 78K/IV Series
IE-78K4-R-EX2Conversion board for emulation probes required to use the IE-784908-NS-
EM1 on the IE-784000-R. The board is not needed when the conventional
product IE-784908-R-EM1 is used.
EP-78064-GF-REmulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100Socket to be mounted on target system board made for 100-pin plastic QFP
(GF-3BA type)
ID78K4Integrated debugger for IE-784000-R
SM78K4System simulator common to 78K/IV Series
DF784908Device file for µPD784908 Subseries
(4) Real-time OS
RX78K/IVReal-time OS for 78K/IV Series
MX78K4OS for 78K/IV Series
92
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
(5) Cautions on using development tools
• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784908.
• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784908.
• The NP-100GF is a product made by Naito Densei Machidaseisakusho Co., Ltd. (+81-44-822-3813). Contact
an NEC distributor regarding the purchase of these products.
• The host machines and OSs suitable for each software are as follows.
PD784908 Subseries Special Function Register TableU11589J—
78K/IV Series User's Manual InstructionsU10905JU10905E
78K/IV Series Instruction TableU10594J—
78K/IV Series Instruction SetU10595J—
78K/IV Series Application Note Software BasicsU10095JU10095E
Documents related to development tools (User's Manual)
Document NameDocument No.
JapaneseEnglish
RA78K4 Assembler PackageLanguageU11162JU11162E
OperationU11334JU11334E
RA78K4 Structured Assembler PreprocessorU11743JU11743E
CC78K4 C CompilerLanguageU11571JU11571E
OperationU11572JU11572E
PG-1500 PROM ProgrammerU11940JU11940E
PG-1500 Controller PC-9800 Series (MS-DOSTM) BasedEEU-704EEU-1291
PG-1500 Controller IBM PC Series (PC DOSTM) BasedEEU-5008U10540E
IE-78K4-NSU13356JU13356E
IE-784000-RU12903JU12903E
IE-784908-R-EM1U11876J—
IE-784908-NS-EM1U13743JUnder preparation
EP-78064EEU-934EEU-1469
SM78K4 System Simulator Windows BasedReferenceU10093JU10093E
SM78K Series System SimulatorExternal Part User OpenU10092JU10092E
Interface Specifications
ID78K4-NS Integrated Debugger PC BasedReferenceU12796JU12796E
ID78K4 Integrated Debugger Windows BasedReferenceU10440JU10440E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS BasedReferenceU11960JU11960E
CautionThe above documents may be revised without notice. Use the latest versions when you design
application systems.
94
Data Sheet U11680EJ2V0DS00
µ
PD784907, 784908
Documents related to embedded software (User's Manual)
Document NameDocument No.
JapaneseEnglish
78K/IV Series Real-Time OSFundamentalU10603JU10603E
InstallationU10604JU10604E
DebuggerU10364J—
78K/IV Series OS MX78K4FundamentalU11779J—
Other documents
Document NameDocument No.
JapaneseEnglish
NEC IC PACKAGE MANUAL (CD-ROM)—C13388E
Semiconductor Device Mounting Technology ManualC10535JC10535E
Quality Grades on NEC Semiconductor DeviceC11531JC11531E
NEC Semiconductor Device Reliability/Quality Control SystemC10983JC10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)C11892JC11892E
Guide to Quality Assurance for Semiconductor Devices—MEI-1202
Guide to Microcontroller-Related Products by Third PartiesU11416J—
CautionThe above documents may be revised without notice. Use the latest versions when you design
application systems.
Data Sheet U11680EJ2V0DS0095
µ
PD784907, 784908
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
96
Data Sheet U11680EJ2V0DS00
µ
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J98. 11
PD784907, 784908
Data Sheet U11680EJ2V0DS0097
µ
PD784907, 784908
FIP, IEBus, and EEPROM are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents in this publication may include preliminary version. However, what preliminary versions
are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
Data Sheet U11680EJ2V0DS00
M4 96. 5
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