NEC PD784907, PD784908 Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD784907, 784908

16-BIT SINGLE-CHIP MICROCONTROLLER

The μPD784907 and μPD784908 are products of the μPD784908 Subseries in the 78K/IV Series. These products contain various peripheral hardware such as IEBusTM controller, ROM, RAM, I/O ports, 8-bit resolution A/D, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU.

In addition, the μPD78P4908 (one-time PROM product), which is used to evaluate the functions of mask ROM versions, and development tools are also available.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

	μPD784908 Subseries User's Manual Hardware : U11787E
	78K/IV Series User's Manual Instruction		: U10905E
FEATURES
• 78K/IV Series		• Watchdog timer: 1 channel
• Minimum instruction execution time: 320 ns (at 6.29 MHz)		• Clock output function
	160 ns (at 12.58 MHz)	Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16
• Number of I/O ports: 80		• A/D converter:	8-bit resolution × 8 channels
• Timer/counters: 16-bit timer/counter × 3 units		• On-chip IEBus controller
16-bit timer × 1 unit		• Watch timer
• Serial interface: 4 channels		• Low-power consumption
UART/IOE (3-wire serial I/O): 2 channels		• Supply voltage: VDD = 4.0 to 5.5 V
CSI (3-wire serial I/O):	2 channels		(Main clock: fXX = 12.58 MHz,
• PWM outputs: 2			internal system clock = fXX,
• Standby function			fCYK = 79 ns)
HALT/STOP/IDLE mode			VDD = 3.5 to 5.5 V
• Clock frequency division function			(Other than above, fCYK = 159 ns)

APPLICATIONS

Car audios, etc.

This document describes the μPD784908 unless otherwise specified.

The information in this document is subject to change without notice.

Document No. U11680EJ2V0DS00 (2nd edition)	The mark shows major revised points.
Date Published February 1999 N CP(K)
Printed in Japan	©		1996

μPD784907, 784908

ORDERING INFORMATION

Part number	Package	Internal ROM	Internal RAM
		(bytes)	(bytes)
μPD784907GF-×××-3BA	100-pin plastic QFP (14 × 20 mm)	96 K	3,584
μPD784908GF-×××-3BA	100-pin plastic QFP (14 × 20 mm)	128 K	4,352

Remark ××× indicates ROM code suffix.

2	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

78K/IV SERIES PRODUCT LINEUP

: Under mass production

: Under development

Standard models

μPD784026

Enhanced A/D,

16-bit timer, and power management

ASSP models

μPD784955

For DC inverter control

μPD784908

On-chip IEBus controller

μPD784915

For software servo control, on-chip analog circuit

for VCR, enhanced timer

		I2C bus supported					Multi-master I2C bus supported
			μPD784038Y						μPD784225Y
		μPD784038							μPD784225
	Enhanced internal memory capacity,						80 pins,
	pin compatible with the μPD784026						ROM correction added
Multi-master I2C bus supported							Multi-master I2C bus supported
		μ							μPD784218Y
		PD784216Y
		μPD784216							μPD784218
	100 pins,						Enhanced internal memory capacity,
	enhanced I/O and						ROM correction added
	internal memory capacity
			μ
			PD784054
		μ
		PD784046
On-chip 10-bit A/D

μPD784938

Enhanced functions of the μPD784908, enhanced internal memory capacity, ROM correction added

Multi-master I2C bus supported

μPD784928Y

μPD784928

Enhanced functions of the μPD784915

Data Sheet U11680EJ2V0DS00

3

										μPD784907, 784908
	FUNCTIONS
					Part Number	μPD784907				μPD784908
	Item
	Number of basic instructions					113
	(mnemonics)
	General-purpose register					8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
	Minimum instruction execution					320 ns/636 ns/1.27 μs/2.54 μs (at 6.29 MHz)
	time					160 ns/320 ns/636 ns/1.27 μs (at 12.58 MHz)
	Internal				ROM	96 K			128 K
	memory
					RAM	3,584 bytes			4,352 bytes
	Memory space					1 Mbyte with program and data spaces combined
	I/O ports				Total	80
					Input	8
					Input/output	72
		Additional			LED direct	24
		function			drive outputs
		pins Note
					Transistor	8
					direct drive
					N-ch open	4
					drain
	Real-time output ports					4 bits × 2, or 8 bits × 1
	IEBus controller					Incorporated (simplified)
	Timer/counter					Timer/counter 0:	Timer register × 1			Pulse output capability
						(16 bits)	Capture register × 1			• Toggle output
							Compare register × 2			• PWM/PPG output
										• One-shot pulse output
						Timer/counter 1:	Timer register × 1			Real-time output port
						(16 bits)	Capture register × 1
							Capture/compare register × 1
							Compare register × 1
						Timer/counter 2:	Timer register × 1			Pulse output capability
						(16 bits)	Capture register × 1			• Toggle output
							Capture/compare register × 1			• PWM/PPG output
							Compare register × 1
						Timer 3:	Timer register × 1
						(16 bits)	Compare register × 1
	Watch timer					Interrupt requests are generated at 0.5-second intervals. (A watch clock oscillator is
						incorporated.)
						Either the main clock (6.29 MHz/12.58 MHz) or watch clock (32.7 kHz) can be selected
						as the input clock.
	Clock output					Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
	PWM outputs					12-bit resolution × 2 channels
	Serial interface					UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
						CSI (3-wire serial I/O):		2 channels
	A/D converter					8-bit resolution × 8 channels

Note Additional function pins are included in the I/O pins.

4	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

		Part Number	μPD784907	μPD784908
Item
Watchdog timer			1 channel
Standby			HALT/STOP/IDLE modes
Interrupt		Hardware source	27 (20 internal, 7 external (sampling clock variable input: 1))
		Software source	BRK or BRKCS instruction, operand error
		Non-maskable	1 internal, 1 external
		Maskable	19 internal, 6 external
			4-level programmable priority
			3 operation statuses: vectored interrupt, macro service, context switching
Power supply voltage			VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns)
			VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns)
Package			100-pin plastic QFP (14 × 20 mm)

Data Sheet U11680EJ2V0DS00

5

μPD784907, 784908

			CONTENTS
1.	DIFFERENCES BETWEEN μPD784908 SUBSERIES PRODUCTS .......................................			8
2.	MAJOR DIFFERENCES BETWEEN μPD784908 AND μPD78098 SUBSERIES ..................			9
3.	PIN CONFIGURATION (TOP VIEW) .........................................................................................			10
4.	SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK)) .....			12
5.	BLOCK DIAGRAM .....................................................................................................................			13
6.	PIN FUNCTION ...........................................................................................................................			14
	6.1	Port Pins ............................................................................................................................................		14
	6.2	Non-Port Pins ...................................................................................................................................		16
	6.3	Pin I/O Circuits and Recommended Connections of Unused Pins ..........................................		18
7.	CPU ARCHITECTURE ...............................................................................................................			22
	7.1	Memory Space ..................................................................................................................................		22
	7.2	CPU Registers ..................................................................................................................................		25
		7.2.1	General - purpose registers ................................................................................................	25
		7.2.2	Control registers ................................................................................................................	26
		7.2.3 Special function registers (SFRs) ....................................................................................		27
8.	PERIPHERAL HARDWARE FUNCTIONS ................................................................................			33
	8.1	Ports	...................................................................................................................................................	33
	8.2	Clock Generator ...............................................................................................................................		35
	8.3	Real-Time .....................................................................................................................Output Port		38
	8.4	Timers/Counters ...............................................................................................................................		39
	8.5	Watch ......................................................................................................................................Timer		41
	8.6	PWM ..........................................................................................................Output (PWM0, PWM1)		42
	8.7	A/D Converter ...................................................................................................................................		43
	8.8	Serial .................................................................................................................................Interface		44
		8.8.1 .......................................Asynchronous serial interface/3-wire serial I/O (UART/IOE)		45
		8.8.2 ...........................................................................................Clocked serial interface (CSI)		47
	8.9	Clock ....................................................................................................................Output Function		48
	8.10	Edge ................................................................................................................Detection Function		49
	8.11	Watchdog ...............................................................................................................................Timer		49
	8.12	Simplified ............................................................................................................IEBus Controller		50
9.	INTERRUPT ............................................................................................................FUNCTION			53
	9.1	Interrupt ...............................................................................................................................Source		53
	9.2	Vectored ............................................................................................................................Interrupt		55
	9.3	Context ............................................................................................................................Switching		56
	9.4	Macro ...................................................................................................................................Service		56
	9.5	Examples ....................................................................................of Macro Service Applications		57

6	Data Sheet U11680EJ2V0DS00

			μPD784907, 784908
10.	LOCAL BUS INTERFACE .........................................................................................................		59
	10.1	Memory Expansion ..........................................................................................................................	59
	10.2	Memory Space ..................................................................................................................................	60
	10.3	Programmable Wait .........................................................................................................................	61
	10.4	Pseudo-Static RAM Refresh Function ..........................................................................................	61
	10.5	Bus Hold Function ...........................................................................................................................	61
11.	STANDBY FUNCTION ...............................................................................................................		62
12.	RESET FUNCTION .....................................................................................................................		63
13.	REGULATOR ..............................................................................................................................		64
14.	INSTRUCTION SET ....................................................................................................................		65
15.	ELECTRICAL SPECIFICATIONS ..............................................................................................		70
16.	PACKAGE DRAWING ................................................................................................................		89
17.	RECOMMENDED SOLDERING CONDITIONS ........................................................................		90
APPENDIX A DEVELOPMENT TOOLS ..........................................................................................			91
APPENDIX B RELATED DOCUMENTS .........................................................................................			94

Data Sheet U11680EJ2V0DS00

7

μPD784907, 784908

1. DIFFERENCES BETWEEN μPD784908 SUBSERIES PRODUCTS

The only difference between the μPD784907 and μPD784908 is their internal memory capacities.

The μPD78P4908 is produced by replacing the mask ROM in the μPD784907 or μPD784908 with 128-Kbyte onetime PROM. Table 1-1 shows the differences between these products.

Table 1-1. Differences between the μPD784908 Subseries Products

Part Number	μPD784907	μPD784908	μPD78P4908
Item
Internal ROM	96 K (mask ROM)	128 K (mask ROM)	128 K (one-time PROM)
Internal RAM	3,584 bytes	4,352 bytes
Regulator		Provided	None
Power supply voltage	VDD = 4.0 to 5.5 V		VDD = 4.5 to 5.5 V
	(Main clock: fXX = 12.58 MHz, internal system clock = fXX,		(Main clock: fXX = 12.58 MHz,
	fCYK = 79 ns)		internal system clock = fXX,
	VDD = 3.5 to 5.5 V		fCYK = 79 ns)
	(other than above, fCYK = 159 ns)		VDD = 4.0 to 5.5 V
			(other than above,
			fCYK = 159 ns)
Electrical specifications	Refer to the data sheet of each product.

8	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

2. MAJOR DIFFERENCES BETWEEN μPD784908 AND μPD78098 SUBSERIES

Series Name	μPD784908 Subseries	μPD78098 Subseries
Item
Number of basic instructions	113	63
(mnemonics)
Minimum instruction execution	320/160 ns	480 ns
time	(at 6.29/12.58 MHz operation)	(at 6.29 MHz operation)
Timer/counter	16-bit timer/counter × 1	16-bit timer/counter × 1
	8/16-bit timer/counter × 2	8/16-bit timer/counter × 2
	8/16-bit timer × 1	Watch timer
	Watch timer
	Single clock	Dual clock
	Watch clock for clock operation
Watchdog timer	Provided
Serial interface	UART/IOE (3-wire serial I/O): 2 channels	UART (3-wire serial I/O): 1 channel
	CSI (3-wire serial I/O): 2 channels	CSI/SBI (3-wire serial I/O): 1 channel
		CSI (3-wire serial I/O): 1 channel

PWM output			2	None
A/D converter			8-bit resolution × 8 channels
D/A converter			None
Interrupt		Hardware source	27	23 (two test flags)
		Internal	20	14
		External	7	7
External extended function			Provided (up to 1 Mbyte)	None
IEBus controller			Incorporated (simplified)	Incorporated (complete hardware)
Power supply voltage			• Mask ROM version	VDD = 2.7 to 6.0 V
			VDD = 4.0 to 5.5 V
			(Main clock: fXX = 12.58 MHz,
			internal system clock = fXX, fCYK = 79 ns)
			VDD = 3.5 to 5.5 V
			(other than above, fCYK = 159 ns)

•PROM version VDD = 4.5 to 5.5 V

(Main clock: fXX = 12.58 MHz,

internal system clock = fXX, fCYK = 79 ns) VDD = 4.0 to 5.5 V

(other than above, fCYK = 159 ns)

Package	100-pin plastic QFP (14 × 20 mm)	80-pin plastic QFP (14 × 14 mm)
		80-pin plastic WQFN (14 × 14 mm):
		μPD78P098A only

Data Sheet U11680EJ2V0DS00

9

μPD784907, 784908

3. PIN CONFIGURATION (TOP VIEW)

• 100-pin plastic QFP (14 × 20 mm)

μPD784907GF-×××-3BA

μPD784908GF-×××-3BA

	P35/TO1	P34/TO0 P33/SO0 P32/SCK0 P31/TxD/SO1	P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1	P21/INTP0 P20/NMI TX RX AVSS	AVREF1	AVDD	P77/ANI7
P36/TO2	100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81							P76/ANI6
	1						80
P37/TO3	2						79	P75/ANI5
P100	3						78	P74/ANI4
P101	4						77	P73/ANI3
P102	5						76	P72/ANI2
P103	6						75	P71/ANI1
P104	7						74	P70/ANI0
P105/SCK3	8						73	TEST Note 1
P106/SI3	9						72	PWM1
P107/SO3	10						71	PWM0
RESET	11						70	P17
XT2	12						69	P16
XT1	13						68	P15
VSS	14						67	P14/TxD2/SO2
X2	15						66	P13/RxD2/SI2
X1	16						65	P12/ASCK2/SCK2
REGOFF Note 2	17						64	P11
REGC Note 3	18						63	P10
VDD	19						62	ASTB/CLKOUT
P00	20						61	P90
P01	21						60	P91
P02	22						59	P92
P03	23						58	P93
P04	24						57	P94
P05	25						56	P95
P06	26						55	P96
P07	27						54	P97
P67/REFRQ/HLDAK	28						53	P40/AD0
P66/WAIT/HLDRQ	29						52	P41/AD1
P65/WR	30						51	P42/AD2
	31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
	P64/RD	P63/A19 P62/A18 P61/A17 P60/A16	P57/A15 P56/A14 P55/A13 P54/A12 VSS VDD P53/A11	P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6	P45/AD5	P44/AD4	P43/AD3

Notes 1. Connect the TEST pin directly to VSS.

2.Connect the REGOFF pin directly to VSS (select regulator operation).

3.Connect the REGC pin to VSS via a capacitor of the order of 1 μF.

10	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

A8 to A19:

Address bus

PWM0, PWM1:

Pulse width modulation output

AD0 to AD7:

Address/data bus

RD:

Read strobe

ANI0 to ANI7:

Analog input

Refresh request

REFRQ:

ASCK, ASCK2:

Asynchronous serial clock

REGC:

Regulator capacitance

ASTB:

Address strobe

REGOFF:

Regulator off

AVDD:

Analog power supply

Reset

RESET:

AVREF1:

Reference voltage

IEBus receive data

RX:

AVSS:

Analog ground

RXD, RXD2:

Receive data

CI:

Clock input

to

Serial clock

SCK0

SCK3:

CLKOUT:

Clock output

SI0 to SI3:

Serial input

HLDAK:

Hold acknowledge

SO0 to SO3:

Serial output

HLDRQ:

Hold request

TEST:

Test

INTP0 to INTP5:

Interrupt from peripherals

TO0 to TO3:

Timer output

NMI:

Non-maskable interrupt

IEBus transmit data

TX:

P00 to P07:

Port 0

TXD, TXD2:

Transmit data

P10 to P17:

Port 1

VDD:

Power supply

P20 to P27:

Port 2

VSS:

Ground

P30 to P37:

Port 3

WAIT:

Wait

Write strobe

P40 to P47:

Port 4

WR:

P50 to P57:

Port 5

X1, X2:

Crystal (main system clock)

P60 to P67:

Port 6

XT1, XT2:

Crystal (watch)

P70 to P77:

Port 7

P90 to P97:

Port 9

P100 to P107:

Port 10

Data Sheet U11680EJ2V0DS00

11

μPD784907, 784908

4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK))

Front panel

μPD784908

	Remote-controll	Interrupt input
	signal reception
	circuit	General-purpose
	μ	port
	PC2800A, etc.
FIPTM	Key
	matrix
	FIP	3-wire serial I/O
		SIO with automatic
	controller/driver
		transmission/reception
	μPD16312, etc.
		function
LED		REGOFF
display
	Audio control	REGC
	circuit

Electronic			3-wire serial I/O
volume

IEBus controller

EEPROMTM

IEBus

Cassette deck unit

Tuner pack	CD unit
	CD changer,
	one CD, etc.

DSP unit

TV unit

IEBus driver/ receiver

12	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

	5. BLOCK DIAGRAM
	NMI	Programmable
	INTP0 to INTP5	interrupt controller
	INTP3	Timer/counter 0
	TO0
		(16 bits)
	TO1
	INTP0	Timer/counter 1
		(16 bits)
	INTP1
	INTP2/CI	Timer/counter 2
	TO2	(16 bits)
	TO3
		Timer 3
		(16 bits)
	P00 to P03	Real-time output
	P04 to P07	port
	PWM0
	PWM1	PWM
	ANI0 to ANI7
	AVDD
	AVREF1	A/D converter
	AVSS
	INTP5
	TX
	RX	IEBus controller
	RESET
	TEST
	X1	System control
	X2
	REGC	(regulator)
	REGOFF
	VDD
	VSS
	XT1
	XT2	Watch timer

			UART/IOE2
			Baud-rate
			generator
			UART/IOE1
			Baud-rate
			generator
			Clocked serial
			interface
	78K /IV	ROM
	CPU core		Clocked serial
			interface 3
			Clock output
			Bus interface
	RAM
			Port 0
			Port 1
			Port 2
			Port 3
			Port 4
			Port 5
	Watchdog timer		Port 6
			Port 7
			Port 9
			Port 10

RxD/SI1

TxD/SO1

ASCK/SCK1

RxD2/SI2

TxD2/SO2

ASCK2/SCK2

SCK0

SO0

SI0

SCK3

SO3

SI3

ASTB /CLKOUT

AD0 to AD7 A8 to A15 A16 to A19

RD

WR

WAIT/HLDRQ

REFRQ/HLDAK

P00 to P07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P90 to P97

P100 to P107

Remark The internal ROM and RAM capacities differ depending on the product.

Data Sheet U11680EJ2V0DS00

13

μPD784907, 784908

6. PIN FUNCTIONS

6.1Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00 to P07

I/O

—

Port 0 (P0):

•

8-bit I/O port.

•

Can be used as a real-time output port (4 bits × 2).

•

Input and output can be specified by 1-bit units.

•

The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

•

Can drive transistors.

P10

I/O

—

Port 1 (P1):

•

8-bit I/O port.

P11

—

•

Input and output can be specified in 1-bit units.

P12

ASCK2/SCK2

•

The use of on-chip pull-up resistors can be simultaneously specified by

P13

RxD2/SI2

software for all pins in input mode.

P14

TxD2/SO2

•

Can drive LEDs.

P15 to P17

—

P20

Input

NMI

Port 2 (P2):

•

8-bit input port.

P21

INTP0

• P20 does not function as a general-purpose port (non-maskable interrupt).

P22

INTP1

However, the input level can be checked by an interrupt service routine.

P23

INTP2/CI

•

The use of on-chip pull-up resistors can be specified by software for pins

P24

INTP3

P22 to P27 (in 6-bit units).

P25

•

The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by a

INTP4/ASCK/SCK1

CSIM1 specification.

P26

INTP5

P27

SI0

P30

I/O

RxD/SI1

Port 3 (P3):

•

8-bit I/O port.

P31

TxD/SO1

•

Input and output can be specified in 1-bit units.

P32

SCK0

•

The use of on-chip pull-up resistors can be simultaneously specified by

P33

SO0

software for all pins in input mode.

P34 to P37

TO0 to TO3

•

The use of the N-ch open drain can be specified for pins P32 and P33.

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

•

8-bit I/O port.

•

Input and output can be specified in 1-bit units.

•

The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LEDs.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

•

8-bit I/O port.

•

Input and output can be specified in 1-bit units.

•

The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LEDs.

14	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

6.1Port Pins (2/2)

Pin Name	I/O			Alternate Function						Function
P60 to P63	I/O			A16 to A19					Port 6 (P6):
									•	8-bit I/O port.
P64				RD
									•	Input and output can be specified in 1-bit units.
P65				WR
									•	The use of on-chip pull-up resistors can be simultaneously specified by
P66
				WAIT/HLDRQ						software for all pins in input mode.
P67
				REFRQ/HLDAK
P70 to P77	I/O			ANI0 to ANI7					Port 7 (P7):
									•	8-bit I/O port.
									•	Input and output can be specified in 1-bit units.
P90 to P97	I/O							—	Port 9 (P9):
									•	8-bit I/O port.
									•	Input and output can be specified in 1-bit units.
									•	The use of on-chip pull-up resistors can be simultaneously specified by
										software for all pins in input mode.
P100 to	I/O							—	Port 10 (P10):
P104									•	8-bit I/O port.
									•	Input and output can be specified in 1-bit units.
P105				SCK3
									•	The use of on-chip pull-up resistors can be simultaneously specified by
P106				SI3
										software for all pins in input mode.
P107				SO3					•	The use of the N-ch open drain can be specified for pins P105 and P107.

Data Sheet U11680EJ2V0DS00

15

μPD784907, 784908

6.2Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TO0 to TO3

Output

P34 to P37

Timer output

CI

Input

P23/INTP2

Input of a count clock for timer/counter 2

RxD

Input

P30/SI1

Serial data input (UART0)

RxD2

P13/SI2

Serial data input (UART2)

TxD

Output

P31/SO1

Serial data output (UART0)

TxD2

P14/SO2

Serial data output (UART2)

ASCK

Input

Baud rate clock input (UART0)

P25/INTP4/SCK1

ASCK2

P12/SCK2

Baud rate clock input (UART2)

SI0

Input

P27

Serial data input (3-wire serial I/O 0)

SI1

P30/RxD

Serial data input (3-wire serial I/O 1)

SI2

P13/RxD2

Serial data input (3-wire serial I/O 2)

SI3

P106

Serial data input (3-wire serial I/O 3)

SO0

Output

P33

Serial data output (3-wire serial I/O 0)

SO1

P31/TxD

Serial data output (3-wire serial I/O 1)

SO2

P14/TxD2

Serial data output (3-wire serial I/O 2)

SO3

P107

Serial data output (3-wire serial I/O 3)

I/O

P32

Serial clock I/O (3-wire serial I/O 0)

SCK0

SCK1

P25/INTP4/ASCK

Serial clock I/O (3-wire serial I/O 1)

P12/ASCK2

Serial clock I/O (3-wire serial I/O 2)

SCK2

SCK3

P105

Serial clock I/O (3-wire serial I/O 3)

NMI

Input

P20

External interrupt

—

INTP0

P21

request

• Input of a count clock for timer/counter 1

• Capture/trigger signal for CR11 or CR12

INTP1

P22

• Input of a count clock for timer/counter 2

•

Capture/trigger signal for CR22

INTP2

P23/CI

• Input of a count clock for timer/counter 2

•

Capture/trigger signal for CR21

INTP3

P24

• Input of a count clock for timer/counter 0

•

Capture/trigger signal for CR02

INTP4

—

P25/ASCK/SCK1

INTP5

P26

Input of a conversion start trigger for A/D converter

AD0 to AD7

I/O

P40 to P47

Time multiplexing address/data bus (for connecting external memory)

A8 to A15

Output

P50 to P57

High-order address bus (for connecting external memory)

A16 to A19

Output

P60 to P63

High-order address bus during address expansion (for connecting external

memory)

Output

P64

Strobe signal output for reading the contents of external memory

RD

Output

P65

Strobe signal output for writing on external memory

WR

Input

P66/HLDRQ

Wait insertion

WAIT

Output

P67/HLDAK

Refresh pulse output to external pseudo static memory

REFRQ

HLDRQ

Input

Input of bus hold request

P66/WAIT

HLDAK

Output

Output of bus hold response

P67/REFRQ

ASTB

Output

CLKOUT

Latch timing output of time multiplexing address (A0 to A7) (for connecting

external memory)

16	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

6.2Non-Port Pins (2/2)

	Pin Name			I/O	Alternate Function	Function
	CLKOUT			Output	ASTB	Clock output
	PWM0			Output	—	PWM output 0
	PWM1			Output	—	PWM output 1
	RX			Input	—	Data input (IEBus)
				Output	—	Data output (IEBus)
	TX
	REGC			—	—	Capacitance connection for stabilizing the regulator output/power supply
						when the regulator is stopped. Connect to VSS via a capacitor of order of 1μF.
	REGOFF			—	—	Signal for specifying regulator operation
	RESET			Input	—	Chip reset
	X1			Input	—	Crystal input for system clock oscillation (A clock pulse can also be input
						to the X1 pin.)
	X2			—
	XT1			Input	—	Watch clock connection
	XT2			—	—
	ANI0 to ANI7			Input	P70 to P77	Analog voltage input for A/D converter
	AVREF1			—	—	To apply the reference voltage for A/D converter
	AVDD					Positive power supply for A/D converter
	AVSS					GND for A/D converter
	VDD					Positive power supply
	VSS					GND
	TEST			Input		Connect directly to VSS. (This pin is for IC test.)

Data Sheet U11680EJ2V0DS00

17

μPD784907, 784908

6.3Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-1.

For each type of input/output circuit, refer to Figure 6-1.

Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00 to P07

5-A

I/O

Input:

Connect to VDD

Output: Leave open

P10, P11

P12/ASCK2/SCK2

8-A

P13/RxD2/SI2

5-A

P14/TxD2/SO2

P15 to P17

P20/NMI

2

Input

Connect to VDD or VSS

P21/INTP0

P22/INTP1

2-A

Connect to VDD

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1

8-A

I/O

Input:

Connect to VDD

Output: Leave open

P26/INTP5

2-A

Input

Connect to VDD

P27/SI0

P30/RxD/SI1

5-A

I/O

Input:

Connect to VDD

Output: Leave open

P31/TxD/SO1

10-A

P32/SCK0

P33/SO0

P34/TO0 to P37/TO3

5-A

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0 to P77/ANI7

20

I/O

Input:

Connect to VDD or VSS

Output: Leave open

P90 to P97

5-A

P100 to P104

10-A

P105/SCK3

P106/SI3

8-A

P107/SO3

10-A

ASTB/CLKOUT

4

Output

Leave open

18	Data Sheet U11680EJ2V0DS00

									μPD784907, 784908
					Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (2/2)
					Pin Name		I/O Circuit Type	I/O	Recommended Connections of Unused Pins
						2		Input	—
		RESET
		TEST				1			Connect directly to VSS
		XT2					—	—	Leave open
		XT1					—	Input	Connect to VSS
		PWM0, PWM1				3		Output	Leave open
						1		Input	Connect to VDD or VSS
		RX
						3		Output	Leave open
		TX
		AVREF1					—	—	Connect to VSS
		AVSS
		AVDD							Connect to VDD

Caution Connect an I/O pin, whose input/output mode is undefined, to VDD via a resistor of several 10 kΩ (especially if the voltage on the reset input pin rises higher than the low level input at power on or when the mode is being switched between input and output by software).

Remark Since type numbers are commonly used in the 78K Series, these numbers are not always serial in each

product (some circuits are not included).

Data Sheet U11680EJ2V0DS00

19

μPD784907, 784908

		Figure 6-1. I/O Circuits for Pins
Type 1			Type 4
				VDD
		VDD	Data	P
		P		OUT
IN			Output	N
			disable
		N
			Push-pull output which can output high impedance
			(both the positive and negative channels are off.)
Type 2			Type 5-A
				VDD
			Pull-up	P
			enable
				VDD
IN
			Data	P
				IN/OUT
Schmitt trigger input with hysteresis characteristics			Output	N
			disable
			Input
			enable
Type 2-A			Type 8-A
	VDD			VDD
			Pull-up	P
		Pull-up	enable
	P			VDD
		enable
			Data	P
IN				IN/OUT
			Output	N
			disable
Schmitt trigger input with hysteresis characteristics
Type 3			Type 10-A
				VDD
		VDD	Pull-up	P
			enable
		P-ch		VDD
			Data	P
Data		OUT
				IN/OUT
			Open
		N-ch	drain	N
			Output
			disable

20	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

	Type 20	VDD
	Data	P
		IN/OUT
	Output	N
	disable
	Comparator	P
	+
		N
	–
	VREF
	(Threshold voltage)
	Input
	enable

Data Sheet U11680EJ2V0DS00

21

μPD784907, 784908

7. CPU ARCHITECTURE

7.1Memory Space

A memory space of 1 Mbyte can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once.

(1)When the LOCATION 0 instruction is executed

•Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number	Internal Data Area	Internal ROM Area
μPD784907	0F100H to 0FFFFH	00000H to 0F0FFH
		10000H to 17FFFH
μPD784908	0EE00H to 0FFFFH	00000H to 0FDFFH
		10000H to 1FFFFH

Caution The following internal ROM areas, existing at the same addresses as the internal data areas,

cannot be used when the LOCATION 0 instruction is executed:

Part Number	Unusable Area
μPD784907	0F100H to 0FFFFH (3,840 bytes)
μPD784908	0EE00H to 0FFFFH (4,608 bytes)

•External memory

The external memory is accessed in external memory expansion mode.

(2)When the LOCATION 0FH instruction is executed

•Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number	Internal Data Area	Internal ROM Area
μPD784907	FF100H to FFFFFH	00000H to 17FFFH
μPD784908	FEE00H to FFFFFH	00000H to 1FFFFH

•External memory

The external memory is accessed in external memory expansion mode.

22	Data Sheet U11680EJ2V0DS00

U11680EJ2V0DS00 Sheet Data

23

Figure 7-1. μPD784907 Memory Map

F FFF FH

1 8 0 0 0H

1 7FFFH

1 0 0 0 0H

0 FFFFH

0 FFDFH

0 FFD0H

0 FF 0 0H

0 FEFFH

0 F1 0 0H

0 F0 FFH

0 0 0 0 0H

When the LOCATION 0 instruction is executed

External memory (928 Kbytes)Note 1

Internal ROM (32,768 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (3,584 bytes)

Internal ROM

Note 4

(61,696 bytes)

	0 FEFFH
		General-purpose
		registers (128 bytes)
	0 FE8 0H
	0 FE7 FH
	0 FE3 9H
		Macro service control
	0 FE0 6H	word area (42 bytes)
	0 FD0 0H	Data area (512 bytes)
	0 FCF FH	Program/data area
	0 F1 0 0H	(3,072 bytes)
	1 7 F F F H
	1 0 0 0 0 H
		Note 2
	0 F0 FFH	Program/data areaNote 3
	0 1 0 0 0H
	0 0F FFH	CALLF entry area
	0 0 8 0 0H	(2 Kbytes)
	0 0 7 FFH
	0 0 0 8 0H
	0 0 0 7 FH	CALLT table area
	0 0 0 4 0H	(64 bytes)
	0 0 0 3 FH	Vector table area
	0 0 0 0 0H	(64 bytes)

F F F F F H

F F F D F H

F F F D 0 H

F F F 0 0 H

F FEF FH F FEFFH

F FE8 0H	F F1 0 0H
F FE7 FH	F F0 F FH

F FE3 9H

F FE0 6H

F FD0 0H

F FCF FH

F F1 0 0H

1 7F FFH

1 8 0 0 0H

1 7FFFH

0 0 0 0 0H

When the LOCATION 0FH instruction is executed

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (3,584 bytes)

External memory (946,432 bytes)Note 1

	Internal ROM	Note 4
	(96 Kbytes)

Notes 1. Accessed in external memory expansion mode.

2.This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3.When the LOCATION 0 instruction is executed: 94,464 bytes When the LOCATION 0FH instruction is executed: 98,304 bytes

4.Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

784908 PD784907,μ

24

U11680EJ2V0DS00 Sheet Data

FF F FFH

20 0 0 0H

1FF F FH

10 0 0 0H

0FF F FH

0FFDFH

0FFD0H

0FF 0 0H 0FEF FH

0EE0 0H 0EDFFH

00 0 0 0H

When the LOCATION 0 instruction is executed

External memory (896 Kbytes)Note 1

Internal ROM (65,536 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (4,352 bytes)

	Internal ROM	Note 4
	(60,928 bytes)

Figure 7-2. μPD784908 Memory Map

0FEFFH
	General-purpose
	registers (128 bytes)
0FE8 0H
0FE7 FH
0FE3 9H
	Macro service control
0FE0 6H	word area (42 bytes)
0FD0 0H	Data area (512 bytes)
0FCF FH	Program/data area
0EE0 0H	(3,840 bytes)
1 F F F F H
1 0 0 0 0 H
	Note 2
0EDFFH	Program/data areaNote 3
01 0 0 0H
00 FFFH	CALLF entry area
00 8 0 0H	(2 Kbytes)
00 7 FFH
00 0 8 0H
00 0 7 FH	CALLT table area
00 0 4 0H	(64 bytes)
00 0 3 FH	Vector table area
00 0 0 0H	(64 bytes)

F F F F F H

F F F D F H

F F F D 0 H

F F F 0 0 H

FFEF FH FFEFFH

FFE8 0H	FEE0 0H
FFE7 FH	FEDFFH

FFE3 9H

FFE0 6H

FFD0 0H

FFCFFH

FEE0 0H

1F FFFH

20 0 0 0H

1F FFFH

00 0 0 0H

When the LOCATION 0FH instruction is executed

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (4,352 bytes)

External memory (912,896 bytes)Note 1

Internal ROM

(128 Kbytes)	Note 4

Notes 1. Accessed in external memory expansion mode.

2.This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3.When the LOCATION 0 instruction is executed: 126,464 bytes When the LOCATION 0FH instruction is executed: 131,072 bytes

4.Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

784908 PD784907,μ

μPD784907, 784908

7.2CPU Registers

7.2.1General-purpose registers

A set of general-purpose registers consists of sixteen 8-bit general-purpose registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.

Eight banks of this register set are provided. The user can switch between banks by software or the context switching function.

General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM.

Figure 7-3. General-Purpose Register Format

	A (R1)	X (R0)
		AX (RP0)
	B (R3)	C (R2)
		BC (RP1)
	R5	R4
		RP2
	R7	R6
		RP3
V	R9	R8

	VVP (RG4)	VP (RP4)
U	R11		R10
	UUP (RG5)	UP (RP5)
T	D (R13)		E (R12)
	TDE (RG6)	DE (RP6)
W	H (R15)		L (R14)
	WHL (RG7)	HL (RP7)				8 banks

The character strings enclosed in parentheses represent absolute names.

Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series.

Data Sheet U11680EJ2V0DS00

25

μPD784907, 784908

7.2.2Control registers

(1)Program counter (PC)

This register is a 20-bit program counter. The program counter is automatically updated by program execution.

Figure 7-4. Format of Program Counter (PC)

19

0

PC

(2)Program Status Word (PSW)

This register holds the CPU state. The program status word is automatically updated by program execution.

Figure 7-5. Format of Program Status Word (PSW)

		15	14	13	12	11	10	9	8
	PSWH	UF	RBS2	RBS1	RBS0
	PSW
		7	6	5	4	3	2	1	0
	PSWL	S	Z	RSSNote	AC	IE	P/V	0	CY

Note This flag is used to maintain compatibility with the 78K/III Series. This flag must be set to 0 when programs for the 78K/III Series are not being used.

(3)Stack pointer (SP)

This register is a 24-bit pointer for holding the start address of the stack. The higher 4 bits must be set to 0.

Figure 7-6. Format of Stack Pointer (SP)

	23		20		0
SP	0	0	0	0

26	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

7.2.3Special function registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFHNote.

Note On execution of the LOCATION 0 instruction. FFF00H to FFFFFH when the LOCATION 0FH instruction is executed.

Caution Do not access an address in this area where no SFR is allocated, as the μPD784908 may be placed in the deadlock state. The deadlock state can be cleared only by a reset.

Table 7-1 lists the special function registers (SFRs). The symbols of the table columns are explained below.

•	Symbol ....................................	Symbol indicating an on-chip SFR. The symbols listed in the table are reserved
		words for the NEC assembler (RA78K4). In the C compiler (CC78K4), the
		symbols can be used as sfr variables with the #pragma sfr command.
•	R/W .........................................	Indicates whether the SFR is read-only, write-only, or read/write.
		R/W: Read/write
		R:	Read-only.
		W:	Write-only.
• Bit units for manipulation .......		Indicates the maximum number of bits that can be manipulated whenever an SFR
		is manipulated. An SFR that supports 16-bit manipulation can be described in
		the sfrp operand. For address specification, an even-numbered address must
		be specified.
		An SFR that can be manipulated in 1-bit units can be described as the operand
		of a bit manipulation instruction.
•	After reset	Indicates the state of the register when the			signal has been input.
				RESET

Data Sheet U11680EJ2V0DS00

27

μPD784907, 784908

Table 7-1. Special Function Registers (SFRs) (1/5)

AddressNote	Special Function Register (SFR) Name	Symbol		R/W	Bit Units for Manipulation			After Reset
					1 bit	8 bits	16 bits
0FF00H	Port 0	P0		R/W			—	Undefined
0FF01H	Port 1	P1					—
0FF02H	Port 2	P2		R			—
0FF03H	Port 3	P3		R/W			—
0FF04H	Port 4	P4					—
0FF05H	Port 5	P5					—
0FF06H	Port 6	P6					—	00H
0FF07H	Port 7	P7					—	Undefined
0FF09H	Port 9	P9					—
0FF0AH	Port 10	P10					—
0FF0EH	Port 0 buffer register L	P0L					—
0FF0FH	Port 0 buffer register H	P0H					—
0FF10H	Compare register (timer/counter 0)	CR00			—	—
0FF12H	Capture/compare register (timer/counter 0)	CR01			—	—
0FF14H	Compare register L (timer/counter 1)	CR10	CR10W		—
0FF15H	Compare register H (timer/counter 1)	—			—	—
0FF16H	Capture/compare register L (timer/counter 1)	CR11	CR11W		—
0FF17H	Capture/compare register H (timer/counter 1)	—			—	—
0FF18H	Compare register L (timer/counter 2)	CR20	CR20W		—
0FF19H	Compare register H (timer/counter 2)	—			—	—
0FF1AH	Capture/compare register L (timer/counter 2)	CR21	CR21W		—
0FF1BH	Capture/compare register H (timer/counter 2)	—			—	—
0FF1CH	Compare register L (timer 3)	CR30	CR30W		—
0FF1DH	Compare register H (timer 3)	—			—	—
0FF20H	Port 0 mode register	PM0					—	FFH
0FF21H	Port 1 mode register	PM1					—
0FF23H	Port 3 mode register	PM3					—
0FF24H	Port 4 mode register	PM4					—
0FF25H	Port 5 mode register	PM5					—
0FF26H	Port 6 mode register	PM6					—
0FF27H	Port 7 mode register	PM7					—
0FF29H	Port 9 mode register	PM9					—
0FF2AH	Port 10 mode register	PM10					—
0FF2EH	Real-time output port control register	RTPC					—	00H
0FF30H	Capture/compare control register 0	CRC0			—		—	10H
0FF31H	Timer output control register	TOC					—	00H
0FF32H	Capture/compare control register 1	CRC1			—		—
0FF33H	Capture/compare control register 2	CRC2			—		—	10H

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

28	Data Sheet U11680EJ2V0DS00

μPD784907, 784908

Table 7-1. Special Function Registers (SFRs) (2/5)

AddressNote	Special Function Register (SFR) Name	Symbol		R/W	Bit Units for Manipulation				After Reset
					1 bit	8 bits		16 bits
0FF36H	Capture register (timer/counter 0)	CR02		R	—	—			0000H
0FF38H	Capture register L (timer/counter 1)	CR12	CR12W		—
0FF39H	Capture register H (timer/counter 1)	—			—	—
0FF3AH	Capture register L (timer/counter 2)	CR22	CR22W		—
0FF3BH	Capture register H (timer/counter 2)	—			—	—
0FF41H	Port 1 mode control register	PMC1		R/W				—	00H
0FF43H	Port 3 mode control register	PMC3						—
0FF4AH	Port 10 mode control register	PMC10						—
0FF4EH	Register L for optional pull-up resistor	PUOL						—
0FF4FH	Register H for optional pull-up resistor	PUOH						—
0FF50H	Timer register 0	TM0		R	—	—			0000H
0FF51H				—	—
0FF52H	Timer register 1	TM1	TM1W		—
0FF53H		—			—	—
0FF54H	Timer register 2	TM2	TM2W		—
0FF55H		—			—	—
0FF56H	Timer register 3	TM3	TM3W		—
0FF57H		—			—	—
0FF5CH	Prescaler mode register 0	PRM0		R/W	—			—	11H
0FF5DH	Timer control register 0	TMC0						—	00H
0FF5EH	Prescaler mode register 1	PRM1			—			—	11H
0FF5FH	Timer control register 1	TMC1						—	00H
0FF68H	A/D converter mode register	ADM						—	00H
0FF6AH	A/D conversion result register	ADCR		R	—			—	Undefined
0FF6CH	A/D current cut selection register	IEAD		R/W				—	00H
0FF6FH	Clock timer mode register	WM						—
0FF70H	PWM control register	PWMC						—	05H
0FF71H	PWM prescaler register	PWPR			—			—	00H
0FF72H	PWM modulo register 0	PWM0			—	—			Undefined
0FF74H	PWM modulo register 1	PWM1			—	—
0FF7DH	One-shot pulse output control register	OSPC						—	00H
0FF80H	Clocked serial interface mode register 3	CSIM3						—
0FF82H	Clocked serial interface mode register	CSIM						—

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

Data Sheet U11680EJ2V0DS00

29

μPD784907, 784908

Table 7-1. Special Function Registers (SFRs) (3/5)

AddressNote	Special Function Register (SFR) Name	Symbol		R/W		Bit Units for Manipulation			After Reset
						1 bit	8 bits	16 bits
0FF84H	Clocked serial interface mode register 1	CSIM1		R/W				—	00H
0FF85H	Clocked serial interface mode register 2	CSIM2						—
0FF86H	Serial shift register	SIO				—		—	Undefined
0FF88H	Asynchronous serial interface mode register	ASIM						—	00H
0FF89H	Asynchronous serial interface mode register 2	ASIM2						—
0FF8AH	Asynchronous serial interface status register	ASIS		R				—
0FF8BH	Asynchronous serial interface status register 2	ASIS2						—
0FF8CH	Serial receive buffer: UART0	RXB				—		—	Undefined
	Serial transmission shift register: UART0	TXS		W		—		—
	Serial shift register: IOE1	SIO1		R/W		—		—
0FF8DH	Serial receive buffer: UART2	RXB2		R		—		—
	Serial transmission shift register: UART2	TXS2		W		—		—
	Serial shift register: IOE2	SIO2		R/W		—		—
0FF8EH	Serial shift register 3: IOE3	SIO3				—		—
0FF90H	Baud rate generator control register	BRGC				—		—	00H
0FF91H	Baud rate generator control register 2	BRGC2				—		—
0FFA0H	External interrupt mode register 0	INTM0						—
0FFA1H	External interrupt mode register 1	INTM1						—
0FFA4H	Sampling clock selection register	SCS0				—		—
0FFA8H	In-service priority register	ISPR		R				—
0FFAAH	Interrupt mode control register	IMC		R/W				—	80H
0FFACH	Interrupt mask register 0L	MK0L	MK0						FFFFH
0FFADH	Interrupt mask register 0H	MK0H
0FFAEH	Interrupt mask register 1L	MK1L	MK1						FFFFH
0FFAFH	Interrupt mask register 1H	MK1H
0FFB0H	Bus control register	BCR						—	00H
0FFB2H	Unit address register	UAR				—	—		0000H
0FFB4H	Slave address register	SAR				—	—
0FFB6H	Partner address register	PAR		R		—	—
0FFB8H	Control data register	CDR		R/W		—		—	01H
0FFB9H	Telegraph length register	DLR				—		—

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,

F0000H is added to each address.

30	Data Sheet U11680EJ2V0DS00