NEC PD784907, PD784908 Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD784907, 784908

16-BIT SINGLE-CHIP MICROCONTROLLER

The µPD784907 and µPD784908 are products of the µPD784908 Subseries in the 78K/IV Series. These products

contain various peripheral hardware such as IEBus serial interface, and interrupt functions, as well as a high-speed, high-performance CPU.

In addition, the

versions, and development tools are also available.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

PD78P4908 (one-time PROM product), which is used to evaluate the functions of mask ROM

PD784908 Subseries User's Manual Hardware : U11787E

78K/IV Series User's Manual Instruction : U10905E

controller, ROM, RAM, I/O ports, 8-bit resolution A/D, timers,

FEATURES

•78K/IV Series

•Minimum instruction execution time: 320 ns (at 6.29 MHz)

160 ns (at 12.58 MHz)

•Number of I/O ports: 80

•Timer/counters: 16-bit timer/counter × 3 units

16-bit timer × 1 unit

•Serial interface: 4 channels

UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O): 2 channels

•PWM outputs: 2

•Standby function

HALT/STOP/IDLE mode

•Clock frequency division function

APPLICATIONS

Car audios, etc.

•Watchdog timer: 1 channel

•Clock output function

Selectable from f

CLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16

•A/D converter: 8-bit resolution × 8 channels

•On-chip IEBus controller

•Watch timer

•Low-power consumption

•Supply voltage: VDD = 4.0 to 5.5 V

(Main clock: f internal system clock = f

CYK = 79 ns)

DD = 3.5 to 5.5 V

V (Other than above, f

XX = 12.58 MHz,

XX,

CYK = 159 ns)

This document describes the µPD784908 unless otherwise specified.

The information in this document is subject to change without notice.

Document No. U11680EJ2V0DS00 (2nd edition) Date Published February 1999 N CP(K) Printed in Japan

The mark shows major revised points.

1996

PD784907, 784908

ORDERING INFORMATION

Part number Package Internal ROM Internal RAM

(bytes) (bytes)

PD784907GF-×××-3BA 100-pin plastic QFP (14 × 20 mm) 96 K 3,584

PD784908GF-×××-3BA 100-pin plastic QFP (14 × 20 mm) 128 K 4,352

Remark ××× indicates ROM code suffix.

Data Sheet U11680EJ2V0DS00

78K/IV SERIES PRODUCT LINEUP

: Under mass production

: Under development

PD784907, 784908

Standard models

PD784026

Enhanced A/D, 16-bit timer, and power management

ASSP models

PD784955

For DC inverter control

PD784908

On-chip IEBus controller

I2C bus supported

PD784038Y

PD784038

Enhanced internal memory capacity, pin compatible with the PD784026

PD784216Y

PD784216

100 pins, enhanced I/O and internal memory capacity

PD784054

PD784046

On-chip 10-bit A/D

PD784938

Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added

Multi-master I2C bus supported

PD784225Y

PD784225

80 pins, ROM correction added

Multi-master I2C bus supportedMulti-master I2C bus supported

PD784218Y

PD784218

Enhanced internal memory capacity, ROM correction added

PD784915

For software servo control, on-chip analog circuit for VCR, enhanced timer

Multi-master I2C bus supported

PD784928Y

PD784928

Enhanced functions of the PD784915

3Data Sheet U11680EJ2V0DS00

FUNCTIONS

PD784907, 784908

Part Number

Item Number of basic instructions 113

(mnemonics) General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution 320 ns/636 ns/1.27 µs/2.54 µs (at 6.29 MHz)

time 160 ns/320 ns/636 ns/1.27 µs (at 12.58 MHz) Internal ROM 96 K 128 K

memory Memory space 1 Mbyte with program and data spaces combined

I/O ports Total 80

Additional LED direct 24 function drive outputs

Note

pins

Real-time output ports 4 bits × 2, or 8 bits × 1 IEBus controller Incorporated (simplified) Timer/counter Timer/counter 0: Timer register × 1 Pulse output capability

Watch timer Interrupt requests are generated at 0.5-second intervals. (A watch clock oscillator is

Clock output Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port) PWM outputs 12-bit resolution × 2 channels Serial interface UART/IOE (3-wire serial I/O):2 channels (on-chip baud rate generator)

A/D converter 8-bit resolution × 8 channels

RAM 3,584 bytes 4,352 bytes

Input 8 Input/output 72

Transistor 8 direct drive

N-ch open 4 drain

(16 bits) Capture register × 1 • Toggle output

Timer/counter 1: Timer register × 1 Real-time output port (16 bits) Capture register × 1

Timer/counter 2: Timer register × 1 Pulse output capability (16 bits) Capture register × 1 • Toggle output

Timer 3: Timer register × 1 (16 bits) Compare register × 1

incorporated.) Either the main clock (6.29 MHz/12.58 MHz) or watch clock (32.7 kHz) can be selected as the input clock.

CSI (3-wire serial I/O): 2 channels

PD784907

Compare register × 2 • PWM/PPG output

Capture/compare register × 1 Compare register × 1

Capture/compare register × 1 • PWM/PPG output Compare register × 1

PD784908

• One-shot pulse output

Note Additional function pins are included in the I/O pins.

Data Sheet U11680EJ2V0DS00

PD784907, 784908

Part Number

Item Watchdog timer 1 channel Standby HALT/STOP/IDLE modes Interrupt Hardware source 27 (20 internal, 7 external (sampling clock variable input: 1))

Software source BRK or BRKCS instruction, operand error Non-maskable 1 internal, 1 external Maskable 19 internal, 6 external

4-level programmable priority 3 operation statuses: vectored interrupt, macro service, context switching

Power supply voltage VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns)

VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns)

Package 100-pin plastic QFP (14 × 20 mm)

PD784907

PD784908

5Data Sheet U11680EJ2V0DS00

PD784907, 784908

CONTENTS

1. DIFFERENCES BETWEEN µPD784908 SUBSERIES PRODUCTS....................................... 8

2. MAJOR DIFFERENCES BETWEEN µPD784908 AND µPD78098 SUBSERIES .................. 9

3. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 10

4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK))..... 12

5. BLOCK DIAGRAM ..................................................................................................................... 13

6. PIN FUNCTION........................................................................................................................... 14

6.1 Port Pins............................................................................................................................................ 14

6.2 Non-Port Pins ................................................................................................................................... 16

6.3 Pin I/O Circuits and Recommended Connections of Unused Pins .......................................... 18

7. CPU ARCHITECTURE ............................................................................................................... 2 2

7.1 Memory Space .................................................................................................................................. 22

7.2 CPU Registers .................................................................................................................................. 25

7.2.1 General-purpose registers................................................................................................ 2 5

7.2.2 Control registers ................................................................................................................ 26

7.2.3 Special function registers (SFRs).................................................................................... 27

8. PERIPHERAL HARDWARE FUNCTIONS................................................................................ 33

8.1 Ports................................................................................................................................................... 33

8.2 Clock Generator ............................................................................................................................... 35

8.3 Real-Time Output Port ..................................................................................................................... 38

8.4 Timers/Counters............................................................................................................................... 39

8.5 Watch Timer...................................................................................................................................... 41

8.6 PWM Output (PWM0, PWM1) .......................................................................................................... 42

8.7 A/D Converter ................................................................................................................................... 43

8.8 Serial Interface ................................................................................................................................. 44

8.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................... 45

8.8.2 Clocked serial interface (CSI)........................................................................................... 47

8.9 Clock Output Function .................................................................................................................... 48

8.10 Edge Detection Function ................................................................................................................ 49

8.11 Watchdog Timer............................................................................................................................... 49

8.12 Simplified IEBus Controller............................................................................................................ 50

9. INTERRUPT FUNCTION............................................................................................................ 53

9.1 Interrupt Source ............................................................................................................................... 53

9.2 Vectored Interrupt............................................................................................................................ 55

9.3 Context Switching............................................................................................................................ 56

9.4 Macro Service ................................................................................................................................... 56

9.5 Examples of Macro Service Applications .................................................................................... 5 7

Data Sheet U11680EJ2V0DS00

PD784907, 784908

10. LOCAL BUS INTERFACE ......................................................................................................... 59

10.1 Memory Expansion .......................................................................................................................... 59

10.2 Memory Space.................................................................................................................................. 60

10.3 Programmable Wait ......................................................................................................................... 6 1

10.4 Pseudo-Static RAM Refresh Function .......................................................................................... 61

10.5 Bus Hold Function........................................................................................................................... 6 1

11. STANDBY FUNCTION ............................................................................................................... 62

12. RESET FUNCTION..................................................................................................................... 63

13. REGULATOR.............................................................................................................................. 64

14. INSTRUCTION SET .................................................................................................................... 65

15. ELECTRICAL SPECIFICATIONS.............................................................................................. 70

16. PACKAGE DRAWING ................................................................................................................ 8 9

17. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 90

APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 91

APPENDIX B RELATED DOCUMENTS ......................................................................................... 94

7Data Sheet U11680EJ2V0DS00

PD784907, 784908

1. DIFFERENCES BETWEEN µPD784908 SUBSERIES PRODUCTS

The only difference between the µPD784907 and µPD784908 is their internal memory capacities. The µPD78P4908 is produced by replacing the mask ROM in the µPD784907 or µPD784908 with 128-Kbyte one-

time PROM. Table 1-1 shows the differences between these products.

Table 1-1. Differences between the

PD784908 Subseries Products

Part Number

Item Internal ROM 96 K (mask ROM) 128 K (mask ROM) 128 K (one-time PROM) Internal RAM 3,584 bytes 4,352 bytes Regulator Provided None Power supply voltage VDD = 4.0 to 5.5 V VDD = 4.5 to 5.5 V

(Main clock: fXX = 12.58 MHz, internal system clock = fXX, (Main clock: fXX = 12.58 MHz, fCYK = 79 ns) internal system clock = fXX, VDD = 3.5 to 5.5 V fCYK = 79 ns) (other than above, fCYK = 159 ns) VDD = 4.0 to 5.5 V

Electrical specifications Refer to the data sheet of each product.

PD784907

PD784908

PD78P4908

(other than above, fCYK = 159 ns)

Data Sheet U11680EJ2V0DS00

PD784907, 784908

2. MAJOR DIFFERENCES BETWEEN µPD784908 AND µPD78098 SUBSERIES

Series Name

Item Number of basic instructions 113 63

(mnemonics) Minimum instruction execution 320/160 ns 480 ns

time (at 6.29/12.58 MHz operation) (at 6.29 MHz operation) Timer/counter 16-bit timer/counter × 1 16-bit timer/counter × 1

8/16-bit timer/counter × 2 8/16-bit timer/counter × 2 8/16-bit timer × 1 Watch timer Watch timer

Single clock Dual clock

Watch clock for clock operation Watchdog timer Provided Serial interface UART/IOE (3-wire serial I/O): 2 channels UART (3-wire serial I/O): 1 channel

CSI (3-wire serial I/O): 2 channels CSI/SBI (3-wire serial I/O): 1 channel

PWM output 2 None A/D converter 8-bit resolution × 8 channels D/A converter None Interrupt Hardware source 27 23 (two test flags)

Internal 20 14

External 7 7 External extended function Provided (up to 1 Mbyte) None IEBus controller Incorporated (simplified) Incorporated (complete hardware) Power supply voltage • Mask ROM version VDD = 2.7 to 6.0 V

VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns)

• PROM version VDD = 4.5 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 4.0 to 5.5 V (other than above, fCYK = 159 ns)

Package 100-pin plastic QFP (14 × 20 mm) 80-pin plastic QFP (14 × 14 mm)

PD784908 Subseries

PD78098 Subseries

CSI (3-wire serial I/O): 1 channel

80-pin plastic WQFN (14 × 14 mm):

PD78P098A only

9Data Sheet U11680EJ2V0DS00

3. PIN CONFIGURATION (TOP VIEW)

• 100-pin plastic QFP (14 × 20 mm)

PD784907GF-×××-3BA

PD784908GF-×××-3BA

P35/TO1

P34/TO099P33/SO0

P32/SCK0

P31/TxD/SO1

100

2P37/TO3 3P100 4P101 5P102 6P103 7P104 8P105/SCK3 9P106/SI3 10P107/SO3 11RESET 12XT2 13XT1 14V

15X2

Note 2 Note 3

16X1 17REGOFF 18REGC 19VDD 20P00 21P01 22P02 23P03 24P04 25P05 26P06 27P07 28P67/REFRQ/HLDAK 29P66/WAIT/HLDRQ 30P65/WR

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P30/RxD/SI1

P27/SI094P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI87TX86RX85AVSS84AVREF183AVDD82P77/ANI7

PD784907, 784908

80 P76/ANI61P36/TO2 79 P75/ANI5 78 P74/ANI4 77 P73/ANI3 76 P72/ANI2 75 P71/ANI1 74 P70/ANI0 73 TEST 72 PWM1 71 PWM0 70 P17 69 P16 68 P15 67 P14/TxD2/SO2 66 P13/RxD2/SI2 65 P12/ASCK2/SCK2 64 P11 63 P10 62 ASTB/CLKOUT 61 P90 60 P91 59 P92 58 P93 57 P94 56 P95 55 P96 54 P97 53 P40/AD0 52 P41/AD1 51 P42/AD2

Note 1

P64/RD

P63/A19

P62/A18

P61/A17

Notes 1. Connect the TEST pin directly to V

2. Connect the REGOFF pin directly to VSS (select regulator operation).

3. Connect the REGC pin to V

VDD

P51/A9

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

SS.

SS via a capacitor of the order of 1

Data Sheet U11680EJ2V0DS00

P53/A11

P52/A10

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

PD784907, 784908

A8 to A19: Address bus AD0 to AD7: Address/data bus ANI0 to ANI7: Analog input ASCK, ASCK2: Asynchronous serial clock ASTB: Address strobe

DD: Analog power supply

AV AVREF1: Reference voltage AVSS: Analog ground CI: Clock input CLKOUT: Clock output HLDAK: Hold acknowledge HLDRQ: Hold request INTP0 to INTP5: Interrupt from peripherals NMI: Non-maskable interrupt P00 to P07: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P37: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P60 to P67: Port 6 P70 to P77: Port 7 P90 to P97: Port 9 P100 to P107: Port 10

PWM0, PWM1: Pulse width modulation output RD: Read strobe REFRQ: Refresh request REGC: Regulator capacitance REGOFF: Regulator off RESET: Reset RX: IEBus receive data

XD, RXD2: Receive data

R SCK0 to SCK3: Serial clock SI0 to SI3: Serial input SO0 to SO3: Serial output TEST: Test TO0 to TO3: Timer output TX: IEBus transmit data

XD, TXD2: Transmit data

T VDD: Power supply VSS: Ground WAIT: Wait WR: Write strobe X1, X2: Crystal (main system clock) XT1, XT2: Crystal (watch)

11Data Sheet U11680EJ2V0DS00

PD784907, 784908

4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK))

Front panel PD784908

Remote-controll

FIP

FIP controller/driver

signal reception circuit

PC2800A, etc.

Key matrix

PD16312, etc.

Interrupt input

SIO with automatic transmission/reception function

LED display

Audio control circuit

Electronic volume

EEPROM

3-wire serial I/O

General-purpose port

3-wire serial I/O

IEBus controller

REGOFF

REGC

Cassette deck unit

Tuner pack

IEBus driver/ receiver

IEBus

CD unit

CD changer, one CD, etc.

DSP unit

TV unit

Data Sheet U11680EJ2V0DS00

5. BLOCK DIAGRAM

PD784907, 784908

NMI

INTP0 to INTP5

INTP3

TO0 TO1

INTP0

INTP1

INTP2/CI

TO2 TO3

P00 to P03

P04 to P07

PWM0 PWM1

Programmable interrupt controller

Timer/counter 0

(16 bits)

Timer/counter 1

(16 bits)

Timer/counter 2

(16 bits)

Timer 3

(16 bits)

Real-time output port

PWM

78K/IV CPU core

RAM

ROM

UART/IOE2

Baud-rate generator

UART/IOE1

Baud-rate generator

Clocked serial interface

Clocked serial interface 3

Clock output

Bus interface

RxD/SI1 TxD/SO1

ASCK/SCK1

RxD2/SI2 TxD2/SO2

ASCK2/SCK2

SCK0 SO0 SI0

SCK3 SO3 SI3

ASTB/CLKOUT AD0 to AD7 A8 to A15 A16 to A19

RD WR WAIT/HLDRQ REFRQ/HLDAK

ANI0 to ANI7

REF1

INTP5

RESET

TEST

X1 X2

REGC

REGOFF

V V

XT1 XT2

DD SS

A/D converter

IEBus controller

System control

(regulator)

Watch timer

Watchdog timer

Remark The internal ROM and RAM capacities differ depending on the product.

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 9

Port 10

P00 to P07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P90 to P97

P100 to P107

13Data Sheet U11680EJ2V0DS00

6. PIN FUNCTIONS

6.1 Port Pins (1/2)

Pin Name I/O Alternate Function Function

P00 to P07 I/O — Port 0 (P0):

• 8-bit I/O port.

• Can be used as a real-time output port (4 bits × 2).

• Input and output can be specified by 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode.

• Can drive transistors.

P10 I/O — P11 — P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 P15 to P17 — P20 Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 P30 I/O RxD/SI1 P31 TxD/SO1 P32 SCK0 P33 SO0 P34 to P37 TO0 to TO3 P40 to P47 I/O AD0 to AD7 Port 4 (P4):

P50 to P57 I/O A8 to A15 Port 5 (P5):

Port 1 (P1):

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LEDs.

Port 2 (P2):

• 8-bit input port.

• P20 does not function as a general-purpose port (non-maskable interrupt).

However, the input level can be checked by an interrupt service routine.

• The use of on-chip pull-up resistors can be specified by software for pins

P22 to P27 (in 6-bit units).

• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by a

CSIM1 specification.

Port 3 (P3):

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• The use of the N-ch open drain can be specified for pins P32 and P33.

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode.

• Can drive LEDs.

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode.

• Can drive LEDs.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

6.1 Port Pins (2/2)

Pin Name I/O Alternate Function Function P60 to P63 I/O A16 to A19 P64 RD P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK P70 to P77 I/O ANI0 to ANI7 Port 7 (P7):

P90 to P97 I/O — Port 9 (P9):

P100 to I/O — P104

P105 SCK3 P106 SI3 P107 SO3

Port 6 (P6):

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode.

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

Port 10 (P10):

• 8-bit I/O port.

• Input and output can be specified in 1-bit units.

• The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode.

• The use of the N-ch open drain can be specified for pins P105 and P107.

PD784907, 784908

15Data Sheet U11680EJ2V0DS00

PD784907, 784908

6.2 Non-Port Pins (1/2)

Pin Name I/O Alternate Function Function TO0 to TO3 Output P34 to P37 Timer output CI Input P23/INTP2 Input of a count clock for timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) RxD2 P13/SI2 Serial data input (UART2) TxD Output P31/SO1 Serial data output (UART0) TxD2 P14/SO2 Serial data output (UART2) ASCK Input P25/INTP4/SCK1 Baud rate clock input (UART0) ASCK2 P12/SCK2 Baud rate clock input (UART2) SI0 Input P27 Serial data input (3-wire serial I/O 0) SI1 P30/RxD Serial data input (3-wire serial I/O 1) SI2 P13/RxD2 Serial data input (3-wire serial I/O 2) SI3 P106 Serial data input (3-wire serial I/O 3) SO0 Output P33 Serial data output (3-wire serial I/O 0) SO1 P31/TxD Serial data output (3-wire serial I/O 1) SO2 P14/TxD2 Serial data output (3-wire serial I/O 2) SO3 P107 Serial data output (3-wire serial I/O 3) SCK0 I/O P32 Serial clock I/O (3-wire serial I/O 0) SCK1 P25/INTP4/ASCK Serial clock I/O (3-wire serial I/O 1) SCK2 P12/ASCK2 Serial clock I/O (3-wire serial I/O 2) SCK3 P105 Serial clock I/O (3-wire serial I/O 3) NMI Input P20 External interrupt — INTP0 P21 request • Input of a count clock for timer/counter 1

• Capture/trigger signal for CR11 or CR12

INTP1 P22 • Input of a count clock for timer/counter 2

• Capture/trigger signal for CR22

INTP2 P23/CI • Input of a count clock for timer/counter 2

• Capture/trigger signal for CR21

INTP3 P24 • Input of a count clock for timer/counter 0

• Capture/trigger signal for CR02 INTP4 P25/ASCK/SCK1 — INTP5 P26 AD0 to AD7 I/O P40 to P47 Time multiplexing address/data bus (for connecting external memory) A8 to A15 Output P50 to P57 High-order address bus (for connecting external memory) A16 to A19 Output P60 to P63 High-order address bus during address expansion (for connecting external

memory) RD Output P64 Strobe signal output for reading the contents of external memory WR Output P65 Strobe signal output for writing on external memory WAIT Input P66/HLDRQ Wait insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Input of bus hold request HLDAK Output P67/REFRQ Output of bus hold response ASTB Output CLKOUT Latch timing output of time multiplexing address (A0 to A7) (for connecting

external memory)

Input of a conversion start trigger for A/D converter

Data Sheet U11680EJ2V0DS00

PD784907, 784908

6.2 Non-Port Pins (2/2)

Pin Name I/O Alternate Function Function CLKOUT Output ASTB Clock output PWM0 Output — PWM output 0 PWM1 Output — PWM output 1 RX Input — Data input (IEBus) TX Output — Data output (IEBus) REGC — — Capacitance connection for stabilizing the regulator output/power supply

when the regulator is stopped. Connect to VSS via a capacitor of order of 1µF. REGOFF — — Signal for specifying regulator operation RESET Input — Chip reset X1 Input — Crystal input for system clock oscillation (A clock pulse can also be input X2 — XT1 Input — Watch clock connection XT2 — — ANI0 to ANI7 Input P70 to P77 Analog voltage input for A/D converter AVREF1 — — To apply the reference voltage for A/D converter AVDD Positive power supply for A/D converter AVSS GND for A/D converter VDD Positive power supply VSS GND TEST Input Connect directly to V

to the X1 pin.)

SS. (This pin is for IC test.)

Data Sheet U11680EJ2V0DS00

PD784907, 784908

6.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-1. For each type of input/output circuit, refer to Figure 6-1.

Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins

P00 to P07 5-A I/O Input: Connect to VDD P10, P11 P12/ASCK2/SCK2 8-A P13/RxD2/SI2 5-A P14/TxD2/SO2 P15 to P17 P20/NMI 2 Input Connect to VDD or VSS P21/INTP0 P22/INTP1 2-A Connect to VDD P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input: Connect to VDD

P26/INTP5 2-A Input Connect to VDD P27/SI0 P30/RxD/SI1 5-A I/O Input: Connect to VDD P31/TxD/SO1 P32/SCK0 10-A P33/SO0 P34/TO0 to P37/TO3 5-A P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 20 I/O Input: Connect to VDD or VSS P90 to P97 5-A P100 to P104 P105/SCK3 10-A P106/SI3 8-A P107/SO3 10-A ASTB/CLKOUT 4 Output Leave open

Output:Leave open

Data Sheet U11680EJ2V0DS00

PD784907, 784908

Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (2/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins RESET 2 Input — TEST 1 Connect directly to VSS XT2 — — Leave open XT1 — Input Connect to V SS PWM0, PWM1 3 Output Leave open RX 1 Input Connect to VDD or VSS TX 3 Output Leave open AVREF1 — — Connect to VSS AVSS AVDD Connect to VDD

Caution Connect an I/O pin, whose input/output mode is undefined, to VDD via a resistor of several

10 kΩ (especially if the voltage on the reset input pin rises higher than the low level input at power on or when the mode is being switched between input and output by software).

Remark Since type numbers are commonly used in the 78K Series, these numbers are not always serial in each

product (some circuits are not included).

Data Sheet U11680EJ2V0DS00

Figure 6-1. I/O Circuits for Pins

Type 1 Type 4

Data

PD784907, 784908

OUT

Push-pull output which can output high impedance (both the positive and negative channels are off.)

Type 2

Type 5-A

Pull-up enable

Schmitt trigger input with hysteresis characteristics

Data

Output disable

Input enable

Type 2-A Type 8-A

Output disable

IN/OUT

Pull-up

Pull-up enable

enable

Data

Output disable

Schmitt trigger input with hysteresis characteristics

Type 3 Type 10-A

Pull-up enable

P-ch

Data

Data OUT

Open

N-ch

drain Output disable

IN/OUT

Data Sheet U11680EJ2V0DS00

Type 20

PD784907, 784908

Output disable

Input enable

Data

Comparator

(Threshold voltage)

IN/OUT

+ –

REF

P N

Data Sheet U11680EJ2V0DS00

PD784907, 784908

7. CPU ARCHITECTURE

7.1 Memory Space

A memory space of 1 Mbyte can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once.

(1) When the LOCATION 0 instruction is executed

• Internal memory The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784907 0F100H to 0FFFFH 00000H to 0F0FFH

10000H to 17FFFH

PD784908 0EE00H to 0FFFFH 00000H to 0FDFFH

10000H to 1FFFFH

Caution The following internal ROM areas, existing at the same addresses as the internal data areas,

cannot be used when the LOCATION 0 instruction is executed:

Part Number Unusable Area

PD784907 0F100H to 0FFFFH (3,840 bytes)

PD784908 0EE00H to 0FFFFH (4,608 bytes)

• External memory The external memory is accessed in external memory expansion mode.

(2) When the LOCATION 0FH instruction is executed

• Internal memory The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784907 FF100H to FFFFFH 00000H to 17FFFH

PD784908 FEE00H to FFFFFH 00000H to 1FFFFH

• External memory The external memory is accessed in external memory expansion mode.

Data Sheet U11680EJ2V0DS00

Figure 7-1.

PD784907 Memory Map

Data Sheet U11680EJ2V0DS00

FFFFFH

18000H 1 7FFFH

10000H 0FFFFH 0 FFDFH 0 FFD0H 0FF00H 0FEFFH

0F100H 0F0FFH

00000H

When the LOCATION 0 instruction is executed

External memory (928 Kbytes)

Note 1

Internal ROM (32,768 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (3,584 bytes)

Internal ROM (61,696 bytes)

Note 4

0FEFFH

0FE80H 0FE7FH

0FE39H 0FE06H

0 FD0 0H 0 FCFFH

0F100H

17FFFH 10000H

0F0FFH 01000H

0 0FFFH

00800H 007FFH

00080H 0007FH

00040H 0003FH

00000H

General-purpose registers (128 bytes)

Macro service control

word area (42 bytes)

Data area (512 bytes)

Program/data area (3,072 bytes)

Note 2

Program/data area

CALLF entry area (2 Kbytes)

CALLT table area (64 bytes)

Vector table area (64 bytes)

Note 3

FFEFFH

FFE80H FFE7FH

FFE39H FFE06H

FFD00H F FCFFH

FF100H

1 7FFFH

FFFFFH FFFDFH FFFD0H FFF00H

FFEFFH

FF100H FF0FFH

18000H 1 7FFFH

00000H

When the LOCATION 0FH instruction is executed

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (3,584 bytes)

External memory (946,432 bytes)

Internal ROM

(96 Kbytes)

Note 1

Note 4

PD784907, 784908

Notes 1. Accessed in external memory expansion mode.

2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed: 94,464 bytes

When the LOCATION 0FH instruction is executed: 98,304 bytes

4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

Figure 7-2.

PD784908 Memory Map

Data Sheet U11680EJ2V0DS00

FFFFFH

20000H 1FFFFH

10000H 0FFFFH 0FFDFH 0FFD0H 0FF 00H 0FEFFH

0EE00H 0EDFFH

00000H

When the LOCATION 0 instruction is executed

External memory (896 Kbytes)

Note 1

Internal ROM (65,536 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (4,352 bytes)

Internal ROM

(60,928 bytes)

Note 4

0FEFFH

0FE8 0H 0FE7 FH

0FE3 9H 0FE0 6H

0FD00H 0FCFFH

0EE00H

1FFFFH 10000H

0EDFFH 01000H

00FFFH

00800H 007 FFH

00080H 0007FH

00040H 0003FH

00000H

General-purpose registers (128 bytes)

Macro service control word area (42 bytes)

Data area (512 bytes)

Program/data area (3,840 bytes)

Note 2

Program/data area

CALLF entry area (2 Kbytes)

CALLT table area (64 bytes)

Vector table area (64 bytes)

Note 3

FFEFFH

FFE 8 0H FFE 7 FH

FFE 3 9H FFE 0 6H

FFD00H FFCFFH

FEE 0 0 H

1FFFFH

FFFFFH FFFDFH FFFD0H FFF00H

FFEFFH

FEE 0 0 H FEDFFH

20000H 1FFFFH

00000H

When the LOCATION 0FH instruction is executed

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM (4,352 bytes)

External memory (912,896 bytes)

Internal ROM

(128 Kbytes)

Note 1

Note 4

PD784907, 784908

Notes 1. Accessed in external memory expansion mode.

2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed: 126,464 bytes

When the LOCATION 0FH instruction is executed: 131,072 bytes

4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

PD784907, 784908

7.2 CPU Registers

7.2.1 General-purpose registers

A set of general-purpose registers consists of sixteen 8-bit general-purpose registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.

Eight banks of this register set are provided. The user can switch between banks by software or the context switching function.

General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM.

Figure 7-3. General-Purpose Register Format

A (R1) X (R0)

AX (RP0)

B (R3) C (R2)

BC (RP1)

R5 R4

RP2

R7 R6

RP3

VVP (RG4)

UUP (RG5)

TDE (RG6)

W L (R14)

WHL (RG7)

The character strings enclosed in parentheses represent absolute names.

R9 R8

VP (RP4)

R11 R10

UP (RP5)

D (R13) E (R12)

DE (RP6)

H (R15)

HL (RP7)

8 banks

Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C,

B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series.

Data Sheet U11680EJ2V0DS00

PD784907, 784908

7.2.2 Control registers

(1) Program counter (PC)

This register is a 20-bit program counter. The program counter is automatically updated by program execution.

Figure 7-4. Format of Program Counter (PC)

19 0

(2) Program Status Word (PSW)

This register holds the CPU state. The program status word is automatically updated by program execution.

Figure 7-5. Format of Program Status Word (PSW)

PSW

PSWH

PSWL

15 14 13 12

UF RBS2 RBS1 RBS0

76543210

S Z RSS

Note

AC IE P/V 0 CY

11 10 9 8

Note This flag is used to maintain compatibility with the 78K/III Series. This flag must be set to 0 when

programs for the 78K/III Series are not being used.

(3) Stack pointer (SP)

This register is a 24-bit pointer for holding the start address of the stack. The higher 4 bits must be set to 0.

Figure 7-6. Format of Stack Pointer (SP)

23 20 0

SP 0 0 0 0

Data Sheet U11680EJ2V0DS00

PD784907, 784908

7.2.3 Special function registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H

Note

and 0FFFFH

Note On execution of the LOCATION 0 instruction. FFF00H to FFFFFH when the LOCATION 0FH instruction

Caution Do not access an address in this area where no SFR is allocated, as the

Table 7-1 lists the special function registers (SFRs). The symbols of the table columns are explained below.

• Symbol.................................... Symbol indicating an on-chip SFR. The symbols listed in the table are reserved

• R/W ......................................... Indicates whether the SFR is read-only, write-only, or read/write.

• Bit units for manipulation ....... Indicates the maximum number of bits that can be manipulated whenever an SFR

• After reset............................... Indicates the state of the register when the RESET signal has been input.

is executed.

in the deadlock state. The deadlock state can be cleared only by a reset.

words for the NEC assembler (RA78K4). In the C compiler (CC78K4), the symbols can be used as sfr variables with the #pragma sfr command.

R/W: Read/write R: Read-only. W: Write-only.

is manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp operand. For address specification, an even-numbered address must be specified. An SFR that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.

PD784908 may be placed

Data Sheet U11680EJ2V0DS00

Table 7-1. Special Function Registers (SFRs) (1/5)

PD784907, 784908

Address

0FF00H Port 0 P0 R/W — Undefined 0FF01H Port 1 P1 — 0FF02H Port 2 P2 R — 0FF03H Port 3 P3 R/W — 0FF04H Port 4 P4 — 0FF05H Port 5 P5 — 0FF06H Port 6 P6 — 00H 0FF07H Port 7 P7 — Undefined 0FF09H Port 9 P9 — 0FF0AH Port 10 P10 — 0FF0EH Port 0 buffer register L P0L — 0FF0FH Port 0 buffer register H P0H —

0FF10H Compare register (timer/counter 0) CR00 — — 0FF12H Capture/compare register (timer/counter 0) CR01 — —

0FF14H Compare register L (timer/counter 1) CR10 0FF15H Compare register H (timer/counter 1) — — —

0FF16H Capture/compare register L (timer/counter 1) CR11 0FF17H Capture/compare register H (timer/counter 1) — — —

0FF18H Compare register L (timer/counter 2) CR20 0FF19H Compare register H (timer/counter 2) — — —

0FF1AH Capture/compare register L (timer/counter 2) CR21 0FF1BH Capture/compare register H (timer/counter 2) — — —

0FF1CH Compare register L (timer 3) CR30 0FF1DH Compare register H (timer 3) — — —

0FF20H Port 0 mode register PM0 — FFH 0FF21H Port 1 mode register PM1 — 0FF23H Port 3 mode register PM3 — 0FF24H Port 4 mode register PM4 — 0FF25H Port 5 mode register PM5 — 0FF26H Port 6 mode register PM6 — 0FF27H Port 7 mode register PM7 — 0FF29H Port 9 mode register PM9 — 0FF2AH Port 10 mode register PM10 — 0FF2EH Real-time output port control register RTPC — 00H 0FF30H Capture/compare control register 0 CRC0 — — 10H 0FF31H Timer output control register TOC — 00H 0FF32H Capture/compare control register 1 CRC1 — — 0FF33H Capture/compare control register 2 CRC2 —

Note

Special Function Register (SFR) Name Symbol R/W

CR10W

CR11W

CR20W

CR21W

CR30W

Bit Units for Manipulation

1 bit 8 bits 16 bits

—

— 10H

After Reset

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

Data Sheet U11680EJ2V0DS00

Table 7-1. Special Function Registers (SFRs) (2/5)

PD784907, 784908

Address

0FF36H Capture register (timer/counter 0) CR02 R — — 0000H 0FF38H Capture register L (timer/counter 1) CR12

0FF39H Capture register H (timer/counter 1) — — — 0FF3AH Capture register L (timer/counter 2) CR22

0FF3BH Capture register H (timer/counter 2) — — — 0FF41H Port 1 mode control register PMC1 R/W — 00H 0FF43H Port 3 mode control register PMC3 — 0FF4AH Port 10 mode control register PMC10 — 0FF4EH Register L for optional pull-up resistor PUOL — 0FF4FH Register H for optional pull-up resistor PUOH —

0FF50H Timer register 0 TM0 R — — 0000H 0FF51H ——

0FF52H Timer register 1 TM1 TM1W — 0FF53H — — —

0FF54H Timer register 2 TM2 TM2W — 0FF55H — — —

0FF56H Timer register 3 TM3 TM3W — 0FF57H — — —

0FF5CH Prescaler mode register 0 PRM0 R/W — — 11H 0FF5DH Timer control register 0 TMC0 — 00H 0FF5EH Prescaler mode register 1 PRM1 — — 11H 0FF5FH Timer control register 1 TMC1 — 00H 0FF68H A/D converter mode register ADM — 00H 0FF6AH A/D conversion result register ADCR R — — Undefined 0FF6CH A/D current cut selection register IEAD R/W — 00H 0FF6FH Clock timer mode register WM — 0FF70H PWM control register PWMC — 05H 0FF71H PWM prescaler register PWPR — — 00H 0FF72H PWM modulo register 0 PWM0 — — Undefined

0FF74H PWM modulo register 1 PWM1 — — 0FF7DH One-shot pulse output control register OSPC — 00H 0FF80H Clocked serial interface mode register 3 CSIM3 — 0FF82H Clocked serial interface mode register CSIM

Note

Special Function Register (SFR) Name Symbol R/W

CR12W

CR22W

Bit Units for Manipulation

1 bit 8 bits 16 bits

—

After Reset

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

Data Sheet U11680EJ2V0DS00

Table 7-1. Special Function Registers (SFRs) (3/5)

PD784907, 784908

Address

0FF84H Clocked serial interface mode register 1 CSIM1 R/W — 00H 0FF85H Clocked serial interface mode register 2 CSIM2 — 0FF86H Serial shift register SIO — — Undefined 0FF88H Asynchronous serial interface mode register ASIM — 00H 0FF89H Asynchronous serial interface mode register 2 ASIM2 — 0FF8AH Asynchronous serial interface status register ASIS R — 0FF8BH Asynchronous serial interface status register 2 ASIS2 — 0FF8CH Serial receive buffer: UART0 RXB — — Undefined

0FF8DH Serial receive buffer: UART2 RXB2 R — —

0FF8EH Serial shift register 3: IOE3 SIO3 — — 0FF90H Baud rate generator control register BRGC — — 00H 0FF91H Baud rate generator control register 2 BRGC2 — — 0FFA0H External interrupt mode register 0 INTM0 — 0FFA1H External interrupt mode register 1 INTM1 — 0FFA4H Sampling clock selection register SCS0 — — 0FFA8H In-service priority register ISPR R — 0FFAAH Interrupt mode control register IMC R/W — 80H 0FFACH Interrupt mask register 0L MK0L MK0 FFFFH 0FFADH Interrupt mask register 0H MK0H 0FFAEH Interrupt mask register 1L MK1L MK1 FFFFH 0FFAFH Interrupt mask register 1H MK1H 0FFB0H Bus control register BCR — 00H 0FFB2H Unit address register UAR — — 0000H

0FFB4H Slave address register SAR — — 0FFB6H Partner address register PAR R — —

0FFB8H Control data register CDR R/W — — 01H 0FFB9H Telegraph length register DLR — —

Note

Special Function Register (SFR) Name Symbol R/W

Serial transmission shift register: UART0 TXS W — — Serial shift register: IOE1 SIO1 R/W — —

Serial transmission shift register: UART2 TXS2 W — — Serial shift register: IOE2 SIO2 R/W — —

Bit Units for Manipulation

1 bit 8 bits 16 bits

After Reset

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,

F0000H is added to each address.

Data Sheet U11680EJ2V0DS00

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