NEC PD78081, PD78082 Service Manual

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD78081(A), 78082(A)

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The μPD78081(A) and 78082(A) are members of the μPD78083 Subseries of the 78K/0 Series microcontrollers. These products are produced with a more stringent quality assurance program than that of the μPD78081 and 78082 (standard models) (NEC classifies these products as “special products” by quality grade).

Besides a high-speed, high-performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, 8-bit resolution A/D converter, timer, serial interface, interrupt control, and other peripheral hardware.

The μPD78P083(A) including a one-time PROM version which can operate in the same power supply voltage range as a mask ROM version, and various development tools are available.

The details of the functions are described in the following User’s Manuals. Be sure to read the documents before

starting design.
μPD78083 Subseries User’s Manual	: IEU-1407
78K/0 Series User’s Manual Instructions	: IEU-1372

FEATURES

• Internal ROM and RAM

Item	Program Memory	Data Memory	Package
	(ROM)	(Internal High-speed RAM)
Part Number
μPD78081(A)	8 Kbytes	256 bytes	44-pin plastic QFP (10 × 10 mm)
μPD78082(A)	16 Kbytes	384 bytes

•Minimum instruction execution time can be changed from high-speed (0.4 μs) to low-speed (12.8 μs)

•I/O ports: 33

•8-bit resolution A/D converter : 8 channels

•Serial interface : 1 channel

3-wire serial I/O/UART mode : 1 channel

•Timer : 3 channels

•Supply voltage : VDD = 1.8 to 5.5 V

APPLICATION FIELDS

Controllers for automobile electronic control systems, gas detector circuit-breakers, various types of safety equipment, etc.

In addition to the μPD78081(A) and 78082(A), this Data Sheet also describes the μPD78081(A2). Unless otherwise specified, however, the μPD78081(A) and 78082(A) are used throughout this Data Sheet as the representative products, and their descriptions also apply to the μPD78081(A2).

The information in this document is subject to change without notice.

Document No. U12436EJ1V0DS00 (1st edition)
Date Published July 1997 N
Printed in Japan	©	1997

μPD78081(A), 78082(A)

ORDERING INFORMATION

Part Number

Package

μPD78081GB(A)-×××-3B4

μPD78081GB(A)-×××-3BS-MTX

μPD78082GB(A)-×××-3B4

μPD78082GB(A)-×××-3BS-MTX

μPD78081GB(A2)-×××-3B4

Note

Note

44-pin plastic QFP (10 × 10 mm)

44-pin plastic QFP (10 × 10 mm)

44-pin plastic QFP (10 × 10 mm)

44-pin plastic QFP (10 × 10 mm)

44-pin plastic QFP (10 × 10 mm)

Note Under planning

Caution μPD78081GB(A) and 78082GB(A) have two kinds of package (Refer to 11. PACKAGE DRAWINGS).

Please consult NEC’s sales representative for the available package.

Remark ××× indicates ROM code suffix.

QUALITY GRADE

Special

Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

DIFFERENCES BETWEEN μPD78081 AND 78082, AND μPD78081(A) AND 78082(A)

Part Number		μPD78081, 78082	μPD78081(A), 78082(A)
Item
Quality grade	Standard		Special
Package	•	42-pin plastic shrink DIP (600 mil)	44-pin plastic QFP (10 × 10 mm)
	•	44-pin plastic QFP (10 × 10 mm)

DIFFERENCES BETWEEN μPD78081(A) AND 78081(A2)

Part Number	μPD78081(A)	μPD78081(A2)
Item
Supply voltage	VDD = 1.8 to 5.5 V	VDD = 5 V ±10%
Minimum instruction execution	0.4 μs (at 5 MHz)	0.57 μs (at 7 MHz)
time
Operating ambient temperature	TA = –40 to 85˚C	TA = –40 to +125˚C

Remark In addition to the above parameters, the supply current also differs. For details, refer to 10. ELECTRICAL

SPECIFICATIONS.

2

μPD78081(A), 78082(A)

78K/0 SERIES DEVELOPMENT

The following shows the 78K/0 Series products development. Subseries names are shown inside frames.

78K/0 Series

			Control
	100-pin		μPD78075B	μPD78075BY
		100-pin	μPD78078	μPD78078Y
		100-pin	μ	μ
			PD78070A	PD78070AY
		100-pin		μPD780018AY
		80-pin	μPD780058	μPD780058Y Note
		80-pin	μPD78058F	μPD78058FY
		80-pin	μPD78054	μPD78054Y
		64-pin	μPD780034	μPD780034Y
		64-pin	μPD780024	μPD780024Y
		64-pin	μPD78014H
		64-pin	μPD78018F	μPD78018FY
		64-pin	μPD78014	μPD78014Y
		64-pin	μPD780001
		64-pin	μPD78002	μPD78002Y
		42/44-pin	μPD78083

	Inverter control
64-pin	μPD780964
64-pin	μPD780924
	FIPTM drive
100-pin	μPD780208
100-pin	μPD780228
80-pin	μPD78044H
80-pin	μPD78044F
	LCD drive
100-pin	μPD780308	μPD780308Y
100-pin	μPD78064B
100-pin	μPD78064	μPD78064Y
	IEBusTM supported
80-pin	μPD78098B
80-pin	μPD78098
	Meter control
80-pin	μPD780973
	LV
64-pin	μPD78P0914

Products in mass production

Products under development

Y subseries products are compatible with I2C bus.

EMI noise reduction version of the μPD78078.

A timer was added to the μPD78054, and the external interface function was enhanced. ROM-less versions of the μPD78078.

Serial I/O of the μPD78078Y was enhanced, and only selected functions are provided. Serial I/O of the μPD78054 was enhanced, EMI noise reduction version.

EMI noise reduction version of the μPD78054.

UART and D/A converter were added to the μPD78014, and I/O was enhanced. An A/D converter of the μPD780024 was enhanced.

Serial I/O of the μPD78018F was enhanced, EMI noise reduction version. EMI noise reduction version of the μPD78018F.

Low-voltage (1.8 V) operation versions of the μPD78014 with several ROM and RAM capacities available. An A/D converter and 16-bit timer were added to the μPD78002.

An A/D converter was added to the μPD78002. Basic subseries for control.

On-chip UART, capable of operating at a low voltage (1.8 V).

An A/D converter of the μPD780924 was enhanced.

On-chip inverter control circuit and UART, EMI noise reduction version.

The I/O and FIP C/D of the μPD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the μPD78044H were enhanced, Display output total: 48 N-ch open-drain input/output was added to the μPD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34

SIO of the μPD78064 was enhanced, and ROM and RAM were expanded. EMI noise reduction version of the μPD78064.

Basic subseries for driving LCDs, On-chip UART.

EMI noise reduction version of the μPD78098.

The IEBus controller was added to the μPD78054.

On-chip automobile meter driving controller/driver.

On-chip PWM output, LV digital code decoder, Hsync counter.

Note Under planning

3

μPD78081(A), 78082(A)

The following table shows the differences among subseries functions.

Function

ROM

Timer

8-bit 10-bit

8-bit

Serial Interface

I/O

VDD

External

MIN.

Subseries Name

Capacity

8-bit 16-bit Watch

WDT

A/D

A/D

D/A

Value Expansion

Control

μPD78075B

32 K to 40 K

4ch

1ch

1ch

1ch

8ch

–

2ch

3ch (UART: 1ch)

88

1.8

V

Available

μPD78078

48 K to 60 K

μPD78070A

–

61

2.7

V

μPD780058

24 K to 60 K

2ch

2ch

3ch (time-division UART: 1ch)

68

1.8

V

μPD78058F

48 K to 60 K

3ch (UART: 1ch)

69

2.7

V

μPD78054

16 K to 60 K

2.0

V

μPD780034

8 K to 32 K

–

8ch

–

3ch (UART: 1ch,

51

1.8

V

μPD780024

8ch

–

time-division 3-wire: 1ch)

μPD78014H

2ch

53

μPD78018F

8 K to 60 K

μPD78014

8 K to 32 K

2.7

V

μPD780001

8 K

–

–

1ch

39

–

μPD78002

8 K to 16 K

1ch

–

53

Available

μPD78083

–

8ch

1ch (UART: 1ch)

33

1.8

V

–

Inverter

μPD780964

8 K to 32 K

3ch

Note

–

1ch

–

8ch

–

2ch (UART: 2ch)

47

2.7

V

Available

control

μPD780924

8ch

–

FIP

μPD780208

32 K to 60 K

2ch

1ch

1ch

1ch

8ch

–

–

2ch

74

2.7

V

–

drive

μPD780228

48 K to 60 K

3ch

–

–

1ch

72

4.5

V

μPD78044H

32 K to 48 K

2ch

1ch

1ch

68

2.7

V

μPD78044F

16 K to 40 K

2ch

LCD

μPD780308

48 K to 60 K

2ch

1ch

1ch

1ch

8ch

–

–

3ch (time-division UART: 1ch)

57

2.0

V

–

drive

μPD78064B

32 K

2ch (UART: 1ch)

μPD78064

16 K to 32 K

IEBus

μPD78098B

40 K to 60 K

2ch

1ch

1ch

1ch

8ch

–

2ch

3ch (UART: 1ch)

69

2.7

V

Available

supported

μPD78098

32 K to 60 K

Meter

μPD780973

24 K to 32 K

3ch

1ch

1ch

1ch

5ch

–

–

2ch (UART: 1ch)

56

4.5 V

–

control

LV

μPD78P0914

32 K

6ch

–

–

1ch

8ch

–

–

2ch

54

4.5

V

Available

Note 10-bit timer: 1 channel

4

				μPD78081(A), 78082(A)
	OVERVIEW OF FUNCTION
		Part Number	μPD78081(A)	μPD78082(A)
	Item
	Internal	ROM	8 Kbytes	16 Kbytes
	memory
		Internal high-speed RAM	256 bytes	384 bytes
	Memory space		64 Kbytes
	General registers		8 bits × 32 registers (8 bits × 8 registers × 4 banks)
	Minimum instruction execution time		On-chip minimum instruction execution time selective function
			0.4 μs/0.8 μs/1.6 μs/3.2 μs/6.4 μs/12.8 μs (at main system clock of 5.0 MHz)
	Instruction set		• 16-bit operation

•Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)

•Bit manipulation (set, reset, test, boolean operation)

•BCD adjustment, etc.

I/O ports				Total	: 33
			• CMOS input		: 01
			• CMOS I/O		: 32
A/D converter			8-bit resolution × 8 channels
Serial interface			3-wire serial I/O/UART mode selectable : 1 channel
Timer			• 8-bit timer/event counter : 2 channels
			• Watchdog timer		: 1 channel
Timer output			2 (8-bit PWM output)
Clock output			19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
			5.0 MHz (at main system clock of 5.0 MHz)
Buzzer output			1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock of 5.0 MHz)
Vectored		Maskable	Internal : 8, external : 3
interrupt
		Non-maskable	Internal : 1
sources
		Software	1
Supply voltage			VDD = 1.8 to 5.5 V
Operating ambient temperature			TA = –40 to +85°C
Package			44-pin plastic QFP (10 × 10 mm)
Caution	The supply voltage and other parameters of the μPD78081(A2) differ from those of the other models.

For details, refer to “DIFFERENCES BETWEEN μPD78081(A) AND 78081(A2)”.

5

μPD78081(A), 78082(A)

CONTENTS

1.	PIN CONFIGURATION (Top View) ...................................................................................................		7
2.	BLOCK DIAGRAM .............................................................................................................................		9
3.	PIN FUNCTIONS ..............................................................................................................................		10
	3.1	Port Pins ...................................................................................................................................................	10
	3.2	Non-port Pins ..........................................................................................................................................	11
	3.3	Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................	12
4.	MEMORY SPACE .............................................................................................................................		14
5.	PERIPHERAL HARDWARE FUNCTIONS ......................................................................................		15
	5.1	Ports ..........................................................................................................................................................	15
	5.2	Clock Generator ......................................................................................................................................	16
	5.3	Timer/Event Counter ...............................................................................................................................	16
	5.4	Clock Output Control Circuit.................................................................................................................	18
	5.5	Buzzer Output Control Circuit ..............................................................................................................	18
	5.6	A/D Converter ..........................................................................................................................................	19
	5.7	Serial Interface ........................................................................................................................................	20
6.	INTERRUPT FUNCTIONS ...............................................................................................................		21
7.	STANDBY FUNCTION .....................................................................................................................		24
8.	RESET FUNCTION ...........................................................................................................................		24
9.	INSTRUCTION SET ..........................................................................................................................		25
10.	ELECTRICAL SPECIFICATIONS ....................................................................................................		28
11.	PACKAGE DRAWINGS ...................................................................................................................		49
12.	RECOMMENDED SOLDERING CONDITIONS ..............................................................................		51
APPENDIX A. DEVELOPMENT TOOLS ..............................................................................................			52
APPENDIX B. RELATED DOCUMENTS ..............................................................................................			54

6

μPD78081(A), 78082(A)

1.PIN CONFIGURATION (Top View)

•44-pin plastic QFP (10 × 10 mm)

μPD78081GB(A)-×××-3B4

μPD78081GB(A)-×××-3BS-MTX Note

μPD78082GB(A)-×××-3B4

μPD78082GB(A)-×××-3BS-MTX Note

μPD78081GB(A2)-×××-3B4

	P11/ANI1	P10/ANI0	AVSS	AVREF	AVDD	VDD	X1	X2	IC	RESET	NC
	44	43	42	41	40	39	38	37	36	35	34
P12/ANI2	1										33	P03/INTP3
P13/ANI3	2										32	P02/INTP2
P14/ANI4	3										31	P01/INTP1
P15/ANI5	4										30	P00
P16/ANI6	5										29	P37
P17/ANI7	6										28	P36/BUZ
P72/ASCK/SCK2	7										27	P35/PCL
P71/TXD/SO2	8										26	P34
P70/RXD/SI2	9										25	P33
P101/TI6/TO6	10										24	P32
P100/TI5/TO5	11										23	NC
	12	13	14	15	16	17	18	19	20	21	22
	P50	P51	P52	P53	P54	VSS	P55	P56	P57	P30	P31

Note Under planning

Cautions 1. Connect IC (Internally Connected) pin directly to VSS.

2.Connect AVDD pin to VDD.

3.Connect AVSS pin to VSS.

4.Connect NC (Non-connection) pin to VSS for noise protection (It can be left open).

7

							μPD78081(A), 78082(A)
ANI0 to ANI7	:	Analog Input	P100, P101			:	Port10
ASCK	:	Asynchronous Serial Clock	PCL			:	Programmable Clock
AVDD	:	Analog Power Supply	RESET			:	Reset
AVREF	:	Analog Reference Voltage	RxD			:	Receive Data
AVSS	:	Analog Ground	SCK2			:	Serial Clock
BUZ	:	Buzzer Clock	SI2			:	Serial Input
IC	:	Internally Connected	SO2			:	Serial Output
INTP1 to INTP3	:	Interrupt from Peripherals	TI5, TI6			:	Timer Input
NC	:	Non-connection	TO5, TO6			:	Timer Output
P00 to P03	:	Port0	TxD			:	Transmit Data
P10 to P17	:	Port1	VDD			:	Power Supply
P30 to P37	:	Port3	VSS			:	Ground
P50 to P57	:	Port5	X1, X2			:	Crystal (Main System Clock)
P70 to P72	:	Port7

8

μPD78081(A), 78082(A)

2. BLOCK DIAGRAM
P100/TI5/TO5	8-bit TIMER/
	EVENT COUNTER 5
P101/TI6/TO6	8-bit TIMER/
	EVENT COUNTER 6
	WATCHDOG	78K/0	ROM
		CPU
	TIMER
		CORE
SI2/RXD/P70	SERIAL
SO2/TXD/P71
	INTERFACE 2
SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

A/D

AVDD

CONVERTER

AVSS

AVREF

RAM

INTP1/P01 to

INTERRUPT

INTP3/P03

CONTROL

BUZ/P36

BUZZER OUTPUT

PCL/P35

CLOCK OUTPUT

CONTROL

VDD VSS IC

PORT 0					P00
					P01 to P03
					P10 to P17
PORT 1
					P30 to P37
PORT 3
					P50 to P57
PORT 5
					P70 to P72
PORT 7
					P100, P101
PORT 10
SYSTEM					RESET
					X1
CONTROL
					X2

Remark The internal ROM and internal high-speed RAM capacities depend on the product.

9

μPD78081(A), 78082(A)

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name	Input/Output		Function		After Reset		Shared by:
P00	Input	Port 0		Input only	Input		—
P01	Input/output	4-bit input/output port		Input/output is specifiable	Input	INTP1
P02				bit-wise. When used as the		INTP2
P03				input port, it is possible to		INTP3
				connect a pull-up resistor by
				software.
P10 to P17	Input/output	Port 1			Input	ANI0 to ANI7
		8-bit input/output port
		Input/output is specifiable bit-wise.
		When used as the input port, it is possible to connect
		a pull-up resistor by software. Note
P30 to P34	Input/output	Port 3			Input		—
P35		8-bit input/output port				PCL
P36		Input/output is specifiable bit-wise.				BUZ
P37		When used as the input port, it is possible to connect					—
		a pull-up resistor by software.
P50 to P57	Input/output	Port 5			Input		—
		8-bit input/output port
		Can drive up to seven LEDs directly.
		Input/output is specifiable bit-wise.
		When used as the input port, it is possible to connect
		a pull-up resistor by software.
P70	Input/output	Port 7			Input	SI2/RxD
P71		3-bit input/output port				SO2/TxD
P72		Input/output is specifiable bit-wise.
							SCK2/ASCK
		When used as the input port, it is possible to connect
		a pull-up resistor by software.
P100	Input/output	Port 10			Input	TI5/TO5
P101		2-bit input/output port				TI6/TO6
		Input/output is specifiable bit-wise.
		When used as the input port, it is possible to connect
		a pull-up resistor by software.

Note When P10/ANI0 to P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the

input mode. The on-chip pull-up resistor is automatically disabled.

10

μPD78081(A), 78082(A)

3.2 Non-port Pins

	Pin Name			Input/Output	Function	After Reset	Shared by:
	INTP1			Input	External interrupt request input by which the active edge	Input	P01
	INTP2				(rising edge, falling edge, or both rising and falling edges) can		P02
	INTP3				be specified.		P03
	SI2			Input	Serial interface serial data input.	Input	P70/RxD
	SO2			Output	Serial interface serial data output.	Input	P71/TxD
				Input/Output	Serial interface serial clock input/output.	Input	P72/ASCK
	SCK2
	RxD			Input	Asynchronous serial interface serial data input.	Input	P70/SI2
	TxD			Output	Asynchronous serial interface serial data output.	Input	P71/SO2
	ASCK			Input	Asynchronous serial interface serial clock input.	Input
							P72/SCK2
	TI5			Input	External count clock input to 8-bit timer (TM5).	Input	P100/TO5
	TI6				External count clock input to 8-bit timer (TM6).		P101/TO6
	TO5			Output	8-bit timer (TM5) output.	Input	P100/TI5
	TO6				8-bit timer (TM6) output.		P101/TI6
	PCL			Output	Clock output. (for main system clock trimming)	Input	P35
	BUZ			Output	Buzzer output.	Input	P36
	ANI0 to ANI7			Input	A/D converter analog input.	Input	P10 to P17
	AVREF			Input	A/D converter reference voltage input.	—		—
	AVDD			—	A/D converter analog power supply. Connected to VDD.	—		—
	AVSS			—	A/D converter ground potential. Connected to VSS.	—		—
	RESET			Input	System reset input.	—		—
	X1			Input	Main system clock oscillation crystal connection.	—		—
	X2			—		—		—
	VDD			—	Positive power supply.	—		—
	VSS			—	Ground potential.	—		—
	IC			—	Internal connection. Connect directly to VSS.	—		—
	NC			—	Does not internally connected. Connect to VSS.	—		—
					(It can be left open)

11

μPD78081(A), 78082(A)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Input/Output Circuit Type of Each Pin

		Pin Name			Input/Output	I/O	Recommended Connection for Unused Pins
					Circuit Type
	P00				2	Input	Connect to VSS.
	P01/INTP1				8-A	Input/output	Connect to VSS via a resistor individually.
	P02/INTP2
	P03/INTP3
	P10/ANI0 to P17/ANI7				11	Input/output	Connect to VDD or VSS via a resistor individually.
	P30 to P32				5-A
	P33, P34				8-A
	P35/PCL				5-A
	P36/BUZ
	P37
	P50 to P57				5-A
	P70/SI2/RxD				8-A
	P71/SO2/TxD				5-A
	P72/SCK2/ASCK				8-A
	P100/TI5/TO5				8-A
	P101/TI6/TO6
	RESET				2	Input	—
	AVREF				—	—	Connect to VSS.
	AVDD						Connect to VDD.
	AVSS						Connect to VSS.
	IC						Connect directly to VSS.
	NC						Connect to VSS (It can be left open).

12

					μPD78081(A), 78082(A)
		Figure 3-1.	Pin Input/Output Circuits
	Type 2			Type 8-A	VDD
				pullup	P-ch
				enable
	IN				VDD
				data	P-ch
					IN/OUT
	Schmitt-triggered input with hysteresis characteristic			output	N-ch
				disable
	Type 5-A	VDD		Type 11	VDD
	pullup			pullup	P-ch
		P-ch		enable
	enable
					VDD
		VDD		data	P-ch
	data	P-ch			IN/OUT
				output
					N-ch
		IN/OUT		disable
					P-ch
	output			Comparator
		N-ch
	disable			+
				–
					N-ch
	input			VREF(threshold voltage)
				input
	enable
				enable

13

μPD78081(A), 78082(A)

4. MEMORY SPACE

The memory map of the μPD78081(A) and 78082(A) is shown in Figure 4-1.

Figure 4-1. Memory Map

				FFFFH
					Special function registers
					(SFR) 256 × 8 bits
				FF00H
				FEFFH
					General-purpose registers
				FEE0H	32 × 8 bits
				FEDFH			nnnnH	Program area
					Internal high-speed RAM Note		1000H
Data							0FFFH
memory								CALLF entry area
space				mmmmH
		mmmmH – 1					0800H
							07FFH
					Use prohibited			Program area
							0080H
				nnnnH + 1			007FH
				nnnnH			0040H	CALLT table area
	Program
					Internal ROM Note		003FH
	memory
	space							Vector table area
				0000H			0000H

Note The internal ROM and internal high-speed RAM capacities depend on the product (See the following table).

	Part Number	Internal ROM Last Address	Internal High-speed RAM Start Address
		nnnnH	mmmmH
	μPD78081(A)	1FFFH	FE00H
	μPD78082(A)	3FFFH	FD80H

14

μPD78081(A), 78082(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports
Input/output ports are classified into two types.
	•	CMOS input (P00)	:	1
	•	CMOS input/output (P01 to P03, Port 1, Port 3, Port 5, Port 7, Port 10)	:	32
		Total	:	33

		Table 5-1. Functions of Ports
Port Name	Pin Name	Function
Port 0	P00	Input only.
	P01 to P03	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.
Port 1	P10 to P17	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.
Port 3	P30 to P37	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.
Port 5	P50 to P57	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.
		LED can be driven directly up to 7 pins.
Port 7	P70 to P72	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.
Port 10	P100, P101	Input/output port. Input/output can be specified bit-wise.
		When used as an input port, on-chip pull-up resistor can be used by software.

15

μPD78081(A), 78082(A)

5.2 Clock Generator

Main system clock generator is incorporated.

It is possible to change the minimum instruction execution time.

• 0.4 μs/0.8 μs/1.6 μs/3.2 μs/6.4 μs/12.8 μs (at main system clock frequency of 5.0 MHz)

Figure 5-1. Clock Generator Block Diagram

X1	Main system	fX		Selector
	clock
X2	oscillator		Division
			circuit	fX
				2
	STOP

Prescaler

fXX

fXX fXX fXX fXX

2

22

23

2 4

Selector

Prescaler

Standby control circuit

Clock to peripheral hardware

CPU clock (fCPU)

5.3 Timer/Event Counter

There are the following three timer/event counter channels:

•	8-bit timer/event counter	:	2 channels
•	Watchdog timer	:	1 channel

Table 5-2. Types and Functions of Timer/Event Counters

		8-bit Timer/Event Counter 5, 6	Watchdog Timer
Type	Interval timer	2 channels	1 channel
	External event counter	2 channels	—
Function	Timer output	2 outputs	—
	PWM output	2 outputs	—
	Square wave output	2 outputs	—
	Interrupt request	2	1

16

μPD78081(A), 78082(A)

2fXX to fXX/29

fXX/211

TI5/P100/TO5,

TI6/P101/TO6

n = 5, 6

Figure 5-2. 8-Bit Timer/Event Counter 5, 6 Block Diagram

Internal bus

8-bit compare register (CRn0)

Match

					INTTMn
	Selector		OVF	Output control	TO5/P100/TI5,
		8-bit timer register n			TO6/P101/TI6
				circuit
		(TMn)
			Clear
		Internal bus

Figure 5-3. Watchdog Timer Block Diagram

fXX			Prescaler
2 3
fXX	fXX	fXX	fXX	fXX	fXX	fXX
2 4	2 5	2 6	2 7	2 8	29	2 11
						Selector	8-bit counter

Control

circuit

INTWDT maskable

interrupt request

RESET

INTWDT non-maskable

interrupt request

17

μPD78081(A), 78082(A)

5.4 Clock Output Control Circuit

This circuit can output clocks of the following frequencies:

•19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (at main system clock frequency of 5.0 MHz)

Figure 5-4. Clock Output Control Circuit Block Diagram

fXX

fXX/2 fXX/22

fXX/23

fXX/24

fXX/25

fXX/26

fXX/27

Selector

	Synchronization	Output control	PCL/P35
	circuit	circuit

5.5 Buzzer Output Control Circuit

This circuit can output clocks of the following frequencies that can be used for driving buzzers:

• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (at main system clock frequency of 5.0 MHz)

Figure 5-5. Buzzer Output Control Circuit Block Diagram

fXX/29

fXX/210

fXX/211

Selector

Output control

BUZ/P36

circuit

18