Page 1
MM54HC175/MM74HC175
Quad D-Type Flip-Flop With Clear
General Description
This high speed D-TYPE FLIP-FLOP with complementary
outputs utilizes advanced silicon-gate CMOS technology to
achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the
ability to drive 10 LS-TTL loads.
Information at the D inputs of the MM54HC175/
MM74HC175 is transferred to the Q and Q
outputs on the
positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available.
All four flip flops are controlled by a common clock and a
common CLEAR. Clearing is accomplished by a negative
pulse at the CLEAR input. All four Q outputs are cleared to a
logical ‘‘0’’ and all four Q
outputs to a logical ‘‘1.’’
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
Features
Y
Typical propagation delay: 15 ns
Y
Wide operating supply voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 80 mA maximum (74HC)
Y
High output drive current: 4 mA minimum (74HC)
and ground.
CC
MM54HC175/MM74HC175 Quad D-Type Flip-Flop With Clear
January 1988
Connection Diagram
Truth Table
(Each Flip-Flop)
Dual-In-Line Package
Top View
Order Number MM54HC175 or MM74HC175
Inputs Outputs
Clear Clock D Q Q
LXXLH
H
H
HLXQ
e
H
high level (steady state)
e
low level (steady state)
L
e
irrelevant
X
e
transition from low to high level
u
e
the level of Q before the indicated
Q
0
steady-state input conditions were established
HH L
u
LL H
u
Q
0
0
TL/F/5319– 1
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5319
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
e
2.0V(tr,tf) 1000 ns
V
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
eb
A
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
Page 3
e
AC Electrical Characteristics V
CC
5V, T
e
A
Symbol Parameter Conditions Typ
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REC
t
S
t
H
t
W
Maximum Operating 60 35 MHz
Frequency
Maximum Propagation 15 25 ns
Delay, Clock to Q or Q
Maximum Propagation 13 21 ns
Delay, Reset to Q or Q
Minimum Removal 20 ns
Time, Clear to Clock
Minimum Setup Time, Data to Clock 20 ns
Minimum Hold Time, Data from Clock 0 ns
Minimum Pulse Width, Clock or Clear 10 16 ns
25§C, C
e
15 pF, t
L
Guaranteed
Limit
e
e
t
6ns
r
f
Units
AC Electrical Characteristics V
CC
Symbol Parameter Conditions V
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REM
t
S
t
H
t
W
tr,t
f
t
TLH,tTHL
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Operating 2.0V 12 6 5 4 MHz
Frequency 4.5V 60 30 24 20 MHz
Maximum Propagation 2.0V 80 150 190 225 ns
Delay, Clock to Q or Q 4.5V 15 30 38 45 ns
Maximum Propagation 2.0V 64 125 158 186 ns
Delay, Reset to Q or Q
Minimum Removal Time 2.0V 100 125 150 ns
Clear to Clock 4.5V 20 25 30 ns
Minimum Setup Time 2.0V 100 125 150 ns
Data to Clock 4.5V 20 25 30 ns
Minimum Hold Time 2.0V 0 0 0 ns
Data from Clock 4.5V 0 0 0 ns
Minimum Pulse Width 2.0V 30 80 100 120 ns
Clear or Clock 4.5V 9 16 20 24 ns
Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
Maximum 2.0V 30 75 95 110 ns
Output Rise and 4.5V 9 15 19 22 ns
Fall Time 6.0V 8 13 16 19 ns
Power Dissipation (per 150 pF
Capacitance (Note 5) package)
Maximum Input 5 10 10 10 pF
Capacitance
e
2.0V to 6.0V, C
CC
e
L
e
T
25§C
A
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
74HC 54HC
eb
T
40 to 85§CT
A
eb
A
55 to 125§C
Typ Guaranteed Limits
6.0V 70 35 28 24 MHz
6.0V 13 26 32 38 ns
4.5V 14 25 32 37 ns
6.0V 12 21 27 32 ns
6.0V 17 21 25 ns
6.0V 17 21 25 ns
6.0V 0 0 0 ns
6.0V 8 14 17 20 ns
6.0V 400 400 400 ns
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
Page 4
Logic Diagram
TL/F/5319– 2
4
Page 5
Physical Dimensions inches (millimeters)
Order Number MM54HC175J or MM74HC175J
Dual-In-Line Package
NS Package J16A
5
Page 6
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package
Order Number MM74HC175N
NS Package N16E
MM54HC175/MM74HC175 Quad D-Type Flip-Flop With Clear
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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Tel: 1(800) 272-9959 Deutsch Tel: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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