National Semiconductor MM54C32, MM74C32 Technical data
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MM54C32/MM74C32 Quad 2-Input OR Gate
MM54C32/MM74C32 Quad 2-Input OR Gate
February 1988
General Description
Employing complementary MOS (CMOS) transistors to
achieve low power and high noise margin, these gates provide the basic functions used in the implementation of digital
integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with
output swings essentially equal to the supply voltage. This
results in high noise immunity over a wide supply voltage
range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge damage.
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54C32 or MM74C32
Features
Y
Wide supply voltage range 3.0V to 15V
Y
Guaranteed noise margin 1.0V
Y
High noise immunity 0.45V VCC(typ.)
Y
Low power fan out of 2
TTL compatibility driving 74L
TL/F/5881– 1
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5881
Absolute Maximum Ratings (Note 1)
b
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
MM54C32
MM74C32
b
0.3V to V
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
Absolute Maximum V
Range 3.0V to 15V
CC
CC
Lead Temperature
65§Ctoa150§C
18V
(Soldering, 10 seconds) 260
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (see 54C/74C Family Characteristics Data Sheet) T
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Output Source Current V
(P-Channel)
Output Source Current V
(P-Channel)
Output Sink Current V
(N-Channel)
Output Sink Current V
(N-Channel)
e
5.0V 3.5 V
CC
e
V
10V 8.0 V
CC
e
5.0V 1.5 V
CC
e
V
10V 2.0 V
CC
CC
V
CC
CC
V
CC
CC
CC
CC
74C, V
74C, V
74C, V
74C, V
CC
CC
CC
CC
e
e
e
e
e
e
e
e
e
e
e
eb
5.0V, I
10V, I
5.0V, I
10V, I
15V, V
15V, V
10 mA 4.5 V
O
eb
10 mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
e
15V 0.005 1.0 mA
IN
e
0V
IN
b
1.0
b
0.005 mA
15V 0.05 15 mA
e
4.5V V
CC
e
4.75V V
CC
e
4.5V 0.8 V
CC
e
4.75V 0.8 V
CC
e
CC
e
CC
e
CC
e
CC
5.0V, V
10V, V
5.0V, V
10V, V
4.5V, I
4.75V, I
4.5V, I
4.75V, I
OUT
OUT
OUT
OUT
eb
360 mA 2.4 V
O
eb
360 mA 2.4 V
O
e
360 mA 0.4 V
O
e
360 mA 0.4 V
O
e
25§C (short circuit current)
A
e
0V
e
0V
e
V
CC
e
V
CC
b
1.5 V
CC
b
1.5 V
CC
b
1.75
b
8.0
b
3.3 mA
b
15 mA
1.75 3.6 mA
8.0 16 mA
C
§
2
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