National Semiconductor MM54HC85, MM74HC85 Service Manual
MM54HC85/MM74HC85
4-Bit Magnitude Comparator
General Description
The MM54HC85/MM74HC85 is a 4-bit magnitude comparator that utilizes advanced silicon-gate CMOS technology. It
is designed for high speed comparison of two four bit words.
This circuit has eight comparison inputs, 4 for each word;
three cascade inputs (A
sion outputs (A
is indicated by a high level on one of the decision outputs.
Thus it may be determined whether one word is ‘‘greater
than,’’ ‘‘less than,’’ or ‘‘equal to’’ the other word. By connecting the outputs of the least significant stage to the cascade inputs of the next stage, words of greater than four bits
can be compared. In addition the least significant stage
must have a high level applied to the A
level to the A
k
k
k
B, AlB, AeB). The result of a comparison
B, and AlB inputs.
B, AlB, AeB); and three deci-
e
B input, and a low
November 1995
The comparator’s outputs can drive 10 low power Schottky
TTL (LS-TTL) equivalent loads, and is functionally, and pin
equivalent to the 54LS85/74LS85. All inputs are protected
from damage due to static discharge by diodes to V
ground.
CC
and
Features
Y
Typical propagation delay: 27 ns
Y
Wide operating voltage range: 2–6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Output drive capability: 10 LS-TTL loads
MM54HC85/MM74HC85 4-Bit Magnitude Comparator
Connection Diagram
Dual-In-Line Package
TL/F/5205– 1
Order Number MM54HC85 or MM74HC85
Truth Table
Comparing Cascading
Inputs Inputs
A3, B3 A2, B2 A1, B1 A0, B0 AlBAkBA
A3lB3 X X X X X X H L L
k
B3 X X X X X X L H L
A3
e
B3 A2lB2 X X X X X H L L
A3
e
B3 A2kB2 X X X X X L H L
A3
e
B3 A2eB2 A1lB1 X X X X H L L
A3
A3eB3 A2eB2 A1kB1 X X X X L H L
e
B3 A2eB2 A1eB1 A0lB0 X X X H L L
A3
A3eB3 A2eB2 A1eB1 A0kB0 X X X L H L
e
B3 A2eB2 A1eB1 A0eB0 H L L H L L
A3
e
B3 A2eB2 A1eB1 A0eB0 L H L L H L
A3
e
B3 A2eB2 A1eB1 A0eB0XXHLLH
A3
e
B3 A2eB2 A1eB1 A0eB0HHLLLL
A3
e
B3 A2eB2 A1eB1 A0eB0LL LHHL
A3
e
BAlBAkBA
Outputs
e
B
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/F/5205
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C
C
2
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