National Semiconductor ADC12V170 User Manual

Evaluation Board User’s Guide for

ADC12V170: 12-Bit, 170 MSPS Analog to Digital Converter

with LVDS Outputs

N www.national.com

Rev 0.0

October 2007

ADC12V170 Evaluation Board User’s Guide

FIN < 1

5

0 MHz

Connector

ADC

Network

FIN > 1

5

0 MHz

Connector

Analog Input

Clock

Buffer

(Reverse

Side)

Analog Input

PD
Jumper

CLK_SEL/DF
Jumper

Analog Input

Single-

Ended

Clock

Input

5.0V Power

Figure 1. ADC12V170 Evaluation Board Connector and Jumper Locations

FutureBus

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ADC12V170 Evaluation Board User’s Guide

1.0 Introduction

The ADC12V170 Evaluation Board is designed to
support the ADC12V170 12-bit 170 Mega Sample Per
Second (MSPS) Analog to Digital Converter with LVDS
Outputs.

The ADC12V170 Evaluation Board comes in two
versions:

1. ADC12V170HFEB (high frequency version)
for input frequencies greater than 150 MHz.

2. ADC12V170LFEB (low frequency version) for
input frequencies less than 150 MHz.

The digital data from the ADC12V170 evaluation board
can be captured with a suitable instrument, such as a
logic analyzer, or with National Semiconductor’s
WaveVision signal path data acquisition hardware and
software platform. The ADC12V170 evaluation board
can be connected to the data acquisition hardware
through the FutureBus connector (schematic reference
designator FB).

The ADC12V170 is compatible with National
Semiconductor’s WaveVision 5.1 and higher Signal
Path Digital Interface Board and associated
WaveVision software. Please note that the
ADC12V170 board is not compatible with previous
versions of the WaveVision hardware (WaveVision 4.x
Digital Interface Boards).

The WaveVision hardware and software package
allows fast and easy data acquisition and analysis. The
WaveVision hardware connects to a host PC via a USB
cable and is fully configured and controlled by the latest
WaveVision software. The latest version of the
WaveVision software is included in this evaluation kit
on a CD-ROM. The WaveVision 5.1 Signal Path Digital
Interface hardware is available through the National
Semiconductor website (part number: WAVEVSN 5.1).

2.0 Board Assembly

Each evaluation board from the factory is configured for
single-ended clock operation and is populated with an
analog input network which has been optimized for one
of two analog input frequencies ranges:

1. ADC12V170HFEB (high frequency version)
for input frequencies greater than 150 MHz.

2. ADC12V170LFEB (low frequency version) for
input frequencies less than 150 MHz.

Please refer to the input circuit configurations
described in the Analog Input Section (4.2) of this
guide.

The location and description of the components on the
ADC12V170 evaluation board can be found in Figure 1
as well as Section 5.0 (Schematic) and Section 7.0 (Bill
of Materials) of this user’s guide.

3.0 Quick Start

The ADC12V170 evaluation board enables easy set up
for evaluating the performance of the ADC12V170.

If the WaveVision data acquisition and data analysis
system is to be used for capturing data, please follow
the Quick Start Guide in the WaveVision User’s Guide
to install the required software and to connect the
WaveVision Digital Interface Board to the PC and to
the ADC12V170 evaluation board. Please note that the
ADC12V170 evaluation board is only compatible with
National Semiconductor’s WaveVision 5.1 and higher
Signal Path Digital Interface boards.

3.1 Evaluation Board Jumper Positions

The ADC12V170 evaluation board jumpers should be
configured as follows. Please refer to Figure 1 for the
exact jumper locations.

1. J1 on the reverse of the board should be shorted.

2. The PD jumper places the ADC12V170 into either
powerdown or sleep mode. Table 1 below shows
how to select between the power modes.

PD Jumper
Setting

Open Normal Operation
1-2 Power-down
3-4 Sleep

Table 1. CLK_SEL/DF Selection Table

3. CLK_SEL/DF pin jumpers select the output data
format (2’s complement or offset binary) and clock
mode (single-ended or differential). Table 2 below
shows how to select between the clock modes and
output data formats. Please note that the
ADC12V170 evaluation board is delivered with the
ADC12V170 clock input configured for single­ended operation and Offset Binary output data
format (Jumper 7-8).

CLK_SEL/DF
Jumper
Setting

1-2 Differential 2’s Complement
3-4 Differential Offset Binary
5-6 Single-Ended 2’s Complement
7-8* Single-Ended Offset Binary

* As assembled from factory.

Table 2. CLK_SEL/DF Selection Table

Mode

Clock Mode Output Data

Format

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ADC12V170 Evaluation Board User’s Guide

3.2 Connecting Power and Signal Sources

1. To power the ADC12V170 evaluation board,
connect a 5.0V power supply capable of supplying
up to 500mA to the green power connector labeled
“+5V” which is located along the bottom edge of
the ADC12V170 evaluation board.

2. Use the FutureBus connector (FB) to connect the
ADC12V170 evaluation board to the instrument
being used to capture the data from the evaluation
board. If the WaveVision Digital Interface Board is
being used for data capture, please consult the
WaveVision User’s Guide for details on installing
and operating the WaveVision hardware and
software system.

3. Connect the clock and signal inputs to the
CLK_IN_SE and AIN_XX (where XX = HF or LF)
SMA connectors.

4.0 Functional Description

4.1 Clock Input

The clock used to sample the analog input should be
applied to the CLK_IN_SE SMA connector (if using the
single-ended clock mode).

To achieve the best noise performance (best SNR), a
low jitter clock source with total additive jitter less than
150 fs should be used. A low jitter crystal oscillator is
recommended, but a sinusoidal signal generator with
low phase noise, such as the SMA100A from Rohde &
Schwarz or the HP8644B (discontinued) from Agilent /
Hewlett Packard, can also be used with a slight
degradation in the noise performance. When using a
low phase noise clock source, the SNR is primarily
degraded by the broadband noise of the signal
generator. The clock signal generator amplitude is
typically set to +19.9 dBm to produce the highest
possible slew rate, but the SNR performance will be
impacted minimally by lowering the signal generator
amplitude slightly. Placing a bandpass filter between
the clock source and the CLK_IN_SE SMA connector
will further improve the noise performance of the ADC

by filtering out the broadband noise of the clock source.
All results in the ADC12V170 datasheet are obtained
with a tunable bandpass filter made by Trilithic, Inc. in
the clock signal path.

The noise performance of the ADC12V170 can be
improved further by making the edge transitions of the
clock signal entering the ADC clock input (pin 11,
CLK+) very sharp. The ADC12V170 evaluation board
is assembled with a high speed buffer gate
(NC7WV125K8X, schematic reference designator U2)
in the clock input path to provide a sharp clock edge to
the clock inputs and improve the noise performance of
the ADC. The amplitude of the clock signal from the
NC7WV125K8X high speed buffer is 3.3V.

4.2 Analog Input

To obtain the best distortion results (best SFDR), the
analog input network on the evaluation board must be
optimized for the signal frequency being applied.

For analog input frequencies up to 150 MHz, the circuit
in Figure 2 is recommended. This is the configuration
of the assembled ADC12V170LFEB as it is delivered
from the factory. For input frequencies above 150
MHz, the circuit in Figure 3 is recommended. This is
the configuration of the assembled ADC12V170HFEB
as it is delivered from the factory.

A low noise signal generator such as the HP8644B is
recommended to drive the signal input of the
ADC12V170 evaluation board. The output of the signal
generator must be filtered to suppress the harmonic
distortion produced by the signal generator and to allow
accurate measurement of the ADC12V170 distortion
performance. A low pass or a bandpass filter is
recommended to filter the analog input signal. In some
cases, a second low pass filter may be necessary. The
bandpass filter on the analog input will further improve
the noise performance of the ADC by filtering the
broadband noise of the signal generator. Data shown
in the ADC12V170 datasheet was taken with a tunable
bandpass filter made by Trilithic in the analog signal
path.

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ADC12V170 Evaluation Board User’s Guide

Figure 2. Analog Input Network of ADC12V170LFEB: FIN < 150 MHz

Figure 3. Analog Input Network of ADC12V170HFEB: FIN > 150 MHz

4.3 ADC Reference and Input Common Mode

The internal 1.0V reference on the ADC12V170 is used
to acquire all of the results in the ADC12V170
datasheet. It is recommended to use the internal
reference on the ADC12V170. However, if an external
reference is required, the ADC12V170 is capable of
accepting an external reference voltage between 0.9V
and 1.1V (1.0V recommended). The input impedance
of the ADC12V170 V
Therefore, to overdrive this pin, the output impedance
of the exernal reference source should be << 9 kΩ.

It is recommended to use the voltage at the VRM pin
(pin 45) of the ADC12V170 to provide the 1.5V
common mode voltage required for the differential
analog inputs V
evaluation board is factory-assembled with VRM
connected to the transformer center-tap through a

and V

IN+

pin (pin 46) is 9 kΩ.

REF

. The ADC12V170

IN-

49.9Ω resistor to provide the necessary common mode
voltage to the differential analog input.

4.4 Board Outputs

The digitized 12-bit output word from the ADC12V170
evaluation board is presented in interleaved double
data rate (DDR) format. The digital output lines from
the ADC12V170 evaluation board consist of 16 lines
which are arranged into 8 LVDS pairs. These 8 pairs
of lines carry the 12-bit output data (6 pairs), the DRDY
signal which should be used to capture the output data
(1 pair) and the over-range bit (OVR) which indicates
that the digital output has exceeded the maximum
digitizable signal (1 pair).

Since the data is presented in interleaved double data
rate (DDR) format, the 12-bit word is output on 6 data
pair lines with half of the data (odd bits: D1+/-, D3+/-,

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