National Semiconductor ADC12H030, ADC12H032, ADC12H034, ADC12H038, ADC12030, ADC12032, ADC12034, ADC12038 Technical data
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ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
General Description
The ADC12030, and ADC12H030 families are 12-bit plus
sign successive approximationA/DconverterswithserialI/O
and configurable input multiplexers. The ADC12032/
ADC12H032, ADC12034/ADC12H034 and ADC12038/
ADC12H038 have 2, 4 and 8 channel multiplexers, respectively.The differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2,A/DIN1andA/DIN2
pins. The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally
connected. The ADC12030 family is tested witha5MHz
clock, while the ADC12H030 family is tested with an 8 MHz
clock. On request, these A/Ds go through a self calibration
process that adjusts linearity, zero and full-scale errors to
less than
The analog inputs can be configured to operate in various
combinationsofsingle-ended,differential,or
pseudo-differential modes.A fully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the
NSC MICROWIRE
LM4040 or LM4041.
±
1 LSB each.
™
. For voltage references see the
Features
n Serial I/O (MICROWIRE Compatible)
n 2, 4, or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Variable resolution and conversion rate
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n Fully tested and guaranteed with a 4.096V reference
n 0V to 5V analog input range with single 5V power
supply
n No Missing Codes over temperature
Key Specifications
n Resolution12-bit plus sign
n 12-bit plus sign conversion time
SCLKThis is the serial data clock input. The clock
DIThis is the serial data input pin. The data ap-
sucessive approximation conversion time
interval and the acquisition time. The rise
and fall times of the clock edges should not
exceed 1 µs.
applied to this input controls the rate at
which the serial data exchange occurs. The
rising edge loads the information on the DI
pin into the multiplexer address and mode
select shift register. This address controls
which channel of the analog input multiplexer (MUX) is selected and the mode of
operation for the A/D. With CS low the falling edge of SCLK shifts the data resulting
from the previous ADC conversion out on
DO, with the exception of the first bit of data.
When CS is low continously, the first bit of
the data is clocked out on the rising edge of
EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not exceed 1 µs.
plied to this pin is shifted by the rising edge
of SCLK into the multiplexer address and
DS011354-9
Top View
mode select register.
5
show the assignment of the multiplexer
address and the mode select data.
DOThe data output pin. This pin is an active
EOCThis pin is an active push/pull output and in-
CS
push/pull output when CS is low. When CS
is high, this output is TRI-STATE. The A/D
conversion result (D0–D12) and converter
status data are clocked out by the falling
edge of SCLK on this pin. The word length
and format of this result can vary (see
1
). The word length and format are controlled by the data shifted into the multiplexer address and mode select register
(see
Table 5
dicates the status of the ADC12030/2/4/8.
When low, it signals that the A/D is busy with
a conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC
signals the end of one of these cycles.
This is the chip select pin. When a logic low
is applied to this pin, the rising edge of
SCLK shifts the data on DI into the address
register. This low also brings DO out of
TRI-STATE. With CS low the falling edge of
SCLK shifts the data resulting from the previous ADC conversion out on DO, with the
Table 2
through
Table
Table
).
www.national.com3
Pin Descriptions (Continued)
exception of the first bit of data. When CS is
low continously, the first bit of the data is
clocked out on the rising edge of EOC (end
of conversion). When CS is toggled the falling edge of CS always clocks out the first bit
of data. CS should be brought low when
SCLK is low. The falling edge of CS resets a
conversion in progress and starts the sequence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely terminated. The
data in the output latches may be corrupted.
Therefore, when CS is brought back low
during a conversion in progress the data
output at that time should be ignored. CS
may also be left continuously low. In this
case it is imperative that the correct number
of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC
supply power is applied it expects to see 13
clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is
the same as the digital output word length.
This word length can be modified by the
data shifted in on the DO pin.
the data required.
DOR
This is the data output ready pin.This pin is
an active push/pull output. It is low when the
conversion result is being shifted out and
goes high to signal that all the data has
been shifted out.
CONV
Alogic low is required on this pin to program
any mode or change the ADC’s configuration as listed in the Mode Programming
Table5
such as 12-bit conversion, 8-bit conversion, Auto Cal, Auto Zero etc. When this
pin is high the ADC is placed in the read
data only mode. While in the read data only
mode, bringing CS low and pulsing SCLK
will only clock out on DO any data stored in
the ADCs output shift register. The data on
DI will be neglected. A new conversion will
not be started and the ADC will remain in
the mode and/or configuration previously
programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.
PDThis is the power down pin. When PD is
high the A/D is powered down; when PD is
low the A/D is powered up. The A/D takes a
maximum of 250 µs to power up after the
command is given.
CH0–CH7These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on
the rising edge of SCLK into the address
register (See
Tables 2, 3, 4
The voltage applied to these inputs should
not exceed V
ing this range on an unselectedchannel will
+ or go below GND. Exceed-
A
corrupt the reading of a selected channel.
COMThis pin is another analog input pin. It is
used as a pseudo ground when the analog
multiplexer is single-ended.
Table5
).
details
MUXOUT1,
MUXOUT2
Thesearethemultiplexeroutput
pins.
A/DIN1, /DIN2 These are the converter input pins. MUX-
OUT1 is usually tied to A/DIN1. MUXOUT2
is usually tied toA/DIN2. If external circuitry
is placed between MUXOUT1 and A/DIN1,
or MUXOUT2 and A/DIN2 it may be necessary to protect these pins. The voltage at
these pins should not exceed V
low AGND (see
+This is the positive analog voltage reference
V
REF
input. In order to maintain accuracy, the
voltage range of V
V
−) is 1 VDCto 5.0 VDCand the voltage
REF
at V
REF
for recommended bypassing.
−The negative voltage reference input. In or-
V
REF
der to maintain accuracy, the voltage at this
Figure 5
REF(VREF
+ cannot exceed VA+. See
pin must not go below GND or exceed V
(See
Figure 6
).
+, VD+These are the analog and digital power sup-
V
A
ply pins. V
gether on the chip. These pins should be
A
+
+
and V
are not connected to-
D
+
or go be-
A
).
=
+−
V
REF
Figure 6
A
tied to the same power supply and bypassed separately (see
ating voltage range of V
4.5 V
to 5.5 VDC.
DC
DGNDThis is the digital ground pin (see
AGNDThis is the analog ground pin (see
Figure 6
). The oper-
+ and VD+is
A
Figure 6
Figure 6
+.
).
).
www.national.com4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
+
=
+=VD+)6.5V
V
(V
Voltage at Inputs and Outputs
Voltage at Analog Inputs
|V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
ESD Susceptability (Note 5)
A
+
except CH0–CH7 and COM−0.3V to V
CH0–CH7 and COMGND −5V to V
+−VD+|300 mV
A
=
25˚C (Note 4)500 mW
T
A
+0.3V
+
±
30 mA
±
120 mA
+5V
Human Body Model1500V
Operating Ratings (Notes 1, 2)
Operating Temperature RangeT
ADC12030CIWM,
ADC12H030CIWM,
ADC12032CIWM,
ADC12H032CIWM,
ADC12034CIN, ADC12034CIWM,
ADC12H034CIN,
ADC12H034CIWM,
ADC12038CIWM,
ADC12H038CIWM−40˚C ≤ T
The following specifications apply for V
sion mode, f
ADC12030, ADC12032, ADC12034 and ADC12038, R
input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply
for T
A
SymbolParameterConditionsTypical
=
=
f
CK
=
=
T
J
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
+
=
+=VD+=+5.0 VDC,V
V
A
=
=
T
A
J
+=+4.096 VDC,V
REF
=
25Ω, source impedance for V
S
25˚C. (Notes 7, 8, 9)
−=0VDC, 12-bit + sign conver-
REF
+ and V
REF
(Note 10)
=
=
f
CK
REF
5 MHz for the
SK
− ≤ 25Ω, fully-differential
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No
12 + signBits (min)
Missing Codes
+ILEPositive Integral Linearity ErrorAfter Auto-Cal (Notes 12, 18)
The following specifications apply for V
sion mode, f
ADC12030, ADC12032, ADC12034 and ADC12038, R
input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=
=
f
CK
=
=
T
J
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
SymbolParameterConditionsTypical
STATIC CONVERTER CHARACTERISTICS
Offset Error8-bit + sign mode,
TUETotal Unadjusted Error8-bit + sign mode
Multiplexer Channel
to Channel Matching
Power Supply SensitivityV
+ Full-Scale Error
− Full-Scale Error
+ Integral Linearity Error
− Integral Linearity Error
Output Data from(Note 20)+10LSB (max)
“12-Bit Conversion of Offset”−10LSB (min)
(see
Table 5
)
Output Data from(Note 20)4095LSB (max)
“12-Bit Conversion of Full-Scale”4093LSB (min)
(see
Table 5
)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plusf
Distortion Ratiof
−3 dB Full Power BandwidthV
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plusf
Distortion Ratiof
−3 dB Full Power BandwidthV
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance85pF
A/DIN1 and A/DIN2 Analog75pF
Input Capacitance
A/DIN1 and A/DIN2 AnalogV
Input Leakage CurrentV
CH0–CH7 and COMGND − 0.05V (min)
Input VoltageV
C
CH
C
MUXOUT
CH0–CH7 and COM
Input Capacitance
MUX Output Capacitance20pF
Units
www.national.com6
Converter Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
ADC12030, ADC12032, ADC12034 and ADC12038, R
input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=
=
f
CK
=
=
T
J
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
SymbolParameterConditionsTypical
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
Off Channel Leakage (Note 16)On Channel=5V and−0.01−0.3µA (min)
CH0–CH7 and COM PinsOff Channel=0V
On Channel Leakage (Note 16)On Channel=5V and0.010.3µA (max)
CH0–CH7 and COM PinsOff Channel=0V
MUXOUT1 and MUXOUT2V
Leakage CurrentV
R
MUX On ResistanceV
ON
R
Matching ChannelV
ON
to ChannelV
Channel to Channel CrosstalkV
MUX Bandwidth90kHz
=
+=VD+=+5.0 VDC,V
V
A
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
+=+4.096 VDC,V
REF
−=0VDC, 12-bit + sign conver-
REF
+ and V
REF
(Note 10)
=
=
f
CK
REF
5 MHz for the
SK
− ≤ 25Ω, fully-differential
Limits
(Note 11)
On Channel=0V and0.010.3µA (max)
Off Channel=5V
On Channel=0V and−0.01−0.3µA (min)
Off Channel=5V
=
MUXOUT
MUXOUT
IN
V
MUXOUT
IN
MUXOUT
IN
5.0V or0.010.3µA (max)
=
0V
=
2.5V and8501150Ω (max)
=
2.4V
=
2.5V and5
=
2.4V
=
5V
=
40 kHz−72dB
PP,fIN
Units
(Limits)
%
DC and Logic Electrical Characteristics
The following specifications apply for V
sion mode, f
ADC12030, ADC12032, ADC12034 and ADC12038, R
input with fixed 2.048V common-mode voltage, and 10(t
for T
A
=
=
f
CK
=
=
T
J
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
+
=
+=VD+=+5.0 VDC,V
V
A
=
=
T
A
J
+=+4.096 VDC,V
REF
=
25Ω, source impedance for V
S
) acquisition time unless otherwise specified. Boldface limits apply
CK
25˚C. (Notes 7, 8, 9)
−=0VDC, 12-bit + sign conver-
REF
REF
+ and V
=
=
f
CK
REF
5 MHz for the
SK
− ≤ 25Ω, fully-differential
SymbolParameterConditionsTypicalLimitsUnits
(Note 10)(Note 11)(Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
ADC12030, ADC12032, ADC12034CS=HIGH, Powered Down, CCLK on
and ADC12038CS=HIGH, Powered Down, CCLK off
600µA
20µA
Digital Supply CurrentAwake2.33.2mA
ADC12H030, ADC12H032,CS=HIGH, Powered Down, CCLK on
ADC12H034 and ADC12H038CS=HIGH, Powered Down, CCLK off
0.9mA
20µA
www.national.com7
DC and Logic Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, f
ADC12030, ADC12032, ADC12034 and ADC12038, R
input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=
=
f
CK
=
=
T
J
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
SymbolParameterConditionsTypicalLimitsUnits
POWER SUPPLY CHARACTERISTICS
+Positive Analog Supply CurrentAwake2.74.0mA (max)
I
A
I
Reference Input CurrentAwake70µA
REF
=
+=VD+=+5.0 VDC,V
V
A
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Notes 7, 8, 9)
A
J
CS=HIGH, Powered Down, CCLK on
CS=HIGH, Powered Down, CCLK off
CS=HIGH, Powered Down
+=+4.096 VDC,V
REF
−=0VDC, 12-bit + sign conver-
REF
REF
+ and V
=
=
f
CK
REF
5 MHz for the
SK
− ≤ 25Ω, fully-differential
(Note 10)(Note 11)(Limits)
10µA
0.1µA
0.1µA
AC Electrical Characteristics
The following specifications apply for V
sion mode, t
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Bold-
face limits apply for T
SymbolParameterConditionsTypical
=
=
t
3 ns, f
r
f
CK
=
T
A
J
+
=
+=VD+=+5.0 VDC,V
V
=
f
SK
=
T
MIN
A
=
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
The following specifications apply for V
sion mode, t
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Bold-
Self-Calibration2(tCK)2(tCK)2(tCK)(min)
or Auto-Zero3(t
Synchronization Time0.2500.40µs (min)
from DOR0.3750.60µs (max)
t
DOR
DOR High Time9(tSK)9(tSK)9(tSK)(max)
when CS is Low
Continuously for Read
Data and Software
Power Up/Down
t
CONV
CONV Valid Data Time8(tSK)8(tSK)8(tSK)(max)
=
+=VD+=+5.0 VDC,V
V
A
=
f
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
(Note 10)
+=+4.096 VDC,V
REF
=
25Ω, source impedance for V
S
=
=
T
A
25˚C. (Note 17)
J
ADC12H030/2/4/8 ADC12030/2/4/8Units
LimitsLimits
−=0VDC, 12-bit + sign conver-
REF
(Note 11)(Note 11)
618.0988.8µs (max)
9.515.2µs (max)
)3(tCK)(max)
CK
1.1251.8µs (max)
1.01.6µs (max)
REF
+ and V
CK
REF
=
f
SK
− ≤ 25Ω,
(Limits)
=
5
AC Electrical Characteristics
The following specifications apply for V
sion mode, t
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Bold-
face limits apply for T
SymbolParameterConditionsTypical
t
HPU
=
=
t
3 ns, f
r
f
CK
=
T
A
J
Hardware Power-Up Time, Time from140250µs (max)
+
=
+=VD+=+5.0 VDC,V
V
=
f
SK
=
T
MIN
A
=
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
to T
; all other limits T
MAX
+=+4.096 VDC,V
REF
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Note 17)
A
J
REF
(Note 10)
−=0VDC, 12-bit + sign conver+ and V
REF
Limits
(Note 11)
CK
REF
=
f
SK
− ≤ 25Ω,
(Limits)
PD Falling Edge to EOC Rising Edge
t
SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to140250µs (max)
EOC Rising Edge
t
ACC
Access Time Delay from2050ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to30ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling05ns (min)
Edge to CS Falling Edge
=
t1H,t0HDelay from CS Rising Edge toR
L
=
3k, C
100 pF40100ns (max)
L
DO TRI-STATE
t
HDI
DI Hold Time from Serial Data515ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data510ns (min)
Clock Rising Edge
=
t
HDO
DO Hold Time from Serial DataR
L
=
3k, C
100 pF2550ns (max)
L
Clock Falling Edge5ns (min)
t
DDO
Delay from Serial Data Clock3550ns (max)
Falling Edge to DO Data Valid
=
5
Units
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AC Electrical Characteristics (Continued)
+
The following specifications apply for V
sion mode, t
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Bold-
face limits apply for T
=
=
t
3 ns, f
r
f
=
CK
=
=
T
A
J
SymbolParameterConditionsTypical
t
RDO
DO Rise Time, TRI-STATE to HighR
DO Rise Time, Low to High1030ns (max)
t
FDO
DO Fall Time, TRI-STATE to LowR
DO Fall Time, High to Low1230ns (max)
t
CD
Delay from CS Falling Edge2545ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling2545ns (max)
Edge to DOR Rising Edge
C
IN
C
OUT
Capacitance of Logic Inputs10pF
Capacitance of Logic Outputs20pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
max=150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
T
J
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
to ensure accurate conversions.
V
DC
) at any pin exceeds the power supplies (V
IN
=
+=VD+=+5.0 VDC,V
V
A
=
f
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
SK
to T
T
MIN
; all other limits T
MAX
=
3k, C
L
=
3k, C
L
IN
=
max − TA)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
(T
D
J
+=+4.096 VDC,V
REF
=
25Ω, source impedance for V
S
=
=
T
25˚C. (Note 17)
A
J
(Note 10)
=
100 pF1030ns (max)
L
=
100 pF1230ns (max)
L
<
GND or V
>
VA+orVD+), the current at that pin should be limited to 30 mA.
IN
max, θJAand the ambient temperature, TA. The maximum
+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55
A
=
f
CK
SK
− ≤ 25Ω,
REF
Units
(Limits)
+ or 5V below GND
A
=
5
Note 8: To guarantee accuracy, it is required that the V
pin.
www.national.com10
+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V
A
DS011354-2
+
AC Electrical Characteristics (Continued)
Note 9: With the test condition for V
=
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see
=
T
J
A
Figure 4
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: The ADC12030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
+−V
REF(VREF
25˚C and represent most likely parametric norm.
−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.
REF
).
=
0.4V for a falling edge and V
IL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
Figures 2, 3
).
=
2.4V for a rising edge. TRI-STATEoutput voltage is forced
IH
DS011354-10
FIGURE 1. Transfer Characteristic
DS011354-11
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
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AC Electrical Characteristics (Continued)
FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS011354-12
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FIGURE 4. Offset or Zero Error Voltage
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9)
Linearity Error Change
vs Clock Frequency
DS011354-53
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Linearity Error Change
vs Temperature
Linearity Error Change
vs Reference Voltage
DS011354-54
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Typical PerformanceCharacteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note
9) (Continued)
Linearity Error Change
vs Supply Voltage
Full-Scale Error Change
vs Reference Voltage
Zero Error Change
vs Temperature
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Full-Scale Error Change
vs Clock Frequency
Full-Scale Error Change
vs Supply Voltage
Zero Error Change
vs Reference Voltage
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Full-Scale Error Change
vs Temperature
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Zero Error Change
vs Clock Frequency
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Zero Error Change
vs Supply Voltage
DS011354-62
DS011354-63
DS011354-64
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