August 4, 2008
ADC124S021
4 Channel, 50 ksps to 200 ksps, 12-Bit A/D Converter
ADC124S021 4 Channel, 50 ksps to 200 ksps, 12-Bit A/D Converter
General Description
The ADC124S021 is a low-power, four-channel CMOS 12-bit
analog-to-digital converter with a high-speed serial interface.
Unlike the conventional practice of specifying performance at
a single sample rate only, the ADC124S021 is fully specified
over a sample rate range of 50 ksps to 200 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be
configured to accept up to four input signals at inputs IN1
through IN4.
The output serial data is straight binary, and is compatible with
several standards, such as SPI™, QSPI™, MICROWIRE,
and many common DSP serial interfaces.
The ADC124S021 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 2.2 mW and 7.9 mW, respectively.
The power-down feature reduces the power consumption to
just 0.14 µW using a +3V supply, or 0.32 µW using a +5V
supply.
The ADC124S021 is packaged in a 10-lead MSOP package.
Operation over the industrial temperature range of −40°C to
+85°C is guaranteed.
Features
Specified over a range of sample rates.
■
Four input channels
■
Variable power management
■
Single power supply with 2.7V - 5.25V range
■
Key Specifications
DNL +0.4 / −0.2 LSB (typ)
■
INL ± 0.35 LSB (typ)
■
SNR 72.0 dB (typ)
■
Power Consumption
■
3V Supply 2.2 mW (typ)
—
■
5V Supply 7.9 mW (typ)
—
Applications
Portable Systems
■
Remote Data Acquisition
■
Instrumentation and Control Systems
■
Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution Specified for Sample Rate Range of:
50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps
12-bit ADC124S021 ADC124S051 ADC124S101
10-bit ADC104S021 ADC104S051 ADC104S101
8-bit ADC084S021 ADC084S051 ADC084S101
Connection Diagram
20124305
TRI-STATE® is a trademark of National Semiconductor Corporation
QSPI™ and SPI™ are trademarks of Motorola, Inc.
© 2008 National Semiconductor Corporation 201243 www.national.com
Ordering Information
Order Code Temperature Range Description Top Mark
ADC124S021
ADC124S021CIMM −40°C to +85°C 10-Lead MSOP Package X21C
ADC124S021CIMMX −40°C to +85°C 10-Lead MSOP Package, Tape & Reel X21C
ADC124S021EVAL Evaluation Board
Block Diagram
20124307
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Description
ANALOG I/O
4-7
DIGITAL I/O
10 SCLK Digital clock input. This clock directly controls the conversion and readout processes.
9 DOUT
8 DIN
1 CS
POWER SUPPLY
2
3 GND The ground return for the supply and signals.
IN1 to IN4 Analog inputs. These signals can range from 0V to VA.
Digital data output. The output samples are clocked out of this pin on falling edges of the
SCLK pin.
Digital data input. The ADC124S021's Control Register is loaded through this pin on rising
edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions
continue as long as CS is held low.
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
V
A
bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within
1 cm of the power pin.
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ADC124S021
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage V
A
Voltage on Any Pin to GND −0.3V to VA +0.3V
−0.3V to 6.5V
Operating Ratings (Notes 1, 2)
Operating Temperature Range
VA Supply Voltage
Digital Input Pins Voltage Range
Clock Frequency 0.8 MHz to 3.2 MHz
Analog Input Voltage
−40°C ≤ TA ≤ +85°C
+2.7V to +5.25V
−0.3V to V
0V to V
Input Current at Any Pin (Note 3) ±10 mA
Package Input Current(Note 3) ±20 mA
Power Consumption at TA = 25°C
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
See (Note 4)
2500V
250V
Junction Temperature +150°C
Package Thermal Resistance
Package
10-lead MSOP 190°C / W
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile specifications.
Refer to www.national.com/packaging. (Note 6)
θ
JA
Storage Temperature −65°C to +150°C
ADC124S021 Converter Electrical Characteristics (Note 9)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, f
CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = T
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
INL Integral Non-Linearity
DNL Differential Non-Linearity
V
OFF
Offset Error +0.37 ±1.3 LSB (max)
OEM Channel to Channel Offset Error Match ±0.1 ±1.0 LSB (max)
FSE Full-Scale Error ±0.52 ±1.5 LSB (max)
FSEM
Channel to Channel Full-Scale Error
Match
±0.1 ±1.0 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-Noise Plus Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR Spurious-Free Dynamic Range
ENOB Effective Number of Bits
Channel-to-Channel Crosstalk
Intermodulation Distortion, Second
IMD
Order Terms
Intermodulation Distortion, Third Order
Terms
FPBW -3 dB Full Power Bandwidth
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
VA = +5.25V
fIN = 39.9 kHz
VA = +5.25V
fa = 40.161 kHz, fb = 41.015 kHz
VA = +5.25V
fa = 40.161 kHz, fb = 41.015 kHz
VA = +5V
VA = +3V
= 0.8 MHz to 3.2 MHz, f
SCLK
MIN
to T
: all other limits TA = 25°C.
MAX
= 50 ksps to 200 ksps,
SAMPLE
Limits
(Note 7)
Units
+0.35 +0.8 LSB (max)
−0.35 −1.1 LSB (min)
+0.4 +1.1 LSB (max)
−0.2 −0.8 LSB (min)
72 69.2 dB (min)
72 70.6 dB (min)
−84 −75 dB (max)
86 76 dB (min)
11.7 11.2 Bits (min)
−86 dB
−87 dB
−88 dB
11 MHz
8 MHz
A
A
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Symbol Parameter Conditions Typical
Limits
(Note 7)
ANALOG INPUT CHARACTERISTICS
V
IN
ADC124S021
I
DCL
C
INA
Input Range
DC Leakage Current ±0.02 ±1 µA (max)
Input Capacitance
Track Mode 33 pF
Hold Mode 3 pF
0 to V
A
DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IN
C
IND
Input High Voltage
Input Low Voltage 0.8 V (max)
Input Current
Digital Input Capacitance 2 4 pF (max)
VA = +5.25V
VA = +3.6V
VIN = 0V or V
A
2.4 V (min)
2.1 V (min)
±0.02 ±10 µA (max)
DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZH
C
OH
OL
OUT
= 200 µA VA − 0.03
Output High Voltage
Output Low Voltage
, I
TRI-STATE® Leakage Current ±0.01 ±1 µA (max)
OZL
SOURCE
I
= 1 mA VA − 0.1
SOURCE
I
= 200 µA
SINK
I
= 1 mA
SINK
0.02 0.4 V (max)
0.1 V
TRI-STATE® Output Capacitance 2 4 pF (max)
VA − 0.5
V
V (min)
I
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
V
A
I
A
P
D
Supply Voltage
VA = +5.25V
f
Supply Current, Normal Mode
(Operational, CS low)
= 200 ksps, fIN = 39.9 kHz
SAMPLE
VA = +3.6V,
f
= 200 ksps, fIN = 39.9 kHz
SAMPLE
0.62 1.0 mA (max)
VA = +5.25V
f
= 0 ksps
Supply Current, Shutdown (CS high)
Power Consumption, Normal Mode
(Operational, CS low)
Power Consumption, Shutdown (CS
high)
SAMPLE
VA = +3.6V,
f
= 0 ksps
SAMPLE
VA = +5.25V
VA = +3.6V,
VA = +5.25V
VA = +3.6V,
0.32 µW
0.14 µW
1.5 2.1 mA (max)
60 nA
38 nA
7.9 11.0 mW (max)
2.2 3.6 mW (max)
2.7 V (min)
5.25 V (max)
AC ELECTRICAL CHARACTERISTICS
f
SCLK
f
S
t
CONV
Maximum Clock Frequency (Note 8)
Sample Rate (Note 8)
Conversion Time 13 SCLK cycles
DC SCLK Duty Cycle
t
ACQ
Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles
f
SCLK
= 3.2 MHz
50
0.8 MHz (min)
3.2 MHz (max)
50 ksps (min)
200 ksps (max)
30 % (min)
70 % (max)
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
Units
V
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ADC124S021 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, f
CL = 35 pF, Boldface limits apply for TA = T
MIN
to T
: all other limits TA = 25°C.
MAX
Symbol Parameter Conditions Typical
t
t
Setup Time SCLK High to CS Falling Edge (Note 10)
CSU
t
Hold time SCLK Low to CS Falling Edge (Note 10)
CLH
t
Delay from CS Until DOUT active
EN
Data Access Time after SCLK Falling Edge
ACC
t
Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)
SU
t
Data Valid SCLK Hold Time +3 10 ns (min)
H
t
SCLK High Pulse Width
CH
t
SCLK Low Pulse Width
CL
Output Falling
t
CS Rising Edge to DOUT High-Impedance
DIS
Output Rising
= 0.8 MHz to 3.2 MHz, f
SCLK
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
SAMPLE
−3.5
−0.5
+4.5
+1.5
+4
+2
+14.5
+13
0.5 x t
0.5 x t
1.8
1.3
1.0
1.0
SCLK
SCLK
= 50 ksps to 200 ksps,
Limits
(Note 7)
Units
10 ns (min)
10 ns (min)
30 ns (max)
30 ns (max)
0.3 x t
0.3 x t
SCLK
SCLK
ns (min)
ns (min)
20 ns (max)
ADC124S021
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Clock may be either high or low when CS
is asserted as long as setup and hold times t
CSU
and t
are strictly observed.
CLH
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Timing Diagrams
ADC124S021
ADC124S021 Operational Timing Diagram
Timing Test Circuit
20124308
20124351
ADC124S021 Serial Timing Diagram
SCLK and CS Timing Parameters
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20124306
20124350
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