MXIC MX23L4100PC-10, MX23L4100MC-12, MX23L4100MC-10, MX23L4100PC-15, MX23L4100PC-12 Datasheet
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MX23L4100
4M-BIT MASK ROM (8/16 BIT OUTPUT)
FEATURES
• Bit organization
- 512K x 8 (byte mode)
- 256K x 16 (word mode)
• Fast access time
- Random access: 100ns
• Current
- Operating: 30mA
- Standby: 20uA
• Supply voltage
- 3.3V±10%
• Package
- 40 pin SOP (500 mil)
- 40 pin PDIP (600 mil)
PIN CONFIGURATION
40 SOP
A17
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
CE
11
VSS
12
OE
13
D0
14
D8
15
D1
16
D9
17
D2
18
D10
19
D3
20
D11
A8
40
A9
39
A10
38
A11
37
A12
36
A13
35
A14
34
A15
33
A16
32
BYTE
31
VSS
30
D15/A-1
29
D7
28
MX23L4100
D14
27
D6
26
D13
25
D5
24
D12
23
D4
22
VCC
21
ORDER INFORMATION
Part No. Access Time Pac ka ge
MX23L4100MC-10 100ns 40 pin SOP
MX23L4100MC-12 120ns 40 pin SOP
MX23L4100MC-15 150ns 40 pin SOP
MX23L4100PC-10 100ns 40 pin PDIP
MX23L4100PC-12 120ns 40 pin PDIP
MX23L4100PC-15 150ns 40 pin PDIP
PIN DESCRIPTION
Symbol Pin Function
A0~A17 Address Inputs
D0~D14 Data Outputs
CE Chip Enable Input
OE Output Enab le Input
Byte Word/ Byte Mode Selection
VCC Pow er Supply Pin
VSS Ground Pin
NC No Connection
MODE SELECTION
40 PDIP
A17
CE
VSS
OE
D10
D11
A8
1
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
A0
9
10
11
12
D0
13
D8
14
D1
15
D9
16
D2
17
18
D3
19
20
40
A9
39
A10
38
A11
37
A12
36
A13
35
A14
34
A15
33
A16
32
BYTE
31
VSS
30
D15/A-1
29
MX23L4100
D7
28
D14
27
D6
26
D13
25
D5
24
D12
23
D4
22
VCC
21
CE OE ByteD15/A-1 D0~D7 D8~D15 Mode Power
H X X X High Z High Z - Stand-by
L H X X High Z High Z - Active
L L H Output D0~D7 D8~D15 Word Active
L L L Input D0~D7 High Z Byte Active
P/N:PM0344 REV. 1.4, JUL. 16, 2001
1
BLOCK DIAGRAM
MX23L4100
A0/(A-1)
A17
CE
BYTE
OE
Address
Buffer
Memory
Array
Sense
Amplifier
Word/
Byte
Output
Buffer
D15/(D7)
ABSOLUTE MAXIMUM RATINGS
Item Symbol Ratings
V oltage on any Pin Relativ e to VSS VIN -0.8V to VCC+2.0V (Note)
Ambient Operating Temperature T opr 0°C to 70°C
Storage T emperature Tstg -65°C to 125°C
Note: Minimum DC v oltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -0.8V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During v oltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
D0
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item Symbol MIN. MAX. Conditions
Output High Voltage VOH 2.4V - IOH = -0.4mA
Output Low Voltage V OL - 0.4V IOL = 1.6mA
Input High Voltage VIH 2.2V VCC+0.3V
Input Low Voltage VIL -0.3V 0.8V
Input Leakage Current ILI - 5uA 0V, VCC
Output Leakage Current ILO - 5uA 0V, VCC
Operating Current (CE toggle) ICC1 - 30mA tRC=100ns, all output open
Standby Current (TTL) ISTB1 - 1mA CE = VIH
Standby Current (CMOS) ISTB2 - 20uA CE > VCC - 0.2V
Input Capacitance CIN - 10pF Ta = 25°C, f = 1MHZ
Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ
P/N:PM0344
2
REV. 1.4, JUL. 16, 2001
MX23L4100
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item Symbol 23L4100-10 23L4100-12 23L4100-15
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 100ns - 120ns - 150ns Address Access Time tAA - 100ns - 120ns - 150ns
Chip Enable Access Time tACE - 100ns - 120ns - 150ns
Output Enable Time tOE - 50ns - 60ns - 70ns
Output Hold After Address tOH - 0ns - 0ns - 0ns
Output High Z Delay tHZ - 20ns - 20ns - 20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaranteed by design over the full v oltage and temperature operating range - not tested.
AC T est Conditions
Input Pulse Levels 0.4V~2.4V
Input Rise and Fall Times 10ns
Input Timing Level 1.4V
Output Timing Level 1.4V
Output Load See Figure
TIMING DIAGRAM
ACCESS TIMING
ADD
CE
ADD ADD ADD
tACE
tOE
IOH (load)=-0.4mA
DOUT
IOL (load)=1.6mA
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
tRC
C<100pF
P/N:PM0344
OE
DATA
tAA
VALID VALID VALID
3
tOH
tHZ
REV. 1.4, JUL. 16, 2001
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