MXIC MX23L4100PC-10, MX23L4100MC-12, MX23L4100MC-10, MX23L4100PC-15, MX23L4100PC-12, MX23L4100MC-15 Datasheet

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MX23L4100

FEATURES

Bit organization

-512K x 8 (byte mode)

-256K x 16 (word mode)

Fast access time

-Random access: 100ns

Current

-Operating: 30mA

-Standby: 20uA

Supply voltage

-3.3V±10%

Package

-40 pin SOP (500 mil)

-40 pin PDIP (600 mil)

PIN CONFIGURATION

40 SOP

 

 

 

 

 

 

 

 

 

 

 

A8

A17

 

 

 

 

40

 

 

 

 

 

 

 

 

 

A7

 

 

2

 

39

 

 

 

A9

 

 

 

 

 

A6

 

 

3

 

38

 

 

 

A10

 

 

 

 

 

A5

 

 

4

 

37

 

 

 

A11

 

 

 

 

 

A4

 

 

5

 

36

 

 

 

A12

 

 

 

 

 

A3

 

 

6

 

35

 

 

 

A13

 

 

 

 

 

A2

 

 

7

 

34

 

 

 

A14

 

 

 

 

 

A1

 

 

8

MX23L4100

33

 

 

 

A15

 

 

 

 

A0

 

 

9

32

 

 

 

A16

 

 

 

 

 

 

 

 

 

10

31

 

 

 

BYTE

CE

 

 

 

 

 

 

 

VSS

 

 

11

30

 

 

 

VSS

 

 

 

 

 

 

 

 

12

29

 

 

 

D15/A-1

OE

 

 

 

 

 

 

 

 

D0

 

 

13

28

 

 

 

D7

 

 

 

 

D8

 

 

14

27

 

 

 

D14

 

 

 

 

 

 

 

 

D1

 

 

15

 

26

 

 

 

D6

 

 

 

 

 

D9

 

 

16

 

25

 

 

 

D13

 

 

 

 

 

D2

 

 

17

 

24

 

 

 

D5

 

 

 

 

 

 

 

 

 

18

 

23

 

 

 

D12

D10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

22

 

 

 

D4

 

D3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

21

 

 

 

VCC

D11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40 PDIP

A17

1

 

40

A8

 

A7

2

 

39

A9

 

A6

3

 

38

A10

 

A5

4

 

37

A11

 

A4

5

 

36

A12

 

A3

6

 

35

A13

 

A2

7

 

34

A14

 

A1

8

MX23L4100

33

A15

 

A0

9

32

A16

 

 

 

 

 

 

BYTE

CE

10

31

VSS

11

30

VSS

 

 

 

29

D15/A-1

 

 

OE

12

D0

13

28

D7

D8

14

 

27

D14

D1

15

 

26

D6

D9

16

 

25

D13

D2

17

 

24

D5

D10

18

 

23

D12

D3

19

 

22

D4

D11

20

 

21

VCC

4M-BIT MASK ROM (8/16 BIT OUTPUT)

ORDER INFORMATION

Part No.

Access Time

Package

MX23L4100MC-10

100ns

40 pin SOP

 

 

 

MX23L4100MC-12

120ns

40 pin SOP

 

 

 

MX23L4100MC-15

150ns

40 pin SOP

 

 

 

MX23L4100PC-10

100ns

40 pin PDIP

 

 

 

MX23L4100PC-12

120ns

40 pin PDIP

 

 

 

MX23L4100PC-15

150ns

40 pin PDIP

 

 

 

PIN DESCRIPTION

 

Symbol

Pin Function

 

A0~A17

Address Inputs

 

 

 

 

 

 

 

 

D0~D14

Data Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable Input

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable Input

 

OE

 

 

 

 

 

 

 

 

 

 

Word/ Byte Mode Selection

 

Byte

 

 

 

 

 

 

 

 

VCC

Power Supply Pin

 

 

 

 

 

 

 

 

VSS

Ground Pin

 

 

 

 

 

 

 

 

NC

No Connection

 

 

 

 

 

 

 

MODE SELECTION

CE

OE

Byte D15/A-1 D0~D7

D8~D15

Mode

Power

H

X

X

X

High Z

High Z

-

Stand-by

 

 

 

 

 

 

 

 

L

H

X

X

High Z

High Z

-

Active

 

 

 

 

 

 

 

 

L

L

H

Output

D0~D7

D8~D15

Word

Active

 

 

 

 

 

 

 

 

L

L

L

Input

D0~D7

High Z

Byte

Active

 

 

 

 

 

 

 

 

P/N:PM0344

REV. 1.4, JUL. 16, 2001

1

MX23L4100

BLOCK DIAGRAM

A0/(A-1)

 

 

Address

 

 

 

 

Memory

 

 

 

 

Sense

 

 

 

 

Word/

 

 

 

 

Output

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer

 

 

 

 

Array

 

 

 

 

Amplifier

 

 

 

 

Byte

 

 

 

 

Buffer

 

 

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D15/(D7)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

BYTE

OE

ABSOLUTE MAXIMUM RATINGS

Item

Symbol

Ratings

Voltage on any Pin Relative to VSS

VIN

-0.8V to VCC+2.0V (Note)

 

 

 

Ambient Operating Temperature

Topr

0°C to 70°C

 

 

 

Storage Temperature

Tstg

-65°C to 125°C

 

 

 

Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -0.8V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.

DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)

Item

Symbol

MIN.

MAX.

 

Conditions

Output High Voltage

VOH

2.4V

-

IOH = -0.4mA

 

 

 

 

 

 

 

 

Output Low Voltage

VOL

-

0.4V

 

IOL = 1.6mA

 

 

 

 

 

 

 

 

Input High Voltage

VIH

2.2V

VCC+0.3V

 

 

 

 

 

 

 

 

 

 

 

 

Input Low Voltage

VIL

-0.3V

0.8V

 

 

 

 

 

 

 

 

 

 

 

 

Input Leakage Current

ILI

-

5uA

0V, VCC

 

 

 

 

 

 

 

 

Output Leakage Current

ILO

-

5uA

0V, VCC

 

 

 

 

 

 

 

 

Operating Current (CE toggle)

ICC1

-

30mA

 

tRC=100ns, all output open

 

 

 

 

 

 

 

 

Standby Current (TTL)

ISTB1

-

1mA

 

 

= VIH

CE

 

 

 

 

 

 

 

 

Standby Current (CMOS)

ISTB2

-

20uA

 

 

 

> VCC - 0.2V

 

CE

 

 

 

 

 

 

 

 

Input Capacitance

CIN

-

10pF

Ta = 25°C, f = 1MHZ

 

 

 

 

 

 

 

 

Output Capacitance

COUT

-

10pF

 

Ta = 25°C, f = 1MHZ

 

 

 

 

 

 

 

 

P/N:PM0344

REV. 1.4, JUL. 16, 2001

2

MXIC MX23L4100PC-10, MX23L4100MC-12, MX23L4100MC-10, MX23L4100PC-15, MX23L4100PC-12, MX23L4100MC-15 Datasheet

MX23L4100

AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)

Item

Symbol

23L4100-10

 

23L4100-12

 

23L4100-15

 

 

 

MIN.

MAX.

 

MIN.

MAX.

MIN.

MAX.

 

 

 

 

 

 

 

 

 

 

 

Read Cycle Time

tRC

100ns

-

 

120ns

-

 

150ns

-

 

 

 

 

 

 

 

 

 

 

 

 

Address Access Time

tAA

-

100ns

-

120ns

-

150ns

 

 

 

 

 

 

 

 

 

 

 

Chip Enable Access Time

tACE

-

100ns

-

120ns

-

150ns

 

 

 

 

 

 

 

 

 

 

 

Output Enable Time

tOE

-

50ns

-

60ns

-

70ns

 

 

 

 

 

 

 

 

 

 

 

Output Hold After Address

tOH

-

0ns

-

0ns

-

0ns

 

 

 

 

 

 

 

 

 

 

 

Output High Z Delay

tHZ

-

20ns

-

20ns

-

20ns

 

 

 

 

 

 

 

 

 

 

 

Note:Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.

AC Test Conditions

Input Pulse Levels

0.4V~2.4V

Input Rise and Fall Times

10ns

 

 

Input Timing Level

1.4V

 

 

Output Timing Level

1.4V

 

 

Output Load

See Figure

 

 

IOH (load)=-0.4mA

DOUT

IOL (load)=1.6mA

C<100pF

TIMING DIAGRAM

Note:No output loading is present in tester load board.

Active loading is used and under software programming control.

Output loading capacitance includes load board's and all stray capacitance.

ACCESS TIMING

ADD

ADD

ADD

 

ADD

 

 

 

tACE

tRC

 

 

CE

 

 

 

 

 

tOE

 

 

 

OE

 

 

 

 

 

 

tAA

tOH

tHZ

DATA

 

VALID

VALID

VALID

P/N:PM0344

 

 

 

REV. 1.4, JUL. 16, 2001

 

 

3

 

 

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