MXIC MX23C3211RC-12, MX23C3211RC-10, MX23C3211MC-10, MX23C3211TC-12, MX23C3211TC-10 Datasheet

MX23C3211

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

NC A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

CE

VSS

OE

D0 D8 D1 D9 D2

D10

D3

D11

A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC

MX23C3211

5 Volt 32-Mbit (4M x 8 / 2M x 16) Mask ROM with Page Mode

FEATURES

• Bit organization

- 4M x 8 (byte mode)

- 2M x 16 (word mode)

• Fast access time

- Random access: 100ns (max.)

- Page access: 30ns (max.)

• Page Size

- 8 words per page

• Current

- Operating:60mA

- Standby:50uA

• Supply voltage

- 5V±10%

• Package

- 44 pin SOP (500mil)

- 48 pin TSOP (12mm x 20mm)

PIN CONFIGURATION

48 TSOP (Normal Type)

1

BYTE

2

A16

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

VSS

A20 A18 A17

A7 A6 A5 A4 A3 A2 A1 A0 CE

13 14 15 16 17 18 19 20 21 22 23 24

MX23C3211

(Normal T ype)

ORDER INFORMATION

Part No. Access Page Access Package

Time Time

MX23C3211MC-10 100ns 30ns 44 pin SOP MX23C3211MC-12 120ns 50ns 44 pin SOP MX23C3211TC-10 100ns 30ns 48 pin TSOP MX23C3211TC-12 120ns 50ns 48 pin TSOP MX23C3211RC-10 100ns 30ns 48 pin TSOP

(Reverse type)

MX23C3211RC-12 120ns 50ns 48 pin TSOP

(Reverse type)

PIN DESCRIPTION

Symbol Pin Function

A0~A20 Address Inputs D0~D14 Data Outputs

48

VSS

47

VSS

46

D15/A-1

45

D7

44

D14

43

D6

42

D13

41

D5

40

D12

39

D4

38

VCC

37

VCC

36

NC

35

D11

34

D3

33

D10

32

D2

31

D9

30

D1

29

D8

28

D0

27

OE

26

VSS

25

VSS

D15/A-1 D15 (Word Mode)/ LSB Address

(Byte Mode) CE Chip Enable Input OE Output Enable Input Byte Word/ Byte Mode Selection VCC Po wer Supply Pin VSS Ground Pin NC No Connection

44 SOP

48 TSOP (Reverse T ype)

48

VSS

47

VSS

46

D15/A-1

45

D7

44

D14

43

D6

42

D13

41

D5

40

D12

39

D4

38

VCC

37

VCC

36

NC

35

D11

34

D3

33

D10

32

D2

31

D9

30

D1

29

D8

28

D0

27

OE

26

VSS

25

VSS

P/N:PM0258

MX23C3211

(Reverse Tp ye)

1

BYTE

2

A16

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

VSS

13

A20

14

A18

15

A17

16

A7

17

A6

18

A5

19

A4

20

A3

21

A2

22

A1

23

A0

24

CE

REV. 3.0,JUL. 17, 2001

1

MX23C3211

MODE SELECTION

CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Po wer

H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H Output D0~D7 D8~D15 Word Active L L L Input D0~D7 High Z Byte Active

BLOCK DIAGRAM

A0/(A-1)

A2

A3

A20

Address

Buffer

Memory

Array

Page

Buffer

Page

Decoder

Word/

Byte

Output

Buffer

D0

D15/(D7)

CE

BYTE

OE

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings

V oltage on any Pin Relativ e to VSS VIN -1.3V to VCC+2.0V (Note) Ambient Operating Temperature T opr 0°C to 70°C Storage T emperature Tstg -65°C to 125°C

Note: Minimum DC v oltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During v oltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.

P/N:PM0258

REV. 3.0, JUL. 17, 2001

2

MX23C3211

DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5V±10%)

Item Symbol MIN. MAX. Conditions

Output High Voltage VOH 2.4V - IOH = -1.0mA Output Low Voltage VOL - 0.4V IOL = 2.1mA Input High Voltage VIH 2.2V VCC+0.3V Input Low Voltage VIL -0.3V 0.8V Input Leakage Current ILI - 5uA 0V , VCC Output Leakage Current ILO - 5uA 0V, VCC Operating Current ICC1 - 60mA tRC = 100ns, all output open Standby Current (TTL) ISTB1 - 1mA CE = VIH Standby Current (CMOS) ISTB2 - 50uA CE>VCC-0.2V Input Capacitance CIN - 10pF Ta = 25°C, f = 1MHZ Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ

AC CHARACTERISTICS (Ta = 0 °C ~ 70°C, VCC = 5V±10%)

Item Symbol 23C3211-10 23C3211-12

MIN. MAX. MIN. MAX.

Read Cycle Time tRC 100ns - 120ns Address Access Time tAA - 100ns - 120ns Chip Enable Access Time tACE - 100ns - 120ns Page Mode Access Time tPA - 30ns - 50ns Output Enable Time tOE - 30ns - 50ns Output Hold After Address tOH 0ns - 0ns Output High Z Delay tHZ - 20ns - 20ns

Note:Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.

AC T est Conditions

Input Pulse Levels 0.4V~ 3.3V Input Rise and Fall Times 10ns Input Timing Level 1.5V Output Timing Le v el 0.8V and 2.0V Output Load See Figure

IOH (load)=-1mA

DOUT

IOL (load)=2.1mA

C<100pF

P/N:PM0258

Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance.

REV. 3.0, JUL. 17, 2001

3