MX10E80501
PRELIMINARY
MX10E8050I /
MX10E8050IA
Major Difference
Feature
Product |
Default |
ISP |
IAP |
Package |
|
Clock mode |
|
|
|
|
|
|
|
|
MX10E8050IPC |
|
|
|
44 Pin PDIP |
MX10E8050IQC |
6 |
UART |
YES |
44 Pin PLCC |
MX10E8050IUC |
|
|
|
44 Pin LQFP |
|
|
|
|
|
MX10E8050IAQC |
6 |
I2C |
YES |
44 Pin PLCC |
|
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
1
PRELIMINARY
MX10E8050I /
MX10E8050IA
FEATURES
-80C51 CPU core
-3.0 ~ 3.6V voltage range
-On-chip Flash program memory with in-system programming ( ISP )
-Operating frequency up to 40MHz (12x), 20MHz(6x)
-64K bytes Flash memory for code memory
-1280 bytes internal data RAM
-Low power consumption
-Code and data memory expandable to 64K Bytes
-Four 8 bit and one 4 bit general purpose I/O ports
-Three standard 16-bit Timers
-In - Application Programming( IAP ) capability
-On-chip Watch Dog Timer
-Four channel PWM outputs/4bit general purpose I/O ports ( PLCC & LQFP only )
-UART
-7 interrupt sources with four priority level
-5 volt tolerant input
-400kb/s I2C
-6x / 12x clock mode
PIN Configurations
|
|
6 |
1 |
40 |
|
|
|
7 |
|
39 |
|
|
|
|
PLCC44 |
|
|
|
|
17 |
|
29 |
|
|
|
18 |
|
28 |
|
Pin |
Function |
Pin |
Function |
Pin |
Function |
1 |
P4.2/PWM2 |
16 |
P3.4/T0 |
31 |
P2.7/A15 |
2 |
P1.0/T2 |
17 |
P3.5/T1 |
32 |
PSEN |
3 |
P1.1/T2EX |
18 |
P3.6/WR |
33 |
ALE |
4 |
P1.2 |
19 |
P3.7/RD |
34 |
P4.1/PWM1 |
5 |
P1.3 |
20 |
XTAL2 |
35 |
EA |
6 |
P1.4 |
21 |
XTAL1 |
36 |
P0.7/AD7 |
7 |
P1.5 |
22 |
VSS |
37 |
P0.6/AD6 |
8 |
P1.6/SCL |
23 |
P4.0/PWM0 |
38 |
P0.5/AD5 |
9 |
P1.7/SDA |
24 |
P2.0/A8 |
39 |
P0.4/AD4 |
10 |
RST |
25 |
P2.1/A9 |
40 |
P0.3/AD3 |
11 |
P3.0/RxD |
26 |
P2.2/A10 |
41 |
P0.2/AD2 |
12 |
P4.3/PWM3 |
27 |
P2.3/A11 |
42 |
P0.1/AD1 |
13 |
P3.1/TxD |
28 |
P2.4/A12 |
43 |
P0.0/AD0 |
14 |
P3.2/INT0 |
29 |
P2.5/A13 |
44 |
VCC |
15 |
P3.3/INT1 |
30 |
P2.6/A14 |
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
2
PRELIMINARY MX10E8050I / MX10E8050IA
44 34
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
33 |
|
|
|
|
(T2) |
P1.0 |
1 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(T2EX) P1.1 |
2 |
|||||
|
|
|
|
|
|
|
|
|
|
|
LQFP44 |
|
|
|
|
|
|
|
|
|
|
|
P1.2 |
3 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P1.3 |
4 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P1.4 |
5 |
|
11 |
|
|
|
|
|
|
|
|
|
|
|
|
23 |
|
|
|
|
|
|
P1.5 |
6 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(SCL)P1.6 |
7 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(SDA)P1.7 |
8 |
||||
|
|
|
|
|
|
12 |
|
|
|
|
22 |
|
|
|
|
|
|
|
|
RESET |
9 |
|||||
Pin |
Function |
|
|
|
Pin |
|
Function |
|
|
Pin |
Function |
(RXD) P3.0 |
10 |
|||||||||||||
1 |
P1.5 |
16 |
|
VSS |
31 |
P0.6/AD6 |
|
(TXD)P3.1 |
11 |
|||||||||||||||||
2 |
P1.6/SCL |
17 |
|
P4.0/PWM0 |
32 |
P0.5/AD5 |
|
|
|
|
|
|
|
|||||||||||||
|
(INT0) P3.2 |
12 |
||||||||||||||||||||||||
3 |
P1.7/SDA |
18 |
|
P2.0/A8 |
33 |
P0.4/AD4 |
||||||||||||||||||||
|
|
|
|
|
|
|
|
|||||||||||||||||||
|
(INT1) P3.3 |
13 |
||||||||||||||||||||||||
4 |
RST |
19 |
|
P2.1/A9 |
34 |
P0.3/AD3 |
||||||||||||||||||||
|
|
|
|
(T0) P3.4 |
14 |
|||||||||||||||||||||
5 |
P3.0/RxD |
20 |
|
P2.2/A10 |
35 |
P0.2/AD2 |
|
|
|
|||||||||||||||||
6 |
P4.3/PWM3 |
21 |
|
P2.3/A11 |
36 |
P0.1/AD1 |
|
|
|
(T1) P3.5 |
15 |
|||||||||||||||
7 |
P3.1/TxD |
22 |
|
P2.4/A12 |
37 |
P0.0/AD0 |
|
|
|
|
|
|
|
|||||||||||||
|
|
(WR) P3.6 |
16 |
|||||||||||||||||||||||
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
38 |
VCC |
|
||||||||||
P3.2/INT0 |
|
23 |
|
P2.5/A13 |
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
(RD) P3.7 |
17 |
||||||||||||||||||||||
|
|
|
|
|
|
24 |
|
P2.6/A14 |
39 |
P4.2/PWM2 |
|
|||||||||||||||
9 |
P3.3/INT1 |
|
||||||||||||||||||||||||
|
|
|
|
XTAL2 |
18 |
|||||||||||||||||||||
10 |
P3.4/T0 |
25 |
|
P2.7/A15 |
40 |
P1.0/T2 |
|
|
|
|||||||||||||||||
11 |
P3.5/T1 |
26 |
|
|
|
|
41 |
P1.1/T2EX |
|
|
|
XTAL1 |
19 |
|||||||||||||
|
PSEN |
|||||||||||||||||||||||||
|
|
|
|
|
|
27 |
|
ALE |
42 |
P1.2 |
|
|
|
|
|
|
|
|||||||||
12 |
P3.6/WR |
|
|
|
|
|
|
VSS |
20 |
|||||||||||||||||
|
43 |
P1.3 |
|
|
|
|
|
|||||||||||||||||||
13 |
|
|
|
28 |
P4.1/PWM1 |
|
|
|
|
|
|
|
||||||||||||||
P3.7/RD |
|
|
|
|
|
|
|
|
||||||||||||||||||
14 |
XTAL2 |
29 |
|
|
|
44 |
P1.4 |
|
|
|
|
|
|
|
||||||||||||
|
EA |
|
|
|
|
|
|
|
||||||||||||||||||
15 |
XTAL1 |
30 |
|
P0.7/AD7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PDIP 40
40 |
VCC |
|
|
|
39 |
P0.0 |
(AD0) |
||
38 |
P0.1 |
(AD1) |
||
37 |
P0.2 |
(AD2) |
||
36 |
P0.3 |
(AD3) |
||
35 |
P0.4 |
(AD4) |
||
34 |
P0.5 |
(AD5) |
||
33 |
P0.6 |
(AD6) |
||
32 |
P0.7 |
(AD7) |
||
31 |
EA |
|
|
|
30 |
ALE |
|
|
|
29 |
PSEN |
|||
28 |
P2.7 |
(A15) |
||
27 |
P2.6 |
(A14) |
||
26 |
P2.5 |
(A13) |
||
25 |
P2.4 |
(A12) |
||
24 |
P2.3 |
(A11) |
||
23 |
P2.2 |
(A10) |
||
22 |
P2.1 |
(A9) |
||
21 |
P2.0 |
(A8) |
Table. 1 Pin Description
|
Package Type |
PDIP |
PLCC |
LQFP |
|
||||
I/O |
SYMBOL |
PIN |
PIN |
PIN |
DESCRIPTION |
||||
|
|
|
|
|
|
|
|
|
|
I/O |
P0.0-P0.7 |
39-32 |
43-36 |
37-30 |
Port:8-bit open drain bidirectional I/O Port |
||||
|
|
|
|
|
|
|
|
|
|
I/O |
P2.0-P2.7 |
21-28 |
24-31 |
18-25 |
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up |
||||
|
|
|
|
|
|
|
|
|
|
I/O |
P1.0-P1.7 |
1-8 |
2-9 |
40-44,1-3 |
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up |
||||
|
|
|
|
|
|
|
|
|
, except P1.6 and P1.7 |
|
|
|
|
|
|
|
|
|
|
I/O |
P3.0-P3.7 |
10-17 |
11,13-19 |
5,7-13 |
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up |
||||
|
|
|
|
|
|
|
|
|
|
I/O |
P4.0~P4.3/ |
NA |
23,34,1,12 |
17,28,39,6 |
4bit Quasi-bidirectional I/O port or PWM PWM0~PWM3 |
||||
|
|
|
|
|
|
|
|
|
|
I |
RESET |
9 |
10 |
4 |
reset input |
||||
|
|
|
|
|
|
|
|
|
|
I |
VCC |
40 |
44 |
38 |
Positive power supply |
||||
|
|
|
|
|
|
|
|
|
|
I |
VSS |
20 |
22 |
16 |
Ground |
||||
|
|
|
|
|
|
|
|
|
|
I |
XTAL1 |
19 |
21 |
15 |
XTAL connection input |
||||
|
|
|
|
|
|
|
|
|
|
O |
|
|
|
|
|
18 |
20 |
14 |
XTAL connection output |
XTAL2 |
|||||||||
O |
|
|
|
29 |
32 |
26 |
Program store enable output |
||
PSEN |
|||||||||
|
|
|
|
|
|
|
|
|
|
O |
ALE |
30 |
33 |
27 |
Address latch enable output |
||||
|
|
|
|
|
|
|
|
|
|
I |
|
|
|
31 |
35 |
29 |
External access input |
||
EA |
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
3
|
|
|
|
|
|
|
|
PRELIMINARY |
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
MX10E8050I / |
|
|
|
|
|
|
|
|
|
MX10E8050IA |
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|||||
Mnemonic |
Pin Number |
|
Type |
Name and Function |
|
||||
|
|
|
|
|
|
|
|
||
|
|
PDIP |
PLCC |
LQFP |
|
|
|
||
|
|
|
|
|
|
|
|
||
Vss |
20 |
22 |
|
16 |
I |
Ground: 0 volt reference |
|
||
Vcc |
40 |
44 |
|
38 |
I |
Power Supply: This is the power supply voltage for normal, |
|||
|
|
|
|
|
|
|
|
idle and power-down operation |
|
|
|
|
|
|
|
||||
P0.0 ~ 0.7 |
39-32 |
43-36 |
37-30 |
I/O |
Port 0: Port 0 is an open drain, bi-directional I/O port. Port 0 |
|
|||
|
|
|
|
|
|
|
|
pins have 1s written to them float and can be used as high |
|
|
|
|
|
|
|
|
|
impedance inputs. Port 0 is also the multiplexed low-order |
|
|
|
|
|
|
|
|
|
address and data bus during accessed to external program |
|
|
|
|
|
|
|
|
|
and data memory. In this application, it uses strong internal |
|
|
|
|
|
|
|
|
|
pull-ups when emitting 1s. |
|
|
|
|
|
|
|
||||
P1.0~1.7 |
1-8 |
2-9 |
40-44 |
I/O |
Port1: Port 1 is an 8-bit bi-directional I/O port with internal |
|
|||
|
|
|
|
|
|
1-3 |
|
pull-ups. Port 1 pins that have 1s written to them are pulled |
|
|
|
|
|
|
|
|
|
high by the internal pull-ups and can be used as inputs. As |
|
|
|
|
|
|
|
|
|
inputs, Port 1 pins that are externally pulled low will source |
|
|
|
|
|
|
|
|
|
current because of the internal pull-ups. Note that P1.6 and |
|
|
|
|
|
|
|
|
|
P1.7 are open drain pins for I2C function. |
|
|
|
|
|
|
|
|
|
Alternate functions for port 1 include: |
|
|
|
1 |
|
2 |
|
40 |
I/O |
T2(P1.0): Timer/Counter 2 external count input/clock out |
|
|
|
2 |
|
3 |
|
41 |
I |
T2EX(P1.1): Timer/Counter 2 Reload / Capture / Direction |
|
|
|
|
|
|
|
|
|
control |
|
|
|
3 |
|
4 |
|
42 |
I |
SDA (P1.7): Data line for I2C |
|
|
|
4 |
|
5 |
|
43 |
I/O |
SCL (P1.6): Clock line for I2C |
|
|
|
5 |
|
6 |
|
44 |
I/O |
|
|
|
|
6 |
|
7 |
|
1 |
I/O |
|
|
|
|
7 |
|
8 |
|
2 |
I/O |
|
|
|
|
8 |
|
9 |
|
3 |
I/O |
|
|
|
|
|
|
|
|
|
|||
P2.0~2.7 |
21-28 |
24-31 |
18-25 |
I/O |
Port 2 : Port 2 is an 8-bit bi-directional I/O port with internal |
||||
|
|
|
|
|
|
|
|
pull-ups. Port2 pins that have 1s written to them are pulled |
|
|
|
|
|
|
|
|
|
high by the internal pull-ups and can be used as inputs. As |
|
|
|
|
|
|
|
|
|
inputs, Port 2 pins that are externally pulled low will source |
|
|
|
|
|
|
|
|
|
current because of the internal pull-ups. Port 2 emits the high |
|
|
|
|
|
|
|
|
|
ordered address byte during fetches from external program |
|
|
|
|
|
|
|
|
|
memory and during accesses to external data memory that |
|
|
|
|
|
|
|
|
|
use 16-bit addresses (MOVX @DPTR). In this application, it |
|
|
|
|
|
|
|
|
|
uses strong internal pull-ups when emitting 1s. During |
|
|
|
|
|
|
|
|
|
accesses to external data memory using 8-bit addresses |
|
|
|
|
|
|
|
|
|
(MOVX@RI), port 2 emits the contents of P2 special |
|
|
|
|
|
|
|
|
|
`function register. |
|
|
|
|
|
|
|
|
|||
P3.0~3.7 |
10-17 |
11, |
5, |
I/O |
Port 3: Port 3 is an 8-bit bi-directional I/O port with internal |
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PRELIMINARY |
||||
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
MX10E8050I / |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
MX10E8050IA |
|
||||
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
13-19 |
7-13 |
|
pull-ups. Port 3 pins that have 1s written to them are pulled |
|||||||||
|
|
|
|
|
|
|
|
|
|
high with the internal pull-ups and can be used as inputs. As |
||||||||
|
|
|
|
|
|
|
|
|
|
inputs, Port 3 pins that are externally pulled low will source |
||||||||
|
|
|
|
|
|
|
|
|
|
current because of the internal pull-ups. Port 3 also serves |
||||||||
|
|
|
|
|
|
|
|
|
|
the special features of MX10E8050I family, as listed below: |
||||||||
|
|
|
|
10 |
11 |
|
5 |
I |
RxD (P3.0) : Serial input port |
|||||||||
|
|
|
|
11 |
13 |
|
7 |
O |
TxD (P3.1) : Serial output port |
|||||||||
|
|
|
|
12 |
14 |
|
8 |
I |
INT0 (P3.2) : External interrupt 0 |
|||||||||
|
|
|
|
13 |
15 |
|
9 |
I |
INT1 (P3.3) : External interrupt 1 |
|||||||||
|
|
|
|
14 |
16 |
|
10 |
I |
T0 (P3.4) : Timer 0 external input |
|||||||||
|
|
|
|
15 |
17 |
|
11 |
I |
T1 (P3.5) : Timer 1 external input |
|||||||||
|
|
|
|
16 |
18 |
|
12 |
O |
WR (P3.6) : External data memory write strobe |
|||||||||
|
|
|
|
17 |
19 |
|
14 |
O |
RD (P3.7) : External data memory read strobe |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
P4.0~P4.3 |
|
|
|
I/O |
Port 4: Port 4 is an 4-bit bi-directional I/O port with internal |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
pull-ups. Port 4 pins that have 1s written to them are pulled |
||||||||
|
|
|
|
|
|
|
|
|
|
high with the internal pull-ups and can be used as inputs. As |
||||||||
|
|
|
|
|
|
|
|
|
|
inputs, Port 4 pins that are externally pulled low will source |
||||||||
|
|
|
|
|
|
|
|
|
|
current because of the internal pull-ups. Port 4 also serves |
||||||||
|
|
|
|
|
|
|
|
|
|
the special features of MX10E8050I family, as listed below: |
||||||||
P4.0 |
|
|
23 |
|
17 |
I |
PWM0 (P4.0) : PWM module output 0 |
|||||||||||
P4.1 |
|
|
34 |
|
28 |
I |
PWM1 (P4.1) : PWM module output 1 |
|||||||||||
P4.2 |
|
|
1 |
|
39 |
I |
PWM2 (P4.2) : PWM module output 2 |
|||||||||||
P4.3 |
|
|
12 |
|
6 |
I |
PWM3 (P4.3) : PWM module output 3 |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RST |
9 |
|
10 |
|
4 |
I |
Reset : A high on this pin for eight machine cycles while the |
|||||||||||
|
|
|
|
|
|
|
|
|
|
oscillator is running, reset the devices. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
ALE |
30 |
33 |
|
27 |
O |
Address Latch Enable: Output pulse for latching the low byte |
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
of the address during an access to external memory. In |
||||||||
|
|
|
|
|
|
|
|
|
|
normal operation, ALE is emitted at constant rate of 1/6 the |
||||||||
|
|
|
|
|
|
|
|
|
|
oscillator frequency in 12x clock mode. 1/3 the oscillator |
||||||||
|
|
|
|
|
|
|
|
|
|
frequency in 6x clock mode, and can be used for external |
||||||||
|
|
|
|
|
|
|
|
|
|
timing or clocking. Note that one ALE pulse is skipped during |
||||||||
|
|
|
|
|
|
|
|
|
|
each access to external data memory. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
PSEN |
|
29 |
32 |
|
26 |
O |
Program Strobe Enable: The read strobe to external program |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
memory. When executing code from external program |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
memory, PSEN is activated twice each machine cycle., |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
except the two PSEN activation are skipped during each |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
access to external data memory. PSEN is not activated |
||||||||
|
|
|
|
|
|
|
|
|
|
during fetch from internal program memory. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
EA |
|
31 |
35 |
|
15 |
I |
External Access Enable/ Programming Supply Voltage: |
EA |
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
must be external held low to enable the device to fetch code |
||||||||
|
|
|
|
|
|
|
|
|
|
from external program memory locations 0000H and FFFFH |
||||||||
|
|
|
|
|
|
|
|
|
|
for 64 K devices. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
XTAL 1 |
19 |
21 |
|
15 |
I |
Crystal 1: Input to the inverting oscillator amplifier and input |
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
to the internal clock generator circuits. |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
XTAL 2 |
18 |
20 |
|
14 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
P/N:PM0887 |
Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005 |
5
PRELIMINARY
MX10E8050I /
MX10E8050IA
BLOCK DIAGRAM
|
|
|
P4.0-P4.3 |
|
P0.0-P0.7 |
P2.0-P2.7 |
|
||
Vcc |
|
|
|
|
|
|
|
|
|
Vss |
|
|
PORT 4 |
PORT 4 |
PORT 0 |
PORT 2 |
|
||
|
|
|
DRIVERS |
LATCH |
DRIVERS |
DRIVERS |
|
||
|
RAM ADDR. |
REGISTER |
RAM |
PWM |
PORT 0 |
PORT 2 |
|
ROM |
|
|
LATCH |
LATCH |
|
|
|||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
PROGRAM |
|
|
|
ACC |
|
|
STACK |
|
T3 |
ADDR. |
|
|
|
|
|
|
REGISTER |
|||
|
|
|
|
|
|
WATCHDOG |
|||
|
|
|
|
|
POINTER |
TIMER |
|
||
|
|
|
TMP2 |
|
TMP1 |
|
|
|
BUFFER |
|
|
|
B |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REGISTER |
|
|
|
|
|
|
||
|
|
|
|
ALU |
|
|
|
|
PC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INCREMENTER |
|
|
|
|
|
|
T0/T1/T2 |
|
|
|
|
|
|
|
|
|
SFRs |
|
|
|
|
|
|
|
PSW |
|
TIMERS |
|
|
PROGRAM |
|
|
|
|
|
|
|
|
|
COUNTER |
PSEN |
|
|
INSTRUCTION REGISTER |
|
|
|
|
|
|
ALE |
TIMING |
|
|
|
|
|
|
DPTR |
|
EA |
AND |
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|||
RST |
CONTROL |
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PORT 1 |
|
I2C |
|
PORT 3 |
|
|
|
|
|
LATCH |
|
|
LATCH |
|
|
|
|
|
|
|
|
|
|
||
|
OSC. |
|
PORT 1 |
|
Input Filter |
|
PORT 3 |
|
|
|
|
DRIVERS |
|
Output Stage |
DRIVERS |
|
|||
|
|
|
|
|
|
||||
|
XTAL1 |
|
XTAL2 |
|
|
|
|
|
|
|
|
|
|
P1.0-P1.7 |
|
|
|
P3.0-P3.7 |
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
6
PRELIMINARY
MX10E8050I /
MX10E8050IA
FUNCTIONAL DESCRIPTION
General
The MX10E8050I Serial is a stand-alone high-performance and low power microcontroller designed for use in many applications which need code programmability.
The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in many applications, not only in development stage, but also in mass production stage.
In addition to the 80C51 standard functions, the MX10E8050I Serial provides a number of dedicated hardware functions. MX10E8050I Serial is a control-oriented CPU with on-chip program and data memory. It can execute program with internal memory up to 64k bytes. MX10E8050I Serial has two software selectable modes of reduced activity for power reduction Idle, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers, serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be terminated by an external reset ,and in addition , by either of the two external interrupts can be terminated as the power down mode does.
MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes internal data memory (RAM), 1k byte auxiliary data memory (AUX-RAM) and 64k byte internal MTP program memory ( FLASH ROM ).
Program Memory
The program memory address space of the MX10E8050I Serial comprises an internal and an external memory space. The MX10E8050I Serial has 64k byte of program memory on-chip.
Program Protection
If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip.
Internal Data Memory
The internal data memory is divided into three physically separated parts: 256 byte of RAM, 1k bytes of AUX-RAM, and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.1 and Table. 2)
- RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank.
-RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register bank.
-AUX-RAM 0 to 1023 is indirectly addressable as the external data memory locations 0 to 1023 by the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. SFRs can only be addressed directly in the address range from 128 to 255.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
7
|
|
|
|
PRELIMINARY |
|
|
|
|
|
|
|
|
|
MX10E8050I / |
|
|
|
|
MX10E8050IA |
|
|
|
|
|
Table. 2 Internal data memory access |
|
|||
|
|
|||
LOCATION |
ADDRESSED |
|||
|
|
|||
RAM 0 to 127 |
DIRECT and INDIRECT |
|||
|
|
|||
RAM 128 to 255 |
INDIRECT only |
|||
|
|
|||
AUX-RAM 0 to 1023 |
INDIRECT only with MOVX |
|||
|
|
|||
Special Function Register (SFR) 128 to 255 |
DIRECT only |
|||
|
|
|
|
|
Fig. 1 shows the internal memory address space. Table 3 shows the Special Function Register (SFR) memory map. Location 0 to 31 at the lower RAM area can be devided into four 8-bit register banks. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.
The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-byte register banks reside in the SFR address space.
Five methods to access memory space are as floww :
-Register
-Direct
-Register-Indirect
-Immediate
-Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing destination operands. Most instructions have a 'destination / source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.
Access to memory addresses is as follows:
-Register in one of the four 8-byte register banks through Direct or Register-Indirect addressing.
-256 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be only be addressed indirectly as data RAM.
-SFR through direct addressing at address location 128-255.
OVERLAPPED SPACE with different access schemes
64k |
255 |
|
|
1023 |
|
|
Indirect |
SFRs |
|
|
|
Only |
direct only |
AUXILIARY |
FLASH memory |
127 |
|
|
|
|
|
RAM |
||
|
|
Direct and |
|
through |
|
|
|
MOVX access |
|
|
|
Indirect |
|
|
|
|
|
0 |
|
|
0 |
|
|
|
|
|
|
|
|
|
|
MAIN RAM |
SFRs |
AUX-RAM |
INTERNAL PROGRAM MEMORY |
INTERNAL DATA MEMORY |
Fig.1 Internal program and data memory address space
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
8
PRELIMINARY
MX10E8050I /
MX10E8050IA
Table. 3 SFR Register Map
HIGH NIBBLE OF SFR ADDRESS
LOW |
8 |
9 |
A |
B |
C |
D |
E |
F |
0 |
P0% |
P1% |
P2% |
P3% |
P4% |
PSW% |
ACC% |
B% |
|
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
00000000 |
00000000 |
00000000 |
|
|
|
|
|
|
|
|
|
1 |
SP |
|
|
|
|
|
|
PWMC |
|
00000111 |
|
|
|
|
|
|
10000000 |
|
|
|
|
|
|
|
|
|
2 |
DPL |
|
AUXR1 |
|
|
|
|
|
|
00000000 |
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3 |
DPH |
|
|
|
|
|
|
PWMP3 |
|
00000000 |
|
|
|
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
4 |
|
|
|
|
|
|
FMCON |
PWM2 |
|
|
|
|
|
|
|
00000001 |
00000000 |
|
|
|
|
|
|
|
|
|
5 |
|
|
|
|
|
|
FMDATA |
PWM3 |
|
|
|
|
|
|
|
00000000 |
00000000 |
|
|
|
|
|
|
|
|
|
6 |
|
|
|
|
|
|
|
PWMP2 |
|
|
|
|
|
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
7 |
PCON |
|
|
IPH |
|
|
|
|
|
00000000 |
|
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
8 |
TCON% |
SCON% |
IE% |
IP% |
T2CON% |
S1CON |
|
PDCON |
|
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
|
00000000 |
|
|
|
|
|
|
|
|
|
9 |
TMOD |
SBUF |
SADDR |
SADEN |
T2MOD |
S1STA |
|
|
|
00000000 |
XXXXXXXX 00000000 |
00000000 |
11111110 |
11111000 |
|
|
|
|
|
|
|
|
|
|
|
|
A |
TL0 |
|
|
|
RCAP2L |
S1DAT |
|
|
|
00000000 |
|
|
|
00000000 |
00000000 |
|
|
|
|
|
|
|
|
|
|
|
B |
TL1 |
|
|
|
RCAP2H |
S1ADR |
EBTCON |
PWMP1 |
|
00000000 |
|
|
|
00000000 |
00000000 |
XXXXXX1X |
00000000 |
|
|
|
|
|
|
|
|
|
C |
TH0 |
|
|
|
TL2 |
|
|
PWM0 |
|
00000000 |
|
|
|
00000000 |
|
|
00000000 |
|
|
|
|
|
|
|
|
|
D |
TH1 |
|
|
|
TH2 |
|
|
PWM1 |
|
00000000 |
|
|
|
00000000 |
|
|
00000000 |
|
|
|
|
|
|
|
|
|
E |
AUXR |
|
|
|
|
|
|
PWMP0 |
|
00000000 |
|
|
|
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
F |
|
|
|
|
|
|
|
T3 |
|
|
|
|
|
|
|
|
11111111 |
|
|
|
|
|
|
|
|
|
NOTES : |
|
|
|
|
|
|
|
|
|
% = Bit addressable register |
|
|
|
|
|
|
|
|
x = Undefined |
|
|
|
|
|
|
|
|
|
|||||||
P/N:PM0887 |
Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005 |
9
PRELIMINARY
MX10E8050I /
MX10E8050IA
Special Function Registers
Symbol |
Description |
Direct |
Bit Address, Symbol, or Alternative Port Function |
Reset |
|||||||
|
|
Address |
MSB |
|
|
|
|
|
LSB |
Function |
|
ACC |
Accumulator |
E0H |
E7 |
E6 |
E5 |
E4 |
E3 |
E2 |
E1 |
E0 |
00H |
|
|
|
|
|
|
|
|
|
|
|
|
AUXR |
Auxiliary |
8EH |
- |
- |
- |
- |
- |
- |
EXTRAM AO |
00000000B |
|
|
|
|
|
|
|
|
|
|
|
|
|
AUXR1 |
Auxiliary1 |
A2H |
- |
- |
ENBOOT |
- |
- |
0 |
- |
DPS |
00000000B |
|
|
|
|
|
|
|
|
|
|
|
|
B |
B register |
F0H |
F7 |
F6 |
F5 |
F4 |
F3 |
F2 |
F1 |
F0 |
00H |
|
|
|
|
|
|
|
|
|
|
|
|
DPTR |
Data pointer(2-byte) |
|
|
|
|
|
|
|
|
|
|
|
Data pointer high |
|
|
|
|
|
|
|
|
|
|
DPH |
Data pointer low |
83H |
|
|
|
|
|
|
|
|
00H |
DPL |
|
82H |
|
|
|
|
|
|
|
|
00H |
|
|
|
|
|
|
|
|
|
|
|
|
EBTCON Enable T3 |
EBH |
|
|
|
|
|
|
EB |
|
xxxxxx1xB |
|
|
|
|
|
|
|
|
|
|
|
|
|
FMCON |
Flash control |
E4H |
PPARAM |
PALE |
PCEB |
POEB |
PWEB |
- |
- |
PREADYB00000001B |
|
|
|
|
|
|
|
|
|
|
|
|
|
FMDATA |
Flash data |
E5H |
Bit7 |
Bit6 |
Bit5 |
Bit4 |
Bit3 |
Bit2 |
Bit1 |
Bit0 |
00000000B |
|
|
|
AF |
AE |
AD |
AC |
AB |
AA |
A9 |
A8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
IE |
Interrupt Enable |
A8H |
EA |
ET2 |
ES1 |
ES |
ET1 |
EX1 |
ET0 |
EX0 |
00000000B |
|
|
|
BF |
BE |
BD |
BC |
BB |
BA |
B9 |
B8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
IP |
Interrupt priority |
B8H |
- |
PT2 |
PS1 |
PS |
PT1 |
PX1 |
PT0 |
PX0 |
x0000000B |
|
|
|
B7 |
B6 |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
IPH |
Interrupt priority |
B7H |
- |
PT2H |
PS1H |
PSH |
PT1H |
PX1H |
PT0H PX0H |
x0000000B |
|
|
high |
|
|
|
|
|
|
|
|
|
|
|
|
|
87 |
86 |
85 |
84 |
83 |
82 |
81 |
80 |
|
|
|
|
|
|
|
|
|
|
|
|
|
P0 |
Port 0 |
80H |
AD7 |
AD6 |
AD5 |
AD4 |
AD3 |
AD2 |
AD1 |
AD0 |
FFH |
|
|
|
97 |
96 |
95 |
94 |
93 |
92 |
91 |
90 |
|
|
|
|
|
|
|
|
|
|
|
|
|
P1 |
Port 1 |
90H |
P17 |
P16 |
P15 |
P14 |
P13 |
P12 |
P11 |
P10 |
FFH |
|
|
|
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
P2 |
Port 2 |
A0H |
AD15 |
AD14 |
AD13 |
AD12 |
AD11 |
AD10 |
AD9 |
AD8 |
FFH |
|
|
|
B7 |
B6 |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
P3 |
Port 3 |
B0H |
RD |
WR |
T1 |
T0 |
INT1 |
INT0 |
TxD |
RxD |
FFH |
|
|
|
|
|
|
|
C3 |
C2 |
C1 |
C0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
P4 |
Port4 |
C0H |
- |
- |
- |
- |
PWM3 |
PWM2 |
PWM1 |
PWM0 |
FH |
|
|
|
|
|
|
|
|
|
|
|
|
PCON |
Power Control |
87H |
SMOD1 |
SMOD0 |
- |
WLE |
GF1 |
GF2 |
PD |
IDL |
00xx0000B |
|
|
|
|
|
|
|
|
|
|
|
|
PDCON |
ROM enable code F8H |
Bit7 |
Bit6 |
Bit5 |
Bit4 |
Bit3 |
Bit2 |
Bit1 |
Bit0 |
00000000B |
|
|
|
|
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PSW |
Program Status Word |
D0H |
CY |
AC |
F0 |
RS1 |
RS0 |
OV |
- |
P |
000000x0B |
|
|
|
|
|
|
|
|
|
|
|
|
PWMC |
PWM control |
F1H |
PWMD |
DSCB |
PWM3E |
PWM2E |
|
DSCA |
PWM1E PWM0E |
1000x000B |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWMP0 |
Prescaler vector 0 |
FEH |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP PWMP |
00000000B |
|
|
|
|
0.7 |
0.6 |
0.5 |
0.4 |
0.3 |
0.2 |
0.1 |
0.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWMP1 |
Prescaler vector 1 |
FBH |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP PWMP |
00000000B |
|
|
|
|
1.7 |
1.6 |
1.5 |
1.4 |
1.3 |
1.2 |
1.1 |
1.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWMP2 |
Prescaler vector 2 |
F6H |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP |
PWMP PWMP |
00000000B |
|
|
|
|
2.7 |
2.6 |
2.5 |
2.4 |
2.3 |
2.2 |
2.1 |
2.0 |
|
|
|
|
|
|
|||||||
PWMP3 Prescaler vector 3 |
F3H |
PWMP |
PWMP |
PWMP PWMP PWMP PWMP PWMP PWMP 00000000B |
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
10
PRELIMINARY
MX10E8050I /
MX10E8050IA
|
|
|
3.7 |
3.6 |
3.5 |
3.4 |
3.3 |
3.2 |
3.1 |
3.0 |
|
PWM0 |
PWM0 ratio |
FCH |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
00000000B |
|
|
|
0.7 |
0.6 |
0.5 |
0.4 |
0.3 |
0.2 |
0.1 |
0.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM1 |
PWM1 ratio |
FDH |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
00000000B |
|
|
|
1.7 |
1.6 |
1.5 |
1.4 |
1.3 |
1.2 |
1.1 |
1.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM2 |
PWM2 ratio |
F4H |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
00000000B |
|
|
|
2.7 |
2.6 |
2.5 |
2.4 |
2.3 |
2.2 |
2.1 |
2.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM3 |
PWM3 ratio |
F5H |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
00000000B |
|
|
|
3.7 |
3.6 |
3.5 |
3.4 |
3.3 |
3.2 |
3.1 |
3.0 |
|
|
|
|
|
|
|
|
|
|
|
||
RACAP2H Timer 2 Capture High CBH |
|
|
|
|
|
|
|
|
00H |
||
RACAP2L |
Timer 2 Capture Low CAH |
|
|
|
|
|
|
|
|
00H |
|
SADDR |
Slave Address |
A9H |
|
|
|
|
|
|
|
|
00H |
SADEN |
Slave address Mask B9H |
|
|
|
|
|
|
|
|
00H |
|
SBUF |
Serial Data Buffer 99H |
|
|
|
|
|
|
|
|
xxxxxxxxB |
|
|
|
|
9F |
9E |
9D |
9C |
9B |
9A |
99 |
98 |
|
|
|
|
|
|
|
|
|
|
|
|
|
SCON |
Serial Control |
98H |
SM0/FE SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
00H |
|
|
|
|
|
|
|
|
|
|
|
|
|
SP |
Stack Pointer |
81H |
|
|
|
|
|
|
|
|
07H |
|
|
|
DF |
DE |
DD |
DC |
DB |
DA |
D9 |
D8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
S1CON |
I2C Control |
D8H |
CR2 |
ENS1 |
STA |
STO |
SI |
AA |
CR1 |
CR0 |
00H |
S1STA |
I2C Status |
D9H |
S1STA.7 |
S1STA.6 |
S1STA.5 |
S1STA.4 |
S1STA.3 |
|
|
|
00H |
S1DAT |
I2C data |
DAH |
S1DAT.7 |
S1DAT.6 |
S1DAT.5 |
S1DAT.4 |
S1DAT.3 |
S1DAT.2 |
S1DAT.1 |
S1DAT.0 |
00H |
S1ADR |
I2C address |
DBH |
S1ADR.7 |
S1ADR.6 |
S1ADR.5 |
S1ADR.4 |
S1ADR.3 S1ADR.2 S1ADR.1 GC |
00H |
|||
TCON |
Timer Control |
88H |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
00H |
|
|
|
CF |
CE |
CD |
CC |
CB |
CA |
C9 |
C8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
T2CON |
Timer 2 Control |
C8H |
TF2 |
EXF2 |
RCLK |
TCLK |
EXEN2 |
TR2 |
C/T2 |
CP/RL |
00H |
|
|
|
|
|
|
|
|
|
|
|
|
T2MOD |
Timer 2 Mode ControlC9H |
- |
- |
- |
- |
- |
- |
T2OE |
DCEN |
xxxxxx00B |
|
|
|
|
|
|
|
|
|
|
|
|
|
TH0 |
Timer High 0 |
8CH |
|
|
|
|
|
|
|
|
00H |
TH1 |
Timer High 1 |
8DH |
|
|
|
|
|
|
|
|
00H |
TH2 |
Timer High 2 |
CDH |
|
|
|
|
|
|
|
|
00H |
TL0 |
Timer Low 0 |
8AH |
|
|
|
|
|
|
|
|
00H |
TL1 |
Timer Low 1 |
8BH |
|
|
|
|
|
|
|
|
00H |
TL2 |
Timer Low 2 |
CCH |
|
|
|
|
|
|
|
|
00H |
|
|
|
|
|
|
|
|
|
|
||
TMOD |
Timer Mode |
89H |
GATE C/T |
M1 |
M0 |
GATE C/T |
M1 |
M0 |
00H |
||
|
|
|
|
|
|
|
|
|
|
|
|
T3 |
Timer 3 |
FFH |
|
|
|
|
|
|
|
|
FFH |
|
|
|
|
|
|
|
|
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
11
PRELIMINARY
MX10E8050I /
MX10E8050IA
AUXR (8EH)
|
|
|
|
|
|
EXTRAM |
A0 |
|
|
|
|
|
|
|
|
- EXTRAM : External RAM Select Switch. Set 1 to select (MOVX) the external RAM directly. Default is 0 to switch (MOVX) to external RAM only when the address is larger than 1k.
- AO : Turn off ALE output in internal execution mode. ( 1 : Turn off )
( 0 : Turn on )
Watchdog Timer/WDT/T3 (FFH)
- WDT consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3.
EBTCON (EBH)
/EW
- /EW: After reset, /EW bit is set, and WDT is disable.
POWER CONTROL Register/PCON (87H)
SMOD1 |
SMOD0 |
X |
WLE |
GF1 |
GF0 |
PD |
IDL |
|
|
|
|
|
|
|
|
-SMOD1: Double baud rate bit for UART.
-SMOD0: Frame error detection bit.
-WLE: Watchdog load enable. This flag must be set prior to loading WDT and is cleared when WDT is loaded.
-GF1/GF0: general-purpose flag bit.
-PD: Power-down bit. Setting it activates power-down mode.
-IDL: Idle mode bit. Setting it activates idle mode.
-The CPU & Peripheral status during 2 power saving mode:
|
Idle mode |
Power-down mode |
CPU |
OFF |
OFF |
|
|
|
Int,Timer. |
ON |
OFF |
|
|
|
Oscillator ckt |
ON |
OFF |
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
12
PRELIMINARY
MX10E8050I /
MX10E8050IA
I/O facilities
MX10E8050I serial has one 8 bits port, port 0, which is open drain, three 8 bits ports, port1/2/3 and a four-bits port port 4 . They are quasi bi-directional ports except P1.6 and P1.7. These five ports are fully compatible to standard 80C51's port 0/1/2/3/4.
-Port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1); external inputs for Timer/ counter 0 and Timer /counter1, and UART receive / transmit.
-Port 1.6, Port 1.7 : pins are used to be I2C clock and data I/O, which are open drain
Port pins which are not used for alternate functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternate function is carried out automatically by writing the associated SFR bit with proper value.
|
|
+3V |
|
2 oscillator |
|
|
penods |
P2 |
|
strong pull-up |
|
|
P1 |
P3 |
|
|
I/O PORT |
|
|
1,2,3,4 |
O |
|
exclude P1.6,P1.7 |
|
|
|
from port latch |
n |
|
|
|
input data
INPUT
BUFFER
read port pin
I/O buffers in the MX10E8050I (Ports 1,2,3,4)
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
13
PRELIMINARY
MX10E8050I /
MX10E8050IA
Timer/Counter
MX10E8050I Serial Timer/Counter 0 and 1 are fully compatible to standard 80C51's.
The MX10E8050I Serial contains two 16-bit Timer/counters, Timer 0 and Timer 1. Timer 0 and Timer 1 may be programmed to carry out the following functions:
-measure time intervals and pulse durations
-count events
-generate interrupt requests.
Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in TMOD SFR that selects the Timer or counter function of the corresponding Timer. In the Timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding samples, when the transition shows a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.
Timer 0 and Timer 1 can be programmed independently to operate in one of four modes (refer to table 5) :
-Mode 0 : 8-bit Timer/counter with devided-by-32 prescaler
-Mode 1 : 16-bit Timer/counter
-Mode 2 : 8-bit Timer/counter with automatic reload
-Mode 3 : Timer 0 :one 8-bit Timer/counter and one 8-bits Timer. Timer 1 :stopped.
When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rgate generator. With a 16 MHz crystal, the counting frequency of these Timer/counters is as follows:
-in the Timer function, the Timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12).
-in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz (oscillator frequency divided by 24).
Both internal and external inputs can be gated to the Timer by a second external source for directly measuring pulse duration.
The Timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.
TMOD : TIMER/COUNTER MODE CONTROL REGISTER
This register is located at address 89H.
Table. 4 TMOD SFR (89H)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
GATE |
C/ T |
M1 |
M0 |
GATE |
C/ T |
M1 |
M0 |
|
|
|
|
|
|
|
|
(MSB) |
|
|
|
|
|
|
(LSB) |
|
|
|
|
|
|
|
|
TIMER 1 |
|
|
|
TIMER 0 |
|
|
|
|
|
|
|
|
|
|
|
keep the above table with the following table
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
14
PRELIMINARY
MX10E8050I /
MX10E8050IA
Table. 5 Description of TMOD bits
MNEMONIC POSITION FUNCTION
TIMER 1
GATE |
|
TMOD.7 |
Timer 1 gating control : when set, Timer/counter '1' is enabled only while 'Int1' |
|
|
|
pin is high and 'tr1' control bit is set. when cleared, Timer/counter '1' is enabled |
|
|
|
whenever 'tr1' control bit is set. |
|
|
|
|
C/T |
|
TMOD.6 |
Timer or counter selector: cleared for Timer operation (input from internal |
|
|
|
system clock). set for counter operation (input from 'T1' input pin). |
|
|
|
|
M1 |
|
TMOD.5 |
Operation mode: see table 6. |
|
|
|
|
M0 |
|
TMOD.4 |
Operation mode: see table 6. |
|
|
|
|
TIMER 0 |
|
|
|
|
|
|
|
GATE |
|
TMOD.3 |
Timer 0 gating control: when set, Timer/Counter '0' is enabled only while 'Int0' |
|
|
|
pin is high and 'tr0' control bit is set. when cleared, Timer/counter '0' is enabled |
|
|
|
whenever 'tr0' control bit is set. |
|
|
|
|
C/T |
|
TMOD.2 |
Timer or counter selector: cleared for Timer operation (input from internal |
|
|
|
system clock). set for counter operation (input from 'T0' input pin). |
|
|
|
|
M1 |
|
TMOD.1 |
Operation mode: see table 6. |
|
|
|
|
M0 |
|
TMOD.0 |
Operation mode: see table 6. |
|
|||
Table. 6 TMOD M1 and M0 operating modes |
|||
|
|
|
|
M1 |
M0 |
FUNCTION |
|
|
|
|
|
0 |
0 |
8-bit Timer/counter : 'THx' with 5-bit prescaler. |
|
|
|
|
|
0 |
1 |
16-bit Timer/counter : 'THx' and 'TLx' are cascaded, there is no prescaler. |
10 8-bit autoload Timer/counter : 'THx' holds a value which is to be reloaded into 'TLx' each time it overflows.
11 Timer 0: TL0 is an 8-bit Timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8- bit Timer controlled by Timer 1 control bits.
11 Timer 1 : Timer/counter 1 stopped.
TCON : TIMER/COUNTER CONTROL REGISTER
This register is located at address 88H.
Notes :
Symbol |
Description |
Direct |
Bit Address, Symbol, or Alternative Port Function |
Reset |
|
|
|
Address |
MSB |
LSB |
Function |
|
|
|
|
|
|
TMOD |
Timer Mode |
89H |
GATE C/T M1 M0 GATE C/T M1 |
M0 |
00H |
|
|
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
15
PRELIMINARY
MX10E8050I /
MX10E8050IA
Table. 7 TCON SFR (88H)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
|
|
|
|
|
|
|
|
(MSB) |
|
|
|
|
|
|
(LSB) |
|
|
|
|
|
|
|
|
keep the above table with the following table
Table. 8 Description of TCON bits
MNEMONIC |
POSITION |
FUNCTION |
TF1 |
TCON.7 |
Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when |
|
|
interrupt is processed. |
|
|
|
TR1 |
TCON.6 |
Timer 1 control bit : set/cleared by software to turn Timer/counter ON/OFF. |
|
|
|
TF0 |
TCON.5 |
Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when |
|
|
interrupt is processed. |
|
|
|
TR0 |
TCON.4 |
Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF. |
|
|
|
IE1 |
TCON.3 |
Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared |
|
|
when interrupt is processed. |
|
|
|
IT1 |
TCON.2 |
Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW |
|
|
level triggered external interrupt. |
|
|
|
IE0 |
TOCN.1 |
Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared |
|
|
when interrupt is processed. |
|
|
|
IT0 |
TOCN.0 |
Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW |
|
|
level triggered external interrupt. |
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
16
PRELIMINARY
MX10E8050I /
MX10E8050IA
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/ T2* in the special function register T2CON (see Figure 2). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 9.
Capture Mode
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure B (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12 clock mode).).
Auto-Reload Mode ( Up or Down Counter )
In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 4). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin.
Figure 5 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.
In Figure 6 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
17
PRELIMINARY
MX10E8050I /
MX10E8050IA
|
|
|
|
|
|
(MSB) |
|
|
|
|
|
|
|
|
|
|
(LSB) |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
TF2 |
|
EXF2 |
RCLK |
TCLK |
EXEN2 |
TR2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/T2 |
|
CP/RL2 |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Symbol |
Position |
Name and Significance |
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TF2 |
T2CON.7 |
|
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set |
||||||||||||||||||
|
|
|
|
|
|
|
|
when either RCLK or TCLK = 1. |
|
|
|
|
|
|
|
|
|
|
|||
EXF2 |
T2CON.6 |
|
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and |
||||||||||||||||||
|
|
|
|
|
|
|
|
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 |
|||||||||||||
|
|
|
|
|
|
|
|
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down |
|||||||||||||
|
|
|
|
|
|
|
|
counter mode (DCEN = 1). |
|
|
|
|
|
|
|
|
|
|
|
||
RCLK |
T2CON.5 |
|
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock |
||||||||||||||||||
|
|
|
|
|
|
|
|
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. |
|||||||||||||
TCLK |
T2CON.4 |
|
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock |
||||||||||||||||||
|
|
|
|
|
|
|
|
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. |
|||||||||||||
EXEN2 |
T2CON.3 |
|
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative |
||||||||||||||||||
|
|
|
|
|
|
|
|
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to |
|||||||||||||
|
|
|
|
|
|
|
|
ignore events at T2EX. |
|
|
|
|
|
|
|
|
|
|
|
||
TR2 |
T2CON.2 |
|
Start/stop control for Timer 2. A logic 1 starts the timer. |
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
T2CON.1 |
|
Timer or counter select. (Timer 2) |
|
|
|
|
|
|
|
|
|
|
||||
C/T2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 in 12 clock mode) |
||||||||||||
|
|
|
|
|
|
|
|
|
1 = External event counter (falling edge triggered). |
|
|
|
|
|
|
|
|
||||
|
|
|
T2CON.0 |
|
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When |
||||||||||||||||
CP/RL2 |
|
||||||||||||||||||||
|
|
|
|
|
|
|
|
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when |
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Figure 2. Timer / Counter 2 (T2CON) Control Register
Table 9 : Timer 2 Operation Modes
RCLK + TCLK |
CP / RL2 |
TR2 |
MODE |
|
|
|
|
0 |
0 |
1 |
16-bit Auto-reload |
|
|
|
|
0 |
1 |
1 |
16-bit Capture |
|
|
|
|
1 |
X |
1 |
Baud rate generator |
|
|
|
|
X |
X |
0 |
( off ) |
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
18
|
|
|
|
PRELIMINARY |
|
|
|
|
MX10E8050I / |
|
|
|
|
MX10E8050IA |
OSC |
÷ n* |
|
|
|
|
C/T2 = 0 |
|
|
|
|
|
TL2 |
TH2 |
TF2 |
|
|
(8-bits) |
(8-bits) |
|
|
|
|
||
|
C/T2 = 1 |
|
|
|
T2 Pin |
|
Control |
|
|
|
|
|
|
|
|
TR2 |
Capture |
|
|
|
|
|
|
|
|
Transition |
|
|
Timer 2 |
|
Detector |
|
|
Interrupt |
|
|
RCAP2L |
RCAP2H |
|
T2EX Pin |
|
|
|
EXF2 |
|
Control |
|
|
|
|
EXEN2 |
|
|
|
* n = 12 in 12 clock mode. |
|
|
|
|
n = 6 in 6 clock mode. |
|
|
|
Figure 3 : Timer 2 in Capture Mode
T2MOD |
Address = 0C9H |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Reset Value = XXXX XX00B |
||||||
|
Not Bit Addressable |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T2OE |
DCEN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bit |
7 |
|
|
6 |
5 |
|
4 |
3 |
|
2 |
|
1 |
0 |
|
|
|||||||
Symbol |
Function |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
- |
Not implemented, reserved for future use.* |
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
T2OE |
Timer 2 Output Enable bit. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
DCEN |
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. |
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Figure 4 : Timer 2 Mode (T2MOD) Control Register
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
19
|
|
|
|
PRELIMINARY |
|
|
|
|
MX10E8050I / |
|
|
|
|
MX10E8050IA |
OSC |
÷ n* |
|
|
|
|
|
C/T2 = 0 |
|
|
|
|
|
TL2 |
TH2 |
|
|
|
(8-BITS) |
(8-BITS) |
|
|
C/T2 = 1 |
|
|
T2 PIN |
|
|
CONTROL |
|
|
|
|
|
|
|
|
TR2 |
RELOAD |
|
|
|
|
|
|
|
TRANSITION |
|
|
|
|
DETECTOR |
|
RCAP2L |
RCAP2H |
|
|
|
|
TF2 |
|
|
|
|
TIMER 2 |
|
|
|
|
INTERRUPT |
T2EX PIN |
|
|
|
EXF2 |
|
|
CONTROL |
|
|
* n = 12 in 12 clock mode. |
EXEN2 |
|
|
|
|
|
|
||
n = 6 in 6 clock mode. |
|
|
|
Figure 5 : Timer 2 in Auto-Reload Mode (DCEN = 0)
|
|
|
(DOWN COUNTING RELOAD VALUE) |
|
|
|
|
|
|
FFH |
FFH |
TOGGLE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EXF2 |
OSC |
÷ n* |
C/T2 = 0 |
|
|
|
|
|
|
|
|
|
OVERFLOW |
|
|
|
|
TL2 |
TH2 |
TF2 |
INTERRUPT |
|
T2 PIN |
C/T2 = 1 |
|
|
|
|
|
|
|
CONTROL |
|
|
|
|
|
|
TR2 |
|
COUNT |
|
|
|
|
|
|
|
|
|
|
|
|
|
DIRECTION |
|
|
|
|
|
|
1 = UP |
|
|
|
|
|
|
0 = DOWN |
|
|
|
|
RCAP2L |
RCAP2H |
|
|
* n = 12 in 12 clock mode. |
(UP COUNTING RELOAD VALUE) |
T2EX PIN |
|
|||
|
|
|
|
|||
n = 6 in 6 clock mode. |
|
|
|
|
|
Figure 6 : Timer 2 Auto-Reload Mode (DCEN = 1)
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
20
PRELIMINARY
MX10E8050I /
MX10E8050IA
Timer 1
Overflow
|
|
|
|
|
÷ 2 |
|
|
OSC |
÷ n* |
|
|
|
"0" |
"1" |
|
|
|
|
|
|
|
||
|
C/T2 = 0 |
|
|
|
|
|
SMOD |
|
|
|
|
"1" |
"0" |
|
|
|
|
TL2 |
TH2 |
|
|
||
|
|
|
|
|
|
||
|
|
(8-bits) |
(8-bits) |
|
|
|
RCLK |
|
C/T2 = 1 |
|
|
|
|
|
|
T2 Pin |
Control |
|
|
|
|
|
|
|
|
|
|
|
÷ 16 |
|
|
|
|
|
|
|
|
RX Clock |
|
|
TR2 |
|
Reload |
"1" |
"0" |
|
|
|
|
|
|
|
TCLK |
||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
Transition |
|
|
|
|
|
|
|
Detector |
RCAP2L |
RCAP2H |
|
|
÷ 16 |
|
|
|
|
|
TX Clock |
|||
|
|
|
|
|
|
||
T2EX Pin |
EXF2 |
Timer 2 |
|
|
|
|
|
|
|
Interrupt |
|
|
|
|
|
|
Control |
|
|
|
|
|
|
|
EXEN2 |
|
|
|
|
|
|
*n = 2 in 12 clock mode. n = 1 in 6 clock mode.
Note availability of additional external interrupt.
Figure 7. Timer 2 in Baud Rate Generator Mode
Table 10 : Timer 2 Generated Commonly Used Baud Rates
Baud Rate |
|
Timer 2 |
|
|
Osc Freq |
|
|
12 clock |
RCAP2H |
RCAP2L |
|
mode |
|
||
|
|
|
|
|
|
|
|
375 k |
12 MHz |
FF |
FF |
9.6 k |
12 MHz |
FF |
D9 |
2.8 k |
12 MHz |
FF |
B2 |
2.4 k |
12 MHz |
FF |
64 |
1.2 k |
12 MHz |
FE |
C8 |
300 |
12 MHz |
FB |
1E |
110 |
12 MHz |
F2 |
AF |
300 |
6 MHz |
FD |
8F |
110 |
6 MHz |
F9 |
57 |
Baud Rate Generator Mode
Bits TCLK and / or RCLK in T2CON (Table 10) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK = 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK = 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With there two bits, the serial port can have different receive and transmit baud rates - one generated by Timer1, the other by Timer2.
Figure 7 shows the Timer2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below :
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates =
16
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
21
PRELIMINARY
MX10E8050I /
MX10E8050IA
The Timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation ( C/T 2* = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator.
Usually, as a timer it would increment every machine cycle ( i.e., 1/6 the oscillator frequency in 6 clock mode, 1/ 12 the oscillator frequency in 12 clock mode). As a baud rate generator, it increments at the oscillator frequency in 6 clock mode (OSC/2 in 12 clock mode).
Thus the baud rate formula is as follows :
Oscillator Frequency
Modes 1 and 3 Baud Rates =
[ n * x [65536 - (RCAP2H, RCAP2L) ] ]
*n = 32 in 12 clock mode or 16 in 6 clock mode
Where : (RCAP2h, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
The Timer 2 as a baud rate generator mode shown in Figure7, is valid only if RCLK and / or TCLK = 1in T2CON register. Note that a rollover in TH2 does not set TF2, and Will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baudrate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer / counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and / or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
Table 10 shows commonly used baud rates and how they can be obtained from Timer 2.
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is :
Timer 2 Overflow Rate
Baud Rate =
16
If Timer 2 is being clocked internally, The baud rate is :
fOSC
Baud Rate =
[ n * x [65536 - (RCAP2H, RCAP2L) ] ]
*n = 32 in 12 clock mode or 16 in 6 clock mode
Where fOSC = Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as :
RCAP2H, RCAP2L = 65536 - ( |
|
fOSC |
) |
|
n * x Baud Rate |
||
|
|
|
Timer / Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 11 for set-up of Timer 2 as a timer. Also see Table 12 for set-up of Timer 2 as a counter.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
22
PRELIMINARY
MX10E8050I /
MX10E8050IA
Table 11 : Timer 2 as a Timer
|
|
T2CON |
|
|
MODE |
INTERNAL CONTROL |
|
EXTERNAL CONTROL |
|
|
|
(Note 1) |
|
(Note 2) |
|
|
|
|
|
16-bit Auto-Reload |
00H |
|
08H |
|
|
|
|
|
|
16-bit Capture |
01H |
|
09H |
|
|
|
|
|
|
Baud rate generator receive and transmit same baud rate |
34H |
|
36H |
|
|
|
|
|
|
Receive only |
24H |
|
26H |
|
|
|
|
|
|
Transmit only |
14H |
|
16H |
|
|
|
|
|
|
Table 12 : Timer 2 as a Counter
|
T2CON |
|
|
MODE |
INTERNAL CONTROL |
|
EXTERNAL CONTROL |
|
(Note 1) |
|
(Note 2) |
|
|
|
|
16-bit |
02H |
|
0AH |
|
|
|
|
Auto-Reload |
03H |
|
0BH |
|
|
|
|
NOTES :
1.Capture / reload occurs only on timer / counter overflow.
2.Capture / reload occurs on timer / counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generatior mode.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
23
PRELIMINARY
MX10E8050I /
MX10E8050IA
Interrupt system
The MX10E8050I Serial contains a 7-source (2 external interrupts, Timer 0, Timer1, Timer2, I2C and UART) with four priority levels interrupt structure.
Each External interrupts INT0 and INT1, can be either level-activated or transition-activated depending on bits IT0 and IT1 in TCON SFR. The flags that actually generate these interrupts are bits IE0, IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware where the service routine is vectored to, if the interrupt is transition-activated. If the interrupt is level-activated the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed, otherwise another interrupt will be generated.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
IE : INTERRUPT ENABLE REGISTER
This register is located at address A8H.
Table. 13 IE SFR (A8H)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
EA |
ET2 |
ES1 |
ES |
ET1 |
EX1 |
ET0 |
EX0 |
|
|
|
|
|
|
|
|
(MSB) |
|
|
|
|
|
|
(LSB) |
|
|
|
|
||||
keep the above table with the following table |
|
|
|
||||
Table. 14 Description of IE bits |
|
|
|
|
|
||
|
|
|
|
|
|||
MNEMONIC POSITION |
FUNCTION |
|
|
|
|||
|
|
|
|
|
|
||
EA |
IE.7 |
|
Disable all interrupt |
|
|
||
|
|
|
- Low, all disabled. |
|
|
||
|
|
|
- High, each interrupt source is individually enabled or disabled by setting or |
||||
|
|
|
clearing its enable bit. |
|
|
||
|
|
|
|
||||
ET2 |
IE.6 |
|
Enable / Disable Timer2 interrupt. |
||||
|
|
|
- Low, disabled |
|
|
|
|
|
|
|
- High, enabled |
|
|
|
|
|
|
|
|
|
|||
ES1 |
IE.5 |
|
Enable / Disable l2C Interrupt. |
|
|||
|
|
|
- Low, disabled |
|
|
|
|
|
|
|
- High, enabled |
|
|
|
|
|
|
|
|
|
|||
ES |
IE.4 |
|
Enable / Disable UART interrupt. |
|
|||
|
|
|
- Low, disabled |
|
|
|
|
|
|
|
- High, enabled |
|
|
|
|
|
|
|
|
||||
ET1 |
IE.3 |
|
Enable / Disable Timer1 overflow interrupt. |
||||
|
|
|
|
||||
EX1 |
IE.2 |
|
Enable / Disable External interrupt 1. |
||||
|
|
|
- Low, disabled |
|
|
|
|
|
|
|
- High, enabled |
|
|
|
|
|
|
|
|
||||
ET0 |
IE.1 |
|
Enable / disable Timer0 overflow interrupt. |
||||
|
|
|
|
||||
EX0 |
IE.0 |
|
Enable / Disable External interrupt 0. |
||||
|
|
|
- Low, disabled |
|
|
|
|
|
|
|
- High, enabled |
|
|
|
|
|
|
|
|
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
24
PRELIMINARY
MX10E8050I /
MX10E8050IA
IP : INTERRUPT PRIORITY REGISTER
This register is located at address B8H.
Table. 15 IP SFR (B8H)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
PT2 |
PS1 |
PS |
PT1 |
PX1 |
PT0 |
PX0 ( LSB ) |
|
|
|
|
|
|
|
|
keep the above table with the following table
Table. 16 Description of IP bits
MNEMONIC |
POSITION |
FUNCTION |
- |
IP.7 |
RESERVED |
|
|
|
PT2 |
IP.6 |
Define Timer2 interrupt priority level. |
|
|
- High, assign a high priority level. |
|
|
|
PS1 |
IP.5 |
Define I2C interrupt priority level. |
|
|
- High, assign a high priority level. |
|
|
|
PS |
IP.4 |
Define interrupt priority level of UART. |
|
|
|
PT1 |
IP.3 |
Define Timer1 overflow interrupt priority level. |
|
|
|
PX1 |
IP.2 |
Define External interrupt 1 interrupt priority level. |
|
|
- High, assign a high priority level. |
|
|
|
PT0 |
IP.1 |
Define Timer0 overflow interrupt priority level. |
|
|
|
PX0 |
IP.0 |
Define External interrupt 0 interrupt priority level. |
|
|
- High, assign a high priority level. |
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
25
PRELIMINARY
MX10E8050I /
MX10E8050IA
IPH : INTERRUPT HIGH PRIORITY REGISTER
This register is located at address B7H.
Table. 17 IPH SFR (B7H)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- PT2H PS1H PSH PT1H PX1H PT0H PX0H ( LSB )
keep the above table with the following table
Table. 18 Description of IPH bits
MNEMONIC |
POSITION |
FUNCTION |
|
- |
IPH.7 |
RESERVED |
|
|
|
|
|
PT2H |
IPH.6 |
Define Timer2 interrupt priority level. |
|
|
|
- High, assign a high priority level. |
|
|
|
|
|
PS1H |
IPH.5 |
Define I2C interrupt priority level. |
|
|
|
- High, assign a high priority level. |
|
|
|
|
|
PSH |
IPH.4 |
Define interrupt priority level of UART. |
|
|
|
|
|
PT1H |
IPH.3 |
Define Timer1 overflow interrupt priority level. |
|
|
|
|
|
PX1H |
IPH.2 |
Define External interrupt 1 interrupt priority level. |
|
|
|
- High, assign a high priority level. |
|
|
|
|
|
PT0H |
IPH.1 |
Define Timer0 overflow interrupt priority level. |
|
|
|
|
|
PX0H |
IPH.0 |
Define External interrupt 0 interrupt priority level. |
|
|
|
- High, assign a high priority level. |
|
|
|
|
|
|
|
|
|
NAME |
PRIORITY WITHIN LEVEL |
VECTOR ADDRESS |
|
|
|
|
|
IE0 |
(HIGHEST) |
1 |
0003H |
|
|
|
|
I2C |
|
2 |
002BH |
TF0 |
|
3 |
000BH |
|
|
|
|
IE1 |
|
4 |
0013H |
|
|
|
|
TF1 |
|
5 |
001BH |
|
|
|
|
RI + TI |
|
6 |
0023H |
|
|
|
|
TF2 + EXF2 |
(LOWEST) |
7 |
0033H |
|
|
|
|
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
26
PRELIMINARY
MX10E8050I /
MX10E8050IA
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the datasheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two and half machine cycles (15 oscillator periods in 6-clock mode, or 30 oscillator periods in 12-clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1,2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH (min.) is applied to RST.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
POWER_DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. The power-down mode can be terminated by a RESET in the same way as in the 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does ont affect the internal data memory and does not affect the internal data memory and does not affect the special function registers. This makes it possible to exit power-down without changing the port output levels. To terminate the power-down mode with any external interrupt INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept low until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the power-down mode will be executed. A reset generated by the watchdog timer terminates the power-down mode in the same way as an external RESET, and only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON.
DESIGN CONSIDERATIONS
At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up.
When the idle mode is terminated by a hardware reset, the device normally resumes program exectution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory.
Table 19 shows the state of I/O ports during low current operation modes.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
27