MSI MS-V119 Schematic

5

Title

Title

Title

RH PCIE RV635 2x256MB GDDR3 DUAL DL-DVI-I DL-DVI-I VO FH Wednesday, October 31, 2007

RH PCIE RV635 2x256MB GDDR3 DUAL DL-DVI-I DL-DVI-I VO FH Wednesday, October 31, 2007

RH PCIE RV635 2x256MB GDDR3 DUAL DL-DVI-I DL-DVI-I VO FH Wednesday, October 31, 2007

REVISION HISTORY

REVISION HISTORY

REVISION HISTORY

D D

Sch

Sch

Sch
Rev

Rev

Rev

C C

PCB

PCB

PCB
Rev

Rev

Rev

0

00A

100

Date

Date

Date

07/13/07

10/25/07 Release To Rev 00

Initial design for RV635 GDDR3

4

NOTE:

NOTE:

NOTE:

3

105-B380xx-00

105-B380xx-00

105-B380xx-00

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.

This schematic represents the PCB, it does not represent any specific SKU.
For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.

Please contact AMD representative to obtain latest BOM closest to the application desired.

Please contact AMD representative to obtain latest BOM closest to the application desired.

REVISION DESCRIPTION

REVISION DESCRIPTION

REVISION DESCRIPTION

2

Date:Schematic No.

Date:Schematic No.

Date:Schematic No.

1

Rev

Rev

Rev

1

1

1

B B

A A

5

4

3

2

1

www.vinafix.vn

5

4

3

2

1

MEMORY CHANNEL A & B - RANK0

GDDR3 4pcs 16Mx32 (256MB)

D D

MEMORY CHANNEL A & B - RANK1

GDDR3 4pcs 16Mx32 (256MB)

RANK0 RANK1

TMDS1

Debug

POWER REGULATORS

From +12V

+VDDC (MPVDD, VDDCI),
+MVDD

From +12V LINEAR:

C C

+5V, +5V_VESA,

From +12V DIRECT:

FAN

From +MVDD Linear (1.1V):

PCIE_VDDC, DPLL_VDDC

From +3.3V:
Direct or Linear (1.8V)

VDD_CT, DPLL_PVDD, DPA_PVDD, DPB_PVDD,
T2PVDD, DPA_VDDR, DPB_VDDR,
T2XVDDR(LTVDD33), T2XVDDC(LTVDD18), AVDD,
A2VDD, A2VDDQ, VDD1DI, VDD2DI,
PCIE_VDDR, PCIE_PVDD, VDDR3, VDDR4,
VDDR5

CrossFire
Interlink
Header

FAN

Connector

Straps

BIOS

Speed control
& temperature
sense

Built-in PWM

INTERRUPT
Temp. Sensing

Dynamic VDDC

CrossFire

DVOCLK
DVPCNTL_[0..2]
DVPDATA[23:0]
DVP_MVP_CNTL[1:0]
GPIO[6:3]
GENERICB, DVALID

GPIO

ROM

Thermal

DDC2

GPIO17
D+/D-

TS_FDO

GPIO20

POWER DELIVERY

+PCIE_SOURCE

B B

+3.3V

3.3V_BUS
delayed circuit

SMPS Enable
Circuit

+12V_BUS

Temperature Critical

RV635

CTF

PCI-Express

DL TMDS1

HPD1

DAC2

CRT2

H/V2Sync

AUX_DDC3

XTALIN

XTALOUT

GENERICA

TMDS2

DL TMDS2

HPD2
(GPIO14)

DAC1

CRT1

H/VSync

DDC1

TVO

STV/HDTV#_OUT_DET

Shunt Resistors

RBG Filters

TVO Filters

Oscillator

XTAL

Shunt Resistors

RBG Filters

AC Coupling Caps

HPD1

DVI-I,
HDMI
Slim-VGA
Connector

5V_VESA2

TVO
Connector

HPD2

DVI-I
Slim-VGA
Connector

5V_VESA

&

&

+3.3V_BUS
+12V_BUS

PCI-Express Bus

RH PCIE RV635 2x256MB GDDR3
DUAL DL-DVI-I HDMI VO FH

REV 0

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - BLOCK DIAGRAM

RV635 GDDR3 - BLOCK DIAGRAM

5

4

3

2

RV635 GDDR3 - BLOCK DIAGRAM

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

21 21

of

21 21

of

21 21

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

7

6

5

4

3

2

1

+12V_BUS

C1

CAP CER 10UF 20% 16V X5R

10UFC110UF

(1206)1.8MM H MAX

+12V_BUS

+12V_BUS

C3

C3

D D

C C

B B

C2

150nF_16V

150nF_16V

150nF_16VC2150nF_16V

LF CAP CER 150NF 10% 16V X7R (0603)

LF CAP CER 150NF 10% 16V X7R (0603)

CAP CER 10UF 10% 6.3V X6S
(0805)1.4MM MAX THICK

Overlap footprints

+3.3V_BUS

MC4

MC4

C4

DNI

+3.3V_BUS

4.7uF_6.3V

4.7uF_6.3V

10uF_X6SC410uF_X6S

C6

C5

1uF_6.3VC61uF_6.3V

100nF_6.3VC5100nF_6.3V

Place these caps as close to the PCIE
connector as possible

SMBCLK(7)

SMBDATA(7) DDC1DATA_TDI (3)

PETn0_GFXRn0(2)

PETp1_GFXRp1(2)
PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)

C0
10nFC010nF

PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

R10RR1
0R

TEST_EN_J
JTAG_TRST#

PRESENCE

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

+12V_BUS

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

+12V#B1
+12V#B2
+12V#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

x16 PCIe

x16 PCIe

Mechanical Key

Mechanical Key

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

JTAG2
JTAG3
JTAG4
JTAG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

PERp0
PERn0

GND#A18

RSVD#A19

GND#A20

PERp1

PERn1
GND#A23
GND#A24

PERp2

PERn2
GND#A27
GND#A28

PERp3

PERn3
GND#A31

RSVD#A32
RSVD#A33

GND#A34

PERp4

PERn4
GND#A37
GND#A38

PERp5

PERn5
GND#A41
GND#A42

PERp6

PERn6
GND#A45
GND#A46

PERp7

PERn7
GND#A49

RSVD#A50

GND#A51

PERp8

PERn8
GND#A54
GND#A55

PERp9

PERn9
GND#A58
GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

MPCIE1

MPCIE1

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

+3.3V_BUS+12V_BUS

PRESENCE

JTCK
JTDI
JTDO
JTMS

TEST_EN_J
JTAG_TRST#

C7
100nF_6.3VC7100nF_6.3V

C9
100nF_6.3VC9100nF_6.3V

C11

C11
100nF_6.3V

100nF_6.3V

C13

C13
100nF_6.3V

100nF_6.3V

C15

C15
100nF_6.3V

100nF_6.3V

C17

C17
100nF_6.3V

100nF_6.3V

C19

C19
100nF_6.3V

100nF_6.3V

C21

C21
100nF_6.3V

100nF_6.3V

C23

C23
100nF_6.3V

100nF_6.3V

C25

C25
100nF_6.3V

100nF_6.3V

C27

C27
100nF_6.3V

100nF_6.3V

C29

C29
100nF_6.3V

100nF_6.3V

C31

C31
100nF_6.3V

100nF_6.3V

C33

C33
100nF_6.3V

100nF_6.3V

C35

C35
100nF_6.3V

100nF_6.3V

C37

C37
100nF_6.3V

100nF_6.3V

PERST#

TP4TP4

TP3TP3

C8
100nF_6.3VC8100nF_6.3V

C10

C10
100nF_6.3V

100nF_6.3V

C12

C12
100nF_6.3V

100nF_6.3V

C14

C14
100nF_6.3V

100nF_6.3V

C16

C16
100nF_6.3V

100nF_6.3V

C18

C18
100nF_6.3V

100nF_6.3V

C20

C20
100nF_6.3V

100nF_6.3V

C22

C22
100nF_6.3V

100nF_6.3V

C24

C24
100nF_6.3V

100nF_6.3V

C26

C26
100nF_6.3V

100nF_6.3V

C28

C28
100nF_6.3V

100nF_6.3V

C30

C30
100nF_6.3V

100nF_6.3V

C32

C32
100nF_6.3V

100nF_6.3V

C34

C34
100nF_6.3V

100nF_6.3V

C36

C36
100nF_6.3V

100nF_6.3V

C38

C38
100nF_6.3V

100nF_6.3V

TP2TP2

TP1TP1

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)PETp0_GFXRp0(2)

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

No JTAG

R2 0RR2 0R
TDA08H0SB1R

TDA08H0SB1R

21345678

21345678

ON

ON

TSW1

TSW1

98
107
116
125
134
143
152
161

TP6TP6

TEST_EN_R (3)

HSYNC1_TRST (3)

VSYNC1_TCK (3)
GEN_D_HPD4_TDO (3,7)

DDC1CLK_TMS (3)

+3.3V

53

1
2

R_RST

R3 0RR3 0R

Table 1: Connection for JTAG

Production
(No JTAG)

Internal Use Only

TSW1 & R2 are located on the bottom side of the board close to PCIE connector.

Install R2 & Don't Install TSW1

Install TSW1 & Don't Install R2

TSW1 Switch #1, 2, 3, 4, 5 and 6 closed (ON)

JTAG

#8 open

TSW1 Switch #1, 2, 3, 4, 5 and 6 open

NO JTAG

#8 closed (ON)

C39

C39
100nF_6.3V

100nF_6.3V

NC7SZ08P5X_NL

NC7SZ08P5X_NL

4

U5

U5

Place R3 in U5

PERST#_buf (2)

SYMBOL LEGEND

DO NOT

DNI

INSTALL
ACTIVE

#

LOW
DIGITAL

GROUND
ANALOG

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - PCI-E Edge Connector

RV635 GDDR3 - PCI-E Edge Connector

8

7

6

5

4

3

RV635 GDDR3 - PCI-E Edge Connector

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

121

of

121

of

121

GROUND

BUO BRING UP

ONLY

Doc No.

Doc No.

Doc No.

105-B380xx-00

105-B380xx-00

105-B380xx-00

1

RevDate:

RevDate:

RevDate:

1

1

1

www.vinafix.vn

5

D D

NOTE: some of the PCIE testpoints will
be available trought via on traces.

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)

PETp1_GFXRp1(1)
PETn1_GFXRn1(1)

PETp2_GFXRp2(1)
PETn2_GFXRn2(1)

PETp3_GFXRp3(1)
PETn3_GFXRn3(1)

PETp4_GFXRp4(1)
PETn4_GFXRn4(1)

PETp5_GFXRp5(1)
PETn5_GFXRn5(1)

PETp6_GFXRp6(1)

C C

B B

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

PETn6_GFXRn6(1)

PETp7_GFXRp7(1)
PETn7_GFXRn7(1)

PETp8_GFXRp8(1)

PETp9_GFXRp9(1)
PETn9_GFXRn9(1)

PETp10_GFXRp10(1)
PETn10_GFXRn10(1)

PETp11_GFXRp11(1)
PETn11_GFXRn11(1)

PETp12_GFXRp12(1)
PETn12_GFXRn12(1)

PETp13_GFXRp13(1)
PETn13_GFXRn13(1)

PETp14_GFXRp14(1)
PETn14_GFXRn14(1)

PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

DNI DNI

R13

R13

R14

R14

51R

51R

51R

51R

402 402

TP11TP11

TP12TP12

TP13TP13

TP14TP14

TP19TP19

TP20TP20

TP21TP21

TP22TP22

TP27TP27

TP28TP28

4

U1A

TP7TP7

TP8TP8

TP9TP9

TP10TP10

TP15TP15

TP16TP16

TP17TP17

TP18TP18

TP23TP23

TP24TP24

TP25TP25

TP26TP26

U1A

AK33

PCIE_RX0P

AJ33

PCIE_RX0N

AJ35

PCIE_RX1P

AJ34

PCIE_RX1N

AH35

PCIE_RX2P

AH34

PCIE_RX2N

AG35

PCIE_RX3P

AG34

PCIE_RX3N

AF33

PCIE_RX4P

AE33

PCIE_RX4N

AE35

PCIE_RX5P

AE34

PCIE_RX5N

AD35

PCIE_RX6P

AD34

PCIE_RX6N

AC35

PCIE_RX7P

AC34

PCIE_RX7N

AB33

PCIE_RX8P

AA33

PCIE_RX8N

AA35

PCIE_RX9P

AA34

PCIE_RX9N

Y35

PCIE_RX10P

Y34

PCIE_RX10N

W35

PCIE_RX11P

W34

PCIE_RX11N

V33

PCIE_RX12P

U33

PCIE_RX12N

U35

PCIE_RX13P

U34

PCIE_RX13N

T35

PCIE_RX14P

T34

PCIE_RX14N

R35

PCIE_RX15P

R34

PCIE_RX15N

AJ31

PCIE_REFCLKP

AJ30

PCIE_REFCLKN

PERST#_buf(1)

AM32

PERSTB

Clock

Clock

PART 1 OF 7

PART 1 OF 7

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

Calibration

PCIE_CALRN
PCIE_CALRP

3

AG31
AG30

AF31
AF30

AF28
AF27

AD31
AD30

AD28
AD27

AB31
AB30

AB28
AB27

AA31
AA30

AA28
AA27

W31
W30

W28
W27

V31
V30

V28
V27

U31
U30

U28
U27

R31
R30

+PCIE_VDDC

402

AG26
AJ27

R9

1.27KR91.27K

R82.0K R82.0K

402

2

GFXTp0_PERp0 (1)
GFXTn0_PERn0 (1)

GFXTp1_PERp1 (1)
GFXTn1_PERn1 (1)

GFXTp2_PERp2 (1)
GFXTn2_PERn2 (1)

GFXTp3_PERp3 (1)
GFXTn3_PERn3 (1)

GFXTp4_PERp4 (1)
GFXTn4_PERn4 (1)

GFXTp5_PERp5 (1)
GFXTn5_PERn5 (1)

GFXTp6_PERp6 (1)
GFXTn6_PERn6 (1)

GFXTp7_PERp7 (1)
GFXTn7_PERn7 (1)

GFXTp8_PERp8 (1)
GFXTn8_PERn8 (1)PETn8_GFXRn8(1)

GFXTp9_PERp9 (1)
GFXTn9_PERn9 (1)

GFXTp10_PERp10 (1)
GFXTn10_PERn10 (1)

GFXTp11_PERp11 (1)
GFXTn11_PERn11 (1)

GFXTp12_PERp12 (1)
GFXTn12_PERn12 (1)

GFXTp13_PERp13 (1)
GFXTn13_PERn13 (1)

GFXTp14_PERp14 (1)
GFXTn14_PERn14 (1)

GFXTp15_PERp15 (1)
GFXTn15_PERn15 (1)

1

For Tektronix LA only

Place close
to ASIC

A A

5

4

RV635 XT A11

RV635 XT A11

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - ASIC PCIE_Interface

RV635 GDDR3 - ASIC PCIE_Interface

3

2

RV635 GDDR3 - ASIC PCIE_Interface

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

221

of

221

of

221

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

5

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 0402, 6.3V
100nF, X7R, 0402
10nF , X7R, 0402

Overlap footprints

4.7uF_6.3V

4.7uF_6.3V

R1090RR109
0R

TR11 0RTR11 0R

TR12 0RTR12 0R

R71KR7
1K

DNI

OUT

E/D

Place close to ASIC

R106 100RR106 100R

R100 100RR100 100R

R101 100RR101 100R

R102 100RR102 100R

R103 100RR103 100R

R104 100RR104 100R

R105 100RR105 100R

MC100

MC100

4.7uF_6.3V

4.7uF_6.3V

GND_T2PVSS

C103

C103

MC103

MC103

10uF_X6S

10uF_X6S

+LTVDD33

+3.3V

R40

R40

R41

R41

4.7K

4.7K

4.7K

4.7K

402 402

DNI

DNI for RV635

DNI

MR71KMR7
1K

3
1

R841MR84
1M

Place R_RTCLK close to XTAL so the
main clock line has shortest stub

D D

+1.8V

B889

B889
BLM15BD121SN1

BLM15BD121SN1

C C

LVT_EN(13)

+1.8V

+3.3V

+T2PVDD

Q100

Q100

SI2304DS

SI2304DS

1

1

SI2304DS

SI2304DS

Q101

Q101

32

32

T2XCM(15)
T2XCP(15)

T2X0M(15)

T2X0P(15)

T2X1M(15)

T2X1P(15)

T2X2M(15)

T2X2P(15)

T2X3M(15)

T2X3P(15)

T2X4M(15)

T2X4P(15)

T2X5M(15)

T2X5P(15)

NS100

NS100
NS_VIA

NS_VIA

1 2

Use 0R

B100

B100

BLM15BD121SN1

BLM15BD121SN1

DNI for RV630

B101

B101

BLM15BD121SN1

BLM15BD121SN1

Use 0R

DNI for RV635

+3.3V

GEN_D_HPD4_TDO(1,7)

XTALOUT_S
is done for
ease of layout

XTALOUT_S

DDC2DATA(13,18)

DDC2CLK(13,18)

CRT2DDCDATA(16)
CRT2DDCCLK(16)

DDC1CLK_TMS(1)

What happens to all the JTAG resistors especially R7 and also the TRs?

Y81

Y81

4

VCC

2

GND

27.000MHz

27.000MHz

XTALIN_S

XTALOUT_S

5

TR41

TR41

TR40

TR40

4.7K

4.7K

4.7K

4.7K

BUO

402 402

TEST_EN_R(1)

1uF_6.3V

1uF_6.3V

C82

C82
12pF_50V

12pF_50V

C83

C83
12pF_50V

12pF_50V

ADDRESS
x100 1100
TBD

C81

C81

2 1

BUO

C80

C80
100nF_6.3V

100nF_6.3V

Y82

Y82

27.000MHz_10PPM

27.000MHz_10PPM

TP40TP40
TP41TP41

I2C DEVICE ADDRESS' ON DDC2

B B

DEVICE
LM63
DP

+3.3V_BUS

B80

B80
BLM15BD121SN1

BLM15BD121SN1

A A

DNI for RV635 DNI for RV635

C101

C101

C100

C100

100nF_6.3V

100nF_6.3V

10uF_X6S

10uF_X6S

+LTVDD18

C108

C108

C109

1uF_6.3V

1uF_6.3V

C109

100nF_6.3V

100nF_6.3V

DNI for RV630

C105

C105
100nF_6.3V

C46

C46
100nF_6.3V

100nF_6.3V

100nF_6.3V

TR13 0RTR13 0R

GPU_DMINUS(18)
GPU_DPLUS(18)

TS_FDO(18)

TP42

TP42
35mil

35mil

PLL_TEST
TEST_EN

C107

C107

1uF_6.3V

1uF_6.3V

DDC1DATA_TDI(1)

DDC2DATA
DDC2CLK

+1.8V

NR81 182RNR81 182R
R81 182RR81 182R

Share one pad

OSC_EN

R85 0RR85 0R

R_RTCLK

MR86 0RMR86 0R

CRT1DDCDATA(15)

CRT1DDCCLK(15)

R43 221RR43 221R
R44 110RR44 110R

HPD1(16)

SDA(7)

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

C102

C102
1uF_6.3V

1uF_6.3V

DNI

SCL(7)

VREFG

XTALIN
XTALOUT

R82

R82
221R

221R

4

AP22
AR22

AN22
AN23

AR23
AP23

AR24
AP24

AR25
AP25

AN26
AN27

AR27
AP27

AL22

AK22

AK27

AL27

AJ26

AH26

AJ22
AN21
AN24
AN25
AN28
AP21
AP26
AR21
AR26

AJ24
AM22
AM24
AM26
AM27

AM29

AL29

AJ15
AH15

AJ5
AJ4

AH14
AG14

AG6

AK6
AM6

AK4
AM4

AG21

AH19
AM30

AD12

AR33
AP33

MR82

MR82
221R

221R

Share one pad

OSC_EN (13,14)

4

U1B

U1B

Integrated

Integrated
LVTM/TMDS2

LVTM/TMDS2

T2XCM
T2XCP

T2X0M
T2X0P

T2X1M
T2X1P

T2X2M
T2X2P

T2X3M
T2X3P

T2X4M
T2X4P

T2X5M
T2X5P

T2PVDD
T2PVSS

T2XVDDC_1
T2XVDDC_2

T2XVDDR_1
T2XVDDR_2

T2XVSSR_1
T2XVSSR_2
T2XVSSR_3
T2XVSSR_4
T2XVSSR_5
T2XVSSR_6
T2XVSSR_7
T2XVSSR_8
T2XVSSR_9
T2XVSSR_10
T2XVSSR_11
T2XVSSR_12
T2XVSSR_13
T2XVSSR_14

Monitor

Monitor

DDC1DATA

Interface

Interface

DDC1CLK
DDC2DATA

DDC2CLK
DDC3DATA_DP3_AUXN

DDC3CLK_DP3_AUXP
DDC4DATA_DP4_AUXN

DDC4CLK_DP4_AUXP
HPD1

SDA

MMI2C

MMI2C

SCL

DMINUS

Thermal

Thermal

DPLUS

Diode

Diode

TS_FDO

PLLTEST

Test

Test

TESTEN

VREFG

XTALIN
XTALOUT

RV635 XT A11

RV635 XT A11

PART 2 OF 7

PART 2 OF 7

V

V
I

I
D

D
E

E
O

O

&

&

M

M
U

U
L

L
T

T
I

I
M

M
E

E
D

D
I

I
A

A

Integrated

Integrated
DP/TMDS

DP/TMDS

TXCAM_DPA3N

TXCAP_DPA3P

TX0M_DPA2N

TX0P_DPA2P

TX1M_DPA1N

TX1P_DPA1P

TX2M_DPA0N

TX2P_DPA0P

TXCBM_DPB3N

TXCBP_DPB3P

TX3M_DPB2N

TX3P_DPB2P

TX4M_DPB1N

TX4P_DPB1P

TX5M_DPB0N

TX5P_DPB0P

DPA_PVDD
DPA_PVSS

DPB_PVDD
DPB_PVSS

DPA_VDDR_1
DPA_VDDR_2

DPA_VSSR_1
DPA_VSSR_2
DPA_VSSR_3
DPA_VSSR_4
DPA_VSSR_5

DPB_VDDR_1
DPB_VDDR_2

DPB_VSSR_1
DPB_VSSR_2
DPB_VSSR_3
DPB_VSSR_4
DPB_VSSR_5

DAC / CRT

DAC / CRT

DAC2 (TV/CRT2)

DAC2 (TV/CRT2)

DP_CALR

HSYNC
VSYNC

RSET
AVDD

AVSSQ

VDD1DI

VSS1DI

H2SYNC
V2SYNC

COMP

R2SET

A2VDDQ

A2VSSQ

VDD2DI

VSS2DI

A2VDD

R116 182RR116 182R
AN9
AN10

R110 182RR110 182R
AR10
AP10

R111 182RR111 182R
AR11
AP11

R112 182RR112 182R
AR12
AP12

AR14
AP14

R113 182RR113 182R
AR15
AP15

R114 182RR114 182R
AR16
AP16

R115 182RR115 182R
AR17
AP17

DP_CALR

AG15
AM14

AL14
AH17

AG17
AP19

AR19
AN11

AN12
AN13
AN14
AN15

AN19
AN20

AN16
AN17
AN18
AR18
AP18

AR31

R

AP31

RB

AR30

G

AP30

GB

AR29

B

AP29

BB

AN29
AN30

AN31
AR32
AP32

AR28
AP28

AM19

R2

AL19

R2B

AM18

G2

AL18

G2B

AM17

B2

AL17

B2B

AM15
AL15

AK18

Y

AK19

C

AK17

R2SET GND_A2VSSQ

AJ21

AL21
AK21

AH22
AG22

AM21

C2030

C2030
10nF

10nF

3

Place close to ASIC Place close to Connector

DPA_TX0P
DPA_TX0N

DPA_TX1P
DPA_TX1N

DPA_TX2P
DPA_TX2N

DPA_TX3P
DPA_TX3N

DPB_TX1P
DPB_TX1N

DPB_TX2P
DPB_TX2N

DPB_TX3P
DPB_TX3N

R128 150RR128 150R

C1120 100nF_6.3VC1120 100nF_6.3V

C1121 100nF_6.3VC1121 100nF_6.3V

C1122 100nF_6.3VC1122 100nF_6.3V

C1123 100nF_6.3VC1123 100nF_6.3V

C1124 100nF_6.3VC1124 100nF_6.3V

C1125 100nF_6.3VC1125 100nF_6.3V

C1126 100nF_6.3VC1126 100nF_6.3V

C1127 100nF_6.3VC1127 100nF_6.3V

C1132 100nF_6.3VC1132 100nF_6.3V

C1133 100nF_6.3VC1133 100nF_6.3V

C1134 100nF_6.3VC1134 100nF_6.3V

C1135 100nF_6.3VC1135 100nF_6.3V

C1136 100nF_6.3VC1136 100nF_6.3V

C1137 100nF_6.3VC1137 100nF_6.3V

Overlap footprints

C110

C110
10nF

10nF

C111

C111
100nF

100nF

C112

C112
1uF_6.3V

1uF_6.3V

C113

C113
10uF_X6S

10uF_X6S

MC113

MC113

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

C114

C114
10nF

10nF

R1030 499RR1030 499R

C1023

C1023
10nF

10nF

R2030 715RR2030 715R

C2021

C2021
100nF_6.3V

100nF_6.3V

C2024

C2024
10nF

10nF

C2031

C2031
100nF_6.3V

100nF_6.3V

C115

C115
100nF

100nF

GND_AVSSQRSET

C2025

C2025
100nF_6.3V

100nF_6.3V

C2032

C2032
1uF_6.3V

1uF_6.3V

C1024

C1024
100nF_6.3V

100nF_6.3V

C2022

C2022
1uF_6.3V

1uF_6.3V

+VDD2DI

C2026

C2026
1uF_6.3V

1uF_6.3V

GND_VSS2DI

C116

C116
1uF_6.3V

1uF_6.3V

C1025

C1025
1uF_6.3V

1uF_6.3V

NS2021 NS_VIANS2021 NS_VIA

C1020

C1020
10nF

10nF

C117

C117
10uF_X6S

10uF_X6S

+VDD1DI

C2033

C2033
10uF_X6S

10uF_X6S

MC117

MC117

4.7uF_6.3V

4.7uF_6.3V

C1021

C1021
100nF_6.3V

100nF_6.3V

NS1021 NS_VIANS1021 NS_VIA

GND_VSS1DI

+A2VDDQ

NS2020 NS_VIANS2020 NS_VIA

12

MC2033

MC2033

4.7uF_6.3V

4.7uF_6.3V

C1022

C1022
1uF_6.3V

1uF_6.3V

12

GND_A2VSSQ

Overlap footprints

3

12

+A2VDD

+DPAB_PVDD

NS110

NS110
NS_VIA

NS_VIA

GND_TPVSS

+DPAB_VDDR

A_DAC1_R (15)
A_DAC1_RB (15)

A_DAC1_G (15)
A_DAC1_GB (15)

A_DAC1_B (15)
A_DAC1_BB (15)

+AVDD

NS1020 NS_VIANS1020 NS_VIA

GND_AVSSQ

A_DAC2_R (16)
A_DAC2_RB (16)

A_DAC2_G (16)
A_DAC2_GB (16)

A_DAC2_B (16)
A_DAC2_BB (16)

HSYNC_DAC2 (7,16)
VSYNC_DAC2 (7,16)

A_DAC2_Y (17)
A_DAC2_C (17)
A_DAC2_COMP (17)

B2030 26R_600mAB2030 26R_600mA

2

12

12

2

R120 499RR120 499R

R122 499RR122 499R

R124 499RR124 499R

R126 499RR126 499R

R132 499RR132 499R

R134 499RR134 499R

R136 499RR136 499R

+1.8V

B887

B887
BLM15BD121SN1

BLM15BD121SN1

+1.8V +1.1V

RV630 RV635

B888

B888
BLM15BD121SN1

BLM15BD121SN1

+1.8V

+1.8V

+1.8V

+3.3V

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

B881

B881
BLM15BD121SN1

BLM15BD121SN1

DNI

TR14 0RTR14 0R

HSYNC_DAC1 (7,15)

DNI

TR10 0RTR10 0R

B884

B884
BLM15BD121SN1

BLM15BD121SN1

B883

B883
BLM15BD121SN1

BLM15BD121SN1

B885

B885
BLM15BD121SN1

BLM15BD121SN1

RV635 GDDR3 - ASIC MAIN

RV635 GDDR3 - ASIC MAIN

RV635 GDDR3 - ASIC MAIN

VSYNC_DAC1 (7,15)
VSYNC1_TCK (1)

R121 499RR121 499R

R123 499RR123 499R

R125 499RR125 499R

R127 499RR127 499R

R133 499RR133 499R

R135 499RR135 499R

R137 499RR137 499R

LVT_EN(13)

HSYNC1_TRST (1)

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

321

321

321

DP_GND

of

of

of

1

1

+1.8V

B882

B882
BLM15BD121SN1

BLM15BD121SN1

1

32

Doc No.

Doc No.

Doc No.

T1XCM (16)
T1XCP (16)

T1X0M (16)
T1X0P (16)

T1X1M (16)
T1X1P (16)

T1X2M (16)
T1X2P (16)

T1X3M (16)
T1X3P (16)

T1X4M (16)
T1X4P (16)

T1X5M (16)
T1X5P (16)

Q110

Q110
SI2304DS

SI2304DS

105-B380xx-00

105-B380xx-00

105-B380xx-00

RevDate:

RevDate:

RevDate:

1

1

1

www.vinafix.vn

C151

C151
1uF_6.3V

1uF_6.3V

C131

C131
100nF_6.3V

100nF_6.3V

C141

C141
1uF_6.3V

1uF_6.3V

5

C152

C152
1uF_6.3V

1uF_6.3V

C132

C132
100nF_6.3V

100nF_6.3V

C142

C142
1uF_6.3V

1uF_6.3V

C133

C133
100nF_6.3V

100nF_6.3V

C143

C143
1uF_6.3V

1uF_6.3V

C154

C154
1uF_6.3V

1uF_6.3V

C134

C134
100nF_6.3V

100nF_6.3V

C144

C144
1uF_6.3V

1uF_6.3V

C155

C155
1uF_6.3V

1uF_6.3V

C135

C135
100nF_6.3V

100nF_6.3V

C145

C145
1uF_6.3V

1uF_6.3V

C136

C136
100nF_6.3V

100nF_6.3V

C146

C146
1uF_6.3V

1uF_6.3V

C157

C157
1uF_6.3V

1uF_6.3V

C137

C137
100nF_6.3V

100nF_6.3V

C147

C147
1uF_6.3V

1uF_6.3V

C158

C158
1uF_6.3V

1uF_6.3V

C138

C138
100nF_6.3V

100nF_6.3V

C148

C148
1uF_6.3V

1uF_6.3V

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 0402, 6.3V
100nF, X7R, 0402
10nF , X7R, 0402

+MVDD

C150

C150
1uF_6.3V

1uF_6.3V

D D

C156

C156
100nF_6.3V

100nF_6.3V

C153

C153
1uF_6.3V

1uF_6.3V

C130

C130
100nF_6.3V

100nF_6.3V

C140

C140
1uF_6.3V

1uF_6.3V

Overlap cap pair foorprints (0805 with 0603)

C127

C124

C124

C125

C125

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

MC125

MC125

MC124

MC124

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

+MVDD

B120

B120

BLM15BD121SN1

BLM15BD121SN1

B121

B121

BLM15BD121SN1

C C

B B

A A

BLM15BD121SN1

NS121 NS_VIANS121 NS_VIA

1 2

GND_VSSRHA_2

B122

B122

BLM15BD121SN1

BLM15BD121SN1

B123

B123

BLM15BD121SN1

BLM15BD121SN1

+1.8V

B886

B886
BLM15BD121SN1

BLM15BD121SN1

NS70 NS_VIANS70 NS_VIA

GND_PVSS

C121

C121
1uF_6.3V

1uF_6.3V

+1.8V

1 2

C127

C126

C126

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

MC126

MC126

MC127

MC127

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

C120

C120

1uF_6.3V

1uF_6.3V

NS120 NS_VIANS120 NS_VIA

1 2
GND_VSSRHA_1

+3.3V

C90

C90
1uF_6.3V

1uF_6.3V

Overlap footprints

MC94

MC94

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

MC70

MC70

4.7uF_6.3V

4.7uF_6.3V

C128

C128
10uF_X6S

10uF_X6S

MC128

MC128

4.7uF_6.3V

4.7uF_6.3V

NS122 NS_VIANS122 NS_VIA

C91

C91
100nF_6.3V

100nF_6.3V

C94

C94
10uF_X6S

10uF_X6S

C70

C70
10uF_X6S

10uF_X6S

C122

C122
1uF_6.3V

1uF_6.3V

1 2

GND_VSSRHB_1

NS123 NS_VIANS123 NS_VIA

GND_VSSRHB_2

C92

C92
1uF_6.3V

1uF_6.3V

C95

C95
1uF_6.3V

1uF_6.3V

+DPLL_PVDD

C129

C129
10uF_X6S

10uF_X6S

MC129

MC129

4.7uF_6.3V

4.7uF_6.3V

1 2

C71

C71
100nF_6.3V

100nF_6.3V

C93

C93
100nF_6.3V

100nF_6.3V

C97

C97
100nF_6.3V

100nF_6.3V

C72

C72
1uF_6.3V

1uF_6.3V

C123

C123
1uF_6.3V

1uF_6.3V

C96

C96
1uF_6.3V

1uF_6.3V

C159

C159
1uF_6.3V

1uF_6.3V

+DPLL_PVDD

GND_PVSS

4

C98

C98
100nF_6.3V

100nF_6.3V

AE14
AE15
AE17
AF12

AR20

AP20

AR35

H35

L22

M10
M35

P10

A12
A16
A20
A24
A28

B35

D35

K10
K12
K24
K26
L14
L15
L17
L18
L19
L21

A25
A32

B25
B32

AP2
AR2

AN1
AP1

A35

AR1

U1E

U1E

A8

M1

T1
Y1

B1
D1
H1

B2
L1

C2
L2

RV635 XT A11

RV635 XT A11

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29

VDDRHA_1
VDDRHA_2

VDDRHB_1
VDDRHB_2

VSSRHA_1
VSSRHA_2

VSSRHB_1
VSSRHB_2

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

VDDR4_1
VDDR4_2

VDDR5_1
VDDR5_2

DPLL_PVDD

DPLL_PVSS

MECH_1
MECH_2
MECH_3

PART 5 OF 7

PART 5 OF 7

Memory I/O

Memory I/O

Selected PLL's

Selected PLL's

Mechanical Pins

Mechanical Pins

3

+MPVDD

GND_MPVSS

+DPLL_VDDC

+PCIE_PVDD

C930

C930
10nF

10nF

C900

C900
10nF

10nF

C161

C161
1uF_6.3V

1uF_6.3V

C171

C171
1uF_6.3V

1uF_6.3V

C160

C160
1uF_6.3V

1uF_6.3V

Overlap cap pair foorprints (0805 with 0603)

+VDDC

C78

C78
100nF_6.3V

100nF_6.3V

C65

C65

C64

C64

100nF_6.3V

100nF_6.3V

10nF

10nF

GND_PVSS

AM35

PCIE_PVDD

R26

PCIE_VDDC_1

W25

PCIE_VDDC_2

W26

PCIE_VDDC_3

AA25

PCIE_VDDC_4

AA26

PCIE_VDDC_5

AB25

PCIE_VDDC_6

AB26

PCIE_VDDC_7

AD26

PCIE_VDDC_8

AF26

PCIE_VDDC_9

U26

PCIE_VDDC_10

V25

PCIE_VDDC_11

V26

PCIE_VDDC_12

AL33

PCIE_VDDR_1

AM33

PCIE_VDDR_2

AN33

PCIE_VDDR_3

AN34

PCIE_VDDR_4

AN35

PCIE_VDDR_5

AP34

PCIE_VDDR_6

AP35

PCIE_VDDR_7

AR34

P

P
O

O
W

W
E

E
R

R

PCIE_VDDR_8

N13

Core PCI-Express

Core PCI-Express

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42
VDDC_43
VDDC_44

BBP_1
BBP_2

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4
VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

MPVDD

MPVSS

DPLL_VDDC

R18
W11
AB19
AC23
AE18
AE19
AE21
AE22
N15
N18
N21
N23
P14
P17
P19
P22
R13
R15
R21
R23
U14
U17
U19
U22
V15
V18
V21
V23
W14
W17
W19
W22
AA15
AA18
AA21
AA23
AB14
AB17
AB22
AC13
AC15
AC18
AC21

U13
V13

M12
M24
P11
P25

R11
R25
U11
U25
AA11
AB11
AD10
AF10

A14

B15

AG19

C931

C931
100nF_6.3V

100nF_6.3V

C162

C162
1uF_6.3V

1uF_6.3V

C172

C172
1uF_6.3V

1uF_6.3V

C184

C184
1uF_6.3V

1uF_6.3V

C181

C181
10uF_X6S

10uF_X6S

MC181

MC181

4.7uF_6.3V

4.7uF_6.3V

C68

C68
100nF_6.3V

100nF_6.3V

1uF_6.3V

1uF_6.3V

C61

C61
100nF_6.3V

100nF_6.3V

Overlap footprints

C932

C932
1uF_6.3V

1uF_6.3V

C920

C920
1uF_6.3V

1uF_6.3V

C901

C901
100nF_6.3V

100nF_6.3V

C163

C163
1uF_6.3V

1uF_6.3V

C173

C173
1uF_6.3V

1uF_6.3V

C69

C69
100nF_6.3V

100nF_6.3V

+MPVDD

C66

C66

C62

C62
1uF_6.3V

1uF_6.3V

C933

C933
10uF_X6S

10uF_X6S

C921

C921
1uF_6.3V

1uF_6.3V

C902

C902
1uF_6.3V

1uF_6.3V

C164

C164
1uF_6.3V

1uF_6.3V

C174

C174
1uF_6.3V

1uF_6.3V

C185

C185
1uF_6.3V

1uF_6.3V

C182

C182
10uF_X6S

10uF_X6S

MC182

MC182

4.7uF_6.3V

4.7uF_6.3V

+VDD_CT

BLM15BD121SN1

BLM15BD121SN1

Overlap footprints

C67

C67

10uF_X6S

10uF_X6S

Overlap footprints

C63

C63
10uF_X6S

10uF_X6S

C922

C922
1uF_6.3V

1uF_6.3V

C903

C903
10nF

10nF

C165

C165
1uF_6.3V

1uF_6.3V

C175

C175
1uF_6.3V

1uF_6.3V

C186

C186
1uF_6.3V

1uF_6.3V

B69

B69

MC933

MC933

4.7uF_6.3V

4.7uF_6.3V

C183

C183
10uF_X6S

10uF_X6S

MC183

MC183

4.7uF_6.3V

4.7uF_6.3V

2

B930

B930

BLM15BD121SN1

BLM15BD121SN1

NS18 NS_VIANS18 NS_VIA

GND_PCIE_PVSS

C923

C923
1uF_6.3V

1uF_6.3V

C904

C904
100nF_6.3V

100nF_6.3V

C166

C166
1uF_6.3V

1uF_6.3V

C176

C176
1uF_6.3V

1uF_6.3V

C944

C944
1uF_6.3V

1uF_6.3V

+1.8V

MC67

MC67

4.7uF_6.3V

4.7uF_6.3V

MC63

MC63

4.7uF_6.3V

4.7uF_6.3V

+PCIE_VDDC

C924

C924
1uF_6.3V

1uF_6.3V

C905

C905
1uF_6.3V

1uF_6.3V

C167

C167
1uF_6.3V

1uF_6.3V

C177

C177
1uF_6.3V

1uF_6.3V

C187

C187
10uF_X6S

10uF_X6S

MC187

MC187

4.7uF_6.3V

4.7uF_6.3V

NS64NS_VIA NS64NS_VIA

GND_MPVSS

+1.8V

12

C925

C925
1uF_6.3V

1uF_6.3V

C906

C906
1uF_6.3V

1uF_6.3V

C168

C168
1uF_6.3V

1uF_6.3V

C178

C178
1uF_6.3V

1uF_6.3V

C945

C945

C946

C946

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C188

C188
10uF_X6S

10uF_X6S

MC188

MC188

4.7uF_6.3V

4.7uF_6.3V

C74

C74
100nF_6.3V

100nF_6.3V

C73

C73
100nF_6.3V

100nF_6.3V

B67 60R_700mAB67 60R_700mA

12

+DPLL_VDDC

Overlap footprints

C926

C926
10uF_X6S

10uF_X6S

C907

C907
1uF_6.3V

1uF_6.3V

C170

C170

C169

C169

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C180

C180

C179

C179

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C947

C947
1uF_6.3V

1uF_6.3V

C189

C189
10uF_X6S

10uF_X6S

MC189

MC189

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

C77

C77

C75

C75

10uF_X6S

10uF_X6S

1uF_6.3V

1uF_6.3V

+VDDCI_2

C76

C76
1uF_6.3V

1uF_6.3V

+VDDC

Install only one of these two

MC926

MC926

4.7uF_6.3V

4.7uF_6.3V

+PCIE_VDDR

C941

C941

C942

C942

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C948

C948
1uF_6.3V

1uF_6.3V

MC77

MC77

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

C79

C79
10uF_X6S

10uF_X6S

B60

B60
BLM15BD121SN1

BLM15BD121SN1

MB60

MB60
BLM15BD121SN1

BLM15BD121SN1

B921 220R_2AB921 220R_2A
Share one pad

Install only one of these two

+1.8V

R9000RR900
0R

+VDDC

C943

C943
1uF_6.3V

1uF_6.3V

+VDDCI_1

MC79

MC79

4.7uF_6.3V

4.7uF_6.3V

R922

R922

1.5R

1.5R

1

R921

R921

0.1R

0.1R

R9200RR920
0R

B77 220R_2AB77 220R_2A

B78 220R_2AB78 220R_2A

+1.1V

+VDDC

+VDDC

+1.1V

+VDDC

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - ASIC Power

RV635 GDDR3 - ASIC Power

5

4

3

2

RV635 GDDR3 - ASIC Power

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

421

of

421

of

421

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

5

4

3

2

1

+MVDD

+MVDD

R291

R291

40.2R

40.2R

402
1%

R292

R292
100R

100R

402
1%

R293

R293

40.2R

40.2R

402
1%

R294

R294
100R

100R

402
1%

DQA_[63..0](8,9)

MVREFS_0

U1C

U1C

DQA_0

P27

C296

C296
10nF

10nF

P28
P31

P32
M27
K29
K31
K32
M33
M34

L34

L35

J33

J34
H33
H34
K27

J29

J30

J31
F29
F32
D30
D32
G33
G34
G35
F34
D34
C34
C35
B34
C24
B24
B23
A23
C21
B21
C20
B20

J22
H22
F22
D21

J19
G19
F19
D19
C19
B19
A19
B18
C16
B16
C15
A15
H18
F18
E18
D18

J17
G15
E15
D15

N35
N34

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFDA
MVREFSA

RV635 XT A11

RV635 XT A11

DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

C298

C298

C299

C299

10nF

10nF

100nF_6.3V

100nF_6.3V

MVREFD_0 MVREFD_1

C297

C297
100nF_6.3V

100nF_6.3V

Part 3 of 7

Part 3 of 7

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11

MAA_A12
MAA_BA0
MAA_BA1
MAA_BA2

DQMAB_0
DQMAB_1
DQMAB_2
DQMAB_3
DQMAB_4
DQMAB_5
DQMAB_6

MEMORY INTERFACE A

MEMORY INTERFACE A

DQMAB_7

DDR1 DDR2 DDR3

DDR1 DDR2 DDR3

Not used

Not used

bidir. strobe

bidir. strobe

bidir. differential strobe

bidir. differential strobe

For DDR2

For DDR2

write strobe

write strobe

read strobe

read strobe

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

ODTA0

ODTA1

CLKA0

CLKA0B

CKEA0
RASA0B
CASA0B

WEA0B

CSA0B_0
CSA0B_1

CLKA1

CLKA1B

CKEA1
RASA1B
CASA1B

WEA1B

CSA1B_0
CSA1B_1

MAA_0

C27

MAA_1

B28

MAA_2

B27

MAA_3

G26

MAA_4

F27

MAA_5

E27

MAA_6

D27

MAA_7

J27

MAA_8

E29

MAA_9

C30

MAA_10

E26

MAA_11

A27
G27

MAA_BA0

C28

MAA_BA1

B29

MAA_BA2

D26

DQMAb_0

M29

DQMAb_1

K33

DQMAb_2

G30

DQMAb_3

E33

DQMAb_4

C22

DQMAb_5

H21

DQMAb_6

C17

DQMAb_7

G17

QSA_0

M30

QSA_1

K34

QSA_2

G31

QSA_3

E34

QSA_4

B22

QSA_5

F21

QSA_6

B17

QSA_7

D17

QSAb_0

M31

QSAb_1

K35

QSAb_2

G32

QSAb_3

E35

QSAb_4

A22

QSAb_5

E21

QSAb_6

A17

QSAb_7

E17
C31

C25

A33

CLKA0 (8,9)

B33

CLKA0b (8,9)

B31

CKEA0 (8,9)

A31

RASA0b (8,9)

C32

CASA0b (8,9)

C29

WEA0b (8,9)

A30

CSA0b_0 (8)

B30

CSA0b_1 (9)

A26

CLKA1 (8,9)

B26

CLKA1b (8,9)

F24

CKEA1 (8,9)

D24

RASA1b (8,9)

H26

CASA1b (8,9)

D22

WEA1b (8,9)

G24

CSA1b_0 (8)

H24

CSA1b_1 (9)

MAA_[11..0] (8,9)

MAA_BA[2..0] (8,9)

DQMAb_[7..0] (8,9)

QSA_[7..0] (8,9)

QSAb_[7..0] (8,9)

+MVDD

+MVDD

R391

R391

40.2R

40.2R

402
1%

R392

R392
100R

100R

402
1%

R393

R393

40.2R

40.2R

402
1%

R394

R394
100R

100R

402
1%

C399

C399
100nF_6.3V

100nF_6.3V

C397

C397
100nF_6.3V

100nF_6.3V

C398

C398
10nF

10nF

C396

C396
10nF

10nF

DRAM_RST(8,9)

MVREFS_1

DQB_[63..0](8,9)

+MVDD

R295

R295

2.0K

2.0K

DNI

MR295

MR295

2.0K

2.0K

R296

R296

4.7K

4.7K

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

R297

R297

4.7K

4.7K

R298

R298
243R

243R

H15
G14
E14
D14
H12
G12
F12
D10
B13
C12
B12
B11

C9

B9
A9
B8

J10
H10
F10

D9

G7

G6

F6
D6
C8
C7

B7

A7

B5

A5
C4

B4
M3
M2
N2
N1
R3
R2

T3

T2
M8
M7

P5

P4
R9
R8
R6
U4
U3
U2
U1

V2

Y3

Y2

AA2
AA1

U9
U7
U6

V4
W9
W7
W6
W4

B14
A13

AA4
AA8
AA7
AA5

U1D

U1D

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MVREFDB
MVREFSB

DRAM_RST
TEST_MCLK
TEST_YCLK
MEMTEST

RV635 XT A11

RV635 XT A11

Part 4 of 7

Part 4 of 7

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11

MAB_A12
MAB_BA0
MAB_BA1
MAB_BA2

DQMBB_0
DQMBB_1
DQMBB_2
DQMBB_3
DQMBB_4
DQMBB_5
DQMBB_6

MEMORY INTERFACE B

MEMORY INTERFACE B

DQMBB_7

DDR1 DDR2 DDR3

DDR1 DDR2 DDR3

Not used

Not used

bidir. strobe

bidir. strobe

bidir. differential strobe

bidir. differential strobe

For DDR2

For DDR2

write strobe

write strobe

read strobe

read strobe

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

ODTB0
ODTB1

CLKB0
CLKB0B

CKEB0
RASB0B
CASB0B

WEB0B

CSB0B_0
CSB0B_1

CLKB1
CLKB1B

CKEB1
RASB1B
CASB1B

WEB1B

CSB1B_0
CSB1B_1

MAB_0

MAB_[11..0] (8,9)

H2

MAB_1

H3

MAB_2

J3

MAB_3

J5

MAB_4

J4

MAB_5

J6

MAB_6

G5

MAB_7

J9

MAB_8

F3

MAB_9

F4

MAB_10

J1

MAB_11

J2
J7

MAB_BA0

G2

MAB_BA1

G3

MAB_BA2

F1

DQMBb_0

D12

DQMBb_1

C10

DQMBb_2

E7

DQMBb_3

C6

DQMBb_4

P3

DQMBb_5

R4

DQMBb_6

W3

DQMBb_7

V8

QSB_0

J14

QSB_1

B10

QSB_2

F9

QSB_3

B6

QSB_4

P2

QSB_5

P8

QSB_6

W2

QSB_7

V6

QSBb_0

H14

QSBb_1

A10

QSBb_2

E9

QSBb_3

A6

QSBb_4

P1

QSBb_5

P7

QSBb_6

W1

QSBb_7

V5
D2

K5

A3

CLKB0 (8,9)

B3

CLKB0b (8,9)

E3

CKEB0 (8,9)

D3

RASB0b (8,9)

C1

CASB0b (8,9)

F2

WEB0b (8,9)

E1

CSB0b_0 (8,9)

E2

CSB0b_1 (9)

K1

CLKB1 (8,9)

K2

CLKB1b (8,9)

K8

CKEB1 (8,9)

K7

RASB1b (8,9)

K4

CASB1b (8,9)

M6

WEB1b (8,9)

L3

CSB1b_0 (8,9)

M4

CSB1b_1 (9)

MAB_BA[2..0] (8,9)

DQMBb_[7..0] (8,9)

QSB_[7..0] (8,9)

QSBb_[7..0] (8,9)

D D

C C

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - ASIC Memory Interface (Channel A & B)

RV635 GDDR3 - ASIC Memory Interface (Channel A & B)

5

4

3

2

RV635 GDDR3 - ASIC Memory Interface (Channel A & B)

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

521

of

521

of

521

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

5

D D

C C

B B

A A

5

4

U1F

U1F

P33

PCIE_VSS_1

V29

PCIE_VSS_2

AB32

PCIE_VSS_3

AG29

PCIE_VSS_4

AJ29

PCIE_VSS_5

AJ32

PCIE_VSS_6

AK32

PCIE_VSS_7

AL34

PCIE_VSS_8

AL35

PCIE_VSS_9

P34

PCIE_VSS_10

P35

PCIE_VSS_11

R27

PCIE_VSS_12

R28

PCIE_VSS_13

R29

PCIE_VSS_14

R32

PCIE_VSS_15

R33

PCIE_VSS_16

T33

PCIE_VSS_17

U29

PCIE_VSS_18

U32

PCIE_VSS_19

V32

PCIE_VSS_20

V34

PCIE_VSS_21

V35

PCIE_VSS_22

W29

PCIE_VSS_23

W32

PCIE_VSS_24

W33

PCIE_VSS_25

Y33

PCIE_VSS_26

AA29

PCIE_VSS_27

AA32

PCIE_VSS_28

AB29

PCIE_VSS_29

AB34

PCIE_VSS_30

AB35

PCIE_VSS_31

AC33

PCIE_VSS_43

AD29

PCIE_VSS_32

AD32

PCIE_VSS_33

AD33

PCIE_VSS_34

AF29

PCIE_VSS_35

AF32

PCIE_VSS_36

AF34

PCIE_VSS_37

AF35

PCIE_VSS_38

AG27

PCIE_VSS_39

AG32

PCIE_VSS_40

AG33

PCIE_VSS_41

AH33

PCIE_VSS_42

A2

VSS_1

P15

VSS_2

R14

VSS_3

V1

VSS_4

W8

VSS_5

AA19

VSS_6

AC17

VSS_7

AF19

VSS_8

AK3

VSS_9

A4

VSS_10

C18

VSS_11

E22

VSS_12

G4

VSS_13

J18

VSS_14

K17

VSS_15

M28

VSS_16

P6

VSS_17

P9

VSS_18

P13

VSS_19

P18

VSS_20

P21

VSS_21

P23

VSS_22

P26

VSS_23

P29

VSS_24

P30

VSS_25

R1

VSS_26

R5

VSS_27

R7

VSS_28

R10

VSS_29

R17

VSS_30

R19

VSS_31

R22

VSS_32

U5

VSS_33

U8

VSS_34

U10

VSS_35

U15

VSS_36

U18

VSS_37

U21

VSS_38

U23

VSS_39

V3

VSS_40

V7

VSS_41

V9

VSS_42

V10

VSS_43

V11

VSS_44

V14

VSS_45

V17

VSS_46

V19

VSS_47

V22

VSS_48

W5

VSS_49

W10

VSS_50

W15

VSS_51

W18

VSS_52

W21

VSS_53

W23

VSS_54

AA3

VSS_55

AA6

VSS_56

AA10

VSS_57

AA14

VSS_58

AA17

VSS_59

AA22

VSS_60

AB5

VSS_61

AB8

VSS_62

AB10

VSS_63

AB13

VSS_64

AB15

VSS_65

AB18

VSS_66

AB21

VSS_67

AB23

VSS_68

AC14

VSS_69

AC19

VSS_70

AC22

VSS_71

AD6

VSS_72

AD24

VSS_73

AF6

VSS_74

AF9

VSS_75

AF14

VSS_76

AF15

VSS_77

AF17

VSS_78

AF18

VSS_79

AF21

VSS_80

AF22

VSS_81

AF24

VSS_82

AG10

VSS_83

AG12

VSS_84

AH21

VSS_85

RV635 XT A11

RV635 XT A11

4

Part 6 of 7

Part 6 of 7

PCI-Express GND

PCI-Express GND

CORE GND

CORE GND

3

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166

3

VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

BBN_1
BBN_2

AJ14
AJ17
AJ18
AJ19
AK9
AK10
AK12
AK15
AK30
AM1
AN3
AN6
AN32
AR8
A11
A18
A21
A29
A34
C3
C5
C11
C13
C14
C23
C26
C33
D4
D7
D29
D33
E10
E12
E19
E24
F7
F14
F15
F17
F26
F30
F33
F35
G1
G9
G10
G18
G21
G22
G29
H17
H19
J12
J15
J21
J24
J26
J32
J35
K3
K6
K9
K14
K15
K18
K19
K21
K22
K28
K30
L33
M5
M9
M26
M32
N3
N14
N17
N19
N22
N33

W13
AA13

2

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - ASIC Grounds

RV635 GDDR3 - ASIC Grounds

2

RV635 GDDR3 - ASIC Grounds

Sheet

Sheet

Sheet

1

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

of

621

of

621

of

621

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

5

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7

D D

DVOCLK

TP84 35milTP84 35mil

DVPCNTL_0

TP85 35milTP85 35mil

DVPCNTL_1

TP86 35milTP86 35mil

DVPCNTL_2

TP87 35milTP87 35mil

DVP_MVP_CNTL_0

TP88 35milTP88 35mil

DVP_MVP_CNTL_1

CrossFire

DVP_MVP_CNTL_0 : DE for bits D[12..23]
DVP_MVP_CNTL_1 : CLK for bits D[12..23]

C C

B B

TP89 35milTP89 35mil

TP60 35milTP60 35mil
TP61 35milTP61 35mil
TP62 35milTP62 35mil
TP63 35milTP63 35mil
TP64 35milTP64 35mil
TP65 35milTP65 35mil
TP66 35milTP66 35mil
TP67 35milTP67 35mil
TP68 35milTP68 35mil
TP69 35milTP69 35mil
TP70 35milTP70 35mil
TP71 35milTP71 35mil
TP72 35milTP72 35mil
TP73 35milTP73 35mil
TP74 35milTP74 35mil
TP75 35milTP75 35mil
TP76 35milTP76 35mil
TP77 35milTP77 35mil
TP78 35milTP78 35mil
TP79 35milTP79 35mil
TP80 35milTP80 35mil
TP81 35milTP81 35mil
TP82 35milTP82 35mil
TP83 35milTP83 35mil

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AM12

AL12

AJ12
AH12
AM10

AL10

AJ10
AH10

AL7

AM9
AL9

AJ9

AK7

AH1
AG1
AH3
AH2
AN8
AP8

AJ3
AJ2

AJ1
AK2
AK1
AL3
AL2
AL1
AM3
AM2
AN2
AP3
AR3
AN4
AR4
AP4
AN5
AR5
AP5
AP6
AR6
AN7
AP7
AR7

U1G

U1G

VIP_0
VIP_1
VIP_2
VIP_3
VIP_4
VIP_5
VIP_6
VIP_7

VPCLK0

VHAD_0
VHAD_1

VPHCTL
VIPCLK

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_MVP_0
DVPCNTL_MVP_1

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

RV635 XT A11

RV635 XT A11

VIP

VIP
Capture

Capture

VIP

VIP
Host

Host

PART 7 OF 7

PART 7 OF 7

General

General
Purpose

Purpose
I/O

I/O

GPIO_15_PWRCNTL_0

GPIO_17_THERMAL_INT

GPIO_20_PWRCNTL_1

GPIO_23_CLKREQB

RESERVED

RESERVED

No Connect

No Connect

CrossFire Card-Edge

Lower Cable Card Edge

J8002J8002

1

DVOCLK
DVPCNTL_2
DVPDATA_1
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_9
DVPDATA_11
DVPCNTL_1

A A

GPIO_3

3
5
7

9
11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

2
4
6
8

DVPDATA_0

10
12

DVPDATA_2

14
16

DVPDATA_4

18
20

DVPDATA_6

22
24

DVPDATA_8

26
28

DVPDATA_10

32

DVPCNTL_0

34
36

GPIO_5

38
40

Bundle A

5

Upper Cable Card Edge

DVP_MVP_CNTL_1
DVP_MVP_CNTL_0
DVPDATA_13
DVPDATA_15
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_23
GENERICB_R
GPIO_4

11
13
15
17
19
21
23
25
27
29 30
31
33
35
37
39

Bundle B (closer to the bracket)

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11
GPIO_12
GPIO_13

GPIO_14_HPD2

GPIO_16_SSIN

GPIO_18_HPD3

GPIO_19_CTF

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_24_TRST

GPIO_25_TDI

GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

GEN_A
GEN_B
GEN_C

GEN_D_HPD4

GEN_E
GEN_F

GEN_G
DVALID

PSYNC

RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8

NC_1
NC_2

NC_3
NC_DRM_0
NC_DRM_1

NC_FAN_TACH

NC_AC_BATT

NC_SMBCLK

NC_SMBDATA

J8001J8001

1

2

3

4

5

6

7

8

9

10
12
14
16
18
20
22
24
26
28

32
34
36
38
40

4

GPIO_0

AG2

GPIO_1

AF2

GPIO_2

AF1
AE3
AE2
AE1
AD3

GPIO_7

AD2

GPIO_8

AD1

GPIO_9

AD5

GPIO_10

AD4

GPIO_11

AC3

GPIO_12

AC2

GPIO_13

AC1

HPD2

AB3

PWRCNTL_0

AB2

GPIO_16

AB1

ThermINT

AF5

GPIO_18

AF4

CTF

AG4

PWRCNTL_1

AG3

GPIO21_BB_EN

AD9

GPIO_22

AD8
AD7
AB4

JTAG_TDI

AB6

JTAG_TCK

AB7

JTAG_TMS

AB9

JTAG_TDO

AA9

GENERICA

AF8

GENERICB

AF7

GENERICC

AG5

GEN_D_HPD4

AP9
AR9
AP13
AR13

DVALID

AJ7

PSYNC

AM7
AG24

AH24
AK24
AK26
AL24
AL26
AG7
AJ6

AG18
AH18
AM34
AF3
AG9

GND_PCIE_PVSS

AK14
AK29
AK34
AK35

R10

R10

DNI

2.0K

2.0K

It is not intended for
production

+3.3V

TC47

TC47
100nF_6.3V

100nF_6.3V

Mating connector: 6010028300G
(HEADER 2X8 1.27MM PITCH, SMD)

Place it at top edge of the board on the bottom side.
Mounting hole is needed and must be aligned with B176

DVPDATA_12
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_20
DVPDATA_22
DVALID_R
GPIO_6

4

GPIO_3
GPIO_4
GPIO_5
GPIO_6

HPD2 (15)
PWRCNTL_0 (13)

ThermINT (18)

CTF (18)

PCIE_CLK_REQb

DNI

TR16 0RTR16 0R

+3.3V

R38

R38

4.7K

4.7K

Do not install for BU

R8001 0RR8001 0R
R8002 0RR8002 0R

GENERICB: Generic I2C_SDA
DVALID: Generic I2C_SCL

CrossFire

FLOW_CONTROL_1 - Lower Cable
FLOW_CONTROL_2 - Upper Cable
SWAP_LOCK_1 - Lower Cable
SWAP_LOCK_2 - Upper Cable

PWRCNTL_1 (13)

JTAG_MODE

MR51KMR5
1K

R39

R39

4.7K

4.7K

SMBCLK (1)

SMBDATA (1)

TR570R TR570R

DNI

BUO

TJ47

TJ47

1

JTAG_MODE

3
5
7

JTAG_TCK

9

JTAG_TMS

11

JTAG_TDI

13

JTAG_TDO

15

2X8SOCKET

2X8SOCKET

DVALID
GENERICB

GENERICA (17)

GEN_D_HPD4_TDO (1,3)

TP46TP46

+EXT_ADJ

2

GPIO_8_R

4

GPIO_22_R

6

GPIO_9_R

8

GPIO_10_R

10

SDA

12

SCL

14
16

TP47TP47

For wire soldering

3

BUO

3

+3.3V

TR50

TR50
10K

10K

TR47

TR47

4.7K

4.7K

TC46

TC46
100nF_6.3V

100nF_6.3V

2

+3.3V

DNI

DNI

DNI

DNI

NTSC

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

BUO

DNI

DNI

DNI

DNI

Dual Rank

DNI

DNI

R50 10KR50 10K

R51 10KR51 10K

R52 10KR52 10K
R53 10KR53 10K

R54 1KR54 1K

R55 10KR55 10K
NR55 1KNR55 1K

R56 1KR56 1K

R57 10KR57 10K

R58 10KR58 10K
R59 10KR59 10K
R63 10KR63 10K
R62 10KR62 10K
R61 10KR61 10K

R65 10KR65 10K
R64 10KR64 10K

R66 10KR66 10K

R67 10KR67 10K

R68 10KR68 10K

R69 10KR69 10K

R70 10KR70 10K

R71 10KR71 10K

R72 10KR72 10K

R73 10KR73 10K

R74 10KR74 10K

R75 10KR75 10K

R76 10KR76 10K

R77 10KR77 10K

R78 10KR78 10K

R88 10KR88 10K

R79 10KR79 10K

R60 10KR60 10K

R87 10KR87 10K

GPIO_8
GPIO_9
GPIO_10
GPIO_22

2

DNI

MR50 10KMR50 10K

DNI

MR51 10KMR51 10K

MR52 10KMR52 10K
MR53 10KMR53 10K

MR54 10KMR54 10K

MR55 10KMR55 10K

DNI

Single Rank

DNI

MR87 10KMR87 10K

MR56 10KMR56 10K

MR58 10KMR58 10K
MR59 10KMR59 10K
MR63 10KMR63 10K
MR62 10KMR62 10K
MR61 10KMR61 10K

MR65 10KMR65 10K
MR64 10KMR64 10K

MR66 10KMR66 10K

MR67 10KMR67 10K

MR68 10KMR68 10K

MR69 10KMR69 10K

MR70 10KMR70 10K

MR71 10KMR71 10K

MR72 10KMR72 10K

MR73 10KMR73 10K

MR74 10KMR74 10K

MR75 10KMR75 10K

MR76 10KMR76 10K

MR77 10KMR77 10K

MR78 10KMR78 10K

MR88 10KMR88 10K

MR79 10KMR79 10K

MR60 10KMR60 10K

TP50TP50

+3.3V+5V

TR48

TR48

4.7K

4.7K
BUOBUO

SDA (3)
SCL (3)

PIN BASED STRAPS

GPIO_0

GPIO_1

GPIO_1

GPIO_2

GPIO_2
GPIO_3

GPIO_3

GPIO_4

SW3A

SW3A

41

DIP_SWX2

DIP_SWX2

GPIO_5

GPIO_7GPIO_7

GPIO_8_R
GPIO_9_R

GPIO_13

GPIO_13
GPIO_12

GPIO_12
GPIO_11

GPIO_11

GENERICC
GENERICB

VSYNC_DAC1

VSYNC_DAC1

HSYNC_DAC1

PSYNC

PSYNC

GPIO21_BB_EN

GPIO21_BB_EN

VID_0

VID_0

VID_1

VID_1

VID_2

VID_2

VID_3

VID_3

VID_4

VID_4

VID_5

VID_5

VID_6

VID_6

VID_7

VID_7

VSYNC_DAC2

VSYNC_DAC2

GPIO_18

HSYNC_DAC2

HSYNC_DAC2

DVALID

DVALID

GPIO_16

Place close to ASIC

R37 33RR37 33R
R47 33RR47 33R
R48 33RR48 33R
R49 33RR49 33R

+3.3V

R45

R45
10K

10K

MR45

MR45
10K

10K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

SW1A

SW1A

41

DIP_SWX2

DIP_SWX2

GPIO_6

SW3B

SW3B

32

DIP_SWX2

DIP_SWX2

SW1B

SW1B

32

DIP_SWX2

DIP_SWX2

CONFIG[3]
CONFIG[2]
CONFIG[1]
CONFIG[0]

VSYNC_DAC1 (3,15)

HSYNC_DAC1 (3,15)

VSYNC_DAC2 (3,16)

HSYNC_DAC2 (3,16)

+3.3V

R46

R46
10K

10K

GPIO_8_R
GPIO_9_R

5

GPIO_10_R

6

GPIO_22_R

1

+3.3V

7
3
8

C47

C47
100nF_6.3V

100nF_6.3V

RV635 GDDR3 - ASIC DVO & GPIOs

RV635 GDDR3 - ASIC DVO & GPIOs

RV635 GDDR3 - ASIC DVO & GPIOs

GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

AMD Internal Use Only - Reserved (Default: 00)

DEBUG_ACCESS
AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: G1=0, G2=1)

AMD Internal Use Only - Reserved (Default: 0)

TV OUT STANDARD (Jumper position overwrite resistor settings)

0 - PAL TVO (Jumper is closed)
1 - NTSC TVO (Jumper is open)

AMD Internal Use Only - Reserved (Default: 0)

GPIO(9,13:11) - CONFIG[3..0]

0010 - 512Kbit AT25F512A (Atmel)
0011 - 1Mbit AT25F1024A (Atmel)
0100 - 512Kbit M25P05A (ST)
0101 - 1Mbit M25P10A (ST)
0101 - 2Mbit M25P20 (ST)
0100 - 512Kbit Pm25LV512 (Chingis)
0101 - 1Mbit Pm25LV010 (Chingis)

AMD Internal Use Only - Reserved (Default: 0)

VIP_DEVICE_STRAP_EN

0: Slave VIP host port devices present (use if Theater is populated)
1: No slave VIP host port devices reporting presence during reset (use for
configurations without video-in)

AMD Internal Use Only - Reserved (HDMI_EN =1 )

VGA DISABLE : 1 for disable (set to 0 for normal operation)

AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

MSI_DIS (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

BIF_AUDIO_EN
0 - Disable HD Audio 1- Enable HD Audio (Default 1 for RV635)

AMD Internal Use Only - Reserved (Default: 0)

64BAR_EN_A (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

AMD Internal Use Only - Reserved (Default: 0)

MEMORY CONFIG
V2SYNC: 0 = 1 rank of memory, 1 = 2 ranks of memory

AMD Internal Use Only - Reserved

BIF_CLK_PM_EN
0 - Disable CLKREQ# power management capability
1 - Enable CLKREQ# power management capability

U2

U2

Q

D
C
S
HOLD
W
VCC

VSS

M25P05-AVNM6P

M25P05-AVNM6P

Sheet

Sheet

Sheet

1

ATI Board Feature I

Default: 0

BIOS1

2

4

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

BIOS1

113-B146XX-XXX

113-B146XX-XXX
VIDEO BIOS

FIRMWARE

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

of

721

of

721

of

721

1

BIOS

BIOS

Doc No.

Doc No.

Doc No.

ATI PCIE FEATURE I

ATI PCIE FEATURE II

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

DQA_9
DQA_11
DQA_10
DQA_12
DQA_8
DQA_13
DQA_15
DQA_14
DQA_31
DQA_28
DQA_29
DQA_30
DQA_27
DQA_26
DQA_24
DQA_25
DQA_2
DQA_4
DQA_1
DQA_3
DQA_7
DQA_5
DQA_0
DQA_6
DQA_16
DQA_17
DQA_23
DQA_18
DQA_21
DQA_19
DQA_22
DQA_20

MAA_BA0
MAA_BA1

MAA_7
MAA_8
MAA_3
MAA_10
MAA_11
MAA_2
MAA_1
MAA_0
MAA_9
MAA_6
MAA_5
MAA_4

MAA_BA2

QSA_1
QSA_3
QSA_0
QSA_2

QSAb_1
QSAb_3
QSAb_0
QSAb_2

DQMAb_1
DQMAb_3
DQMAb_0
DQMAb_2

R218

R218
243R

243R

C239

C239
10nF

10nF

C240

C240

C241

C241

100nF_6.3V

100nF_6.3V

10nF

10nF

R208 60.4RR208 60.4R
R209 60.4RR209 60.4R
R201 60.4RR201 60.4R
R202 60.4RR202 60.4R

R203 121RR203 121R
R204 121RR204 121R
R205 121RR205 121R
R206 121RR206 121R
R207 121RR207 121R

R265 60.4RR265 60.4R
R266 60.4RR266 60.4R
R251 60.4RR251 60.4R
R252 60.4RR252 60.4R

R253 121RR253 121R
R254 121RR254 121R
R255 121RR255 121R
R256 121RR256 121R
R257 121RR257 121R

C205

C205
100nF_6.3V

100nF_6.3V

C216

C216
1uF_6.3V

1uF_6.3V

C226

C226
100nF_6.3V

100nF_6.3V

C231

C231
1uF_6.3V

1uF_6.3V

5

U201

U201
T3
T2
R3
R2

M3
N2

L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2

C3

C2

B3

B2

H10

G9

G4

L4
K2
M9

K11

L9

K10
H11

K9
M4
K3
H2
K4

F9
H9
H3
F4
H4

J10
J11

P3

P10
D10

D3
P2

P11
D11

D2

N3

N10
E10

E3
V9
A4

H1

H12

23CC1287SB12

23CC1287SB12

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

GND | VDD

VDDQ

VSSQ

VDDA

VSSA

RFU2
RFU1
RFU0

+MVDD
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

MF

+MVDD

C242

C242
100nF_6.3V

100nF_6.3V

+MVDD

Rank 0
Top Layer

B201B201
B202B202

C243

C243
10nF

10nF

C294

C294
10nF

10nF

C295

C295
10nF

10nF

+MVDD

+MVDD

+MVDD

R259

R259

2.37K

2.37K

R260

R260

5.49K

5.49K

R261

R261

2.37K

2.37K

R262

R262

5.49K

5.49K

+MVDD

+MVDD

In Single Rank Design use 60.4R (PN 316060R400G)
In Dual Rank Design use 121R (PN3160121000G)
R208, R209, R201, R202
R265, R266, R251, R252

+MVDD

QSA_[7..0](5,9)

QSAb_[7..0](5,9)

+MVDD

C211

C207

C207
100nF_6.3V

100nF_6.3V

C218

C218
1uF_6.3V

1uF_6.3V

C227

C227
100nF_6.3V

100nF_6.3V

C232

C232
1uF_6.3V

1uF_6.3V

5

C209

C209
100nF_6.3V

100nF_6.3V

C211

C210

C210

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C222

C222

C221

C221

C220

C220
1uF_6.3V

1uF_6.3V

Overlap footprints Overlap footprints Overlap footprints

1uF_6.3V

1uF_6.3V

C233

C233
10uF_X6S

10uF_X6S

MC233

MC233

4.7uF_6.3V

4.7uF_6.3V

1uF_6.3V

1uF_6.3V

C235

C235
10uF_X6S

10uF_X6S

MC235

MC235

4.7uF_6.3V

4.7uF_6.3V

C236

C236
10uF_X6S

10uF_X6S

MC236

MC236

4.7uF_6.3V

4.7uF_6.3V

C237

C237
10uF_X6S

10uF_X6S

MC237

MC237

4.7uF_6.3V

4.7uF_6.3V

+MVDD

+MVDD

C251

C251
100nF_6.3V

100nF_6.3V

C262

C262
1uF_6.3V

1uF_6.3V

C273

C273
100nF_6.3V

100nF_6.3V

C278

C278
1uF_6.3V

1uF_6.3V

DQA_[63..0](5,9)

D D

RASA0b(5,9)

+MVDD

C244

C244
10nF

10nF

+MVDD

C245

C245
10nF

10nF

C201

C201
100nF_6.3V

100nF_6.3V

C212

C212
1uF_6.3V

1uF_6.3V

C223

C223
100nF_6.3V

100nF_6.3V

C228

C228
1uF_6.3V

1uF_6.3V

R219

R219

2.37K

2.37K

R220

R220

5.49K

5.49K
+MVDD

R221

R221

2.37K

2.37K

R222

R222

5.49K

5.49K
+MVDD

CLKB0(5,9)
CLKB0b(5,9)
CLKA0(5,9)
CLKA0b(5,9)

CKEA0(5,9)
CSA0b_0(5)
WEA0b(5,9)
RASA0b(5,9)
CASA0b(5,9)

CLKB1(5,9)
CLKB1b(5,9)
CLKA1(5,9)
CLKA1b(5,9)

CKEA1(5,9)
CSA1b_0(5)
WEA1b(5,9)
RASA1b(5,9)
CASA1b(5,9)

C202

C202
100nF_6.3V

100nF_6.3V

C213

C213
1uF_6.3V

1uF_6.3V

C224

C224
100nF_6.3V

100nF_6.3V

C229

C229
1uF_6.3V

1uF_6.3V

CASA0b(5,9)
CKEA0(5,9)

CSA0b_0(5)
WEA0b(5,9)
CLKA0b(5,9)

CLKA0(5,9)

DRAM_RST(5,9)

C238

C238
100nF_6.3V

100nF_6.3V

C203

C203
100nF_6.3V

100nF_6.3V

C214

C214
1uF_6.3V

1uF_6.3V

C225

C225
100nF_6.3V

100nF_6.3V

C230

C230
1uF_6.3V

1uF_6.3V

C C

B B

+MVDD

A A

+MVDD

+MVDD

CSA1b_0(5)

WEA1b(5,9)
RASA1b(5,9)
CASA1b(5,9)
CKEA1(5,9)
CLKA1b(5,9)

CLKA1(5,9)

DRAM_RST(5,9)

C288

C288
100nF_6.3V

100nF_6.3V

C252

C252
100nF_6.3V

100nF_6.3V

C263

C263
1uF_6.3V

1uF_6.3V

C276

C276
100nF_6.3V

100nF_6.3V

C281

C281
1uF_6.3V

1uF_6.3V

DQA_63
DQA_56
DQA_62
DQA_60
DQA_58
DQA_57
DQA_59
DQA_61
DQA_54
DQA_52
DQA_53
DQA_50
DQA_55
DQA_51
DQA_48
DQA_49
DQA_47
DQA_46
DQA_40
DQA_45
DQA_42
DQA_43
DQA_41
DQA_44
DQA_32
DQA_34
DQA_35
DQA_33
DQA_38
DQA_37
DQA_39
DQA_36

MAA_BA2
MAA_BA1
MAA_BA0

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

QSA_7
QSA_6
QSA_5
QSA_4

QSAb_7
QSAb_6
QSAb_5
QSAb_4

DQMAb_7
DQMAb_6
DQMAb_5
DQMAb_4

R210

R210
243R

243R

C290

C290
100nF_6.3V

100nF_6.3V

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

QSAb_0
QSAb_1
QSAb_2
QSAb_3
QSAb_4
QSAb_5
QSAb_6
QSAb_7

C253

C253
100nF_6.3V

100nF_6.3V

C264

C264
1uF_6.3V

1uF_6.3V

C277

C277
100nF_6.3V

100nF_6.3V

C282

C282
1uF_6.3V

1uF_6.3V

4

U202

U202

T3

DQ31 | DQ23

T2

DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1

VSSQ#D4

VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

GND | VDD

C289

C289
10nF

10nF

C291

C291
10nF

10nF

R3
R2
M3
N2

L3

M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

23CC1287SB12

23CC1287SB12

DQMAb_[7..0](5,9)

DQMBb_[7..0](5,9)

C254

C254
100nF_6.3V

100nF_6.3V

C265

C265
1uF_6.3V

1uF_6.3V

4

C255

C255
100nF_6.3V

100nF_6.3V

C266

C266
1uF_6.3V

1uF_6.3V

C256

C256
100nF_6.3V

100nF_6.3V

C267

C267
1uF_6.3V

1uF_6.3V

C257

C257
100nF_6.3V

100nF_6.3V

C268

C268
1uF_6.3V

1uF_6.3V

C283

C283
10uF_X6S

10uF_X6S

MC283

MC283

4.7uF_6.3V

4.7uF_6.3V

VDDQ

VSSQ

VDDA

VSSA

RFU2
RFU1
RFU0

VDD

VSS

MF

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C259

C259
100nF_6.3V

100nF_6.3V

C270

C270
1uF_6.3V

1uF_6.3V

C284

C284
10uF_X6S

10uF_X6S

MC284

MC284

4.7uF_6.3V

4.7uF_6.3V

+MVDD

+MVDD

C292

C292
100nF_6.3V

100nF_6.3V

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

C260

C260
100nF_6.3V

100nF_6.3V

C271

C271
1uF_6.3V

1uF_6.3V

C285

C285
10uF_X6S

10uF_X6S

mC285

mC285

4.7uF_6.3V

4.7uF_6.3V

C293

C293
10nF

10nF

C261

C261
100nF_6.3V

100nF_6.3V

C272

C272
1uF_6.3V

1uF_6.3V

C286

C286
10uF_X6S

10uF_X6S

MC286

MC286

4.7uF_6.3V

4.7uF_6.3V

B251B251
B252B252

+MVDD

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

QSBb_0
QSBb_1
QSBb_2
QSBb_3
QSBb_4
QSBb_5
QSBb_6
QSBb_7

+MVDD

3

QSB_[7..0] (5,9)

QSBb_[7..0] (5,9)

+MVDD

C301

C301
100nF_6.3V

100nF_6.3V

C312

C312
1uF_6.3V

1uF_6.3V

+MVDD

C323

C323
100nF_6.3V

100nF_6.3V

C328

C328
1uF_6.3V

1uF_6.3V

3

C344

C344
10nF

10nF

C345

C345
10nF

10nF

DQB_[63..0](5,9)

+MVDD

+MVDD

C302

C302
100nF_6.3V

100nF_6.3V

C313

C313
1uF_6.3V

1uF_6.3V

C324

C324
100nF_6.3V

100nF_6.3V

C329

C329
1uF_6.3V

1uF_6.3V

R319

R319

2.37K

2.37K

R320

R320

5.49K

5.49K

R321

R321

2.37K

2.37K

R322

R322

5.49K

5.49K

+MVDD

2

U301

U301

DQB_26

T3

DQ31 | DQ23

DQB_25

T2

DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

MAA_BA0
MAA_BA1
MAA_BA2

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

C307

C307
100nF_6.3V

100nF_6.3V

C318

C318
1uF_6.3V

1uF_6.3V

C333

C333
10uF_X6S

10uF_X6S

MC333

MC333

4.7uF_6.3V

4.7uF_6.3V

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F12
VDD#M12

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#G12

VDDA#K12

VSSA#J12

C308

C308
100nF_6.3V

100nF_6.3V

C319

C319
1uF_6.3V

1uF_6.3V

C334

C334
10uF_X6S

10uF_X6S

MC334

MC334

4.7uF_6.3V

4.7uF_6.3V

VDD#F1
VDD#M1
VDD#V2

VSS#A10

VSS#G1

VSS#L1

VSS#L12

VSS#V3

VSS#V10

GND | VDD

GND | VDD

DQB_27

R3

DQB_30

R2

DQB_24

M3

DQB_29

N2

DQB_31

L3

DQB_28

M2

DQB_15

T10

DQB_12

T11

DQB_13

R10

DQB_14

R11

DQB_8

M10

DQB_10

N11

DQB_9

L10

DQB_11

M11

DQB_0

G10

DQB_1

F11

DQB_3

F10

DQB_7

E11

DQB_5

C10

DQB_2

C11

DQB_6

B10

DQB_4

B11

DQB_17

G3

DQB_18 DQB_35

F2

DQB_20

F3

DQB_19

E2

DQB_23

C3

DQB_16

C2

DQB_21

B3

DQB_22

B2

QSB_3
QSB_1
QSB_0
QSB_2

QSBb_3
QSBb_1
QSBb_0
QSBb_2

DQMBb_3
DQMBb_1
DQMBb_0
DQMBb_2

C338

C338
100nF_6.3V

100nF_6.3V

C340

C340
100nF_6.3V

100nF_6.3V

MAB_BA0
MAB_BA1

MAB_7
MAB_8
MAB_3
MAB_10
MAB_11
MAB_2
MAB_1
MAB_0
MAB_9
MAB_6
MAB_5
MAB_4

MAB_BA2

R318

R318
243R

243R

C339

C339
10nF

10nF

C341

C341
10nF

10nF

H10

G9
G4

L4
K2

M9

K11

L9
K10
H11

K9

M4

K3

H2

K4

F9

H9
H3

F4

H4
J10

J11

P3
P10
D10

D3

P2
P11
D11

D2

N3
N10
E10

E3
V9
A4

H1
H12

23CC1287SB12

23CC1287SB12

+MVDD

RASB0b(5,9)

CASB0b(5,9)
CKEB0(5,9)

CSB0b_0(5,9)
WEB0b(5,9)
CLKB0b(5,9)

CLKB0(5,9)

DRAM_RST(5,9)

MAA_BA[2..0](5,9)

MAA_[11..0](5,9) MAB_[11..0](5,9)

C304

C304

C303

C303
100nF_6.3V

100nF_6.3V

C314

C314
1uF_6.3V

1uF_6.3V

100nF_6.3V

100nF_6.3V

C315

C315
1uF_6.3V

1uF_6.3V

C305

C305
100nF_6.3V

100nF_6.3V

C316

C316
1uF_6.3V

1uF_6.3V

C306

C306
100nF_6.3V

100nF_6.3V

C317

C317
1uF_6.3V

1uF_6.3V

VDDQ

VDD

VSSQ

VSS

VDDA

VSSA

RFU2
RFU1
RFU0

MF

MAB_BA[2..0](5,9)

C309

C309
100nF_6.3V

100nF_6.3V

C320

C320
1uF_6.3V

1uF_6.3V

C335

C335
10uF_X6S

10uF_X6S

MC335

MC335

4.7uF_6.3V

4.7uF_6.3V

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C310

C310
100nF_6.3V

100nF_6.3V

C321

C321
1uF_6.3V

1uF_6.3V

+MVDD

C336

C336
10uF_X6S

10uF_X6S

MC336

MC336

4.7uF_6.3V

4.7uF_6.3V

2

+MVDD

+MVDD

C342

C342
100nF_6.3V

100nF_6.3V

+MVDD

+MVDD

B301B301
B302B302

C343

C343
10nF

10nF

C392

C392
10nF

10nF

C393

C393
10nF

10nF

MAB_BA0
MAB_BA1
MAB_BA2

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

C311

C311
100nF_6.3V

100nF_6.3V

C322

C322
1uF_6.3V

1uF_6.3V

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

1

U302

U302

DQB_57

T3

+MVDD

+MVDD

R359

R359

2.37K

2.37K

R360

R360

5.49K

5.49K

R361

R361

2.37K

2.37K

R362

R362

5.49K

5.49K

+MVDD

+MVDD

CSB1b_0(5,9)

DRAM_RST(5,9)

100nF_6.3V

100nF_6.3V

DQB_61
DQB_63
DQB_60
DQB_56
DQB_59
DQB_58
DQB_62
DQB_55
DQB_53
DQB_52
DQB_48
DQB_54
DQB_51
DQB_49
DQB_50
DQB_47
DQB_46
DQB_41
DQB_45
DQB_44
DQB_43
DQB_40
DQB_42
DQB_32

DQB_33
DQB_34
DQB_38
DQB_36
DQB_39
DQB_37

MAB_BA2
MAB_BA1
MAB_BA0

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

WEB1b(5,9)
RASB1b(5,9)
CASB1b(5,9)
CKEB1(5,9)
CLKB1b(5,9)

CLKB1(5,9)

QSB_7
QSB_6
QSB_5
QSB_4

QSBb_7
QSBb_6
QSBb_5
QSBb_4

DQMBb_7
DQMBb_6
DQMBb_5
DQMBb_4

R310

R310
243R

243R

C388

C388
100nF_6.3V

100nF_6.3V

C390

C390

C389

C389
10nF

10nF

C391

C391
10nF

10nF

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23CC1287SB12

23CC1287SB12

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RFU2

RFU1

RFU0

GND | VDD

GND | VDD

VDD

VSS

MF

+MVDD

C351

C351
100nF_6.3V

100nF_6.3V

C362

C362
1uF_6.3V

1uF_6.3V

C352

C352
100nF_6.3V

100nF_6.3V

C363

C363
1uF_6.3V

1uF_6.3V

C353

C353
100nF_6.3V

100nF_6.3V

C364

C364
1uF_6.3V

1uF_6.3V

C354

C354
100nF_6.3V

100nF_6.3V

C365

C365
1uF_6.3V

1uF_6.3V

C355

C355
100nF_6.3V

100nF_6.3V

C366

C366
1uF_6.3V

1uF_6.3V

C356

C356
100nF_6.3V

100nF_6.3V

C367

C367
1uF_6.3V

1uF_6.3V

C357

C357
100nF_6.3V

100nF_6.3V

C368

C368
1uF_6.3V

1uF_6.3V

+MVDD

C384

C373

C373

C374

C374

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C379

C379

C378

C378

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 0

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 0

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 0

C384
10uF_X6S

10uF_X6S

MC384

MC384

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

821

of

821

of

821

1

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C358

C358
100nF_6.3V

100nF_6.3V

C369

C369
1uF_6.3V

1uF_6.3V

C385

C385
10uF_X6S

10uF_X6S

MC385

MC385

4.7uF_6.3V

4.7uF_6.3V

Doc No.

Doc No.

Doc No.

+MVDD

+MVDD

C395

C395

C394

C394

10nF

10nF

100nF_6.3V

100nF_6.3V

C360

C360

C359

C359

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C371

C371

C370

C370

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C387

C387

C386

C386

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

MC386

MC386

MC387

MC387

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

105-B380xx-00

105-B380xx-00

105-B380xx-00

RevDate:

RevDate:

RevDate:

+MVDD

B351B351
B352B352

C361

C361
100nF_6.3V

100nF_6.3V

C372

C372
1uF_6.3V

1uF_6.3V

+MVDD

1

1

1

www.vinafix.vn

5

DQA_[63..0](5,8)

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

R401

R401

2.37K

2.37K

R402

R402

5.49K

5.49K

R415

R415

2.37K

2.37K

R418

R418

5.49K

5.49K

CSA0b_1(5)

DRAM_RST(5,8)

C438

C438
100nF_6.3V

100nF_6.3V

+MVDD

C440

C440
100nF_6.3V

100nF_6.3V

DQA_31
DQA_28
DQA_29
DQA_30
DQA_27
DQA_26
DQA_24
DQA_25
DQA_9
DQA_11
DQA_10
DQA_12
DQA_8
DQA_13
DQA_15
DQA_14
DQA_16
DQA_17
DQA_23
DQA_18
DQA_21
DQA_19
DQA_22
DQA_20
DQA_2
DQA_4
DQA_1
DQA_3
DQA_7
DQA_5
DQA_0
DQA_6

MAA_BA2
MAA_BA1
MAA_BA0

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

WEA0b(5,8)
RASA0b(5,8)
CASA0b(5,8)
CKEA0(5,8)
CLKA0b(5,8)

CLKA0(5,8)

QSA_3
QSA_1
QSA_2
QSA_0

QSAb_3
QSAb_1
QSAb_2
QSAb_0

DQMAb_3
DQMAb_1
DQMAb_2
DQMAb_0

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

QSAb_0

D D

QSAb_1
QSAb_2
QSAb_3
QSAb_4
QSAb_5
QSAb_6
QSAb_7

QSAb_[7..0] (5,8)

DQMAb_[7..0](5,8)

QSA_[7..0] (5,8)

C C

+MVDD

C444

C444
10nF

10nF

B B

+MVDD

C445

C445
10nF

10nF

+MVDD

R428

CSA0b_1(5)
CSA1b_1(5)

R428
121R

121R
R429

R429
121R

121R

R400

R400
243R

243R

C439

C439
10nF

10nF

C441

C441
10nF

10nF

T3

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10

R11
M10
N11

L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2
F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4

J10
J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

U401

U401

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23CC1287SB12

23CC1287SB12

+MVDD

CLKA1(5,8)
CLKA1b(5,8)
CLKB1(5,8)
CLKB1b(5,8)

CKEB1(5,8)
CSB1b_0(5,8)
WEB1b(5,8)
RASB1b(5,8)
CASB1b(5,8)

VDDQ#C12

VDDQ#E12

VDDQ#N12

VDDQ#R12
VDDQ#V12

VSSQ#D12
VSSQ#G11

CLKA0(5,8)
CLKA0b(5,8)
CLKB0(5,8)
CLKB0b(5,8)

CKEB0(5,8)
CSB0b_0(5,8)
WEB0b(5,8)
RASB0b(5,8)
CASB0b(5,8)

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#V1

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#G2

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

GND | VDD

GND | VDD

+MVDD

C408

C403

C403

C402

C402

100nF_6.3V

100nF_6.3V

100nF_6.3V

A A

100nF_6.3V

C413

C413
1uF_6.3V

1uF_6.3V

C414

C414
1uF_6.3V

1uF_6.3V

C404

C404
100nF_6.3V

100nF_6.3V

C415

C415
1uF_6.3V

1uF_6.3V

C405

C405
100nF_6.3V

100nF_6.3V

C416

C416
1uF_6.3V

1uF_6.3V

C406

C406
100nF_6.3V

100nF_6.3V

C417

C417
1uF_6.3V

1uF_6.3V

C407

C407
100nF_6.3V

100nF_6.3V

C418

C418
1uF_6.3V

1uF_6.3V

C408
100nF_6.3V

100nF_6.3V

C419

C419
1uF_6.3V

1uF_6.3V

C409

C409
100nF_6.3V

100nF_6.3V

C420

C420
1uF_6.3V

1uF_6.3V

C410

C410

100nF_6.3V

100nF_6.3V

C421

C421

1uF_6.3V

1uF_6.3V

+MVDD

C423

C423

C426

C426

C427

100nF_6.3V

100nF_6.3V

C431

C431
1uF_6.3V

1uF_6.3V

C427
100nF_6.3V

100nF_6.3V

C432

C432
1uF_6.3V

1uF_6.3V

C435

C435

C436

C436

C437

C434

C434

10uF_X6S

10uF_X6S

10uF_X6S

10uF_X6S

MC434

MC434

MC435

MC435

4.7uF_6.3V

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints Overlap footprints

5

4.7uF_6.3V

10uF_X6S

10uF_X6S

MC436

MC436

4.7uF_6.3V

4.7uF_6.3V

C437

10uF_X6S

10uF_X6S

MC437

MC437

4.7uF_6.3V

4.7uF_6.3V

100nF_6.3V

100nF_6.3V

C428

C428
1uF_6.3V

1uF_6.3V

+MVDD
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

+MVDD
A2

VDD

A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3

VSS

A10
G1
G12
L1
L12
V3
V10

K1
K12

C442

C442

C443

C443
10nF

10nF

100nF_6.3V

100nF_6.3V

J12
J1

VSSA

J3

RFU2

J2

RFU1

V4

RFU0

A9

MF

+MVDD

R437 121RR437 121R
R438 121RR438 121R
R430 121RR430 121R
R431 121RR431 121R

R432 121RR432 121R
R433 121RR433 121R
R434 121RR434 121R
R435 121RR435 121R
R436 121RR436 121R

+MVDD

R446 121RR446 121R
R447 121RR447 121R
R439 121RR439 121R
R440 121RR440 121R

R441 121RR441 121R
R442 121RR442 121R
R443 121RR443 121R C510
R444 121RR444 121R
R445 121RR445 121R

+MVDD

+MVDD
+MVDD

C473

C473
100nF_6.3V

100nF_6.3V

C478

C478
1uF_6.3V

1uF_6.3V

4

Rank 1
Bottom Layer

RASA1b(5,8)

+MVDD

B401B401
B402B402

+MVDD

C492

C492

R408

R408

2.37K

2.37K

10nF

10nF

R409

R409

5.49K

5.49K

+MVDD

R410

R410

C493

C493

2.37K

2.37K

10nF

10nF

R411

R411

5.49K

5.49K

C453

C453

C452

C452

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C464

C464

C463

C463

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C475

C475

C474

C474

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C479

C479

C480

C480

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

4

CASA1b(5,8)
CKEA1(5,8)

CSA1b_1(5)
WEA1b(5,8)
CLKA1b(5,8)

CLKA1(5,8)

DRAM_RST(5,8)

+MVDD

DQA_54
DQA_52
DQA_53
DQA_50
DQA_55
DQA_51
DQA_48
DQA_49
DQA_63
DQA_56
DQA_62
DQA_60
DQA_58
DQA_57
DQA_59
DQA_61
DQA_32
DQA_34
DQA_35
DQA_33
DQA_38
DQA_37
DQA_39
DQA_36
DQA_47
DQA_46
DQA_40
DQA_45
DQA_42
DQA_43
DQA_41
DQA_44

MAA_BA0
MAA_BA1

MAA_7
MAA_8
MAA_3
MAA_10
MAA_11
MAA_2
MAA_1
MAA_0
MAA_9
MAA_6
MAA_5
MAA_4

QSA_6
QSA_7
QSA_4
QSA_5

QSAb_6
QSAb_7
QSAb_4
QSAb_5

DQMAb_6
DQMAb_7
DQMAb_4
DQMAb_5

C488

C488
100nF_6.3V

100nF_6.3V

C490

C490
100nF_6.3V

100nF_6.3V

C454

C454
100nF_6.3V

100nF_6.3V

C465

C465
1uF_6.3V

1uF_6.3V

C476

C476
100nF_6.3V

100nF_6.3V

C481

C481
1uF_6.3V

1uF_6.3V

MAA_BA2

R407

R407
243R

243R

MAA_BA[2..0](5,8)

C455

C455
100nF_6.3V

100nF_6.3V

C466

C466
1uF_6.3V

1uF_6.3V

C489

C489
10nF

10nF

MAA_[11..0](5,8)

T3

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

C491

C491
10nF

10nF

C456

C456
100nF_6.3V

100nF_6.3V

C467

C467
1uF_6.3V

1uF_6.3V

U402

U402

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23CC1287SB12

23CC1287SB12

+MVDD

MAA_BA0
MAA_BA1
MAA_BA2

MAA_11
MAA_10
MAA_9
MAA_8
MAA_7
MAA_6
MAA_5
MAA_4
MAA_3
MAA_2
MAA_1
MAA_0

C457

C457
100nF_6.3V

100nF_6.3V

C468

C468
1uF_6.3V

1uF_6.3V

C483

C483
10uF_X6S

10uF_X6S

MC483

MC483

4.7uF_6.3V

4.7uF_6.3V

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F12

VDD#M12

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1

VSSQ#D4

VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G12

VSS#L12
VSS#V10

VDDA#K12

VSSA#J12

C458

C458
100nF_6.3V

100nF_6.3V

C469

C469
1uF_6.3V

1uF_6.3V

C484

C484
10uF_X6S

10uF_X6S

MC484

MC484

4.7uF_6.3V

4.7uF_6.3V

VDDQ

VDD
VDD#F1
VDD#M1
VDD#V2

VSSQ

VSS
VSS#G1

VSS#L1
VSS#V3

VDDA

VSSA

RFU2
RFU1
RFU0

GND | VDD

GND | VDD

C459

C459
100nF_6.3V

100nF_6.3V

C470

C470
1uF_6.3V

1uF_6.3V

MF

MAB_BA[2..0](5,8)

MAB_[11..0](5,8)

C485

C485
10uF_X6S

10uF_X6S

MC485

MC485

4.7uF_6.3V

4.7uF_6.3V

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

+MVDD

C460

C460
100nF_6.3V

100nF_6.3V

C471

C471
1uF_6.3V

1uF_6.3V

C486

C486
10uF_X6S

10uF_X6S

MC486

MC486

4.7uF_6.3V

4.7uF_6.3V

+MVDD

+MVDD

C494

C494
100nF_6.3V

100nF_6.3V

C461

C461
100nF_6.3V

100nF_6.3V

C472

C472
1uF_6.3V

1uF_6.3V

+MVDD

QSBb_0
QSBb_1
QSBb_2
QSBb_3
QSBb_4
QSBb_5
QSBb_6
QSBb_7

C495

C495
10nF

10nF

MAB_BA0
MAB_BA1
MAB_BA2

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

DQMBb_[7..0](5,8)

B451B451
B452B452

3

+MVDD

3

QSB_[7..0] (5,8)

DQB_[63..0](5,8)

QSBb_[7..0] (5,8)

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

+MVDD

C544

C544
10nF

10nF

C545

C545
10nF

10nF

+MVDD

C501

C501
100nF_6.3V

100nF_6.3V

C512

C512
1uF_6.3V

1uF_6.3V

+MVDD

C528

C528
1uF_6.3V

1uF_6.3V

2

U501

R500

R500
243R

243R

C539

C539
10nF

10nF

C541

C541
10nF

10nF

C504

C504
100nF_6.3V

100nF_6.3V

C515

C515
1uF_6.3V

1uF_6.3V

U501

T3

DQ31 | DQ23

T2

DQ30 | DQ22

R3

DQ29 | DQ21

R2

DQ28 | DQ20

M3

DQ27 | DQ19

N2

DQ26 | DQ18

L3

DQ25 | DQ17

M2

DQ24 | DQ16

T10

DQ23 | DQ31

T11

DQ22 | DQ30

R10

DQ21 | DQ29

R11

DQ20 | DQ28

M10

DQ19 | DQ27

N11

DQ18 | DQ26

L10

DQ17 | DQ25

M11

DQ16 | DQ24

G10

DQ15 | DQ7

F11

DQ14 | DQ6

F10

DQ13 | DQ5

E11

DQ12 | DQ4

C10

DQ11 | DQ3

C11

DQ10 | DQ2

B10

DQ9 | DQ1

B11

DQ8 | DQ0

G3

DQ7 | DQ15

F2

DQ6 | DQ14

F3

DQ5 | DQ13

E2

DQ4 | DQ12

C3

DQ3 | DQ11

C2

DQ2 | DQ10

B3

DQ1 | DQ9

B2

DQ0 | DQ8

H10

BA2 | RAS

G9

BA1 | BA0

G4

BA0 | BA1

L4

A11 | A7

K2

A10 | A8

M9

A9 | A3

K11

A8/AP | A10

L9

A7 | A11

K10

A6 | A2

H11

A5 | A1

K9

A4 | A0

M4

A3 | A9

K3

A2 | A6

H2

A1 | A5

K4

A0 | A4

F9

CS | CAS

H9

WE | CKE

H3

RAS | BA2

F4

CAS | CS

H4

CKE | WE

J10

CK

J11

CK

P3

RDQS3 | RDQS2

P10

RDQS2 | RDQS3

D10

RDQS1 | RDQS0

D3

RDQS0 | RDQS1

P2

WDQS3 | WDQS2

P11

WDQS2 | WDQS3

D11

WDQS1 | WDQS0

D2

WDQS0 | WDQS1

N3

DM3 | DM2

N10

DM2 | DM3

E10

DM1 | DM0

E3

DM0 | DM1

V9

RESET

A4

ZQ

H1

VREF

H12

VREF#H12

23CC1287SB12

23CC1287SB12

+MVDD

CSB0b_1(5)
CSB1b_1(5)

C506

C506

C505

C505

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C517

C517

C516

C516

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Overlap footprints

C507

C507
100nF_6.3V

100nF_6.3V

C518

C518
1uF_6.3V

1uF_6.3V

C534

C534
10uF_X6S

10uF_X6S

MC534

MC534

4.7uF_6.3V

4.7uF_6.3V

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ#B4

VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1

VSSQ#P4

VSSQ#P9

VSSQ#P12

VSSQ#T1

VSSQ#T4

VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA#K12

VSSA#J12

GND | VDD

GND | VDD

R528

R528
121R

121R
R529

R529
121R

121R

C508

C508
100nF_6.3V

100nF_6.3V

C519

C519
1uF_6.3V

1uF_6.3V

C535

C535
10uF_X6S

10uF_X6S

MC535

MC535

4.7uF_6.3V

4.7uF_6.3V

DQB_15
DQB_12
DQB_13
DQB_14
DQB_8
DQB_10
DQB_9
DQB_11
DQB_26
DQB_25
DQB_27
DQB_30
DQB_24
DQB_29
DQB_31
DQB_28
DQB_17
DQB_18
DQB_20
DQB_19
DQB_23
DQB_16
DQB_21
DQB_22
DQB_0
DQB_1 DQB_46
DQB_3
DQB_7
DQB_5
DQB_2
DQB_6
DQB_4

MAB_BA2
MAB_BA1
MAB_BA0

MAB_11
MAB_10
MAB_9
MAB_8
MAB_7
MAB_6
MAB_5
MAB_4
MAB_3
MAB_2
MAB_1
MAB_0

CSB0b_1(5)

WEB0b(5,8)
RASB0b(5,8)
CASB0b(5,8)
CKEB0(5,8)
CLKB0b(5,8)

CLKB0(5,8)

QSB_1
QSB_3
QSB_2
QSB_0

QSBb_1
QSBb_3
QSBb_2
QSBb_0

DQMBb_1
DQMBb_3
DQMBb_2
DQMBb_0

R501

R501

2.37K

2.37K

C538

C538

R502

R502

100nF_6.3V

100nF_6.3V

5.49K

5.49K
+MVDD

R515

R515

2.37K

2.37K

C540

C540

R518

R518

100nF_6.3V

100nF_6.3V

5.49K

5.49K

C503

C503

C502

C502

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C513

C513

C514

C514

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

C523

C523
100nF_6.3V

100nF_6.3V

VDDQ

VDD

VSSQ

VDDA

VSSA

RFU2
RFU1
RFU0

VSS

MF

+MVDD

C536

C536
10uF_X6S

10uF_X6S

MC536

MC536

4.7uF_6.3V

4.7uF_6.3V

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C509

C509
100nF_6.3V

100nF_6.3V

C520

C520
1uF_6.3V

1uF_6.3V

2

+MVDD

+MVDD

C543

C543

C542

C542

10nF

10nF

100nF_6.3V

100nF_6.3V

C510

C511

C511

100nF_6.3V

100nF_6.3V

100nF_6.3V

100nF_6.3V

C522

C522

C521

C521

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

+MVDD

C537

C537
10uF_X6S

10uF_X6S

MC537

MC537

4.7uF_6.3V

4.7uF_6.3V

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

1

U502

MAB_BA0
MAB_BA1

MAB_7
MAB_8
MAB_3
MAB_10
MAB_11
MAB_2
MAB_1
MAB_0
MAB_9
MAB_6
MAB_5
MAB_4

MAB_BA2

R507

R507
243R

243R

C589

C589
10nF

10nF

C591

C591
10nF

10nF

T3

T2
R3
R2
M3
N2

L3
M2

T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11

G3

F2

F3

E2
C3
C2

B3

B2

H10

G9
G4

L4

K2
M9

K11

L9

K10
H11

K9
M4

K3
H2

K4

F9
H9
H3

F4
H4
J10

J11

P3

P10
D10

D3

P2

P11
D11

D2
N3

N10
E10

E3

V9

A4

H1

H12

U502

DQ31 | DQ23
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8

BA2 | RAS
BA1 | BA0
BA0 | BA1

A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4

CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK

CK
RDQS3 | RDQS2

RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1

WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1

DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1

RESET
ZQ

VREF
VREF#H12

23CC1287SB12

23CC1287SB12

+MVDD

VDDQ

VDDQ#A12

VDDQ#C1
VDDQ#C4
VDDQ#C9

VDDQ#C12

VDDQ#E1
VDDQ#E4
VDDQ#E9

VDDQ#E12

VDDQ#J4

VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9

VDDQ#N12

VDDQ#R1
VDDQ#R4
VDDQ#R9

VDDQ#R12

VDDQ#V1

VDDQ#V12

VDD#A11

VDD#F1

VDD#F12

VDD#M1

VDD#M12

VDD#V2

VDD#V11

VSSQ
VSSQ#B4
VSSQ#B9

VSSQ#B12

VSSQ#D1
VSSQ#D4
VSSQ#D9

VSSQ#D12

VSSQ#G2

VSSQ#G11

VSSQ#L2

VSSQ#L11

VSSQ#P1
VSSQ#P4
VSSQ#P9

VSSQ#P12

VSSQ#T1
VSSQ#T4
VSSQ#T9

VSSQ#T12

VSS#A10

VSS#G1

VSS#G12

VSS#L1

VSS#L12

VSS#V3

VSS#V10

VDDA

VDDA#K12

VSSA#J12

VSSA

RFU2

RFU1

RFU0

GND | VDD

GND | VDD

C583

C583

10uF_X6S

10uF_X6S

MC583

MC583

4.7uF_6.3V

4.7uF_6.3V

Overlap footprints

C592

C592
10nF

10nF

C593

C593
10nF

10nF

B501B501
B502B502

+MVDD

+MVDD+MVDD

+MVDD

R508

R508

2.37K

2.37K

R509

R509

5.49K

5.49K

R510

R510

2.37K

2.37K

R511

R511

5.49K

5.49K

RASB1b(5,8)

CASB1b(5,8)
CKEB1(5,8)

CSB1b_1(5)
WEB1b(5,8)
CLKB1b(5,8)

CLKB1(5,8)

DRAM_RST(5,8)DRAM_RST(5,8)

C588

C588
100nF_6.3V

100nF_6.3V

+MVDD

DQB_55
DQB_53
DQB_52
DQB_48
DQB_54
DQB_51
DQB_49
DQB_50
DQB_57
DQB_61
DQB_63
DQB_60
DQB_56
DQB_59
DQB_58
DQB_62
DQB_32
DQB_35
DQB_33
DQB_34
DQB_38
DQB_36
DQB_39
DQB_37
DQB_47

DQB_41
DQB_45
DQB_44
DQB_43
DQB_40
DQB_42

QSB_6
QSB_7
QSB_4
QSB_5

QSBb_6
QSBb_7
QSBb_4
QSBb_5

DQMBb_6
DQMBb_7
DQMBb_4
DQMBb_5

C590

C590
100nF_6.3V

100nF_6.3V

+MVDD

C552

C551

C551
100nF_6.3V

100nF_6.3V

C562

C562
1uF_6.3V

1uF_6.3V

C552
100nF_6.3V

100nF_6.3V

C563

C563
1uF_6.3V

1uF_6.3V

C553

C553
100nF_6.3V

100nF_6.3V

C564

C564
1uF_6.3V

1uF_6.3V

C554

C554
100nF_6.3V

100nF_6.3V

C565

C565
1uF_6.3V

1uF_6.3V

C555

C555
100nF_6.3V

100nF_6.3V

C566

C566
1uF_6.3V

1uF_6.3V

C556

C556
100nF_6.3V

100nF_6.3V

C567

C567
1uF_6.3V

1uF_6.3V

C557

C557
100nF_6.3V

100nF_6.3V

C568

C568
1uF_6.3V

1uF_6.3V

+MVDD

C575

C574

C574
100nF_6.3V

100nF_6.3V

C579

C579
1uF_6.3V

1uF_6.3V

C575
100nF_6.3V

100nF_6.3V

C580

C580
1uF_6.3V

1uF_6.3V

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

921

of

921

of

921

1

C573

C573
100nF_6.3V

100nF_6.3V

C578

C578
1uF_6.3V

1uF_6.3V

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 1

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 1

RV635 GDDR3 - MEM CH A&B 128-bit 256MB RANK 1

VDD

VSS

MF

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

A2
A11
F1
F12
M1
M12
V2
V11

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10

K1
K12

J12
J1

J3
J2
V4

A9

C584

C584
10uF_X6S

10uF_X6S

MC584

MC584

4.7uF_6.3V

4.7uF_6.3V

C558

C558
100nF_6.3V

100nF_6.3V

C569

C569
1uF_6.3V

1uF_6.3V

Doc No.

Doc No.

Doc No.

+MVDD

+MVDD

C594

C594
100nF_6.3V

100nF_6.3V

+MVDD

C585

C585
10uF_X6S

10uF_X6S

MC585

MC585

4.7uF_6.3V

4.7uF_6.3V

C559

C559
100nF_6.3V

100nF_6.3V

C570

C570
1uF_6.3V

1uF_6.3V

105-B380xx-00

105-B380xx-00

105-B380xx-00

C595

C595
10nF

10nF

C586

C586
10uF_X6S

10uF_X6S

MC586

MC586

4.7uF_6.3V

4.7uF_6.3V

C560

C560
100nF_6.3V

100nF_6.3V

C571

C571
1uF_6.3V

1uF_6.3V

RevDate:

RevDate:

RevDate:

+MVDD

B551B551
B552B552

+MVDD

C561

C561
100nF_6.3V

100nF_6.3V

C572

C572
1uF_6.3V

1uF_6.3V

1

1

1

www.vinafix.vn

8

D D

+PW_VDDC_HGDR

UGATE(11)

+PW_VDDC_M

PHASE(11)

+PW_VDDC_LGDR

LGATE(11)

VDDC2_FB(13)

+VDDC_B

C C

+PW_VDDC_HGD

+PW_VDDC_LGD

R1315

R1315

42.2K

42.2K

place R1315 close to IC pin4

U1303

U1303

1

BOOT

2

UGATE

3

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

VDDC_FB

FB

8
7
6
5

+PW_VDDC_M
VDDC_COMP

VDDC_FB

7

+VDD_VCC

C1303

C1303

0.22uF

0.22uF

+PW_VDDC_LGD

VDDC_EN (11)

R1308 20KR1308 20K

+PW_VDDC_HGD +PW_VDDC_HGDR

+PW_VDDC_M

+PW_VDDC_LGDR

R13220RR1322

603

0R

402

6

R1321 0RR1321 0R

402

Q1302

Q1302

QL

4 5
3
2
1

BSC119N03SG

BSC119N03SG

Thermal

Thermal

Pad

Pad

Q1301

Q1301

QH

4 5
3
2
1

BSC119N03SG

BSC119N03SG

9

6
7
8

Thermal

Thermal

Pad

Pad

RC snubber values shown
are for reference only,
tuning is required

5

9

6
7
8

Place Rs and Cs across QL

VDDC_FB

ML1301

ML1301

1 2

L1301

L1301

1 2

R1319

R1319
33MOHM

33MOHM

1210
1%

C1308

C1308
10nF_25V

10nF_25V

402
X7R
25V

PCMC104T-1R5MN

PCMC104T-1R5MN

1.7UH

1.7UH

Rs

Cs

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

MULTI FOOTPRINT

12

NS1300

NS1300
NS_VIA

NS_VIA

Rt2

RFB1
R1311

R1311
10K

10K

402
1%

4

C1313

C1313

3.9nF

3.9nF

402
10%

R1313

R1313

3.65K

3.65K

402
5%

Place R1 and
R4 close to
PWM and
routed with
separate
20mil trace to
the ASIC

3

+12V_BUS

C1395

C1395

100uF_16V

C1343

C1343
10UF_16V

10UF_16V

1206

100uF_16V
SM 6.3mm Dia

C1344

C1344
180uF_16V

180uF_16V

SM 10mm Dia

Overlap

L1322

L1322

L1323

R13200RR1320

R13180RR1318
0R

0R

C1349

C1349

C1339

C1339

4.7uF_16V

4.7uF_16V

4.7uF_16V

4.7uF_16V

805

805

16V
X7R

L1323

B1301

0.47uH_17.5A

0.47uH_17.5A

C1337

C1337

4.7uF_16V

4.7uF_16V

C1324

C1324

Y5V

10uf

10uf

1206

B1301
60R_6A

60R_6A

C1330

C1330
10UF_16V

10UF_16V

1206805805

Mirrored on PCB

+VDDC

IND_0.47uH_7A

IND_0.47uH_7A

Overlap

C1340

C1340

4.7uF_16V

4.7uF_16V

Mirrored on PCBMirrored on PCB Overlap

C1323

C1323

Y5V

10uf

10uf

6.3V

1206 6.3V

Mirrored on PCB

2

+VDDC_Source

C1382

C1382
270uF_16V

270uF_16V

TH 10mm Dia

+VDDC +VDDC +VDDC

***

C1325

C1325
1500uF_2.5V

1500uF_2.5V

***

***

MC1325

MC1325
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT 8 x 8 mm, TH

***

NC1325

NC1325
820uF_2.5V

820uF_2.5V

***

1

+PW_VDDC_HGDR

MQ1301

MQ1301

+VDDC_Source

Thermal

Thermal

Pad

Pad

B B

+PW_VDDC_M

COMPENSATION CIRCUIT FILTERED SMPS VCC

402

VDDC_COMP

C1312

C1312

C1314

390pF

390pF

603

50V

NPOX7R

5%

R1314 0RR1314 0R

R13090RR1309
0R

share pad of R1314,R1309

8

C1314
100nF

100nF

402
X5R

10V
10%

VDDC_FB

+VDD_VCC

7

+12V_BUS

C1307

C1307
100nF

100nF

603
X7R
5%

C1311

C1311
15nF

15nF

402

A A

R1312

R1312

2.94K

2.94K

402
1%

10V
10%

BOOT CIRCUIT

3

D1301

D1301

1

2

BAT54A

BAT54A

C1305

C1305
100nF

100nF

603 X7R

16V

5%

6

+12V_BUS

+VDDC_B

C1306

C1306
150nF_16V

150nF_16V

4 5
3
2
1

FDS7096N3

FDS7096N3

+PW_VDDC_M

9

6
7
8

5

+PW_VDDC_LGDR

MQ1302

MQ1302

Thermal

Thermal

4 5
3
2
1

FDS7096N3

FDS7096N3

Pad

Pad

9

6
7
8

4

MULTI FOOTPRINT

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - VDDC SMPS 01

RV635 GDDR3 - VDDC SMPS 01

3

RV635 GDDR3 - VDDC SMPS 01

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

10 21

of

10 21

of

10 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

D D

C C

UGATE1

UGATE(10)

PHASE1

PHASE(10)

LGATE1

LGATE(10)

B B

R6090RR609
0R

C635

C635

4.7uF_16V

4.7uF_16V

Mirrored on PCB

678

9

Q601

Q601

Pad

Pad

Thermal

Thermal

123

4 5

UGATE1

BSC119N03SG

BSC119N03SG

PHASE1

A A

Q603

Q603

BSC042N03S

BSC042N03S

LGATE1

567

8

9

432

1

L621

L621
IND_0.47uH_7A

IND_0.47uH_7A

R6080RR608
0R

Overlap

C632

C632

C634

C634

4.7uF_16V

4.7uF_16V

4.7uF_16V

4.7uF_16V

805805

Mirrored on PCB

Actual Vendor TBD Actual Vendor TBD

Q604

Q604

BSC042N03S

BSC042N03S

LGATE1

8

+12V_BUS

+12V_BUS

L620

L620

0.47uH_17.5A

0.47uH_17.5A

C633

C633

C621

C621

4.7uF_16V

4.7uF_16V

10UF_16V

10UF_16V

805805

Mirrored on PCB

567

8

9

R607R607 R615

432

1

7

R666

R666

12.1K

12.1K
VDDC_EN

VDDC_EN (10)

R6670RR667
0R

VDDC_SHDN_N EN1

VDDC_SHDN_N(18)

EN1_N(13)

C690

C690

100uF

100uF

SM 6.3mm Dia

B600

B600
60R_6A

60R_6A

C622

C622

C623

C623

10UF_16V

10UF_16V

180uF_16V

180uF_16V

12061206

SM 10mm Dia SM 10mm Dia

L601

L601

1 2

PCMB105T-R47MS

PCMB105T-R47MS

ML601

ML601

220nH_31A

220nH_31A

NL601

NL601

1 2

HC1018

HC1018

KL601

KL601

1 2

1.7UH

1.7UH

R604

R604

4.87K

4.87K

1/10W
0603

C604

C604

X7R

100nF

100nF

R602R602

FB_S

CSP1

7

EN1_N

+VDDC_Source

C680

C680
270uF_16V

270uF_16V

TH 10mm Dia

Overlap

+VDDC

Overlap Overlap

R605

R605

R615

681R

681R

681R

681R

CSN1

6

12V Bus power for 12V
Gate Drive

+12V_BUS +12V_BUS

R670

R670
10R

10R

402

R6980RR698
0R

1

Q679

Q679
MMBT3904

MMBT3904

2 3

C681

C681
270uF_16V

270uF_16V
TH 10mm Dia

Overlap

L611

L611

12

PCMB105T-R47MS

PCMB105T-R47MS

ML611

ML611

220nH_31A

220nH_31A

NL611

NL611

12

HC1018

HC1018

KL611

KL611

12

1.7UH

1.7UH

CSN2

R614

R614

4.87K

4.87K

1/10W
0603

C614

C614

X7R

100nF

100nF

R612R612

CSP2

6

Choosing Different Gate Drive

5V Gate Drive R630, R670, C660,

8V Gate Drive R631, R632,

12V Gate Drive R630, C660,

Pass Transistor Circuit for 8V Gate Drive

This circuit is only for 8V
gate drive application

C626

C626
180uF_16V

180uF_16V

R617R617

FB_S

Assume VCC consumes 200mA total including
5VCC providing buffered output sourcing a
minimum 20mA requirement

P(Q_8VCC)max = (12V-8V)*0.2A = 800mW

32

R661

R661

Q661

Q661

10K

10K

1

SI2304DS

SI2304DS

VCC

EN1 VCCDRV

R6990R R6990R
R6860R R6860R
R6850R R6850R
R6840R R6840R

C625

C625
10UF_16V

10UF_16V

1206

Mirrored on PCB

678

9

Q611

Q611

Thermal

Thermal

Pad

Pad

123

4 5

UGATE2

BSC119N03SG

BSC119N03SG

567

8

9

Q613

Q613

BSC042N03S

BSC042N03S

432

1

Populate Do Not PopulateGate Drive

R631, R632

R630, C660,
R661, Q661

R670

VDDC_EN

SS_ICOMP

VDDC_REFIN_EN

C624

C624

C627

C627

10UF_16V

10UF_16V

4.7uF_16V

4.7uF_16V

Mirrored on PCB

R661, Q661

R670

R631, R632,
R661, Q661

VCCDRV

C628

C628

4.7uF_16V

4.7uF_16V

805805

8

1

5

D611

D611

3

OPTIONAL

BAT54A

BAT54A

LGATE2

R664

R664

Rdroop

100K

100K

Droop Option

C670

C670
10UF

10UF

C694

C694

1206

1UF_16V

1UF_16V

X5R

X7R

16V

C629

C629

4.7uF_16V

4.7uF_16V

805

Mirrored on PCB

PHASE2

567

9

Q614

Q614

BSC042N03S

BSC042N03S

432

LGATE2LGATE2

5

LGATE1

603

D601

D601

3

OPTIONAL

BAT54A

BAT54A

Populate - For 5V Gate Drive application
Remove - For 8V or 12V Gate Drive application

C631

C631

4.7uF_16V

4.7uF_16V

8051206

+VDDC +VDDC

Overlap

Overlap

2

1

C612

C612
1uF

1uF

PHASE2

R6130RR613
0R

VCC

R6030RR603
0R

PHASE1

C602

C602
1uF

1uF

1

2

***

C641

C641
1500uF_2.5V

1500uF_2.5V

***

***

C642

C642
1500uF_2.5V

1500uF_2.5V

***

TP601

TP601
35mil

35mil

UGATE1

UGATE2

19

20

21

22

23

24
25

26
27
28
29

4

POK > 1 used to control
other on-board enables

PWRGD1

R634 10KR634 10K

R6110RR611
0R

U601

U601

uPI6201AQ

uPI6201AQ

PHASE2

LGATE2

VCCDRV/DROOP

VCC

LGATE1

PHASE1
PGND

PGND26
PGND27
PGND28
PGND29

R601 0RR601 0R

R632R632

***

MC641

MC641
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

+VDDC+VDDC

***

MC642

MC642
1000uF_5mR

1000uF_5mR

***

SP/POSCAP, SMT8 mm Dia, SMT

4

17

18

UGATE2

UGATE11BOOT125VCC3AGND4BUSEN5CSP1

+VDDC

+VDDC

BOOT2

5VCC

***

NC641

NC641
820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

***

NC642

NC642
820uF_2.5V

820uF_2.5V

***

8 x 8 mm, TH

16

REFOUT/POK

3

External Reference is used when
REFIN is driven by voltage ranged
from 0.4V to 3.3V

VDDC_REFIN_EN

C659

C659
100nF

100nF

402

DNI

10V

Overlap the footprints
for MR655 and C655

Current

PGND Option

Compensation

Css if
current

C655

comp.
not
used

SS_ICOMP

14

SS/ICOMP

COMP/DROOP

IOUT/IMAX/DROOP

C671

C671
100nF

100nF

402 10V
X5R

+5V

C646

C646

Y5V

10uf

10uf

1206 6.3V

3

C655
47nF_16V

47nF_16V

402
25V

13

FB

RT

CSP2

CSN2

CSN1

6

VDDC_EN

R6310RR631
0R

C647

C647

Y5V

10uf

10uf

1206 6.3V

MR6550RMR655

0R

15

REFIN/EN

C660

C660
1uF_6.3V

1uF_6.3V

402

6.3V

Y5V

5VCC applied externally or generated internally from the IC, must

be in regulation before IC start soft-start sequence.

For 5V Gate Drive application

External filtered +5V_EXT
is applied to this pin

+VDDC

C645

C645

Y5V

10uf

10uf

6.3V

1206 6.3V

R6361KR636
1K

R654

R654
150R

150R

402

402

6.3V

C654

C654
470nF_6.3V

470nF_6.3V

FB

C607

C607
220pF_50V

220pF_50V

12

R_RT

R655

R655

402

30.1K

30.1K

11

10

C638

C638
100nF

100nF

402 10V
X5R

9

C613

C613

X7R402
50V

1nF

1nF

8

R616R616

7

R606R606

C603

C603

X7R402
50V

1nF

1nF

+VDDC

C648

C648

Y5V

10uf

10uf

1206

2

5VCC

Internal Reference is
used when REFIN is
pull-up to > 4.5V

Share Pad with R639

VDDC1_FB

FB_S

R6580RR658
0R

+VDDC

12

NS600

NS600
NS_VIA

NS_VIA

Type III compensation

R3

R653

R653

2.67K

2.67K

402

R651

R651

5.11K

5.11K

402 C3

C653

C653

Rt1

2.2nF_50V

2.2nF_50V

402

X7R
50V

R6560RR656

COMP_FB

0R

R663

R663
100K

100K

Rdroop

Droop Option

Iout

Iout (13)

R6620RR662
0R

Rdroop

CSP2

CSN2

CSN1

CSP1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

R696

R696

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

300R

300R

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

805

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - VDDC SMPS 02

RV635 GDDR3 - VDDC SMPS 02

RV635 GDDR3 - VDDC SMPS 02

2

X7R
10V

COMP_GND

R6570RR657
0R

R2

R652

R652
15K

15K

402

C2 C1

C652

C652
10nF

10nF

402

C651

C651
33pF_50V

33pF_50V

402

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Sheet

Sheet

Sheet

VDDC1_FB (13)

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

of

11 21

of

11 21

of

11 21

1

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

7

6

5

4

3

2

+VDDC_Source

1

Thermal

Thermal

Pad

Pad

+MVDDC_S

9

6
7
8

RC snubber values shown
are for reference only,
tuning is required

MVDDC_FB

C715

C715
10UF

10UF

on PCB

CAP CER 10UF 20% 16V X5R
(1206)1.8MM H MAX

NL701 PCMC063T-2R2MNNL701 PCMC063T-2R2MN

1 2

ML701 HAH1030-R47-RML701 HAH1030-R47-R

1 2

L701 2.2uH_13AL701 2.2uH_13A

1 2

R719

R719
33MOHM

33MOHM

1210
1%

C708

C708
10nF_25V

10nF_25V

402
X7R
25V

Place Rs and Cs across QL

C716

C716
10UF

10UF

12061206

Rs

Cs

C717

C717

4.7uF_16V

4.7uF_16V

805

Use16V 0805 MLCCMirrored
Mirrored on PCB

Overlap

C713

C713

1.8nF_50V

1.8nF_50V

402
10%

Rt

RFB1

R713

R713

R711

R711

7.87K

7.87K

10K

10K

402

402

5%

1%

Place R1 and
R3 close to
PWM and
routed with
separate
20mil trace to
the ASIC

0.8V Ref

R4 = (R1 x 0.8V) / (Vout1 - 0.8V)

C719

C719

4.7uF_16V

4.7uF_16V

805

16V
X7R

R7240RR724
0R

C718

C718
150nF_16V

150nF_16V

603

Q701

Q701

QH

+PW_MVDDC_HGD

D D

C703

C703

0.22uF

0.22uF

MVDD_EN (13)

R708 20KR708 20K

+PW_MVDDC_M

402

+PW_MVDDC_LGD

+PW_MVDDC_LGDR

R7220RR722

603

0R

+MVDDC_B

U703

U703

1

BOOT

2

UGATE

3

+PW_MVDDC_LGD

R715

R715

42.2K

42.2K

C C

GND
LGATE4VCC

APW7065

APW7065

PHASE

COMP

FB

8
7
6
5

+PW_MVDDC_M
MVDDC_COMP+PW_MVDDC_HGD

MVDDC_FB

+MVDD_VCC

R721 0RR721 0R

+PW_MVDDC_HGDR

402

QL

4 5
3
2
1

Q702

Q702

Thermal

Thermal

Pad

Pad

BSC119N03SG

BSC119N03SG

MVDDC_FB(13)

4 5
3
2
1

BSC119N03SG

BSC119N03SG

9

6
7
8

***

C725

C725
470uF_10V

470uF_10V

***

Over Lap

L702

L702

IND_0.47uH_7A

IND_0.47uH_7A

Overlap

TH 10mm Dia SM 10mm Dia

Overlap

***

MC725

MC725
470uF_6.3V

470uF_6.3V

***

ALT POLY

ML702

ML702

0.47uH_17.5A

0.47uH_17.5A

Find 100nH
SM Alt. IND

C731

C731
270uF_16V

270uF_16V

KC725

KC725
330uF_2.5V

330uF_2.5V
TAN LP

25mOHM

B701

B701
60R_6A

60R_6A

C732

C732
180uF_16V

180uF_16V

*** ***

C723

C723
100uF_6.3V

100uF_6.3V

1210 1210

*** ***

Over Lap

C730

C730

100uF

100uF

MC723

MC723
330uF_2.5V

330uF_2.5V
TAN LP

25mOHM

+MVDD

C724

C724
100uF_6.3V

100uF_6.3V

+PW_MVDDC_LGDR

MQ702

MQ702

Thermal

Thermal

Pad

Pad

9

4 5
3

6

2

7

1

8

FDS7096N3

FDS7096N3

4

MULTI FOOTPRINT
For SO-8

3

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - MVDD SMPS 01

RV635 GDDR3 - MVDD SMPS 01

RV635 GDDR3 - MVDD SMPS 01

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

12 21

of

12 21

of

12 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

+PW_MVDDC_M

+PW_MVDDC_HGDR

MQ701

MQ701

Thermal

Thermal

Pad

Pad

4 5
3
2
1

FDS7096N3

FDS7096N3

+PW_MVDDC_M

5

+MVDDC_S

9

6
7
8

B B

COMPENSATION CIRCUIT

402

C712

C712
120pF_50V

120pF_50V

50V

603

5%

NPO

R714 0RR714 0R

R7090RR709
0R

MVDDC_COMP

C714

C714
100nF

100nF

402

10V

X5R

10%

MVDDC_FB

C711

A A

C711

6.8nF_25V

6.8nF_25V

402

10V

X7R

10%

R712

R712

8.06K

8.06K

402
1%

8

FILTERED SMPS VCC BOOT CIRCUIT

+MVDD_VCC

7

+12V_BUS

C707

C707
100nF

100nF

603
X7R
5%

6

D701

D701

1

BAT54A

BAT54A

3

C705

C705
100nF

100nF

603 X7R
5%

2

16V

+12V_BUS

+MVDDC_B

402

C706

C706
150nF_16V

150nF_16V

www.vinafix.vn

5

4

3

2

1

Power up Sequencing

+12V_BUS

+12V_BUS

R687

R687
10K

+3.3V_BUS

2.2K

2.2K
R680

R680

R6811KR681
1K

10K

R6881KR688
1K

R689

R689

R6971KR697

1K

5.1K

5.1K

D D

R682

R682

5.1K

5.1K

EN1_N

R683 5.1KR683 5.1K

BUS_RAILS_UP_N

C636

C636

R690 5.1KR690 5.1K

1

Q677

Q677
MMBT3904

MMBT3904

2 3

100nF

100nF

MMBT3904

MMBT3904

1

Q678

Q678

2 3

EN1_N (11)

BUS_RAILS_UP_N (18)

PWRCNTL_1 PWRCNTL_0

GPIO_15GPIO_20

0

1

Vout = Vref * (1+Rt/Rb)
VDDC1 (Dual Phase): Vref = 0.6V, Rt = 5.11K
VDDC2 (Single Phase): Vref = 0.8V, Rt = 10K
MVDDC (Single Phase): Vref = 0.8V, Rt = 10K

VDDC Voltage Settings Using GPIOs (for VDDC1 Dual Phase)

Rf1=42.2K Rf2=20.5K Rf1=

0

10

01

1

0.90V

1.00V

1.15V

1.25V

VDDC Enable Circuit

+3.3V_BUS

+VDDC +12V_BUS

R843

R843

5.1K

C C

R8411KR841
1K

C841

C841
1uF_6.3V

1uF_6.3V

5.1K

5%

Q840

Q840

1

MMBT3904

MMBT3904

2 3

R844 5.1KR844 5.1K

DNI

R846 5.1KR846 5.1K

5%

5%

5.1K

5.1K
R845

R845

LDO1_3_EN

Q841

Q841

1

MMBT3904

MMBT3904

2 3

Q842

Q842

1

MMBT3904

MMBT3904

2 3

LDO1_3_EN (14)

MVDD_EN (12)

PWRCNTL_0(7)

PWRCNTL_1(7)

+3.3V

+3.3V

R1240

R1240
10K

10K

R1241

R1241
10K

10K

Power Play

Output Voltage (V)

Rf2=

R1244

R1244

Rf1 Rf2

30.1K

30.1K

32

1

Q1242

Q1242
BSH111

BSH111

Rf1=
Rf2=

Power-up Default

Share Pad

R1246 0RR1246 0R

R1247 0RR1247 0R

R1245

R1245
12K4

12K4

Resistors to set the output
voltages for +VDDC and +MVDDC

32

Q1240

Q1240
BSH111

BSH111

1

Rb1

R650

R650

10.2K

10.2K

402
RFB2

Rb

RFB2
R710

R710

7.15K

7.15K

402
1%

VDDC1_FB (11)

VDDC2_FB (10)

Rb2

RFB2
R1310

R1310

3.24K

3.24K

402
1%

MVDDC_FB (12)

U1200

+3.3V_BUS +3.3V

Q845

+12V_BUS

C842

C842
10uF_X6S

R849

R849
10K

10K

Q844

Q844

MMBT3904

MMBT3904

2 3

OSC_EN (3,14)

10uF_X6S

C843

C843
100NF

100NF

402
X5R
16V

R848

R848
100K

100K

B B

+1.8V

R847 10KR847 10K

LDO1_POK(3,14)

A A

C844

C844
1uF_6.3V

1uF_6.3V

LDO1_POK

1

5

Q843

Q843
MMBT3904

MMBT3904

2 3

+3.3V

R899

R899

5.1K

5.1K

1

3 2

1

Q845

SI2304DS

SI2304DS

LVT_EN (3)

4

R840

R840
100K

100K

3

DDC2DATA(3,18)

DCC to control VDDC1 and MVDD Voltage.

132­For Testing purposes only

DDC2DATA
DDC2CLK

DDC2CLK(3,18)

+3.3V_BUS

R1202

R1202

1.8R

1.8R
C1201

C1201
10uF

10uF

Iout

Temp Comp

R693

R693

9.09K

9.09K

RpRsRT

R694

R694

9.09K

9.09K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - Power Management

RV635 GDDR3 - Power Management

2

RV635 GDDR3 - Power Management

R1200

R1200
200R

200R
R1201

R1201
200R

200R
R12070RR1207
0R
R12080RR1208
0R

C1200

C1200
100nF_6.3V

100nF_6.3V

Requi

U1200

1

SDA

2

SCL
A111NC#12

9

A0

13

VCC

15

EPAD

3

GND

DS4402

DS4402

OUT0
OUT1

NC#14

NC#4
NC#5

CUR_ADJ_0

8

CUR_ADJ_1

10
12
14

4
5
6

FS1

7

FS0

Buffered VDDC Output Current Monitoring

+12V_BUS

Place caps very
close to power pin

C692

C692
100nF

100nF

603
X7R

1

+

+

3

-

­2 5

R6911KR691
1K

1%

12V Supply Voltage single Op-Amp (U611) :

1. National LM321, SOT23-5, ATI PN - TBD

2. TI alternate? ATI PN - TBD

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

R695

R695

9.09K

9.09K

R6400RR640

Iout(11)

0R

C657

C657
1nF

1nF

X7R

402

50V

R1205 0RR1205 0R
R1209 0RR1209 0R

share pad

R1206 0RR1206 0R

R1203

R1203
127K

127K
R1204

R1204

63.4K

63.4K

C691

C691
100nF

100nF

603

U611

U611

X7R

4

LM321MF_NOPB

LM321MF_NOPB

of

13 21

of

13 21

of

13 21

C693

C693
10nF

10nF

1%

1

VDDC1_FB (11)
VDDC2_FB (10)

MVDDC_FB (12)

TP603

TP603
TP_32mil_SM_top

TP_32mil_SM_top

J601

J601

2 1

header_1x2_2mm_smt

header_1x2_2mm_smt

R692

R692

30.1K

30.1K

Doc No.

Doc No.

Doc No.

105-B380xx-00

105-B380xx-00

105-B380xx-00

RevDate:

RevDate:

RevDate:

1

1

1

www.vinafix.vn

8

7

6

5

4

3

2

1

Regulators for +5V, +5V_VESA and +5V_VESA2

+12V_BUS

MR811

1206

1/4W

R811

R811
47R

47R

MR811
27R

27R

0805

1/8W

MU810

MU810
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

1

U810

U810

1

VIN

VOUT#2

5

NC

VOUT#3

8

NC#8

VOUT#6

ADJ4VOUT

LM317LCDR

LM317LCDR

+5V_VESA

3

GND

2
3

R813

R813

6

499R

499R

7

0402

R1

C811

C811

1uF_6.3V

1uF_6.3V

R814

R814

1.5K

1.5K

0402

R2

MR812

MR812

R812

R812

27R

27R

47R

47R

0805

1206

1/4W

D D

5%

C810

C810
100nF

100nF

0603
16V

1/8W

5%

Vout(V) = Vref (1+R2/R1)

LDO #1:
PCB: 50 to 70mm sq. copper area for cooling

+3.3V_BUS

C C

LDO1_3_EN(13)

LDO #3: Vout = +1.1V +/- 2%

LDO1_POK(3,13)

1206
Use 0.5R

R878

R878

0.50R

0.50R

LDO1_VIN

LDO1_POK
LDO1_EN

10uF_X6S

10uF_X6S

C876

C876

TP871TP871

TP870TP870

+5V

LDO1_POK

C878

C878
1uF_6.3V

1uF_6.3V

U871

U871

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

8
7

FB

6
5
9

R876 0RR876 0R

DNI

+1.8V_LDO1

Vin = +1.45V to 2.0VMAX Iout = 1.4A (TBV) RMS MAX

Iout = 0.8A (TBV) RMS MAXVout = +1.8V +/- 2%Vin = 2.1V to 3.6V MAX

+1.8V_LDO1

R875

R875
12K4

12K4

LDO1_FB

R874

R874
10K

10K

0402

0.1%

VOUT = Vref x (1 + R5/R4)

R5

R4

C875

C875
33pF_50V

33pF_50V

C3

C873

C873
22uF_16V

22uF_16V

DNIDNI

C872

C872
10uF_X6S

10uF_X6S

C871

C871
10uF_X6S

10uF_X6S

Overlap footprints

B869

B869

220R_2A

220R_2A

MR8690RMR869
0R

R8690RR869
0R

THIS RESISTOR IS FOR

C874

C874
100nF

100nF

CURRENT MEASUREMENT

+1.8V+MVDD

PCB: 50 to 70mm sq. copper area for cooling

B B

+MVDD

LDO1_3_EN(13)

1210
Use 0R

R858

R858

0.1R

0.1R

LDO3_VIN

LDO3_EN

10uF_X6S

10uF_X6S

C856

C856

TP851TP851

TP850TP850

LDO3_POK

C858

C858
1uF_6.3V

1uF_6.3V

U851

U851

1

POK

2

EN

3

VIN
CNTL4REFIN

uP7706U8

uP7706U8

GND#8

VOUT

GND#9

+1.1V+5V +1.1V

R855

R855

3.92K

8
7

FB

6

R856 0RR856 0R

5

DNI

9

LDO3_FB

3.92K

R854

R854
10K

10K

0.1%

R5

R4

C855

C855
33pF_50V

33pF_50V

C3

C853

C853
22uF_16V

22uF_16V

DNIDNI

C852

C852
10uF_X6S

10uF_X6S

C851

C851
10uF_X6S

10uF_X6S

C854

C854
100nF

100nF

VOUT = Vref x (1 + R5/R4)

+12V_BUS

MR832

MR832

R832

1206

1/4W

5%

C830

C830
100nF

100nF

0603
16V

R832
47R

47R

27R

27R

0805

1/8W

5%

R831

R831
47R

47R

1206

1/4W

5%

Vout(V) = Vref (1+R2/R1)

+5V_VESA

MR831

MR831
27R

27R

0805

1/8W

5%

MU830

MU830
MCP1702T-5002E/MB

MCP1702T-5002E/MB

IN2OUT

1

U830

U830

1

VIN

VOUT#2

5

NC

VOUT#3

8

NC#8

VOUT#6

ADJ4VOUT

LM317LCDR

LM317LCDR

R833

R833
499R

499R

0402

R1

R834

R834

1.5K

1.5K

0402

R2

1uF_6.3V

1uF_6.3V

C831

C831

+5V

3

GND

2
3
6
7

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - Linear Regulators

RV635 GDDR3 - Linear Regulators

8

7

6

5

4

3

RV635 GDDR3 - Linear Regulators

2

R8350RR835

0R

+5V

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

14 21

of

14 21

of

14 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

7

6

5

4

3

2

1

A_R_DAC1_M

L1001

A_DAC1_R(3)

A_DAC1_RB(3)

A_DAC1_G(3)

D D

C C

B B

A_DAC1_GB(3)

A_DAC1_B(3)

A_DAC1_BB(3)

CRT1DDCDATA(3)

CRT1DDCCLK(3)

HSYNC_DAC1(3,7)

VSYNC_DAC1(3,7)

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

R1027 37.4RR1027 37.4R

R1028 37.4RR1028 37.4R

R1029 37.4RR1029 37.4R

RV635: 10K pull up on 3.3V, 2.2K pull up on 5V
RV630: 24.3K pull up on 3.3V, 19.1K on 5V

+3.3V

R1004

R1004
10K

10K

+3.3V +5V

R1007

R1007
10K

10K

+5V

C1999

C1999
100nF_6.3V

100nF_6.3V

U1999A

U1999A

14

2 3

74VHC125

74VHC125

1

7

U1999B

U1999B

4

5 6

74VHC125

74VHC125

C1004

C1004

R1001

R1001

8.0pF

8.0pF

75R

75R

R1002

R1002

C1005

C1005

8.0pF

8.0pF

75R

75R

R1003

R1003

C1006

C1006

8.0pF

8.0pF

75R

75R

Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane.

+5V

1

32

BSH111

BSH111
Q1001

Q1001

1

32

BSH111

BSH111
Q1002

Q1002

HSYNC_DAC1_B

VSYNC_DAC1_B

L1001
47nH

47nH

C1001

L1002

L1002
47nH

47nH

L1003

L1003
47nH

47nH

C1001
12pF_50V

12pF_50V

A_G_DAC1_M

C1002

C1002
12pF_50V

12pF_50V

A_B_DAC1_M

C1003

C1003
12pF_50V

12pF_50V

R1006 33RR1006 33R

R1009 33RR1009 33R

R1010

R1010

R1011

R1011

10R

10R

10R

10R

R1024 0RR1024 0R

R1025 0RR1025 0R

R1026 0RR1026 0R

R1005

R1005

2.2K

2.2K
DDCDATA_DAC1_5V DDCDATA_DAC1_R

R1008

R1008

2.2K

2.2K
DDCCLK_DAC1_5V

L1004

L1004
36NH

36NH

L1005

L1005
36NH

36NH

L1006

L1006
36NH

36NH

DDCCLK_DAC1_R

HSYNC_DAC1_R

VSYNC_DAC1_R

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F

DDCDATA_DAC1_R
DDCCLK_DAC1_R
HSYNC_DAC1_R

VSYNC_DAC1_R

HPD2(7)

For ESD ProtectionSee BOM for qualified filters

Q1021

Q1021

MMBT3904

MMBT3904

+3.3V

2 3

R1023

R1023
10K

10K

R1022 10KR1022 10K

1

+3.3V

4
5
6

D1001

D1001

CH3
Vp
CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

T2X2M(3)
T2X2P(3)

T2X4M(3)
T2X4P(3)

T2X1M(3)
T2X1P(3)

T2X3M(3)
T2X3P(3)

T2X0M(3)
T2X0P(3)

T2X5M(3)
T2X5P(3)

T2XCP(3)
T2XCM(3)

+5V_VESA

4
5
6

DDCCLK_DAC1_R
DDCDATA_DAC1_R
VSYNC_DAC1_R

HPD_DVI2

A_R_DAC1_F
A_G_DAC1_F
A_B_DAC1_F
HSYNC_DAC1_R

D1002

D1002

CH3
Vp
CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA

C1010

C1010
68pF

68pF

603

DB15 pin

Standard VGA

DDC1 Host

Monitor ID bit 0

11
12
4
15

9

Hardware
Support

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

Monitor ID bit 0

Monitor ID bit 1

Data from display

Monitor ID bit 2

Monitor ID bit 2

Monitor ID bit 3

Open
+5V

N/C

50mA min

Mechanical Key

1A max

No Yes Yes No Yes

J1001

J1001

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DVI_CONNECTOR

DVI_CONNECTOR

1
2

3
11
12

4
15

9
13
14

5

6

7

8
10
16
17

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

CASE
TMDS Data2-

TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

MJ1001

MJ1001

R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17

G3179C219-005

G3179C219-005

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - DAC1&TMDS2

RV635 GDDR3 - DAC1&TMDS2

8

7

6

5

4

3

RV635 GDDR3 - DAC1&TMDS2

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

15 21

of

15 21

of

15 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

7

6

5

4

3

2

1

See BOM for qualified filters

A_R_DAC2_M

L2001

A_DAC2_R(3)

R2027

A_DAC2_RB(3)

A_DAC2_G(3)

D D

A_DAC2_GB(3)

A_DAC2_B(3)

A_DAC2_BB(3)

R2027

37.4R

37.4R

R2028

R2028

37.4R

37.4R

R2029

R2029

37.4R

37.4R

C2004

C2004

R2001

R2001

8.0pF

8.0pF

75R

75R

402

402

R2002

R2002

C2005

C2005

8.0pF

8.0pF

75R

75R

402

402

C2006

C2006

R2003

R2003

8.0pF

8.0pF

75R

75R

402

Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane.

L2001
47nH

47nH

R20240RR2024
0R

L2002

L2002
47nH

47nH

R20250RR2025
0R

L2003

L2003
47nH

47nH

R20260RR2026
0R

C2001

C2001

402

12pF_50V

12pF_50V

A_G_DAC2_M

C2002

C2002

402

12pF_50V

12pF_50V

A_B_DAC2_M

C2003

C2003

402402

12pF_50V

12pF_50V

L2004

L2004
36NH

36NH

L2005

L2005
36NH

36NH

L2006

L2006
36NH

36NH

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F

DDCDATA_DAC2_R
DDCCLK_DAC2_R

+3.3V

4
5
6

HSYNC_DAC2_R
VSYNC_DAC2_R

D2001

D2001

CH3
Vp
CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

+5V_VESA

4
5
6

For ESD Protection

D2002

D2002

CH3
Vp
CH4

CM1213-04

CM1213-04

3

CH2

2

Vn

1

CH1

C2010

C2010
68pF

68pF

603

+5V_VESA

MJ2001

MJ2001

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

G3179C219-005

G3179C219-005

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

+3.3V

R2004

CRT2DDCDATA(3)

C C

CRT2DDCCLK(3)

HSYNC_DAC2(3,7)

VSYNC_DAC2(3,7)

B B

SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane

DNI for RV635

DNI for RV635

R2004

24.3K

24.3K

+3.3V +5V

R2007

R2007

24.3K

24.3K

U1999C

U1999C

9 8

74VHC125

74VHC125

10

U1999D

U1999D

13

12 11

74VHC125

74VHC125

DNI for RV630

DNI for RV630

1

BSH111

BSH111
Q2001

Q2001

R2040 0RR2040 0R

1

BSH111

BSH111
Q2002

Q2002

R2041 0RR2041 0R

HSYNC_DAC2_B

VSYNC_DAC2_B

+5V

R2005

R2005

2.2K

2.2K

402

DDCDATA_DAC2_5V DDCDATA_DAC2_R

32

RV635: no pull up on 3.3V, 2.2K pull up on 5V
RV630: 24.3K pull up on 3.3V, 19.1K on 5V

R2008

R2008

2.2K

2.2K

402 402

DDCCLK_DAC2_5V

32

R2010

R2010

R2011

R2011

R2006 33RR2006 33R

R2009 33RR2009 33R

10R

10R

10R

10R

HPD1(3)

402

402

402

DDCCLK_DAC2_R

HSYNC_DAC2_R

VSYNC_DAC2_R

Q2021

Q2021

MMBT3904

MMBT3904

+3.3V

2 3

R2023

R2023
10K

10K

R2022 10KR2022 10K

1

T1X2M(3)
T1X2P(3)

T1X4M(3)
T1X4P(3)

T1X1M(3)
T1X1P(3)

T1X3M(3)
T1X3P(3)

T1X0M(3)
T1X0P(3)

T1X5M(3)
T1X5P(3)

T1XCP(3)
T1XCM(3)

DDCCLK_DAC2_R
DDCDATA_DAC2_R
VSYNC_DAC2_R

A_R_DAC2_F
A_G_DAC2_F
A_B_DAC2_F
HSYNC_DAC2_R

DB15 pin

Standard VGA
Monitor ID bit 0

11

Monitor ID bit 1

12

Monitor ID bit 2

4

Monitor ID bit 3

15

N/C

9

Mechanical Key

Hardware

No Yes Yes No Yes

Support

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V_VESA

HPD_DVI1

DDC1 Host
Monitor ID bit 0

Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1
C2
C3
C4
C5
C6

26
27
28
29
30

DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max

J2001

J2001

CASE
TMDS Data2-

TMDS Data2+
TMDS Data2/4 Shield
TMDS Data4­TMDS Data4+
DDC Clock
DDC Data
Analog VSYNC
TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

DVI_CONNECTOR

DVI_CONNECTOR

DDC2AB Host
Monitor ID bit 0

SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - DAC2/TMDS1

RV635 GDDR3 - DAC2/TMDS1

8

7

6

5

4

3

RV635 GDDR3 - DAC2/TMDS1

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

16 21

of

16 21

of

16 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

D D

7

6

5

4

3

2

1

A_DAC2_Y(3)

R3001

R3001
75R

75R

A_DAC2_C(3)

R3002

R3002
75R

75R

A_DAC2_COMP(3)

R3003

R3003
75R

75R

C C

Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI

DAC2_C_F
DAC2_COMP_F

R3011 0RR3011 0R

R3004 0RR3004 0R
R3005 0RR3005 0R
R3006 0RR3006 0R

Install for Dell

GENERICA(7)

DNI for Dell

402

STV/HDTV#_DET PIN6
DAC2_Y_DINDAC2_Y_F

DAC2_C_DIN
DAC2_COMP_DIN

+3.3V

R3008

R3008
10K

10K

C3007

C3007
82pF

82pF

Install for Dell

R3010 0RR3010 0R

R3009 0RR3009 0R

C3009

C3009

C3008

C3008

82pF

82pF

82pF

82pF

L3001 470nH_250mAL3001 470nH_250mA

C3001

C3001
47pF_50V

47pF_50V

L3002 470nH_250mAL3002 470nH_250mA

C3002

C3002
47pF_50V

47pF_50V

L3003 470nH_250mAL3003 470nH_250mA

C3003

C3003
47pF_50V

47pF_50V

R30070RR3007
0R

DNI for Dell

The 7-pin MiniDIN footprint allows one of the two MiniDINs:

B B

- 7-pin Svideo/Composite MiniDIN P/N 6071001500G

- 4-pin Svideo MiniDIN P/N 6070001000G

DAC2_Y_F

C3004

C3004
47pF_50V

47pF_50V

DAC2_C_F

C3005

C3005
47pF_50V

47pF_50V

DAC2_COMP_F

C3006

C3006
47pF_50V

47pF_50V

Install for Dell only when it's needed for EMI

C3010

C3010
82pF

82pF

TV Out

J3001

J3001

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

CompIn

5

SYNC

1

GND

2

GND#2

8

Rpin5

CASE

9

CASE#9

10

CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - TVO

RV635 GDDR3 - TVO

8

7

6

5

4

3

RV635 GDDR3 - TVO

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

17 21

of

17 21

of

17 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

8

7

6

5

26R_600mA

26R_600mA

B4002

B4002

+VDDC_Source

4

B4001

B4001

26R_600mA

26R_600mA

+12V_BUS

3

2

1

For 2-WIRE FAN ONLY

D D

+3.3V +3.3V

R4032

R4032

R4003

R4003

2.61K

2.61K

10K

10K

DDC2CLK(3,13)

DDC2DATA(3,13)

TS_FDO(3)

Place R4032, and R4033 on
the bottom side. Easily
accessiable.

C C

R4001 100RR4001 100R
R4002 100RR4002 100R
R4015 0RR4015 0R

R4033 20KR4033 20K

DNI

+3.3V_BUS

R1254

R1254
10K

10K

LM63 is for BU only, until built-in fan controller is verified.

C4003

C4003

C4002

C4002

C4001

C4001

1uF_6.3V

1uF_6.3V

10uF_X6S

SCL_R
SDA_R
TINT_R

10uF_X6S

8
7
6

U4001

U4001

SMBCLK
SMBDAT
ALERT
GND5PWM

LM63CIMAX

LM63CIMAX

100pF_50V

100pF_50V

VDD

D+

D-

TS_FDO

R4004

R4004
10K

10K

GPU_DPLUS

1
2
3
4

C4004

C4004

2.2nF_50V

2.2nF_50V
GPU_DMINUS

GPU_DPLUS (3)

GPU_DMINUS (3)ThermINT(7)

Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA

Not intended for production
LED off shows the fault

+3.3V_BUS

TR1256

TR1256
499R

499R

TR1257

TR1257

2.2K

2.2K

TQ1250

TQ1250

1

MMBT3904

MMBT3904

2 3
21

TD1250TD1250

For fan with 3.3V PWM (bypass) install 0R (TBV)

MR4005 10KMR4005 10K

R4005 10KR4005 10K

PWMLM63_PWM

Q4001

Q4001

1

MMBT3904

MMBT3904

2 3

C4008

C4008
1uF

1uF

0805
16V

+12V_BUS

R4006

R4006

2.61K

2.61K

1%

+3.3V_BUS +3.3V_BUS

MR4006

MR4006

5.1K

5.1K

R40391KR4039

1

1K

For 4-WIRE FAN ONLY

R4007

R4007
20K

20K

1%

DNI

R4036

R4036
10K

10K

Q4030

Q4030
MMBT3904

MMBT3904

2 3

PWM

R4008

R4008

2.37K

2.37K

TP4001

TP4001

35mil

35mil

MR40360RMR4036

0R

DNI (bypass for fan
with 3.3V PWM)

C4007

C4007
1uF

1uF

805
16V
Y5V

R4011

R4011
100K

100K

DNI

+12V_BUS

TACH

DNI

For testing purposes only

1

R4030

R4030
100K

100K

R4031 15KR4031 15K
R4014 0RR4014 0R

R4034

R4034
100K

100K

32

MQ4004

MQ4004

2SB1188

2SB1188

C4010

C4010
10uF

10uF

DNI

MJ4030MJ4030

1
2

Header is 2mm, and
it does not follow

2.54mm spacing as 4-pin
PWM Fan Specification

4
3
2

J4030

J4030

1

1X4 3A 2MM

1X4 3A 2MM

Overlap MJ4030 and J4030

R1250 2.2KR1250 2.2K

H1B

H1B

FANSINK

FANSINK

1

2 3

R1255

R1255

5.1K

5.1K

9

10111213141516

Q1252

Q1252
MMBT3904

MMBT3904

+3.3V_BUS

1

32

C1251

C1251
1uF_6.3V

1uF_6.3V

R1252

R1252
10K

10K

Q1250

Q1250
BSH111

BSH111

7

+3.3V_BUS

H1C

H1C

FANSINK

FANSINK

17181920212223

C1250

C1250
100nF_6.3V

100nF_6.3V

Bypass Switch
(not for production)

2

1

DIP_SWX2

DIP_SWX2
SW2B

SW2B

3 2

24

U1250

U1250

8

7

NC7SZ74K8X

NC7SZ74K8X

D

PR

Vcc

C

G4CL

6

H1D

H1D

FANSINK

FANSINK

5

Q

3

Q

DIP_SWX2

DIP_SWX2
SW2A

SW2A

4 1

25262728293031

R1259

R1259

2.2K

2.2K

R1257

R1257
100K

100K

32

R12601KR1260

1

1K

1

H1F

H1E

H1E

FANSINK

FANSINK

33343536373839

6

H1F

FANSINK

FANSINK

41424344454647

40

If Critical Temperature is reached this will
force the fan to run at full speed while

Q1253

Q1253

power is removed from GPU & rest of the

MMBT3904

MMBT3904

2 3

board.

VDDC_SHDN_N (11)

Q1251

Q1251
MMBT3904

MMBT3904

2 3

H1G

H1G

FANSINK

FANSINK

49505152535455

48

5

56

H1H

H1H

FANSINK

FANSINK

58596061626364

57

See BOM for qualified option.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - Thermal Management

RV635 GDDR3 - Thermal Management

4

3

RV635 GDDR3 - Thermal Management

2

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

18 21

of

18 21

of

18 21

Doc No.

Doc No.

Doc No.

1

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

BUS_RAILS_UP_N(13)

B B

CTF(7)

H1A

A A

H1A

FANSINK

FANSINK

2345678

1

USE FANSINK FOR RV630 GDDR3, p/n 7121033200G

8

www.vinafix.vn

5

DVI/DVI SCREWS with top tab

ASSY-SCREW1

ASSY-SCREW1

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>

<3rd part field>

ASSY-SCREW3

ASSY-SCREW3

D D

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>

<3rd part field>

ASSY1

ASSY1

ANTISTATIC

ANTISTATIC
BAG

BAG

6_X_11

6_X_11

C C

ASSY-SCREW2

ASSY-SCREW2

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>

<3rd part field>

ASSY-SCREW4

ASSY-SCREW4

SCREW

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT

JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>

<3rd part field>

BKT1

BKT1

BRACKET

BRACKET

8020038600G

8020038600G

ASSY-SCREW5

ASSY-SCREW5

SCREW

SCREW
SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L

4

DNI

SK1

SK1

SOCKET_880

SOCKET_880

RV635 Socket

MT2

MT2
MT_Hole_0.136_in_6VIA

MT_Hole_0.136_in_6VIA

PCB1

PCB1

PCB

PCB

109-B380xx-00

109-B380xx-00

3

2

1

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices

© 2007 Advanced Micro Devices
This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,

This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement

and is provided only to entities under a non-disclosure agreement
with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure

with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose

is strictly prohibited. Use of this schematic and design for any purpose
other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement

other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind

with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,

regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular

any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting

purpose, and disclaims responsibility forany consequences resulting
from use of the information included herein.

from use of the information included herein.

from use of the information included herein.

Title

Title

Title

RV635 GDDR3 - Mechanical

RV635 GDDR3 - Mechanical

5

4

3

2

RV635 GDDR3 - Mechanical

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.

Advanced Micro Devices Inc.
1 Commerce Valley Drive East

1 Commerce Valley Drive East

1 Commerce Valley Drive East
Markham, Ontario

Markham, Ontario

Markham, Ontario

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Wednesday, October 31, 2007

Sheet

Sheet

Sheet

of

19 21

of

19 21

of

19 21

1

Doc No.

Doc No.

Doc No.

RevDate:

RevDate:

RevDate:

1

1

1

105-B380xx-00

105-B380xx-00

105-B380xx-00

www.vinafix.vn

www.vinafix.vn

www.vinafix.vn