MSI MS-V117 Schematic
A B C D E F G H
P393-A01 Base Design
1
P393-A01, G92, 8Mx32/16Mx32 GDDR3 (800/1000 MHz),
DVI-I-DL, DVI-I-DL/DisplayPort, HDTVout/Stereo
Table of Contents:
Page 1: Overview
Page 2: PCI Express 1.0
2
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBB Partition
Page 7: FBC Partition
Page 8: FBD Partition
Page 9: FrameBuffer Net Rules
Page 10: DACA Interface
Page 11: DACC Interface
Page 12: IFP A/B and C/D Interface
3
Page 13: DACB and Stereo Interface
Page 14: Multi-use IO(MIO) Interface
Page 15: DisplayPort Transmitter
Page 16: MISC: GPIO, I2C, BIOS, PLL, and XTAL
Page 17: Thermal Control/Protection and SPDIF Input
Page 18: Power/GND and Decoupling
Page 19: Configuration Straps and Mechanical
Page 20: Power Supply: 5V, STEREO_5V, 2V5, DP_PWR
Page 21: Power Supply: 1V2, 1V8
Page 22: Power Supply: FBVDD/Q, 8V5
4
Page 23: Power Supply: NVVDD Regulator
Page 24: Power Supply: NVVDD Phase 1 & 2
Page 25: Power Supply: NVVDD Phase 3
Page 26: Power Supply: Filter/Detection 3V3, 12V, 12V_PEX6
Page 27: Power Supply: Hybrid Power
5
1.V117-0C Base on P393
2.page 2 del Q1209,R1219,R58,R55, circuit ,del net pex_rst link page27
3.page 10 del I2CA_SCR_R,I2CA_SDA_R link net Page 27
4.page 11 del I2CB_SCR_R,I2CB_SDA_R link net page27
5.page 15 del Display port circuit
6.page 16 del I2CS for Hybrid power circuit , del GPIO 4/10 net, R91 link gnd, del R66,R75
7.page 14 del MIOB_D2/3/4/5/6/7/10 net link page 19
8.page 20 del DP_POWER circuit
9.page 27 del Hybrid power circuit
10.page 3/5/6. update FBA_CMD(25..0)/FBB_CMD(25..0)
11.page 4/7/8. update FBC_CMD(25..0)/FBD_CMD(25..0)
12.page 17. del GPIO4_FAN_PWM_R net
13.page 17. Del SPDIF circuit , change p403 SPDIF circuit
14.page 12. add EMI
VARIANT ASSEMBLY
SKU
BASE
B
SKU_DT_0000
1
2
SKU_DT_0002
3
SKU_WS_0500
4
5
SKU_DT_0004
6
7
8
<UNDEFINED>
9
<UNDEFINED>
10
<UNDEFINED>
11
<UNDEFINED> <UNDEFINED>
<UNDEFINED>
12
<UNDEFINED>
13
<UNDEFINED>
14
<UNDEFINED>
15
NVPN
600-10393-base-100
600-10393-0000-100
600-10393-0002-100
600-50393-0500-100
600-50393-0501-100SKU_WS_0501
600-10393-0004-100 P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P393 G92-300 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-200 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-875 512MB GDDR3 16Mx32 DVI-I+DP+STEREO
P393 G92-850 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
<UNDEFINED><UNDEFINED><UNDEFINED>
<UNDEFINED><UNDEFINED><UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
www.vinafix.vn
ASSEMBLY
PAGE DETAIL
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Overview
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
SUMMARY
SUMMARY
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date:
Date:
Date:
SUMMARY
MS-V117
MS-V117
MS-V117
Thursday, October 18, 2007
Thursday, October 18, 2007
Thursday, October 18, 2007
Sheet of
Sheet of
Sheet of
HFDBA
1
1
1
100
100
100
27
27
27
A B C D E F G H
Page2: PCI Express 1.0
12V
C51
C51
4.7UF
4.7UF
16V
16V
20%
20%
X7R
X7R
1206
1206
COMMON
COMMON
GND
1
3V3
See filtering on page 26
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C50
C50
4.7UF
4.7UF
16V
16V
20%
20%
X7R
X7R
1206
1206
COMMON
COMMON
PEX_PRSNT1*
PEX_PRSNT2*
C54
C54
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
3V3_AUX
CN1
CN1
CON_FINGER_PEX_164
CON_FINGER_PEX_164
CON_X16
CON_X16
COMMON
COMMON
B1
+12V
B2
+12V
A2
+12V
A3
+12V
B3
+12V/RSVD
B8
+3V3
A9
+3V3
A10
+3V3
B10
+3V3AUX
A1
PRSNT1
B17
PRSNT2
B12
RSVD
B4
GND
A4
GND
B7
GND
A12
GND
B13
GND
A15
GND
B16
GND
B18
GND
A18
GND
GND
B31
PRSNT2
A19
RSVD
B30
RSVD
A32
RSVD
A20
GND
B21
GND
B22
GND
A23
GND
A24
GND
B25
GND
B26
GND
A27
GND
A28
GND
B29
GND
A31
GND
B32
GND
GND
B48
PRSNT2
A33
RSVD
A34
GND
B35
GND
B36
GND
A37
GND
A38
GND
B39
GND
B40
GND
A41
GND
A42
GND
B43
GND
B44
GND
A45
GND
A46
GND
B47
GND
B49
GND
A49
GND
GND
B81
PRSNT2
A50
RSVD
B82
RSVD
A51
GND
B52
GND
B53
GND
A54
GND
A55
GND
B56
GND
B57
GND
A58
GND
A59
GND
B60
GND
B61
GND
A62
GND
A63
GND
B64
GND
B65
GND
A66
GND
A67
GND
B68
GND
B69
GND
A70
GND
A71
GND
B72
GND
B73
GND
A74
GND
A75
GND
B76
GND
B77
GND
A78
GND
A79
GND
B80
GND
A82
GND
GND
END OF X1
END OF X1
END OF X4
END OF X4
END OF X8
END OF X8
END OF X16
END OF X16
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
B5
B6
B11
WAKE
PEX_RST*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TX0_C
A16
PEX_TX0_C*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TX1_C
A21
PEX_TX1_C*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TX2_C
A25
PEX_TX2_C*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TX3_C
A29
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TX4_C
A35
PEX_TX4_C*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TX5_C
A39
PEX_TX5_C*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TX6_C
A43
PEX_TX6_C*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TX7_C
A47
PEX_TX7_C*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TX8_C
A52
PEX_TX8_C*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TX9_C
A56
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TX10_C
A60
PEX_TX10_C*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TX11_C
A64
PEX_TX11_C*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TX12_C
A68
PEX_TX12_C*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TX13_C
A72
PEX_TX13_C*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TX14_C
A76
PEX_TX14_C*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TX15_C
A80
PEX_TX15_C*
A81
PEX_RX15
B78
PEX_RX15*
B79
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
PEX_TX3_C*
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
PEX_TX9_C*
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
* PRSNT# isolation bypass option
R696
R696
0
0
5%
5%
0402
0402
DNI
DNI
(OPT)
17
C917 .1UF
C917 .1UF
C915
C915
10V0402
10V0402
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C907
C907
C906
C906
0402 10V
0402 10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C904
C904
C894
C894
0402
10V
0402
10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C890
C890
C885
C885
0402
0402
10V
10V
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C872
C872
C869
C869
0402
10V
0402
10V
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C857
C857
C853
C853
0402
0402
10V
10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C843
C843
C837
C837
0402
10V
0402
10V
10%
10%
X5R
X5R
.1UF
.1UF
C818
C818
C811
C811
0402
0402
10V
10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C800
C800
C791
C791
0402
0402
10V
10V
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C768
C768
C763
C763
0402
0402
10V
10V
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C736
C736
C729
C729
0402
0402
10V
10V
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C707
C707
0402
0402
10V
10V
C704
C704
10%
10%
0402 10V
0402 10V
X5R
X5R
.1UF
.1UF
C697
C697
0402
0402
10V
10V
C692
C692
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C681
C681
C677
C677
0402
0402
10V
10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C674
C674
C673
C673
0402
0402
10V
10V
10%
10%
0402
0402
X5R
X5R
.1UF
.1UF
C671
C671
C670
C670
0402
10V
0402
10V
10%
10%
0402
0402
X5R
X5R
Stuff only to bypass the micro-controller
GPU_RST*
IN
PEX_TX0
.1UF
.1UF
PEX_TX0*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX1
.1UF
.1UF
PEX_TX1*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX2
.1UF
.1UF
PEX_TX2*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX3
.1UF
.1UF
PEX_TX3*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX4
.1UF
.1UF
PEX_TX4*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX5
.1UF
.1UF
PEX_TX5*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX6
.1UF
.1UF
PEX_TX6*
10%
10%
10V0402
10V0402
COMMON
COMMON
X5R
X5R
PEX_TX7
.1UF
.1UF
PEX_TX7*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX8
.1UF
.1UF
PEX_TX8*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX9
.1UF
.1UF
PEX_TX9*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX10
.1UF
.1UF
PEX_TX10*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX11
.1UF
.1UF
PEX_TX11*
10%
10%
COMMON
COMMON
X5R
X5R
PEX_TX12
.1UF
.1UF
PEX_TX12*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX13
.1UF
.1UF
PEX_TX13*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX14
.1UF
.1UF
PEX_TX14*
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
PEX_TX15
PEX_TX15*
.1UF
.1UF
10%
10%
10V
10V
COMMON
COMMON
X5R
X5R
C GE
JTAG_TRST*
R692
0
R692
0
DNI
0402
DNI
0402
(OPT)
5%
5%
JTAG_TCLK
R700
0
R700
0
DNI
0402
DNI
0402
(OPT)
5%
5%
JTAG_TDI
R697
0
R697
0
DNI
0402
DNI
0402
(OPT)
5%
5%
JTAG_TDO
R695
0
R695
0
DNI
0402
DNI
0402
(OPT)
5%
5%
JTAG_TMS
R693
0
R693
0
0402
0402
DNI
DNI
(OPT)
5%
5%
G1A
G1A
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
1/24 PCI EXPRESS
1/24 PCI EXPRESS
AR9
PEX_RST
AK10
PEX_REFCLK
AL10
PEX_REFCLK
AM11
PEX_TX0
AM10
PEX_TX0
AP9
PEX_RX0
AP10
PEX_RX0
AN10
PEX_TX1
AN11
PEX_TX1
AR10
PEX_RX1
AR11
PEX_RX1
AN12
PEX_TX2
AM12
PEX_TX2
AT11
PEX_RX2
AT12
PEX_RX2
AL12
PEX_TX3
AK12
PEX_TX3
AP12
PEX_RX3
AP13
PEX_RX3
AM14
PEX_TX4
AM13
PEX_TX4
AR13
PEX_RX4
AR14
PEX_RX4
AN13
PEX_TX5
AN14
PEX_TX5
AT14
PEX_RX5
AT15
PEX_RX5
AN15
PEX_TX6
AM15
PEX_TX6
AP15
PEX_RX6
AP16
PEX_RX6
AL15
PEX_TX7
AK15
PEX_TX7
AR16
PEX_RX7
AR17
PEX_RX7
AM16
PEX_TX8
AN16
PEX_TX8
AT17
PEX_RX8
AT18
PEX_RX8
AN17
PEX_TX9
AN18
PEX_TX9
AP18
PEX_RX9
AP19
PEX_RX9
AM18
PEX_TX10
AM17
PEX_TX10
AR19
PEX_RX10
AR20
PEX_RX10
AL18
PEX_TX11
AK18
PEX_TX11
AT20
PEX_RX11
AT21
PEX_RX11
AM19
PEX_TX12
AN19
PEX_TX12
AP21
PEX_RX12
AP22
PEX_RX12
AN20
PEX_TX13
AN21
PEX_TX13
AR22
PEX_RX13
AR23
PEX_RX13
AM21
PEX_TX14
AM20
PEX_TX14
AT23
PEX_RX14
AT24
PEX_RX14
AL21
PEX_TX15
AK21
PEX_TX15
AR24
PEX_RX15
AR25
PEX_RX15
GPU_RST*PEX_RST*
R1205
0
R1205
0
COMMON
COMMON
0402
0402
5%
5%
3V3_F
TMS2TRST*
TDI4GND
VCC
TDO8TCK
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT
PEX_PLLAVDD
PEX_PLLDVDD
PEX_PLLAGND
PEX_PLLDGND
ASSEMBLY
PAGE DETAIL
J501
J501
FEMALE
FEMALE
1.274MM
1.274MM
0
0
CON_HDR_002X004_TH
CON_HDR_002X004_TH
DNI
DNI
1
3
5
7
RFU
RFU
KEY
KEY
(OPT)
AH21
AJ21
AH22
AJ22
AH23
AJ23
AH16
AF17
AH17
AF18
AH18
AF19
AH19
AE20
AF20
AH20
AJ20
AM9
AN9
AK19
AK20
AE15
AE17
AF15
C752
C752
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C753
C753
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C745
C745
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
SNN_PEXCAL_PD_VDDQ
SNN_PEXCAL_PD_GND
PEX_PLLAVDD
Fix for G92 NC pin issue
GND
3V3_F
R683
R683
10K
10K
5%
5%
0402
0402
COMMON
COMMON
C773
C773
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C767
C767
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C765
C765
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PEX_TEST_PLL_CLK_OUT
Termination = 200ohm
Place on bottom side
for test access
R688
R688
R677
R677
180
180
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
R689
R689
R681
R681
270
270
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
C790
C790
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C746
C746
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C772
C772
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
3V3_AUX
3.3V
C63
C63
.1UF
.1UF
16V
16V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
R649
R649
200
200
5%
5%
0402
0402
COMMON
COMMON
Place components within 750mils from pad
Replaced bead with 10nH inductor per SI recommendation
C802
C802
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C771
C771
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C770
C770
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C785
C785
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
AE16
GND
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
PCI Express 1.0
C792
C792
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
JTAG
G1B
G1B
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
23/24 JTAG
23/24 JTAG
AK6
JTAG_TCLK
AL8
JTAG_TMS
AL7
JTAG_TDI
AK7
JTAG_TDO
AL9
JTAG_TRST
C731
C731
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C727
C727
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C93
C93
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
1
1V2
C699
C699
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
1V2
GND
C92
C92
10UF
10UF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
GND
2
3
4
1V2
L6
10nH
L6
10nH
IND_SMD_0402
IND_SMD_0402
COMMON
COMMON
C95
C95
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Thursday, November 15, 2007
Date:
Thursday, November 15, 2007
Date:
Thursday, November 15, 2007
Sheet of
Sheet of
Sheet of
HFDBA
5
<RevCode>
<RevCode>
<RevCode>
227
227
227
www.vinafix.vn
A B C D E F G H
Page3: MEMORY: GPU Partition A/B
1
5,9
5,9
5,9
BI
BI
OUT
IN
OUT
GND GND
FBA_D[63..0]
FBA_DQM[7..0]
FBA_DQS_RN[7..0]
FBA_DQS_WP[7..0]
FBVDD
C676
C676
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
R616
R616
549
549
1%
1%
0402
0402
COMMON
COMMON
R615
R615
1.33K
1.33K
1%
1%
0402
0402
COMMON
COMMON
5,9
2
3
4
9
5
G1D
G1C
G1C
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
2/24 MEM_A
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM0
0
FBA_DQM1
1
FBA_DQM2
2
FBA_DQM3
3
FBA_DQM4
4
FBA_DQM5
5
FBA_DQM6
6
FBA_DQM7
7
FBA_DQS_RN0
0
FBA_DQS_RN1
1
FBA_DQS_RN2
2
FBA_DQS_RN3
3
FBA_DQS_RN4
4
FBA_DQS_RN5
5
FBA_DQS_RN6
6
FBA_DQS_RN7
7
FBA_DQS_WP0
0
FBA_DQS_WP1
1
FBA_DQS_WP2
2
FBA_DQS_WP3
3
FBA_DQS_WP4
4
FBA_DQS_WP5
5
FBA_DQS_WP6
6
FBA_DQS_WP7
7
FB_VREF1
AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34
AG35
AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29
AK35
AM33
AF33
AF34
AN34
AM24
AP32
AR27
AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27
AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26
J29
2/24 MEM_A
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
FB_VREF1
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_DEBUG
FBCAL0_PD_VDDQ
FBCAL0_PU_GND
FBCAL0_TERM_GND
FBA_DLLAVDD
FBA_PLLAVDD
FBA_PLLGND
DDR3
60
40
40
0.7 FBVDDQVREF RATIO
FBA_CMD0
AK28
FBA_CMD1
AK29
FBA_CMD2
AN30
FBA_CMD3
AM27
FBA_CMD4
AN28
FBA_CMD5
AL29
FBA_CMD6
AM30
FBA_CMD7
AJ31
FBA_CMD8
AK31
FBA_CMD9
AH31
FBA_CMD10
AK25
FBA_CMD11
AM26
FBA_CMD12
AL31
FBA_CMD13
AN29
FBA_CMD14
AK27
FBA_CMD15
AK26
FBA_CMD16
AN27
FBA_CMD17
AL25
FBA_CMD18
AJ30
FBA_CMD19
AM31
FBA_CMD20
AH30
FBA_CMD21
AL30
FBA_CMD22
AH29
FBA_CMD23
AL28
FBA_CMD24
AH28
FBA_CMD25
AM28
AG30
AG28
AF28
FBA_CLK0
AH26
FBA_CLK0*
AH27
FBA_CLK1
AJ29
FBA_CLK1*
AJ28
AJ24
RFU
AH24
RFU
AH25
FB_CAL_PD_VDDQ0 FB_CAL_PD_VDDQ1
J28
FB_CAL_PU_GND0 FB_CAL_PU_GND1
H28
FB_CAL_TERM_GND0 FB_CAL_TERM_GND1
H29
FBAB_PLLAVDD
AC29
AD29
AE29
GND
C702
C702
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place components as close
as possible to the pad
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBA_CMD[25..0]
OUT
OUT
OUT
OUT
5,9
5,9
5,9
5,9
5,9
OUT
136BGA CMD Mapping
ADDR
CMD
A<4>CMD0
CMD1 RAS*
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
CMD5
A<4>
A<3>
CMD6
CMD7 BA2
CS0*
CMD8
A<11>
CMD9
CMD10
CAS*
CMD11
WE*
CMD12
BA0
CMD13
A<5>
CMD14
A<12>
CMD15
RST
CMD16
A<7>
CMD17
A<10>
CMD18
CKE
CMD19
A<0>
CMD20
A<9>
CMD21
A<6>
CMD22
A<2>
CMD23
A<8>
CMD24
A<3>
CMD25
A<1>
CMD26
A<13>
CMD27
BA2
CMD28
N/A
FBVDD
R626
R626
60.4
60.4
1%
1%
0402
0402
DNI
DNI
(OPT) (OPT)
9FBA_DEBUG
BI
FBVDD
R624 60.4
R624 60.4
COMMON
COMMON
1%
1%
0402
0402
R620
40.2
R620
40.2
COMMON
COMMON
1%
1%
0402
0402
R619
40.2
R619
40.2
COMMON
COMMON
1%
1%
0402
0402
9
BI
240R@100MHz
240R@100MHz
C687
C687
C708
C708
1UF
1UF
.1UF
.1UF
10V
10V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
Place these components within
750 mils of the pad
C688
C688
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
1V2
LB501
LB501
COMMONIND_SMD_0402
COMMONIND_SMD_0402
9
C675
C675
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
FBB_D[63..0]
6,9
BI
FBB_DQM[7..0]
6,9
OUT
FBB_DQS_RN[7..0]
6,9
IN
FBB_DQS_WP[7..0]
6,9
OUT
FBVDD
R629
R629
549
549
1%
1%
0402
0402
COMMON
BI
COMMON
C710
C710
R628
R628
.1UF
.1UF
1.33K
1.33K
1%
1%
10V
10V
10%
10%
0402
0402
COMMON
COMMON
X5R
X5R
0402
0402
COMMON
COMMON
GND
GND
FBB_D0
0
FBB_D1
1
FBB_D2
2
FBB_D3
3
FBB_D4
4
FBB_D5
5
FBB_D6
6
FBB_D7
7
FBB_D8
8
FBB_D9
9
FBB_D10
10
FBB_D11
11
FBB_D12
12
FBB_D13
13
FBB_D14
14
FBB_D15
15
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_D32
32
FBB_D33
33
FBB_D34
34
FBB_D35
35
FBB_D36
36
FBB_D37
37
FBB_D38
38
FBB_D39
39
FBB_D40
40
FBB_D41
41
FBB_D42
42
FBB_D43
43
FBB_D44
44
FBB_D45
45
FBB_D46
46
FBB_D47
47
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_DQM0
0
FBB_DQM1
1
FBB_DQM2
2
FBB_DQM3
3
FBB_DQM4
4
FBB_DQM5
5
FBB_DQM6
6
FBB_DQM7
7
FBB_DQS_RN0
0
FBB_DQS_RN1
1
FBB_DQS_RN2
2
FBB_DQS_RN3
3
FBB_DQS_RN4
4
FBB_DQS_RN5
5
FBB_DQS_RN6
6
FBB_DQS_RN7
7
FBB_DQS_WP0
0
FBB_DQS_WP1
1
FBB_DQS_WP2
2
FBB_DQS_WP3
3
FBB_DQS_WP4
4
FBB_DQS_WP5
5
FBB_DQS_WP6
6
FBB_DQS_WP7
7
FB_VREF2
G1D
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
3/24 MEM_B
3/24 MEM_B
G36
FBBD0
G35
FBBD1
H36
FBBD2
H34
FBBD3
J35
FBBD4
J34
FBBD5
K34
FBBD6
K35
FBBD7
J31
FBBD8
K32
FBBD9
J30
FBBD10
H30
FBBD11
L32
FBBD12
K30
FBBD13
M31
FBBD14
L30
FBBD15
G31
FBBD16
J32
FBBD17
J33
FBBD18
F33
FBBD19
H31
FBBD20
E33
FBBD21
F31
FBBD22
F32
FBBD23
F35
FBBD24
G34
FBBD25
F36
FBBD26
F34
FBBD27
C35
FBBD28
D34
FBBD29
C36
FBBD30
D35
FBBD31
N35
FBBD32
M34
FBBD33
L34
FBBD34
N36
FBBD35
P36
FBBD36
P34
FBBD37
R36
FBBD38
R34
FBBD39
AC33
FBBD40
Y33
FBBD41
Y30
FBBD42
AB30
FBBD43
AA32
FBBD44
AD32
FBBD45
AD33
FBBD46
AA33
FBBD47
T36
FBBD48
R35
FBBD49
T34
FBBD50
U36
FBBD51
W35
FBBD52
U34
FBBD53
V34
FBBD54
W36
FBBD55
AC36
FBBD56
AA36
FBBD57
AC34
FBBD58
AB34
FBBD59
AA35
FBBD60
Y34
FBBD61
Y36
FBBD62
W34
FBBD63
J36
FBBDQM0
M32
FBBDQM1
H33
FBBDQM2
E34
FBBDQM3
N34
FBBDQM4
Y32
FBBDQM5
T35
FBBDQM6
AA34
FBBDQM7
L36
FBBDQS_RN0
K33
FBBDQS_RN1
G32
FBBDQS_RN2
E36
FBBDQS_RN3
M36
FBBDQS_RN4
AB32
FBBDQS_RN5
V35
FBBDQS_RN6
AB35
FBBDQS_RN7
K36
FBBDQS_WP0
L33
FBBDQS_WP1
G33
FBBDQS_WP2
D36
FBBDQS_WP3
M35
FBBDQS_WP4
AB31
FBBDQS_WP5
V36
FBBDQS_WP6
AB36
FBBDQS_WP7
J27
FB_VREF2
FBB_CMD27
FBB_CMD28
FBCAL1_PD_VDDQ
FBCAL1_PU_GND
FBCAL1_TERM_GND
FBB_PLLVDD_NC
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
FBB_DEBUG
FBB_PLLGND
1
FBB_CMD0
P33
FBB_CMD1
N33
FBB_CMD2
R31
FBB_CMD3
U33
FBB_CMD4
V30
FBB_CMD5
T33
FBB_CMD6
T30
FBB_CMD7
N32
FBB_CMD8
R32
FBB_CMD9
P32
FBB_CMD10
U32
FBB_CMD11
U30
FBB_CMD12
P30
FBB_CMD13
V31
FBB_CMD14
T28
FBB_CMD15
W30
FBB_CMD16
V32
FBB_CMD17
T32
FBB_CMD18
N30
FBB_CMD19
P28
FBB_CMD20
P29
FBB_CMD21
U29
FBB_CMD22
N28
FBB_CMD23
R30
FBB_CMD24
M30
FBB_CMD25
T29
N29
AA30
Y29
FBB_CLK0
M28
FBB_CLK0*
L28
FBB_CLK1
W31
FBB_CLK1*
W32
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBB_CMD[25..0]
OUT
OUT
OUT
OUT
6,9
6,9
6,9
6,9
6,9
OUT
2
3
FBVDD
R617
R617
60.4
60.4
1%
1%
0402
0402
DNI
R28
RFU
K29
RFU
C34
DNI
9FBB_DEBUG
BI
FBVDD
R630
60.4R630
H27
H26
J26
AB28
SNN_FBB_PLLVDD_NC
60.4
COMMON
COMMON
1%
1%
0402
0402
R633
R633
40.2
40.2
COMMON
COMMON
1%
1%
0402
0402
R634
40.2R634
40.2
COMMON
COMMON
1%
1%
0402
0402
GND
4
AC28
GND
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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ASSEMBLY
PAGE DETAIL
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition A/B
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Date:
Date:
Thursday, October 18, 2007
Thursday, October 18, 2007
Thursday, October 18, 2007
Sheet of
Sheet of
Sheet of
HFDBA
3
3
3
<RevCode>
<RevCode>
<RevCode>
27
27
27
A B C D E F G H
Page4: MEMORY: GPU Partition C/D
1
FBC_D[63..0]
7
BI
2
3
FBC_DQM[7..0]
7
OUT
FBC_DQS_RN[7..0]
7
IN
4
FBC_DQS_WP[7..0]
7
OUT
G1E
G1E
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
4/24 MEM_C
FBC_D0
0
FBC_D1
1
FBC_D2
2
FBC_D3
3
FBC_D4
4
FBC_D5
5
FBC_D6
6
FBC_D7
7
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_D32
32
FBC_D33
33
FBC_D34
34
FBC_D35
35
FBC_D36
36
FBC_D37
37
FBC_D38
38
FBC_D39
39
FBC_D40
40
FBC_D41
41
FBC_D42
42
FBC_D43
43
FBC_D44
44
FBC_D45
45
FBC_D46
46
FBC_D47
47
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_DQM0
0
FBC_DQM1
1
FBC_DQM2
2
FBC_DQM3
3
FBC_DQM4
4
FBC_DQM5
5
FBC_DQM6
6
FBC_DQM7
7
FBC_DQS_RN0
0
FBC_DQS_RN1
1
FBC_DQS_RN2
2
FBC_DQS_RN3
3
FBC_DQS_RN4
4
FBC_DQS_RN5
5
FBC_DQS_RN6
6
FBC_DQS_RN7
7
FBC_DQS_WP0
0
FBC_DQS_WP1
1
FBC_DQS_WP2
2
FBC_DQS_WP3
3
FBC_DQS_WP4
4
FBC_DQS_WP5
5
FBC_DQS_WP6
6
FBC_DQS_WP7
7
C18
C17
A17
B16
C14
A16
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
C23
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30
C16
C20
G14
C26
A28
D29
D27
B33
B15
A21
D14
B25
A27
E30
E25
A33
A15
A20
E13
A25
A26
D30
E26
A32
4/24 MEM_C
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_DEBUG
FBC_PLLVDD_NC
FBC_DLLAVDD
FBC_PLLAVDD
FBC_PLLGND
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_CMD0
F18
FBC_CMD1
H20
FBC_CMD2
E18
FBC_CMD3
E20
FBC_CMD4
D23
FBC_CMD5
G24
FBC_CMD6
D24
FBC_CMD7
G23
FBC_CMD8
D20
FBC_CMD9
E22
FBC_CMD10
J21
FBC_CMD11
E21
FBC_CMD12
G20
FBC_CMD13
F22
FBC_CMD14
H21
FBC_CMD15
E17
FBC_CMD16
E19
FBC_CMD17
D21
FBC_CMD18
E23
FBC_CMD19
F19
FBC_CMD20
E24
FBC_CMD21
G21
FBC_CMD22
G19
FBC_CMD23
G25
FBC_CMD24
G18
FBC_CMD25
G22
G17
F15
G15
FBC_CLK0
H17
FBC_CLK0*
J16
FBC_CLK1
J24
FBC_CLK1*
H23
H24
RFU
J25
RFU
FBC_DEBUG
H16
SNN_FBC_PLLVDD_NC
H13
FBCD_PLLAVDD
J11
J12
J13
GND
C832
C832
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBC_CMD[25..0]
OUT
OUT
OUT
OUT
7
7
7
7
7
OUT
136BGA CMD Mapping
ADDR
CMD
CMD0 A<4>
CMD1 RAS*
CMD2
A<5>
CMD3
BA1
CMD4
A<2>
CMD5
A<4>
CMD6
A<3>
BA2CMD7
CMD8
CS0*
CMD9 A<11>
CMD10
CAS*
CMD11
WE*
CMD12
BA0
CMD13
A<5>
CMD14
A<12>
CMD15
RST
CMD16
A<7>
CMD17
A<10>
CMD18
CKE
CMD19
A<0>
CMD20
A<9>
CMD21
A<6>
CMD22
A<2>
CMD23
A<8>
CMD24
A<3>
CMD25
A<1>
CMD26
A<13>
CMD27
BA2
CMD28
N/A
FBVDD
R638
R638
60.4
60.4
1%
1%
0402
0402
DNI
DNI
(OPT) (OPT)
BI
BI
1V2
240R@100MHz
240R@100MHz
LB503
LB503
IND_SMD_0402COMMON
IND_SMD_0402COMMON
C841
C841
C855
C822
C822
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C855
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C852
C852
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
FBD_D[63..0]
8
BI
FBD_DQM[7..0]
8
OUT
FBD_DQS_RN[7..0]
8
IN
FBD_DQS_WP[7..0]
OUT
8
FBD_D0
0
FBD_D1
1
FBD_D2
2
FBD_D3
3
FBD_D4
4
FBD_D5
5
FBD_D6
6
FBD_D7
7
FBD_D8
8
FBD_D9
9
FBD_D10
10
FBD_D11
11
FBD_D12
12
FBD_D13
13
FBD_D14
14
FBD_D15
15
FBD_D16
16
FBD_D17
17
FBD_D18
18
FBD_D19
19
FBD_D20
20
FBD_D21
21
FBD_D22
22
FBD_D23
23
FBD_D24
24
FBD_D25
25
FBD_D26
26
FBD_D27
27
FBD_D28
28
FBD_D29
29
FBD_D30
30
FBD_D31
31
FBD_D32
32
FBD_D33
33
FBD_D34
34
FBD_D35
35
FBD_D36
36
FBD_D37
37
FBD_D38
38
FBD_D39
39
FBD_D40
40
FBD_D41
41
FBD_D42
42
FBD_D43
43
FBD_D44
44
FBD_D45
45
FBD_D46
46
FBD_D47
47
FBD_D48
48
FBD_D49
49
FBD_D50
50
FBD_D51
51
FBD_D52
52
FBD_D53
53
FBD_D54
54
FBD_D55
55
FBD_D56
56
FBD_D57
57
FBD_D58
58
FBD_D59
59
FBD_D60
60
FBD_D61
61
FBD_D62
62
FBD_D63
63
FBD_DQM0
0
FBD_DQM1
1
FBD_DQM2
2
FBD_DQM3
3
FBD_DQM4
4
FBD_DQM5
5
FBD_DQM6
6
FBD_DQM7
7
FBD_DQS_RN0
0
FBD_DQS_RN1
1
FBD_DQS_RN2
2
FBD_DQS_RN3
3
FBD_DQS_RN4
4
FBD_DQS_RN5
5
FBD_DQS_RN6
6
FBD_DQS_RN7
7
FBD_DQS_WP0
0
FBD_DQS_WP1
1
FBD_DQS_WP2
2
FBD_DQS_WP3
3
FBD_DQS_WP4
4
FBD_DQS_WP5
5
FBD_DQS_WP6
6
FBD_DQS_WP7
7
G1F
G1F
BGA_1148_P100_375X375_G3_256B
BGA_1148_P100_375X375_G3_256B
COMMON
COMMON
5/24 MEM_D
5/24 MEM_D
H3
FBDD0
J3
FBDD1
J1
FBDD2
J2
FBDD3
M3
FBDD4
K3
FBDD5
L3
FBDD6
M1
FBDD7
H1
FBDD8
G3
FBDD9
G1
FBDD10
G2
FBDD11
F3
FBDD12
E1
FBDD13
D1
FBDD14
D2
FBDD15
P4
FBDD16
N7
FBDD17
M7
FBDD18
N5
FBDD19
P5
FBDD20
R7
FBDD21
T7
FBDD22
P7
FBDD23
C1
FBDD24
C5
FBDD25
C2
FBDD26
B4
FBDD27
A3
FBDD28
B3
FBDD29
C4
FBDD30
C3
FBDD31
A8
FBDD32
C6
FBDD33
C7
FBDD34
A7
FBDD35
C8
FBDD36
C9
FBDD37
A9
FBDD38
B9
FBDD39
E12
FBDD40
E9
FBDD41
F9
FBDD42
G10
FBDD43
D10
FBDD44
G12
FBDD45
F12
FBDD46
D11
FBDD47
F4
FBDD48
E4
FBDD49
D4
FBDD50
D5
FBDD51
D8
FBDD52
E7
FBDD53
D7
FBDD54
D9
FBDD55
B13
FBDD56
C11
FBDD57
A13
FBDD58
C13
FBDD59
A11
FBDD60
A10
FBDD61
B10
FBDD62
C10
FBDD63
K2
FBDDQM0
E3
FBDDQM1
N4
FBDDQM2
D3
FBDDQM3
B7
FBDDQM4
G11
FBDDQM5
F5
FBDDQM6
C12
FBDDQM7
K1
FBDDQS_RN0
F2
FBDDQS_RN1
R6
FBDDQS_RN2
A4
FBDDQS_RN3
B6
FBDDQS_RN4
E10
FBDDQS_RN5
E6
FBDDQS_RN6
A12
FBDDQS_RN7
L1
FBDDQS_WP0
F1
FBDDQS_WP1
R5
FBDDQS_WP2
A5
FBDDQS_WP3
A6
FBDDQS_WP4
E11
FBDDQS_WP5
D6
FBDDQS_WP6
B12
FBDDQS_WP7
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
FBD_DEBUG
FBD_PLLVDD_NC
FBD_PLLGND
1
FBD_CMD0
M6
FBD_CMD1
G5
FBD_CMD2
L7
FBD_CMD3
K5
FBD_CMD4
J10
FBD_CMD5
G8
FBD_CMD6
F8
FBD_CMD7
G6
FBD_CMD8
H6
FBD_CMD9
F6
FBD_CMD10
K8
FBD_CMD11
L5
FBD_CMD12
H4
FBD_CMD13
G4
FBD_CMD14
K9
FBD_CMD15
L4
FBD_CMD16
K4
FBD_CMD17
K7
FBD_CMD18
G7
FBD_CMD19
J4
FBD_CMD20
F7
FBD_CMD21
J5
FBD_CMD22
J6
FBD_CMD23
H7
FBD_CMD24
L8
FBD_CMD25
J7
M5
H9
G9
FBD_CLK0
L9
FBD_CLK0*
M9
FBD_CLK1
J9
FBD_CLK1*
J8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBD_CMD[25..0]
OUT
OUT
OUT
OUT
8
8
8
8
OUT
8
2
3
FBVDD
R645
R645
60.4
60.4
1%
1%
0402
0402
DNI
H10
RFU
L11
RFU
FBD_DEBUG
N8
SNN_FBD_PLLVDD_NC
H11
DNI
BI
4
H12
GND
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
Place components as close
as possible to the pad
GND
www.vinafix.vn
Place these components within
750 mils of the pad
ASSEMBLY
PAGE DETAIL
GND
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
MEMORY: GPU Partition C/D
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Date:
Date:
Thursday, October 18, 2007
Thursday, October 18, 2007
Thursday, October 18, 2007
Sheet of
Sheet of
Sheet of
HFDBA
427
427
427
5
<RevCode>
<RevCode>
<RevCode>
A B C D E F G H
Page5: FBA Partition
M6A
136BGA CMD Mapping
ADDR
136MAP
RAS*
1
2
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R592
R592
121
121
1%
1%
0402
0402
DNI
DNI
FBA_CLK0_MIDPT
FBA_CMD[25..0] FBA_CMD[25..0]
3,5,9
IN
3,9 FBA_CLK0
IN
3,9
IN
R589
R589
R588
R588
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C615
C615
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
9
GND
IN
FBA_CMD1
1
FBA_CMD10
10
FBA_CMD11
11
FBA_CMD8
8
FBA_CMD19
19
FBA_CMD25
25
22
FBA_CMD24
24
FBA_CMD0
0
FBA_CMD2
2
FBA_CMD21
21
FBA_CMD16
16
FBA_CMD23
23
FBA_CMD20
20
FBA_CMD17
17
FBA_CMD9
9
FBA_CMD12
12
3
FBA_CMD3
7
FBA_CMD7
FBA_CMD18
18
FBA_CMD18
FBA_CLK0*
FBA_CMD14 FBA_CMD14
14
FBA_CMD15 FBA_CMD15
15
FBA_CMD15
FBA_ZQ0
R604
R604
R585
R585
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDD
C146
C146
.047UF
.047UF
16V
16V
10%
10%
X7R
3
X7R
0402
0402
COMMON
COMMON
GND
BI
BI
BI
BI
FBA_D[63..0]
FBA_DQM[7..0]
FBA_DQS_RN[7..0]
FBA_DQS_WP[7..0]
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_DQM0
0
FBA_DQM1
1
FBA_DQM2
2
FBA_DQM3
3
4
FBA_DQM5
5
FBA_DQM6
6
FBA_DQM7
7
FBA_DQS_RN0
0
FBA_DQS_RN1
1
FBA_DQS_RN2
2
FBA_DQS_RN3
3
FBA_DQS_RN4
4
FBA_DQS_RN5
5
FBA_DQS_RN6
6
FBA_DQS_RN7
7
FBA_DQS_WP0
0
FBA_DQS_WP1
1
FBA_DQS_WP2
2
FBA_DQS_WP3
3
FBA_DQS_WP4
4
FBA_DQS_WP5
5
FBA_DQS_WP6
6
FBA_DQS_WP7
7
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_DQM0
FBA_DQS_RN0
FBA_DQS_WP0
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_DQM4
FBA_DQS_RN4
FBA_DQS_WP4
3,9
3,9
4
3,9
3,9
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
M6A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
GND
R115
R115
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
K12
C132
C132
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
J12
M6E
M6E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
L10
DQ0
T10
DQ1
M10
DQ2
R11
DQ3
T11
DQ4
R10
DQ5
N11
DQ6
M11
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M7E
M7E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
L3
DQ0
R3
DQ1
T3
DQ2
M3
DQ3
M2
DQ4
N2
DQ5
T2
DQ6
R2
DQ7
N3
DQM
P3
RDQS
P2
WDQS
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_DQM1
FBA_DQS_RN1
FBA_DQS_WP1
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_DQM5
FBA_DQS_RN5
FBA_DQS_WP5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDD
F1
M1
A2
V2
A11
V11
F12
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBA_VREF0
H1
FBA_VREF2
H12
M6B
M6B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
R3
DQ0
T2
DQ1
R2
DQ2
N2
DQ3
T3
DQ4
M3
DQ5
M2
DQ6
L3
DQ7
N3
DQM
P3
RDQS
P2
WDQS
M7A
M7A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
B10
DQ0
E11
DQ1
F11
DQ2
C10
DQ3
C11
DQ4
G10
DQ5
F10
DQ6
B11
DQ7
E10
DQM
D10
RDQS
D11
WDQS
FBVDD
R111
R111
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
R109
R109
C131
C131
1.33K
1.33K
.1UF
.1UF
R2
1%
1%
10V
10V
10%
10%
0402
0402
COMMON
COMMON
X5R
X5R
0402
0402
COMMON
GND
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
COMMON
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_DQM2
FBA_DQS_RN2
FBA_DQS_WP2
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_DQM6
FBA_DQS_RN6
FBA_DQS_WP6
GND
C GE
OUT
136BGA CMD Mapping
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
9
M6C
M6C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
F2
DQ0
G3
DQ1
F3
DQ2
C2
DQ3
E2
DQ4
C3
DQ5
B3
DQ6
B2
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M7B
M7B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
B3
DQ0
C3
DQ1
F3
DQ2
C2
DQ3
F2
DQ4
E2
DQ5
B2
DQ6
G3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
ASSEMBLY
PAGE DETAIL
136MAPADDR
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD00A<4>
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
R593
R593
121
121
1%
1%
0402
0402
DNI
DNI
3,5,9
IN
3,9 FBA_CLK1
IN
3,9
IN
R602
R602
R601
R601
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
FBA_CLK1_MIDPT
COMMON
C616
C616
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
COMMON
COMMON
FBVDD
0402
0402
GND
FBVDD
R120
R120
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R123
R123
1.33K
1.33K
R2
1%
1%
0402
0402
C149
C149
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
9
OUT
GND
M6D
M6D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_DQM3FBA_DQM4
FBA_DQS_RN3
FBA_DQS_WP3
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DQM7
FBA_DQS_RN7
FBA_DQS_WP7
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBA Partition
COMMON
E11
B11
F11
G10
C10
C11
B10
F10
E10
D10
D11
M7C
M7C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
M11
N11
M10
L10
T10
R11
T11
R10
N10
P10
P11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M7D
M7D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
FBA_CMD7
7
FBA_CMD8
8
FBA_CMD18
18
FBA_CMD10
10
FBA_CMD5 FBA_CMD5
5
FBA_CMD13
13
FBA_CMD21FBA_CMD22
21
FBA_CMD20
20
FBA_CMD19
19
FBA_CMD25
25
FBA_CMD4
4
FBA_CMD9
9
FBA_CMD17
17
FBA_CMD6
6
FBA_CMD23
23
FBA_CMD16
16
FBA_CMD3
3
12
FBA_CMD12
1
FBA_CMD1
FBA_CMD11
11
FBA_CLK1*
14
15
FBA_ZQ1
9
IN
FBVDD
C134
C134
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
Decoupling
for FBA Lo
Decoupling
for FBA Hi
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
R116
R116
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
K12
C147
C147
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
J12
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDD
C624
C624
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C647
C647
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C576
C576
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
FBVDD
COMMON
COMMON
C595
C595
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C646
C646
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C623
C623
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBVDD
F1
M1
A2
V2
A11
V11
F12
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
GND
G12
L12
FBA_VREF1
H1
FBA_VREF3
H12
C608
C608
C598
C598
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C587
C587
C614
C614
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C632
C632
C574
C574
4.7UF
4.7UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0805
0805
0805
0805
COMMON
COMMON
COMMON
COMMON
C629
C629
C637
C637
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C617
C617
C642
C642
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C577
C577
C579
C579
4.7UF
4.7UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0805
0805
0805
0805
COMMON
COMMON
COMMON
COMMON
FBA_CMD4
FBA_CMD6
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
GDDR3: VREF = 0.70 * FBVDDQ
1.41V = 2.0V * 1.33K/(549 + 1.33K)
R597
R597
1%
1%
0402
0402
R598
R598
1%
1%
0402
0402
R591
R591
1%
1%
0402
0402
R587
R587
1%
1%
0402
0402
R599
R599
1%
1%
0402
0402
R595
R595
1%
1%
0402
0402
R590
R590
1%
1%
0402
0402
R579
R579
1%
1%
0402
0402
FBVDD
R119
R119
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R122
R122
1.33K
1.33K
R2
1%
1%
0402
0402
C148
C148
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
9
OUT
GND
C597
C597
C636
C636
C625
C625
C599
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C641
C641
1UF
1UF
Place 1uF caps at
16V
16V
center of memory
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C585
C585
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C600
C600
C601
C601
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C581
C581
1UF
1UF
Place 1uF caps at
16V
16V
center of memory
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C633
C633
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
C599
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C584
C584
C580
C580
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
C609
C609
C627
C627
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C589
C589
C638
C638
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
121
121
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
R112
R112
R110
R110
1.33K
1.33K
549
549
0402
0402
0402
0402
C630
C630
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C586
C586
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C628
C628
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C582
C582
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
FBVDD
1
2
FBVDD
R1
1%
1%
R2
1%
1%
GND
C631
C631
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C133
C133
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
9
OUT
3
C602
C602
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
C635
C635
C640
C640
.1UF
.1UF
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C596
C596
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
(OPT) (OPT)(OPT)(OPT)(OPT)(OPT)
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C626
C626
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
4
GND
GND
C588
C588
C583
C583
.1UF
.1UF
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
Sheet of
Sheet of
Sheet of
HFDBA
GND
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
GND
527
527
527
5
<RevCode>
<RevCode>
<RevCode>
www.vinafix.vn
A B C D E F G H
Page6: FBB Partition
136BGA CMD Mapping
ADDR
136MAP
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
BA2
CMD7
CMD12
BA0
CMD3
BA1
1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23
A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
2
CKE
CMD15
RST
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
R613
R613
121
121
1%
1%
(OPT)
0402
0402
DNI
DNI
FBB_CLK0_MIDPT
3
IN
3
IN
R609
R609
COMMON
COMMON
3
FBB_D[63..0]
BI
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
FBB_DQM[7..0]
BI
3
FBB_DQS_RN[7..0]
BI
3
FBB_DQS_WP[7..0]
BI
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBB_CMD[25..0]
IN
3
R611
R611
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
C659
C659
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
IN
COMMON
COMMON
GND
FBB_CMD1
1
FBB_CMD10
10
FBB_CMD11
11
FBB_CMD8
8
FBB_CMD19
19
FBB_CMD25
25
22
FBB_CMD24
24
FBB_CMD0
0
2
FBB_CMD21
21
FBB_CMD16
16
FBB_CMD23
23
FBB_CMD20
20
FBB_CMD17
17
FBB_CMD9
9
12
FBB_CMD12
3
FBB_CMD3
7
FBB_CMD7
FBB_CMD18
18
FBB_CLK0
FBB_CLK0*
FBB_CMD14 FBB_CMD14
14
FBB_CMD15 FBB_CMD15
15
FBB_CMD15
FBB_ZQ0
FBB_CMD18
R606
R606
R608
R608
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDD
C109
C109
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
FBB_D0
0
FBB_D1
1
FBB_D2
2
FBB_D3
3
FBB_D4
4
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_D5
5
FBB_D6
6
FBB_D7
7
FBB_DQM0
FBB_DQS_RN0
FBB_DQS_WP0
FBB_D32
32
FBB_D33
33
FBB_D34
34
FBB_D35
35
FBB_D36
36
FBB_D37
37
FBB_D38
38
FBB_D39
39
FBB_DQM4
FBB_DQS_RN4
FBB_DQS_WP4
M5A
M5A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
GND
R104
R104
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
K12
C129
C129
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
J12
M5E
M5E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
L10
DQ0
R10
DQ1
M10
DQ2
R11
DQ3
T11
DQ4
T10
DQ5
M11
DQ6
N11
DQ7
N10
DQM
P10
RDQS
P11
WDQS
M8E
M8E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
L3
DQ0
R3
DQ1
T3
DQ2
M2
DQ3
M3
DQ4
T2
DQ5
R2
DQ6
N2
DQ7
N3
DQM
P3
RDQS
P2
WDQS
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_DQM1
FBB_DQS_RN1
FBB_DQS_WP1
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_DQM5
FBB_DQS_RN5
FBB_DQS_WP5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBVDD
F1
M1
A2
V2
A11
V11
F12
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBB_VREF0
H1
FBB_VREF2
H12
M5B
M5B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
M2
DQ0
T3
DQ1
R2
DQ2
N2
DQ3
R3
DQ4
T2
DQ5
M3
DQ6
L3
DQ7
N3
DQM
P3
RDQS
P2
WDQS
M8A
M8A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
F10
DQ0
E11
DQ1
F11
DQ2
B10
DQ3
B11
DQ4
C10
DQ5
G10
DQ6
C11
DQ7
E10
DQM
D10
RDQS
D11
WDQS
FBVDD
R105
R105
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
R106
R106
1.33K
1.33K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_DQM2
FBB_DQS_RN2
FBB_DQS_WP2
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_DQM6
FBB_DQS_RN6
FBB_DQS_WP6
C GE
C108
C108
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
OUT
G3
C3
B3
E2
F3
C2
B2
F2
E3
D3
D2
R11
R10
T10
N11
M10
T11
M11
L10
N10
P10
P11
ASSEMBLY
PAGE DETAIL
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
3
3
R586
R586
121
121
1%
1%
(OPT)
0402
0402
DNI
DNI
FBB_CLK1_MIDPT
COMMON
COMMON
FBB_CMD[25..0]
3
IN
IN
IN
R596
R596
R600
R600
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
FBVDD
C610
C610
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
FBVDD
R107
R107
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R108
R108
1.33K
1.33K
1%
1%
0402
0402
OUT
C128
C128
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
M5C
M5C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M8B
M8B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_DQM3FBB_DQM4
FBB_DQS_RN3
FBB_DQS_WP3
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_DQM7
FBB_DQS_RN7
FBB_DQS_WP7
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBB Partition
M5D
M5D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
E11
B11
F11
C11
B10
C10
G10
F10
E10
D10
D11
M8C
M8C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
E2
C2
G3
F2
B3
F3
B2
C3
E3
D3
D2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
FBB_CMD3
12
FBB_CMD12
1
FBB_CMD1
11
14
15
FBB_ZQ1
IN
FBVDD
C130
C130
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
Decoupling
for FBB Lo
Decoupling
for FBB Hi
FBB_CMD7
FBB_CMD8
FBB_CMD18
FBB_CMD10
FBB_CMD5
FBB_CMD13
FBB_CMD21FBB_CMD22
FBB_CMD20
FBB_CMD19
FBB_CMD25FBB_CMD2
FBB_CMD4
FBB_CMD9
FBB_CMD17
FBB_CMD6
FBB_CMD23
FBB_CMD16
FBB_CMD11
FBB_CLK1
FBB_CLK1*
GND
GND
R121
R121
243
243
1%
1%
0402
0402
COMMON
COMMON
C141
C141
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M8D
M8D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
FBVDD
FBVDD
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VREF
C666
C666
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C645
C645
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C672
C672
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C590
C590
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C591
C591
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C572
C572
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBVDD
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBB_VREF1
H1
FBB_VREF3
H12
C656
C656
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C665
C665
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C644
C644
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C618
C618
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C649
C649
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C605
C605
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBVDD
R118
R118
549
549
1%
1%
0402
0402
COMMON
COMMON
R117
R117
1.33K
1.33K
1%
1%
0402
0402
COMMON
COMMON
GND
C661
C661
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C663
C663
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C664
C664
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C613
C613
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C620
C620
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C603
C603
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C652
C652
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C669
C669
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C634
C634
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C621
C621
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
FBB_CMD4
FBB_CMD6
FBB_CMD5
FBB_CMD13
FBB_CMD22
FBB_CMD24
FBB_CMD0
FBB_CMD2
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
R1
OUT
C144
C144
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C660
C660
C667
C667
C655
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place 1uF caps at
center of memory
C654
C654
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
C607
C607
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
Place 1uF caps at
center of memory
C612
C612
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
C655
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C651
C651
C668
C668
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
C639
C639
C606
C606
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C611
C611
C619
C619
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
R605
R605
R603
R603
R594
R594
R584
R584
R614
R614
R610
R610
R612
R612
R607
R607
COMMON
COMMON
COMMON
COMMON
FBVDD
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
121
121
COMMON
COMMON
1%
1%
0402
0402
1
2
FBVDD
R114
R114
549
549
R1
1%
1%
0402
R113
R113
1.33K
1.33K
0402
0402
0402
C657
C657
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
1%
1%
GND
OUT
C136
C136
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
3
C653
C653
C650
C650
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
C662
C648
C648
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C622
C622
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C662
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C575
C575
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
4
GND
C658
C658
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C643
C643
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
C578
C573
C573
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
Sheet of
Sheet of
Sheet of
HFDBA
C578
.1UF
.1UF
GND
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
GND
627
627
627
5
<RevCode>
<RevCode>
<RevCode>
C604
C604
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
www.vinafix.vn
A B C D E F G H
Page7: FBC Partition
M3A
136BGA CMD Mapping
136MAPADDR
CMD1
1
2
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23
A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
9,4
9,4
FBVDD
R659
R659
121
121
1%
1%
0402
0402
DNI
DNI
FBC_CLK0_MIDPT FBC_CLK1_MIDPT
FBC_CMD[25..0] FBC_CMD[25..0]
IN
9,7,4
IN
IN
R658
R658
R655
R655
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C864
C864
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
9,
GND
FBC_CMD1
1
FBC_CMD10
10
FBC_CMD11
11
FBC_CMD8
8
FBC_CMD19
19
FBC_CMD25
25
22
FBC_CMD24
24
FBC_CMD0
0
FBC_CMD2
2
FBC_CMD21
21
FBC_CMD16
16
FBC_CMD23
23
FBC_CMD20
20
FBC_CMD17
17
FBC_CMD9
9
12
FBC_CMD12
3
FBC_CMD3
7
FBC_CMD7
18
FBC_CMD18
FBC_CLK0
FBC_CLK0*
FBC_CMD14 FBC_CMD14
14
FBC_CMD15 FBC_CMD15
15
FBC_CMD15
FBC_ZQ0
IN
FBC_CMD18
R640
R640
R635
R635
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDD
C86
C86
.047UF
.047UF
16V
16V
10%
10%
X7R
3
X7R
0402
0402
COMMON
COMMON
GND
BI
BI
BI
BI
FBC_D[63..0]
FBC_DQM[7..0]
FBC_DQS_RN[7..0]
FBC_DQS_WP[7..0]
FBC_D0
0
FBC_D1
1
FBC_D2
2
FBC_D3
3
FBC_D4
4
FBC_DQM0
0
FBC_DQM1
1
FBC_DQM2
2
FBC_DQM3
3
4
FBC_DQM5
5
FBC_DQM6
6
FBC_DQM7
7
FBC_DQS_RN0
0
FBC_DQS_RN1
1
FBC_DQS_RN2
2
FBC_DQS_RN3
3
FBC_DQS_RN4
4
FBC_DQS_RN5
5
FBC_DQS_RN6
6
FBC_DQS_RN7
7
FBC_DQS_WP0
0
FBC_DQS_WP1
1
FBC_DQS_WP2
2
FBC_DQS_WP3
3
FBC_DQS_WP4
4
FBC_DQS_WP5
5
FBC_DQS_WP6
6
FBC_DQS_WP7
7
FBC_D5
5
FBC_D6
6
FBC_D7
7
FBC_DQM0
FBC_DQS_RN0
FBC_DQS_WP0
FBC_D32
32
FBC_D33
33
FBC_D34
34
FBC_D35
35
FBC_D36
36
FBC_D37
37
FBC_D38
38
FBC_D39
39
FBC_DQM4
FBC_DQS_RN4
FBC_DQS_WP4
9,4
4
9,4
9,4
9,4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
M3A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
GND
R93
R93
243
243
1%
1%
0402
0402
COMMON
COMMON
GND
K1
K12
C87
C87
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
J1
J12
B11
C11
F11
G10
C10
E11
F10
B10
E10
D10
D11
M2
R3
T3
M3
L3
N2
R2
T2
N3
P3
P2
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
M3E
M3E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4E
M4E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_DQM1
FBC_DQS_RN1
FBC_DQS_WP1
FBC_D40
40
FBC_D41
41
FBC_D42
42
FBC_D43
43
FBC_D44
44
FBC_D45
45
FBC_D46
46
FBC_D47
47
FBC_DQM5
FBC_DQS_RN5
FBC_DQS_WP5
FBVDD
F1
M1
A2
V2
A11
V11
F12
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF0
H1
FBC_VREF2
H12
M2
T2
R2
N2
R3
T3
L3
M3
N3
P3
P2
B10
E11
F11
C11
B11
G10
F10
C10
E10
D10
D11
GND
M3B
M3B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M4A
M4A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBVDD
R95
R95
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
R97
R97
1.33K
1.33K
R2
1%
1%
0402
0402
COMMON
COMMON
GND
GDDR3: VREF = 0.70 * FBVDDQ
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_DQM2
FBC_DQS_RN2
FBC_DQS_WP2
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_DQM6
FBC_DQS_RN6
FBC_DQS_WP6
C84
C84
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C GE
OUT
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
M3C
M3C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
C2
DQ0
G3
DQ1
F3
DQ2
E2
DQ3
F2
DQ4
B2
DQ5
B3
DQ6
C3
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M4B
M4B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
L10
DQ0
M11
DQ1
R11
DQ2
T11
DQ3
R10
DQ4
M10
DQ5
N11
DQ6
T10
DQ7
N10
DQM
P10
RDQS
P11
WDQS
ASSEMBLY
PAGE DETAIL
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
R623
R623
121
121
1%
1%
0402
0402
DNI
DNI
IN
9,7,4
IN
9,4
IN
9,4
R621
R621
R625
R625
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDD
C703
C703
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
FBVDD
R94
R94
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R96
R96
1.33K
1.33K
1%
1%
0402
0402
OUT
C83
C83
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
M3D
M3D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_DQM3FBC_DQM4
FBC_DQS_RN3
FBC_DQS_WP3
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_DQM7
FBC_DQS_RN7
FBC_DQS_WP7
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBC Partition
COMMON
L10
M10
N11
R10
T11
R11
M11
T10
N10
P10
P11
M4C
M4C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
E2
B2
G3
C2
C3
F2
B3
F3
E3
D3
D2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
FBC_CMD12
1
FBC_CMD1
11
14
15
IN
9,
FBVDD
C100
C100
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
Decoupling
for FBC Lo
Decoupling
for FBC Hi
FBC_CMD7
FBC_CMD8
FBC_CMD18
FBC_CMD10
FBC_CMD5
FBC_CMD13
FBC_CMD21FBC_CMD22
FBC_CMD20
FBC_CMD19
FBC_CMD25
FBC_CMD4
FBC_CMD9
FBC_CMD17
FBC_CMD23
FBC_CMD16
FBC_CMD3
FBC_CMD11
FBC_CLK1
FBC_CLK1*
GND
GND
FBC_ZQ1
R102
R102
243
243
1%
1%
0402
0402
COMMON
COMMON
C98
C98
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
M4D
M4D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
FBVDD
FBVDD
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VREF
C835
C835
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C882
C882
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C893
C893
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C685
C685
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C690
C690
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C691
C691
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBVDD
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
GND
G12
L12
FBC_VREF1
H1
FBC_VREF3
H12
C850
C850
C836
C836
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C838
C838
C880
C880
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C883
C883
C840
C840
4.7UF
4.7UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0805
0805
0805
0805
COMMON
COMMON
COMMON
COMMON
C742
C742
C726
C726
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C689
C689
C766
C766
1UF
1UF
1UF
1UF
16V
16V
16V
16V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0603
0603
0603
0603
COMMON
COMMON
COMMON
COMMON
C738
C738
C678
C678
4.7UF
4.7UF
4.7UF
4.7UF
6.3V
6.3V
6.3V
6.3V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0805
0805
0805
0805
COMMON
COMMON
COMMON
COMMON
FBC_CMD4
FBC_CMD6
FBC_CMD5FBC_CMD6
FBC_CMD13
FBC_CMD22
FBC_CMD24
FBC_CMD0
FBC_CMD2
GDDR3:
VREF = 0.70 * FBVDDQ
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R101
R101
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R99
R99
1.33K
1.33K
1%
1%
0402
0402
OUT
C103
C103
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
C847
C847
C834
C834
C887
C887
.1UF
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C813
C813
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C749
C749
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C741
C741
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
Place 1uF caps at
center of memory
C888
C888
C875
C875
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
C695
C695
C684
C684
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
Place 1uF caps at
center of memory
C696
C696
C683
C683
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date:
Date:
Date:
R632
121
R632
121
COMMON
COMMON
1%
1%
0402
0402
R631
121
R631
121
COMMON
COMMON
1%
1%
0402
0402
R622
121
R622
121
COMMON
COMMON
1%
1%
0402
0402
R627
121
R627
121
COMMON
COMMON
1%
1%
0402
0402
R654
121
R654
121
COMMON
COMMON
1%
1%
0402
0402
R648
121
R648
121
COMMON
COMMON
1%
1%
0402
0402
R653 121
R653 121
COMMON
COMMON
1%
1%
0402
0402
R657 121
R657 121
COMMON
COMMON
1%
1%
0402
0402
FBVDD
R100
R100
549
549
1%
1%
0402
0402
COMMON
COMMON
R98
R98
1.33K
1.33K
1%
1%
0402
0402
COMMON
COMMON
GND
C878
C878
C876
C876
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C851
C851
C846
C846
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
C740
C740
C739
C739
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C725
C725
C748
C748
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
<Doc>
<Doc>
<Doc>
Thursday, October 18, 2007
Thursday, October 18, 2007
Thursday, October 18, 2007
FBVDD
R1
R2
C102
C102
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C830
C830
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C886
C886
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C686
C686
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C693
C693
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
Sheet of
Sheet of
Sheet of
HFDBA
C889
C889
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C829
C829
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C694
C694
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C717
C717
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
OUT
GND
GND
(OPT)(OPT)(OPT)(OPT)(OPT)(OPT)
GND
GND
GND
GND
<RevCode>
<RevCode>
<RevCode>
727
727
727
1
2
3
4
5
www.vinafix.vn
A B C D E F G H
Page8: FBD Partition
M1A
GND
GND
GND
C57
C57
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C11
E11
F11
G10
B11
F10
C10
B10
E10
D10
D11
L10
R10
T10
N11
T11
M10
M11
R11
N10
P10
P11
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
R28
R28
243
243
1%
1%
0402
0402
COMMON
COMMON
K1
K12
J1
J12
M1E
M1E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M2E
M2E
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M1A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBVDD
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_DQM1
FBD_DQS_RN1
FBD_DQS_WP1
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_DQM5
FBD_DQS_RN5
FBD_DQS_WP5
F1
VDD
M1
VDD
A2
VDD
V2
VDD
A11
VDD
V11
VDD
F12
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
N2
T2
R2
R3
T3
M2
L3
M3
N3
P3
P2
C10
F11
E11
B11
C11
G10
F10
B10
E10
D10
D11
FBVDD
GND
GND
FBD_VREF0
FBD_VREF2
M1B
M1B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M2A
M2A
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
FBVDD
R42
R42
549
549
1%
1%
0402
0402
COMMON
COMMON
R47
R47
1.33K
1.33K
1%
1%
0402
0402
COMMON
COMMON
GND
FBD_D16
16
FBD_D17
17
FBD_D18
18
FBD_D19
19
FBD_D20
20
FBD_D21
21
FBD_D22
22
FBD_D23
23
FBD_DQM2
FBD_DQS_RN2
FBD_DQS_WP2
FBD_D48
48
FBD_D49
49
FBD_D50
50
FBD_D51
51
FBD_D52
52
FBD_D53
53
FBD_D54
54
FBD_D55
55
FBD_DQM6
FBD_DQS_RN6
FBD_DQS_WP6
R1
R2
GDDR3: VREF = 0.70 * FBVDDQ
1.41V = 2.0V * 1.33K/(549 + 1.33K)
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
C GE
136BGA CMD Mapping
ADDR
136MAP
RAS*
CMD1
CMD10
CAS*
CMD11
WE*
CS0*
CMD8
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
1
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
0A<4>
CMD0
0A<5>
CMD2
1A<2>
CMD4
CMD6
1A<3>
1A<4>
CMD5
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23
A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
2
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
(OPT)
R706
R706
121
121
1%
1%
0402
0402
DNI
DNI
4,9
IN
4,9
IN
COMMON
COMMON
FBD_CLK0_MIDPT
FBD_CMD[25..0] FBD_CMD[25..0]
4,8,9
IN
R709
R709
R707
R707
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
C958
C958
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
9
GND
FBD_CMD1
1
FBD_CMD10
10
FBD_CMD11
11
FBD_CMD8
8
FBD_CMD19
19
FBD_CMD25
25
22
FBD_CMD24
24
FBD_CMD0
0
FBD_CMD2
2
FBD_CMD21
21
FBD_CMD16
16
FBD_CMD23
23
FBD_CMD20
20
FBD_CMD17
17
FBD_CMD9
9
FBD_CMD12
12
3
FBD_CMD3
7
FBD_CMD7
FBD_CMD18
18
FBD_CMD18
FBD_CLK0
FBD_CLK0*
FBD_CMD14 FBD_CMD14
14
FBD_CMD15 FBD_CMD15
15
FBD_CMD15
FBD_ZQ0
IN
R690
R690
R694
R694
10K
10K
10K
10K
5%
5%
5%
5%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
FBVDD
C43
C43
.047UF
.047UF
16V
16V
10%
10%
X7R
3
X7R
0402
0402
COMMON
COMMON
GND
4,9
4
5
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FBD_D[63..0]
BI
FBD_D0
0
FBD_D1
1
FBD_D2
2
FBD_D3
FBD_DQM[7..0]
4,9
BI
FBD_DQS_RN[7..0]
4,9
BI
FBD_DQS_WP[7..0]
4,9
BI
FBD_DQM0
0
FBD_DQM1
1
FBD_DQM2
2
FBD_DQM3
3
4
FBD_DQM5
5
FBD_DQM6
6
FBD_DQM7
7
FBD_DQS_RN0
0
FBD_DQS_RN1
1
FBD_DQS_RN2
2
FBD_DQS_RN3
3
FBD_DQS_RN4
4
FBD_DQS_RN5
5
FBD_DQS_RN6
6
FBD_DQS_RN7
7
FBD_DQS_WP0
0
FBD_DQS_WP1
1
FBD_DQS_WP2
2
FBD_DQS_WP3
3
FBD_DQS_WP4
4
FBD_DQS_WP5
5
FBD_DQS_WP6
6
FBD_DQS_WP7
7
3
FBD_D4
4
FBD_D5
5
FBD_D6
6
FBD_D7
7
FBD_DQM0
FBD_DQS_RN0
FBD_DQS_WP0
FBD_D32
32
FBD_D33
33
FBD_D34
34
FBD_D35
35
FBD_D36
36
FBD_D37
37
FBD_D38
38
FBD_D39
39
FBD_DQM4
FBD_DQS_RN4
FBD_DQS_WP4
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
9
OUT
C55
C55
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
M1C
M1C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
E2
DQ0
F3
DQ1
C3
DQ2
F2
DQ3
G3
DQ4
B2
DQ5
B3
DQ6
C2
DQ7
E3
DQM
D3
RDQS
D2
WDQS
M2B
M2B
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
R3
DQ0
T3
DQ1
R2
DQ2
T2
DQ3
N2
DQ4
L3
DQ5
M3
DQ6
M2
DQ7
N3
DQM
P3
RDQS
P2
WDQS
ASSEMBLY
PAGE DETAIL
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R682
R682
121
121
1%
1%
0402
0402
DNI
DNI
FBD_CLK1_MIDPT
(OPT)
4,8,9
IN
4,9 FBD_CLK1
IN
4,9
IN
R678
R678
R676
R676
243
243
243
243
1%
1%
1%
1%
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
C929
C929
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
FBVDD
FBVDD
R26
R26
549
549
R1
1%
1%
0402
0402
COMMON
COMMON
COMMON
COMMON
R27
R27
1.33K
1.33K
R2
1%
1%
0402
0402
C42
C42
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
9
OUT
GND
M1D
M1D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
FBD_D24
24
FBD_D25
25
FBD_D26
26
FBD_D27
27
FBD_D28
28
FBD_D29
29
FBD_D30
30
FBD_D31
31
FBD_DQM3FBD_DQM4
FBD_DQS_RN3
FBD_DQS_WP3
FBD_D56
56
FBD_D57
57
FBD_D58
58
FBD_D59
59
FBD_D60
60
FBD_D61
61
FBD_D62
62
FBD_D63
63
FBD_DQM7
FBD_DQS_RN7
FBD_DQS_WP7
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FBD Partition
COMMON
M10
T10
L10
M11
T11
R11
N11
R10
N10
P10
P11
M2C
M2C
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
COMMON
B2
C3
C2
B3
E2
G3
F2
F3
E3
D3
D2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
RDQS
WDQS
M2D
M2D
BGA_0136_P080_140X110
BGA_0136_P080_140X110
BGA136
BGA136
COMMON
GND
R69
R69
243
243
1%
1%
0402
0402
COMMON
COMMON
C59
C59
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
COMMON
CS0 CAS
A8/AP A10
CKE WE
CLK
CLK
NC/RFU
NC/CS1 NC/CS1
SEN (GND)
NONMIRROR
NONMIRROR
RESET
MIRROR
ZQ
VDDA
VDDA
VSSA
VSSA
*CS1 is required 32Mx32 Memories
*CS1 is required 32Mx32 Memories
FBVDD
FBVDD
BA2RAS
CS0CAS
CKEWE
A4A0
A5A1
A6A2
A9A3
A0A4
A1A5
A2A6
A11A7
A3A9
A8/APA10
A7A11
BA1BA0
BA0BA1
RASBA2
MIRROR
MIRROR
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VREF
C950
C950
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C967
C967
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C977
C977
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C934
C934
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C908
C908
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C933
C933
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBD_CMD7
7
FBD_CMD8
8
FBD_CMD18
18
FBD_CMD10
10
FBD_CMD5
5
FBD_CMD13
13
FBD_CMD21FBD_CMD22
21
FBD_CMD20
20
FBD_CMD19
19
FBD_CMD25
25
FBD_CMD4
4
FBD_CMD9
9
FBD_CMD17
17
FBD_CMD6 FBD_CMD6
6
FBD_CMD23
23
FBD_CMD16
16
FBD_CMD3
3
12
FBD_CMD12
1
FBD_CMD1
FBD_CMD11
11
FBD_CLK1*
14
15
FBD_ZQ1
9
IN
GND
FBVDD
C68
C68
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
Decoupling
for FBD Lo
Decoupling
for FBD Hi
FBVDD
F1
M1
A2
V2
A11
V11
F12
FBVDD
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
GND
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBD_VREF1
H1
FBD_VREF3
H12
C969
C969
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C938
C938
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C962
C962
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C930
C930
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C941
C941
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C910
C910
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
R59
R59
COMMON
COMMON
R51
R51
1.33K
1.33K
COMMON
COMMON
GND
C961
C961
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C949
C949
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C965
C965
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
C935
C935
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C925
C925
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C942
C942
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0805
0805
COMMON
COMMON
FBD_CMD4
FBD_CMD5
FBD_CMD13
FBD_CMD22
FBD_CMD24
FBD_CMD0
FBD_CMD2
GDDR3: VREF = 0.70 * FBVDDQ
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
549
549
R1
1%
1%
0402
0402
1%
1%
0402
0402
OUT
C64
C64
.1UF
.1UF
R2
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
FBVDD
R79
R79
549
549
1%
1%
0402
0402
R76
R76
1.33K
1.33K
1%
1%
0402
0402
GND
C948
C948
C957
C943
C943
C972
C972
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C952
C952
1UF
1UF
Place 1uF caps at
16V
16V
center of memory
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C974
C974
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
C937
C937
C927
C927
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C920
C920
1UF
1UF
Place 1uF caps at
16V
16V
center of memory
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C936
C936
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
(OPT) (OPT) (OPT) (OPT) (OPT) (OPT)
C957
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C944
C944
C963
C963
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
C931
C931
C924
C924
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C926
C926
C932
C932
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
DNI
DNI
DNI
DNI
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
Date:
Thursday, October 18, 2007
FBVDD
1
R679
121
R679
121
COMMON
COMMON
1%
1%
0402
0402
R684
121
R684
121
COMMON
COMMON
1%
1%
0402
0402
R685
121
R685
121
COMMON
COMMON
1%
1%
0402
0402
R687
121
R687
121
COMMON
COMMON
1%
1%
0402
0402
R705
121
R705
121
COMMON
COMMON
1%
1%
0402
0402
R701
121
R701
121
COMMON
COMMON
1%
1%
0402
0402
R703
121
R703
121
COMMON
COMMON
1%
1%
0402
0402
R710
121
R710
121
COMMON
COMMON
1%
1%
0402
0402
2
R1
9
R2
GND
C953
C953
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C947
C947
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C70
C70
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
9
OUT
3
C940
C940
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
C971
C971
C956
C956
C955
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C919
C919
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C955
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C916
C916
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
4
GND
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
C928
C928
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
C914
C914
C939
C939
C923
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
Sheet of
Sheet of
Sheet of
HFDBA
C923
.1UF
.1UF
GND
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
GND
<RevCode>
<RevCode>
<RevCode>
827
827
827
5
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
DNI
DNI
www.vinafix.vn
A B C D E F G H
Page9: FrameBuffer Net Rules
1
2
3
4
NET RULES for FrameBuffer A/B NET RULES for FrameBuffer C/D
NET NV_CRITICAL
FBA_CLK0
3,5
OUT
FBA_CLK0*
3,5
OUT
FBA_CLK1
3,5
OUT
FBA_CLK1*
3,5
OUT
FBA_CMD[25..0]
3,5
OUT
FBA_DQS_WP[7..0]
3,5
OUT
FBA_DQS_RN[7..0]
3,5
IN
FBA_DQM[7..0]
3,5
OUT
3,5
3,6
3
3
3
FBA_D[63..0]
BI
NET
FBB_CLK0
3,6
OUT
FBB_CLK0*
3,6
OUT
FBB_CLK1
3,6
OUT
FBB_CLK1*
3,6
OUT
FBB_CMD[25..0]
3,6
OUT
FBB_DQS_WP[7..0]
3,6
OUT
FBB_DQS_RN[7..0]
3,6
IN
FBB_DQM[7..0]
3,6
OUT
FBB_D[63..0]
BI
FBA_DEBUG
BI
FBB_DEBUG
BI
FBAB_PLLAVDD
BI
FBA_VREF0
5
BI
FBA_VREF1
5
BI
FBA_VREF2
5
BI
FBA_VREF3
5
BI
FBA_ZQ0
5
BI
FBA_ZQ1
5
BI
FBB_VREF0
6
BI
FBB_VREF1
6
BI
FBB_VREF2
6
BI
FBB_VREF3
6
BI
FBB_ZQ0
6
BI
FBB_ZQ1
6
BI
NV_CRITICAL NV_IMPEDANCE DIFFPAIR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.2V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
MIN_WIDTHMAX_CURRENTVOLTAGENET MIN_WIDTHMAX_CURRENTVOLTAGENET
12MIL0.02A
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
0.02A 12MIL
NET NV_CRITICAL
FBC_CLK0
4,7
OUT
FBC_CLK0*
4,7
OUT
FBC_CLK1
4,7
OUT
FBC_CLK1*
4,7
OUT
FBC_CMD[25..0]
4,7
OUT
FBC_DQS_WP[7..0]
4,7
OUT
FBC_DQS_RN[7..0]
4,7
IN
FBC_DQM[7..0]
4,7
OUT
4,7
4,8
4
4
4
7
7
7
7
7
7
8
8
8
8
8
8
FBC_D[63..0]
BI
NET
FBD_CLK0
4,8
OUT
FBD_CLK0*
4,8
OUT
FBD_CLK1
4,8
OUT
FBD_CLK1*
4,8
OUT
FBD_CMD[25..0]
4,8
OUT
FBD_DQS_WP[7..0]
4,8
OUT
FBD_DQS_RN[7..0]
4,8
IN
FBD_DQM[7..0]
4,8
OUT
FBD_D[63..0]
BI
FBC_DEBUG
BI
FBD_DEBUG
BI
FBCD_PLLAVDD
BI
FBC_VREF0
BI
FBC_VREF1
BI
FBC_VREF2
BI
FBC_VREF3
BI
FBC_ZQ0
BI
FBC_ZQ1
BI
FBD_VREF0
BI
FBD_VREF1
BI
FBD_VREF2
BI
FBD_VREF3
BI
FBD_ZQ0
BI
FBD_ZQ1
BI
1
1
1
1
1
1
1
1
1
NV_CRITICAL NV_IMPEDANCE DIFFPAIR
1
1
1
1
1
1
1
1
1
1
1
1.2V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
12MIL0.02A
1
2
3
4
3
3
FB_VREF1
BI
FB_VREF2
BI
1.40V
1.40V
0.02A 12MIL
0.02A 12MIL
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C GE
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ASSEMBLY
PAGE DETAIL
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
FrameBuffer Net Rules
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
Micro-Star International Co., LTD.
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc>
Custom
<Doc>
Custom
<Doc>
Custom
Date:
Date:
Date:
Thursday, October 18, 2007
Thursday, October 18, 2007
Thursday, October 18, 2007
Sheet of
Sheet of
Sheet of
HFDBA
927
927
927
5
<RevCode>
<RevCode>
<RevCode>
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