MSI MS-V117 Schematic 20
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
P393-A01 DT SKU 4
G92-270, 16Mx32 GDDR3 900 MHz,
DVI-I-DL, DVI-I-DL, HDTVout
Table of Contents:
Page 1: Overview
Page 2: PCI Express 1.0
Page 3: MEMORY: GPU Partition A/B
Page 4: MEMORY: GPU Partition C/D
Page 5: FBA Partition
Page 6: FBB Partition
Page 7: FBC Partition
Page 8: FBD Partition
Page 9: FrameBuffer Net Rules
Page 10: DACA Interface
Page 11: DACC Interface
Page 12: IFP A/B and C/D Interface
Page 13: DACB and Stereo Interface
Page 14: Multi-use IO(MIO) Interface
Page 15: DisplayPort Transmitter
Page 16: MISC: GPIO, I2C, BIOS, PLL, and XTAL
Page 17: Thermal Control/Protection and SPDIF Input
Page 18: Power/GND and Decoupling
Page 19: Configuration Straps and Mechanical
Page 20: Power Supply: 5V, STEREO_5V, 2V5, DP_PWR
Page 21: Power Supply: 1V2, 1V8
Page 22: Power Supply: FBVDD/Q, 8V5
Page 23: Power Supply: NVVDD Regulator
Page 24: Power Supply: NVVDD Phase 1 & 2
Page 25: Power Supply: NVVDD Phase 3
Page 26: Power Supply: Filter/Detection 3V3, 12V, 12V_PEX6
Page 27: Power Supply: Hybrid Power
BASE
SKU_DT_0000
SKU_DT_0002
SKU_WS_0500
SKU_WS_0501
SKU_DT_0004
SKU_DT_0006
SKU_WS_0503
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
Overview
www.vinafix.vn
600-10393-base-100
600-10393-0000-100
600-10393-0002-100
600-50393-0500-100
600-50393-0501-100
600-10393-0004-100
600-10393-0006-100
600-50393-0503-100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
P393 - BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P393 G92-300 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-200 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-875 512MB GDDR3 16Mx32 DVI-I+DP+STEREO
P393 G92-850 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I, Apple
P393 G92-875 512Mb GDDR4 16Mx32 DVI-I+DVI-I+STEREO
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10393-0004-100 A
p393_a01
whill
1 OF 27
28-SEP-2007
J501
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININ
23/24 JTAG
JTAG_TDI
JTAG_TCLK
JTAG_TMS
JTAG_TDO
JTAG_TRST
KEY
TRST*
TCK
GND
TMS
TDO
VCC
TDI
IN
IN
1/24 PCI EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
RFU
RFU
PEX_PLLAVDD
PEX_PLLDGND
PEX_PLLAGND
PEX_PLLDVDD
PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT
PEX_TX0
PEX_REFCLK
PEX_REFCLK
PEX_RST
PEX_TX0
PEX_RX1
PEX_TX1
PEX_RX0
PEX_TX2
PEX_TX2
PEX_RX2
PEX_TX3
PEX_RX1
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX1
PEX_RX0
PEX_RX2
PEX_RX5
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX4
PEX_TX4
PEX_RX4
PEX_TX6
PEX_RX5
PEX_RX4
PEX_TX5
PEX_TX5
PEX_TX7
PEX_TX9
PEX_RX8
PEX_TX8
PEX_RX9
PEX_RX7
PEX_TX9
PEX_TX10
PEX_RX7
PEX_TX8
PEX_TX10
PEX_RX9
PEX_RX8
PEX_RX10
PEX_RX11
PEX_RX10
PEX_TX12
PEX_TX12
PEX_RX11
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX11
PEX_TX11
PEX_TX14
PEX_RX15
PEX_RX15
PEX_TX15
PEX_TX15
PEX_RX14
PEX_RX14
PEX_TX14
INININ
OUT
S
D
G
IN
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
HDR_2F4
FEMALE
3V3_F
1
3
5
7
1.274MM
0
KEY6_JTAG_SMALL
NO STUFF
2
4
8
AH21
AJ21
AH22
AJ22
AH23
AJ23
AH16
AF17
AH17
AF18
AH18
AF19
AH19
AE20
AF20
AH20
AJ20
PEX_PLL_CLK_OUT
AM9
PEX_PLL_CLK_OUT*
AN9
SNN_PEXCAL_PD_VDDQ
AK19
SNN_PEXCAL_PD_GND
AK20
PEX_PLLAVDD
AE15
AE17
Fix for G92 NC pin issue
AF15
AE16
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
PCI Express 1.0
www.vinafix.vn
2<
27<>
2> 27>
.1UF
10V
10%
.1UF
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UFC800
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
.1UF
10V
10%
16<
27<
0402
0402
C894
0402
C885
0402
C869
0402
C853
0402
C837
C811
0402
C791
0402
C763
0402
C729
0402
C704
0402
C692
0402
0402
C673
0402
C670
R692
0402
0402
R697
0402
R695
0402
R693
0402
5%
5%
5%
5%
5%
0
NO STUFF
0R700
NO STUFF
0
NO STUFF
0
NO STUFF
0
NO STUFF
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
27> 16>
G1
G92-300-A1
BGA1148
COMMON
AR9
AK10
AL10
AM11
AM10
AP9
AP10
AN10
AR10
AR11
AN12
AM12
AT11
AT12
AL12
AK12
AP12
AP13
AM14
AM13
AR13
AR14
AN13
AN14
AT14
AT15
AN15
AM15
AP15
AP16
AL15
AK15
AR16
AR17
AN16
AT17
AT18
AN17
AN18
AP18
AP19
AM18
AM17
AR19
AR20
AL18
AK18
AT20
AT21
AM19
AN19
AP21
AP22
AN20
AN21
AR22
AR23
AM21
AM20
AT23
AT24
AL21
AK21
AR24
AR25
.1UFC915
10V
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V0402
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UF
10V
.1UFC677
10V
.1UF
10V
.1UF
10V0402
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
X5R
10%
10%
X5R
10%
X5R
10%
X5R
10%
X5R
GPU_RST*
PEX_TX0
PEX_TX0*
COMMON
PEX_TX1
PEX_TX1* AN11
COMMON
PEX_TX2
PEX_TX2*
COMMON
PEX_TX3
PEX_TX3*
COMMON
PEX_TX4
PEX_TX4*
COMMON
PEX_TX5
PEX_TX5*
COMMON
PEX_TX6
PEX_TX6*
COMMON
PEX_TX7
PEX_TX7*
COMMON
PEX_TX8 AM16
PEX_TX8*
COMMON
PEX_TX9
PEX_TX9*
COMMON
PEX_TX10
PEX_TX10*
COMMON
PEX_TX11
PEX_TX11*
COMMON
PEX_TX12
PEX_TX12*
COMMON
PEX_TX13
PEX_TX13*
COMMON
PEX_TX14
PEX_TX14*
COMMON
PEX_TX15
PEX_TX15*
COMMON
Page2: PCI Express 1.0
12V
3V3
See filtering on page 26
1
PEX_REFCLK_EN
C50
C51
4.7UF
4.7UF
16V
16V
20%
20%
X7R
X7R
1206
1206
COMMON
COMMON
GND
PEX_PRSNT1*
SNN_PEX_PRSNT2_A
SNN_PEX_RSVD1
SNN_PEX_PRSNT2_B
SNN_PEX_RSVD2
SNN_PEX_RSVD3
SNN_PEX_RSVD4
SNN_PEX_PRSNT2_C
SNN_PEX_RSVD5
V_BE_GS=+/-20V
MAX_WATTAGE=0.36W@25C
MAX_CURRENT=0.88A
R_DS_ON=3.5R
CONTINUOUS_CURRENT=0.22A@31C
MAX_VOLTAGE=50V
1G1D1S
2
NO STUFF
SOT23_1G1D1S
BSS138
Q1209
3
PEX_PRSNT2*
SNN_PE_RSVD6
SNN_PE_RSVD7
27>
C54
.1UF
16V
10%
X7R
0402
COMMON
3V3_AUX
GND
GND
GND
GND
PEX_PRSNT1*
CN1
NONPHY-X16-B
CON_X16
CON_PCIEXP_X16_EDGE
NO STUFF
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
R1219
0402
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
I2CS_SCL_R
B5
I2CS_SDA_R
B6
SNN_PEX_WAKE*
B11
PEX_RST*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TX0_C
A16
PEX_TX0_C*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TX1_C
A21
PEX_TX1_C*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TX2_C
A25
PEX_TX2_C*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TX3_C
A29
PEX_TX3_C*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TX4_C
A35
PEX_TX4_C*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TX5_C
A39
PEX_TX5_C*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TX6_C
A43
PEX_TX6_C*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TX7_C
A47
PEX_TX7_C*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TX8_C
A52
PEX_TX8_C*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TX9_C
A56
PEX_TX9_C*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TX10_C
A60
PEX_TX10_C*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TX11_C
A64
PEX_TX11_C*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TX12_C
A68
PEX_TX12_C*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TX13_C
A72
PEX_TX13_C*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TX14_C
A76
PEX_TX14_C*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TX15_C
A80
PEX_TX15_C*
A81
PEX_RX15
B78
PEX_RX15*
B79
PEX_PRSNT2*
0
COMMON
5%
* PRSNT# isolation bypass option
R696
0
5%
0402
NO STUFF
C917
0402
COMMON
X5R
C907
0402 10V .1UFC906
COMMON
X5R
C904
0402
COMMON
X5R
C890
0402
COMMON
X5R
C872
0402
COMMON
X5R
C857
0402
COMMON
X5R
C843
0402
COMMON
X5R
C818
0402
COMMON
X5R
0402
COMMON
X5R
C768
0402
COMMON
X5R
C736
0402
COMMON
X5R
C707
0402
COMMON
X5R X5R
C697
0402
COMMON
X5R
C681
0402
COMMON
X5R
C674
0402
COMMON
X5R
C671
0402
COMMON
X5R
3V3_F
GND
C752
.1UF
10V
10%
X5R
0402
COMMON
C753
10V
10%
X5R
0402
COMMON
C745
.1UF
10V
10%
X5R
0402
COMMON
PEX_TEST_PLL_CLK_OUT
Termination = 200ohm
Place on bottom side
for test access
R683
10K
5%
0402
COMMON
3V3_AUX
GND
C773
.1UF
10V
10%
X5R
0402
COMMON
C767
.1UF.1UF
10V
10%
X5R
0402
COMMON
C765
.1UF
10V
10%
X5R
0402
COMMON
C63
.1UF
16V
10%
X7R
0402
COMMON
R688
R677
180
10K
5%
5%
0402
0402
COMMON
3.3V
.01A
10MIL
COMMON
R649
200
5%
0402
COMMON
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
R689
R681
270
10K
5%
5%
0402
0402
COMMON
COMMON
GND
.1UF
10V
10%
X5R
0402
R55
47K
5%
0402
NO STUFF
C771
1UF
6.3V
10%
X5R
0402
C770
1UF 4.7UF
6.3V
10%
X5R
0402
COMMON
C785
1UF
6.3V
10%
X5R
0402
COMMON
C790
1UF
6.3V
10%
X5R
0402
COMMON
C746
1UF
6.3V
10%
X5R
0402
COMMON
C772
1UF
6.3V
10%
X5R
0402
COMMON
R58
47K
5%
0402
NO STUFF
Place components within 750mils from pad
Replaced bead with 10nH inductor per SI recommendation
C792C802
1UF
6.3V
10%
X5R
0402
JTAG
AK6
AL8
AL7
AK7
AL9
C731
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMON
C727
6.3V
10%
X5R
0603
COMMON
I2CS_SCL_R
I2CS_SDA_R
G1
G92-300-A1
BGA1148
COMMON
GND
GND
L6
C93
4.7UF
6.3V
10%
X5R
0603
COMMONCOMMONCOMMON
C699
10UF
6.3V
20%
X5R
0805
COMMON
C92
10UF
6.3V
20%
X5R
0805
COMMON
1V2
1V2
2< 16<
2< 16<
10nH
COMMON0402
16<>
1V2
GND
27> 16>
27<>
C95
4.7UF
6.3V
10%
X5R
0603
COMMON
PEX NET RULES
PEX_PLLAVDD
PEX_PLLDVDD
NV_CRITICALNET
PEX_REFCLK
PEX_REFCLK*
PEX_TX0_C
PEX_TX0_C*
PEX_TX1_C
PEX_TX1_C*
PEX_TX2_C
PEX_TX2_C*
PEX_TX3_C
PEX_TX3_C*
PEX_TX4_C
PEX_TX4_C*
PEX_TX5_C
PEX_TX5_C*
PEX_TX6_C
PEX_TX6_C*
PEX_TX7_C
PEX_TX7_C*
PEX_TX8_C
PEX_TX8_C*
PEX_TX9_C
PEX_TX9_C*
PEX_TX10_C
PEX_TX10_C*
PEX_TX11_C
PEX_TX11_C*
PEX_TX12_C
PEX_TX12_C*
PEX_TX13_C
PEX_TX13_C*
PEX_TX14_C
PEX_TX14_C*
PEX_TX15_C
PEX_TX15_C*
PEX_RX0
PEX_RX0* 1
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
PEX_RX15*
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
PEX_RST*
PEX_TRST*
PEX_TCLK
PEX_TDI
PEX_TDO
PEX_TMS
JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1PEX_TX4*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
1.2V
1.2V
100DIFF
100DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
90DIFF
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
50OHM
0.25A
0.10A
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT
600-10393-0004-100 A
p393_a01
whill
DIFFPAIRNV_IMPEDANCE
PEX_REFCLK
PEX_REFCLK
PEX_TX0_C
PEX_TX0_C
PEX_TX1_C
PEX_TX1_C
PEX_TX2_C
PEX_TX2_C
PEX_TX3_C
PEX_TX3_C
PEX_TX4_C
PEX_TX4_C
PEX_TX5_C
PEX_TX5_C
PEX_TX6_C
PEX_TX6_C
PEX_TX7_C
PEX_TX7_C
PEX_TX8_C
PEX_TX8_C
PEX_TX9_C
PEX_TX9_C
PEX_TX10_C
PEX_TX10_C
PEX_TX11_C
PEX_TX11_C
PEX_TX12_C
PEX_TX12_C
PEX_TX13_C
PEX_TX13_C
PEX_TX14_C
PEX_TX14_C
PEX_TX15_C
PEX_TX15_C
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
MIN_WIDTHMAX_CURRENTVOLTAGENET
12MIL
12MIL
2 OF 27
28-SEP-2007
27< 2>
Page3: MEMORY: GPU Partition A/B
OUT
OUT
OUT
OUT
OUT
BI
3/24 MEM_B
FBB_CMD6
FBB_CMD4
FBB_CMD5
FBB_CMD3
FBB_CMD1
FBB_CMD2
FBB_CMD0
FBB_CMD7
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD19
FBB_CMD18
FBB_CMD17
FBB_CMD16
FBB_CMD14
FBB_CMD15
FBB_CMD13
FBB_CMD12
FBB_CMD11
FBB_CMD9
FBB_CMD10
FBB_CMD8
FBB_CLK1
FBB_CLK0
FBB_CLK0
FBB_CMD28
FBB_CLK1
RFU
RFU
FBB_DEBUG
FBCAL1_PD_VDDQ
FBCAL1_PU_GND
FBB_PLLVDD_NC
FBCAL1_TERM_GND
FBB_PLLGND
FBBD6
FBBD4
FBBD5
FBBD3
FBBD2
FBBD1
FBBD0
FBBD7
FBBD27
FBBD26
FBBD25
FBBD24
FBBD23
FBBD22
FBBD21
FBBD19
FBBD20
FBBD17
FBBD16
FBBD15
FBBD13
FBBD12
FBBD11
FBBD9
FBBD10
FBBD8
FBBD14
FBBD18
FBBD47
FBBD46
FBBD45
FBBD44
FBBD42
FBBD43
FBBD41
FBBD40
FBBD39
FBBD37
FBBD38
FBBD36
FBBD35
FBBD34
FBBD32
FBBD33
FBBD31
FBBD30
FBBD29
FBBD28
FBBD48
FBBDQM2
FBBDQM1
FBBDQM0
FBBD62
FBBD63
FBBD60
FBBD61
FBBD59
FBBD57
FBBD58
FBBD55
FBBD56
FBBD54
FBBD53
FBBD52
FBBD50
FBBD51
FBBD49
FBBDQS_RN6
FBBDQS_WP2
FBBDQS_WP1
FBBDQS_WP0
FBBDQS_RN7
FBBDQS_RN4
FBBDQS_RN5
FBBDQS_RN3
FBBDQS_RN2
FBBDQS_RN1
FBBDQS_RN0
FBBDQM7
FBBDQM6
FBBDQM4
FBBDQM5
FBBDQM3
FBBDQS_WP3
FB_VREF2
FBBDQS_WP7
FBBDQS_WP6
FBBDQS_WP5
FBBDQS_WP4
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBIBIBI
2/24 MEM_A
FBA_CMD6
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD7
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD19
FBA_CMD18
FBA_CMD17
FBA_CMD16
FBA_CMD14
FBA_CMD15
FBA_CMD13
FBA_CMD12
FBA_CMD11
FBA_CMD9
FBA_CMD10
FBA_CMD8
FBA_CMD22
FBA_CMD21
FBA_CMD20
FBA_CMD28
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
RFU
RFU
FBA_DEBUG
FBCAL0_PU_GND
FBCAL0_TERM_GND
FBCAL0_PD_VDDQ
FBA_PLLAVDD
FBA_DLLAVDD
FBA_PLLGND
FBAD6
FBAD4
FBAD5
FBAD3
FBAD2
FBAD1
FBAD0
FBAD7
FBAD20
FBAD21
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD19
FBAD17
FBAD15
FBAD12
FBAD13
FBAD11
FBAD9
FBAD10
FBAD8
FBAD27
FBAD14
FBAD16
FBAD18
FBAD45
FBAD44
FBAD42
FBAD41
FBAD37
FBAD38
FBAD36
FBAD35
FBAD32
FBAD33
FBAD31
FBAD30
FBAD29
FBAD28
FBAD46
FBAD40
FBAD39
FBAD43
FBAD34
FBAD47
FBAD48
FBAD60
FBADQM2
FBADQM1
FBAD61
FBAD58
FBAD57
FBAD55
FBAD56
FBAD54
FBAD53
FBAD52
FBAD51
FBAD50
FBAD49
FBAD59
FBADQM0
FBAD63
FBAD62
FBADQS_WP2
FBADQS_RN7
FBADQS_RN5
FBADQS_RN3
FBADQS_RN2
FBADQM4
FBADQM3
FBADQS_RN6
FBADQS_RN4
FBADQM7
FBADQM6
FBADQM5
FBADQS_RN1
FBADQS_RN0
FBADQS_WP0
FBADQS_WP1
FBADQS_WP3
FBADQS_WP5
FBADQS_WP4
FBADQS_WP7
FBADQS_WP6
FB_VREF1
OUTINOUT
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G92-300-A1
BGA1148
AH35
AH36
AH34
AJ34
AK36
AJ36
AK34
AL34
AH32
AK33
AJ33
AH33
AL33
AN32
AN33
AN31
AE32
AF30
AF32
AE30
AE31
AC30
AC32
AD30
AG36
AG34
AF36
AD36
AD34
AD35
AE34
AP36
AN35
AM34
AP35
AP34
AP33
AT34
AR34
AM22
AM25
AN26
AN24
AK24
AL22
AK23
AM23
AT32
AT33
AR33
AP31
AR30
AT30
AP30
AT29
AP26
AP27
AT25
AP25
AR28
AP28
AT28
AP29
AK35
AF33
AF34
AN34
AM24
AP32
AR27
AL35
AK32
AG33
AE36
AM36
AN22
AR31
AT27
AL36
AL32
AG32
AE35
AN36
AN23
AT31
AT26
J29
COMMON
CALIBRATION PIN
FB_CALx_PD_VDDQ
FB_CALx_PU_GND
FB_CALx_TERM_GND
VREF RATIO
DDR3
60
40
40
0.7 FBVDDQ
FBA_CMD<0>
AK28
FBA_CMD<1>
AK29
FBA_CMD<2>
AN30
FBA_CMD<3>
AM27
FBA_CMD<4>
AN28
FBA_CMD<5>
AL29
AM30
FBA_CMD<6>
FBA_CMD<7>
AJ31
FBA_CMD<8>
AK31
FBA_CMD<9>
AH31
FBA_CMD<10>
AK25
FBA_CMD<11>
AM26
FBA_CMD<12>
AL31
FBA_CMD<13>
AN29
FBA_CMD<14>
AK27
FBA_CMD<15>
AK26
FBA_CMD<16>
AN27
FBA_CMD<17>
AL25
FBA_CMD<18>
AJ30
FBA_CMD<19>
AM31
FBA_CMD<20>
AH30
FBA_CMD<21>
AL30
FBA_CMD<22>
AH29
FBA_CMD<23>
AL28
FBA_CMD<24>
AH28
FBA_CMD<25>
AM28
SNN_FBA_CMD_26AG30
SNN_FBA_CMD_27
AG28
SNN_FBA_CMD_28
AF28
FBA_CLK0
AH26
FBA_CLK0*
AH27
FBA_CLK1
AJ29
FBA_CLK1*
AJ28
SNN_FBA_RFU0
AJ24
SNN_FBA_RFU1AH24
FBA_DEBUG
AH25
FB_CAL_PD_VDDQ0
J28
FB_CAL_PU_GND0
H28
FB_CAL_TERM_GND0
H29
FBAB_PLLAVDD
AC29
AD29
AE29
GND
Place components as close
as possible to the pad
C702
.1UF
10V
10%
X5R
0402
COMMON
GND
C676
.1UF
10V
10%
X5R
0402
COMMON
GND
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_RN<7..0>
FBA_DQS_WP<7..0>
FBVDD
R616
549
1%
0402
COMMON
R615
1.33K
1%
0402
COMMON
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBA_D<0>
FBA_D<1>
FBA_D<2>
FBA_D<3>
FBA_D<4>
FBA_D<5>
FBA_D<6>
FBA_D<7>
FBA_D<8>
FBA_D<9>
FBA_D<10>
FBA_D<11>
FBA_D<12>
FBA_D<13>
FBA_D<14>
FBA_D<15>
FBA_D<16>
FBA_D<17>
FBA_D<18>
FBA_D<19>
FBA_D<20>
FBA_D<21>
FBA_D<22>
FBA_D<23>
FBA_D<24>
FBA_D<25>
FBA_D<26> AG35
FBA_D<27>
FBA_D<28>
FBA_D<29>
FBA_D<30>
FBA_D<31>
FBA_D<32>
FBA_D<33>
FBA_D<34>
FBA_D<35>
FBA_D<36>
FBA_D<37>
FBA_D<38>
FBA_D<39>
FBA_D<40>
FBA_D<41>
FBA_D<42>
FBA_D<43>
FBA_D<44>
FBA_D<45>
FBA_D<46>
FBA_D<47>
FBA_D<48>
FBA_D<49>
FBA_D<50>
FBA_D<51>
FBA_D<52>
FBA_D<53>
FBA_D<54>
FBA_D<55>
FBA_D<56>
FBA_D<57>
FBA_D<58>
FBA_D<59>
FBA_D<60>
FBA_D<61>
FBA_D<62>
FBA_D<63>
FBA_DQM<0>
FBA_DQM<1> AM33
FBA_DQM<2>
FBA_DQM<3>
FBA_DQM<4>
FBA_DQM<5>
FBA_DQM<6>
FBA_DQM<7>
FBA_DQS_RN<0>
FBA_DQS_RN<1>
FBA_DQS_RN<2>
FBA_DQS_RN<3>
FBA_DQS_RN<4>
FBA_DQS_RN<5>
FBA_DQS_RN<6>
FBA_DQS_RN<7>
FBA_DQS_WP<0>
FBA_DQS_WP<1>
FBA_DQS_WP<2>
FBA_DQS_WP<3>
FBA_DQS_WP<4>
FBA_DQS_WP<5>
FBA_DQS_WP<6>
FBA_DQS_WP<7>
FB_VREF1
9<> 5<>
9> 5<>
9< 5<>
9> 5<>
9<>
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C708
.1UF
10V
10%
X5R
0402
COMMON
0
1
2
3
4
5
6
7
8
9
FBA_CMD<28..0>
FBVDD
R626
60.4
1%
0402
NO STUFF
5<
5<
5<
5<
9>
9>
9>
9>
9> 5<
136BGA CMD Mapping
ADDR
CMD
A<4>
CMD0
RAS*CMD1
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
A<4>
CMD5
A<3>
CMD6
BA2
CMD7
CS0*
CMD8
A<11>
CMD9
CAS*
CMD10
CMD11 WE*
BA0
CMD12
A<5>
CMD13
A<12>
CMD14
RST
CMD15
A<7>
CMD16
A<10>
CMD17
CKE
CMD18
A<0>
CMD19
A<9>
CMD20
A<6>
CMD21
A<2>
CMD22
A<8>
CMD23
A<3>
CMD24
A<1>
CMD25
A<13>
CMD26
BA2
CMD27
N/A
CMD28
6<> 9<>
9> 6<>
9<>
FBVDD
60.4
9<>
R624
0402
R620
0402
R619
0402
COMMON
1%
40.2
COMMON
1%
40.2
COMMON
1%
GND
1V2
9<
9>
6<>
6<>
9<>
240R@100MHz
LB501
COMMONBEAD_0402
C688
C687
4.7UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0402
COMMON
COMMON
Place these components within
750 mils of the pad
C675
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
MEMORY: GPU Partition A/B
www.vinafix.vn
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_RN<7..0>
FBB_DQS_WP<7..0>
C710
.1UF
10V
10%
X5R
0402
COMMON
GND
FBVDD
GND
R629
549
1%
0402
COMMON
R628
1.33K
1%
0402
COMMON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBB_D<0>
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_D<5>
5
FBB_D<6>
6
FBB_D<7>
7
FBB_D<8>
8
FBB_D<9>
9
FBB_D<10>
10
FBB_D<11>
11
FBB_D<12>
12
FBB_D<13>
13
FBB_D<14>
14
FBB_D<15>
15
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_D<32>
32
FBB_D<33>
33
FBB_D<34>
34
FBB_D<35>
35
FBB_D<36>
36
FBB_D<37>
37
FBB_D<38>
38
FBB_D<39>
39
FBB_D<40>
40
FBB_D<41>
41
FBB_D<42>
42
FBB_D<43>
43
FBB_D<44>
44
FBB_D<45>
45
FBB_D<46>
46
FBB_D<47>
47
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50>
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DQM<0>
FBB_DQM<1>
FBB_DQM<2>
FBB_DQM<3>
FBB_DQM<4>
FBB_DQM<5>
FBB_DQM<6>
FBB_DQM<7>
FBB_DQS_RN<0>
FBB_DQS_RN<1>
FBB_DQS_RN<2>
FBB_DQS_RN<3>
FBB_DQS_RN<4>
FBB_DQS_RN<5>
FBB_DQS_RN<6>
FBB_DQS_RN<7>
FBB_DQS_WP<0>
FBB_DQS_WP<1>
FBB_DQS_WP<2>
FBB_DQS_WP<3>
FBB_DQS_WP<4>
FBB_DQS_WP<5>
FBB_DQS_WP<6>
FBB_DQS_WP<7>
FB_VREF2
G1
G92-300-A1
BGA1148
COMMON
G36
G35
H36
H34
J35
J34
K34 T30
K35
J31
K32
J30
H30
L32
K30
M31
L30
G31
J32
J33
F33
H31
E33
F31
F32
F35
G34
F36
F34
C35
D34
C36
D35
N35
M34
L34
N36
P36
P34
R36
R34
AC33
Y33
Y30
AB30
AA32
AD32
AD33
AA33
T36
R35
T34
U36
W35
U34
V34
W36
AC36
AA36
AC34
AB34
AA35
Y34
Y36
W34
J36
M32
H33
E34
N34
Y32
T35
AA34
L36
K33
G32
E36
M36
AB32
V35
AB35
K36
L33
G33
D36
M35
AB31
V36
AB36
J27
FBB_CMD<0>
P33
FBB_CMD<1>
N33
FBB_CMD<2>
R31
FBB_CMD<3>
U33
FBB_CMD<4>
V30
FBB_CMD<5>
T33
FBB_CMD<6>
FBB_CMD<7>
N32
FBB_CMD<8>
R32
FBB_CMD<9>
P32
FBB_CMD<10>
U32
FBB_CMD<11>
U30
FBB_CMD<12>
P30
FBB_CMD<13>
V31
FBB_CMD<14>
T28
FBB_CMD<15>
W30
FBB_CMD<16>
V32
FBB_CMD<17>
T32
FBB_CMD<18>
N30
FBB_CMD<19>
P28
FBB_CMD<20>
P29
FBB_CMD<21>
U29
FBB_CMD<22>
N28
FBB_CMD<23>
R30
FBB_CMD<24>
M30
FBB_CMD<25>
T29
SNN_FBB_CMD_26
N29
SNN_FBB_CMD_27
AA30
SNN_FBB_CMD_28
Y29
FBB_CLK0
M28
FBB_CLK0*
L28
FBB_CLK1
W31
FBB_CLK1*
W32
SNN_FBB_RFU0
R28
SNN_FBB_RFU1
K29
FBB_DEBUG
C34
FB_CAL_PD_VDDQ1
H27
FB_CAL_PU_GND1
H26
FB_CAL_TERM_GND1
J26
SNN_FBB_PLLVDD_NC
AB28
AC28
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBB_CMD<28..0>
6<
6<
6<
6<
FBVDD
R617
60.4
1%
0402
NO STUFF
9>
9>
9>
9>
6< 9>
9<>
60.4
R630
COMMON
0402
1%
40.2
R633
COMMON
0402
1%
40.2
R634
COMMON
0402
1%
600-10393-0004-100 A
p393_a01
whill
FBVDD
GND
3 OF 27
28-SEP-2007
Page4: MEMORY: GPU Partition C/D
OUT
OUT
OUT
OUT
OUT
BI
5/24 MEM_D
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD5
FBD_CMD4
FBD_CMD6
FBD_CMD7
FBD_CMD21
FBD_CMD20
FBD_CMD19
FBD_CMD8
FBD_CMD10
FBD_CMD9
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD23
FBD_CMD22
FBD_CMD27
FBD_CMD26
FBD_CMD25
FBD_CMD24
FBD_CLK1
FBD_CLK1
FBD_CLK0
FBD_CLK0
FBD_CMD28
RFU
RFU
FBD_DEBUG
FBD_PLLVDD_NC
FBD_PLLGND
FBDD0
FBDD1
FBDD2
FBDD3
FBDD4
FBDD5
FBDD6
FBDD7
FBDD9
FBDD21
FBDD25
FBDD8
FBDD10
FBDD11
FBDD12
FBDD13
FBDD15
FBDD14
FBDD16
FBDD17
FBDD18
FBDD20
FBDD19
FBDD22
FBDD23
FBDD24
FBDD26
FBDD27
FBDD28
FBDD29
FBDD30
FBDD31
FBDD33
FBDD32
FBDD36
FBDD35
FBDD38
FBDD37
FBDD40
FBDD41
FBDD39
FBDD42
FBDD43
FBDD44
FBDD45
FBDD46
FBDD47
FBDD34
FBDD48
FBDD57
FBDD58
FBDD59
FBDD60
FBDD49
FBDD50
FBDD51
FBDD52
FBDD53
FBDD54
FBDD56
FBDD55
FBDD61
FBDD62
FBDD63
FBDDQM0
FBDDQM2
FBDDQM1
FBDDQM3
FBDDQM5
FBDDQM4
FBDDQM6
FBDDQM7
FBDDQS_RN0
FBDDQS_RN1
FBDDQS_RN2
FBDDQS_RN3
FBDDQS_RN6
FBDDQS_RN4
FBDDQS_RN7
FBDDQS_WP0
FBDDQS_WP1
FBDDQS_WP2
FBDDQS_RN5
FBDDQS_WP3
FBDDQS_WP4
FBDDQS_WP5
FBDDQS_WP6
FBDDQS_WP7
BI
OUT
OUT
OUT
OUT
OUT
OUTINOUTBIBI
BI
4/24 MEM_C
FBC_CMD6
FBC_CMD5
FBC_CMD4
FBC_CMD3
FBC_CMD2
FBC_CMD1
FBC_CMD0
FBC_CMD7
FBC_CMD24
FBC_CMD25
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD20
FBC_CMD19
FBC_CMD18
FBC_CMD17
FBC_CMD16
FBC_CMD15
FBC_CMD14
FBC_CMD13
FBC_CMD12
FBC_CMD11
FBC_CMD10
FBC_CMD9
FBC_CMD8
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CLK1
FBC_CLK1
FBC_CLK0
FBC_CLK0
RFU
RFU
FBC_DEBUG
FBC_DLLAVDD
FBC_PLLAVDD
FBC_PLLVDD_NC
FBC_PLLGND
FBCD5
FBCD3
FBCD1
FBCD6
FBCD4
FBCD2
FBCD0
FBCD7
FBCD16
FBCD19
FBCD27
FBCD26
FBCD25
FBCD22
FBCD23
FBCD20
FBCD13
FBCD9
FBCD8
FBCD14
FBCD15
FBCD17
FBCD12
FBCD24
FBCD21
FBCD18
FBCD11
FBCD10
FBCD29
FBCD28
FBCD33
FBCD35
FBCD47
FBCD45
FBCD46
FBCD44
FBCD43
FBCD42
FBCD39
FBCD41
FBCD40
FBCD37
FBCD32
FBCD30
FBCD36
FBCD34
FBCD31
FBCD38
FBCD48
FBCD60
FBCD63
FBCDQM0
FBCDQM2
FBCDQM1
FBCD62
FBCD61
FBCD57
FBCD58
FBCD59
FBCD55
FBCD56
FBCD53
FBCD54
FBCD51
FBCD50
FBCD49
FBCD52
FBCDQM5
FBCDQM4
FBCDQM6
FBCDQM7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_RN3
FBCDQM3
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
OUTINOUT
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
G1
G92-300-A1
BGA1148
C18
C17
A17
B16
C14
A16FBC_D<5>
C15
A14
A18
A19
B19
B18
B21
C19
B22
C21
E15
D16
D17
G16
E16
E14
G13
D13
A22
C22
A23
A24
C24
C25
B24
C28
B27
C27
B28
C29
A29
B30
A30
E31
E28
D28
F29
F30
D33
D32
D31
G27
F25
G26
D26
G29
G28
E27
F28
A34
C32
B34
C33
C31
B31
A31
C30
C16
G14
C26
A28
D29
D27
B33
B15
A21
D14
B25
A27
E30
E25
A33
A15
A20
E13
A25
A26
D30
E26
A32
COMMON
H20
E18
E20
D23
G24
D24
G23
D20
E22
J21
E21
G20
F22
H21
E17
E19
D21
E23
F19
E24
G21
G19
G25
G18
G22
F15
G15
H17
J16
J24
H23
H24
H16
H13
J11
J12
J13
GND
FBC_CMD<0>F18
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD_26G17
SNN_FBC_CMD_27
SNN_FBC_CMD_28
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
SNN_FBC_RFU0
SNN_FBC_RFU1J25
FBC_DEBUG
SNN_FBC_PLLVDD_NC
FBCD_PLLAVDD
C832
.1UF
10V
10%
X5R
0402
COMMON
as possible to the pad
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_RN<7..0>
FBC_DQS_WP<7..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBC_D<0>
FBC_D<1>
FBC_D<2>
FBC_D<3>
FBC_D<4>
FBC_D<6>
FBC_D<7>
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_D<16>
FBC_D<17>
FBC_D<18>
FBC_D<19>
FBC_D<20>
FBC_D<21>
FBC_D<22>
FBC_D<23>
FBC_D<24>
FBC_D<25>
FBC_D<26> C23
FBC_D<27>
FBC_D<28>
FBC_D<29>
FBC_D<30>
FBC_D<31>
FBC_D<32>
FBC_D<33>
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_D<48>
FBC_D<49>
FBC_D<50>
FBC_D<51>
FBC_D<52>
FBC_D<53>
FBC_D<54>
FBC_D<55>
FBC_D<56>
FBC_D<57>
FBC_D<58>
FBC_D<59>
FBC_D<60>
FBC_D<61>
FBC_D<62>
FBC_D<63>
FBC_DQM<0>
FBC_DQM<1> C20
FBC_DQM<2>
FBC_DQM<3>
FBC_DQM<4>
FBC_DQM<5>
FBC_DQM<6>
FBC_DQM<7>
FBC_DQS_RN<0>
FBC_DQS_RN<1>
FBC_DQS_RN<2>
FBC_DQS_RN<3>
FBC_DQS_RN<4>
FBC_DQS_RN<5>
FBC_DQS_RN<6>
FBC_DQS_RN<7>
FBC_DQS_WP<0>
FBC_DQS_WP<1>
FBC_DQS_WP<2>
FBC_DQS_WP<3>
FBC_DQS_WP<4>
FBC_DQS_WP<5>
FBC_DQS_WP<6>
FBC_DQS_WP<7>
9<> 7<>
9> 7<>
9< 7<>
9> 7<>
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBVDD
C822
.1UF
10V
10%
X5R
0402
COMMON
FBC_CMD<28..0>
7<
7<
7<
7<
R638
60.4
1%
0402
NO STUFF
9>
9>
9>
9>
9> 7<
136BGA CMD Mapping
ADDR
CMD
A<4>CMD0
RAS*CMD1
A<5>
CMD2
BA1
CMD3
A<2>
CMD4
A<4>
CMD5
A<3>
CMD6
BA2CMD7
CS0*
CMD8
A<11>
CMD9
CAS*
CMD10
CMD11 WE*
BA0
CMD12
A<5>
CMD13
A<12>
CMD14
RST
CMD15
A<7>
CMD16
A<10>
CMD17
CKE
CMD18
A<0>
CMD19
A<9>
CMD20
A<6>
CMD21
A<2>
CMD22
A<8>
CMD23
A<3>
CMD24
A<1>
CMD25
A<13>
CMD26
BA2
CMD27
N/A
CMD28
8<> 9<>
9> 8<>
9<>
8<>
9<
8<>
9<>
C841
1UF
6.3V
10%
X5R
0402
COMMON
Place these components withinPlace components as close
750 mils of the pad
240R@100MHz
LB503
BEAD_0402
C855
4.7UF
6.3V
10%
X5R
0603
COMMON
COMMON
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
MEMORY: GPU Partition C/D
9>
1V2
C852
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
www.vinafix.vn
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_RN<7..0>
FBD_DQS_WP<7..0>
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBD_D<0>
0
FBD_D<1>
1
FBD_D<2>
2
FBD_D<3>
3
FBD_D<4>
4
FBD_D<5>
5
FBD_D<6>
6
FBD_D<7>
7
FBD_D<8>
8
FBD_D<9>
9
FBD_D<10>
10
FBD_D<11>
11
FBD_D<12>
12
FBD_D<13>
13
FBD_D<14>
14
FBD_D<15>
15
FBD_D<16>
16
FBD_D<17>
17
FBD_D<18>
18
FBD_D<19>
19
FBD_D<20>
20
FBD_D<21>
21
FBD_D<22>
22
FBD_D<23>
23
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_D<32>
32
FBD_D<33>
33
FBD_D<34>
34
FBD_D<35>
35
FBD_D<36>
36
FBD_D<37>
37
FBD_D<38>
38
FBD_D<39>
39
FBD_D<40>
40
FBD_D<41>
41
FBD_D<42>
42
FBD_D<43>
43
FBD_D<44>
44
FBD_D<45>
45
FBD_D<46>
46
FBD_D<47>
47
FBD_D<48>
48
FBD_D<49>
49
FBD_D<50>
50
FBD_D<51>
51
FBD_D<52>
52
FBD_D<53>
53
FBD_D<54>
54
FBD_D<55>
55
FBD_D<56>
56
FBD_D<57>
57
FBD_D<58>
58
FBD_D<59>
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<0>
FBD_DQM<1>
FBD_DQM<2>
FBD_DQM<3>
FBD_DQM<4>
FBD_DQM<5>
FBD_DQM<6>
FBD_DQM<7>
FBD_DQS_RN<0>
FBD_DQS_RN<1>
FBD_DQS_RN<2>
FBD_DQS_RN<3>
FBD_DQS_RN<4>
FBD_DQS_RN<5>
FBD_DQS_RN<6>
FBD_DQS_RN<7>
FBD_DQS_WP<0>
FBD_DQS_WP<1>
FBD_DQS_WP<2>
FBD_DQS_WP<3>
FBD_DQS_WP<4>
FBD_DQS_WP<5>
FBD_DQS_WP<6>
FBD_DQS_WP<7>
G1
G92-300-A1
BGA1148
COMMON
H3
J3
J1
J2
M3
K3
L3 F8
M1
H1
G3
G1
G2
F3
E1
D1
D2
P4
N7
M7
N5
P5
R7
T7
P7
C1
C5
C2
B4
A3
B3
C4
C3
A8
C6
C7
A7
C8
C9
A9
B9
E12
E9
F9
G10
D10
G12
F12
D11
F4
E4
D4
D5
D8
E7
D7
D9
B13
C11
A13
C13
A11
A10
B10
C10
K2
E3
N4
D3
B7
G11
F5
C12
K1
F2
R6
A4
B6
E10
E6
A12
L1
F1
R5
A5
A6
E11
D6
B12
FBD_CMD<0>
M6
FBD_CMD<1>
G5
FBD_CMD<2>
L7
FBD_CMD<3>
K5
FBD_CMD<4>
J10
FBD_CMD<5>
G8
FBD_CMD<6>
FBD_CMD<7>
G6
FBD_CMD<8>
H6
FBD_CMD<9>
F6
FBD_CMD<10>
K8
FBD_CMD<11>
L5
FBD_CMD<12>
H4
FBD_CMD<13>
G4
FBD_CMD<14>
K9
FBD_CMD<15>
L4
FBD_CMD<16>
K4
FBD_CMD<17>
K7
FBD_CMD<18>
G7
FBD_CMD<19>
J4
FBD_CMD<20>
F7
FBD_CMD<21>
J5
FBD_CMD<22>
J6
FBD_CMD<23>
H7
FBD_CMD<24>
L8
FBD_CMD<25>
J7
SNN_FBD_CMD_26
M5
SNN_FBD_CMD_27
H9
SNN_FBD_CMD_28
G9
FBD_CLK0
L9
FBD_CLK0*
M9
FBD_CLK1
J9
FBD_CLK1*
J8
SNN_FBD_RFU0
H10
SNN_FBD_RFU1
L11
FBD_DEBUG
N8
SNN_FBD_PLLVDD_NC
H11
H12
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FBVDD
FBD_CMD<28..0>
9>
8<
9>
8<
9>
8<
9>
8<
R645
60.4
1%
0402
NO STUFF
8< 9>
9<>
600-10393-0004-100 A
p393_a01
whill
4 OF 27
28-SEP-2007
Page5: FBA Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16A<7>
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
3>
9>
3>
9>
FBVDD
R592
121
1%
0402
NO STUFF
FBA_CLK0_MIDPT
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
3> 5< 9>
R588 R589
243
1%
0402
COMMON
GND
FBA_CMD<28..0>
243
1%
0402
COMMON
C615
.01UF
25V
10%
X7R
0402
COMMON
9<>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
14
15
FBVDD
R604
10K
5%
0402
COMMON
GND
C146
.047UF
16V
10%
X7R
0402
COMMON
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<7>
FBA_CMD<18>
FBA_CLK0
FBA_CLK0*
SNN_FBA_NC0
FBA_CMD<14>
GND
FBA_CMD<15>
GND
FBA_ZQ0
R585
10K
5%
0402
COMMON
GND
C132
.047UF
16V
10%
X7R
0402
COMMON
R115
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
1%
1%
1%
1%
1%
1%
1%
1%
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R112
549
0402
COMMON
R110
1.33K
04020402
COMMON
FBVDD
1%
1%
GND
FBVDD
R1
R2
C133
.1UF
10V
X5R
0402
COMMON
9<>
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBA_VREF0
FBA_VREF2
FBVDD
GND
GND
FBVDD
R111
549
1%
0402
COMMON
R109
1.33K
1%
0402 0402
COMMON
GND
136BGA CMD Mapping
ADDR 136MAP
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
R120
549
R1
9<>
C131
.1UF
R2
10V
X5R
0402
COMMON
0402
COMMON
R123
1.33K
COMMON
R1
1%
R2
1%
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
R593
121
1%
0402
NO STUFF
C149
.1UF
10V
10%10%
X5R
0402
COMMON
3>
9>
3>
9>
FBA_CLK1_MIDPT
9<>
R602
243
0402
COMMON
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R116
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
R601
243
0402
COMMON
C616
.01UF
25V
10%
X7R
0402
COMMON
1%
FBA_CMD<28..0>
FBVDD
9<>
FBA_CMD<7>
7
FBA_CMD<8>
8
FBA_CMD<18>
18
FBA_CMD<10>
10
FBA_CMD<5>
5
FBA_CMD<13>
13
FBA_CMD<21>
21
FBA_CMD<20>
20
FBA_CMD<19>
19
FBA_CMD<25>
25
FBA_CMD<4>
4
FBA_CMD<9>
9
FBA_CMD<17>
17
FBA_CMD<6>
6
FBA_CMD<23>
23
FBA_CMD<16>
16
FBA_CMD<3>
3
FBA_CMD<12>
12
FBA_CMD<1>
1
FBA_CMD<11>
11
FBA_CLK1
FBA_CLK1*
SNN_FBA_NC1
FBA_CMD<14>
14
GND
FBA_CMD<15>
15
FBA_ZQ1
3> 5< 9>
1%
GND
GND
FBVDD
C134
.047UF
16V
10%
X7R
0402
COMMON
C147
.047UF
16V
10%
X7R
0402
COMMON
GND
FBA_VREF1
FBA_VREF3
FBVDD
FBVDD
GND
GND
R119
549
0402
COMMON
R122
1.33K
COMMON
FBA_CMD<4>
FBA_CMD<6>
FBA_CMD<5>
FBA_CMD<13>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C148
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
9<>
R597
0402
R598
0402
R591
0402
R587
0402
R599
0402
R595
0402
R590
0402
R579
0402
9>
9<
9>
3<>
3>
3<
3>
FBA_D<63..0>
FBA_DQM<7..0>
FBA_DQS_RN<7..0>
FBA_DQS_WP<7..0>
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E11
B11
F11
G10
C10
C11
B10
F10
E10
D10
D11
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M11
N11
M10
T10
R11
T11
R10
N10
P10
P11FBA_DQS_WP<7>
F2
G3
F3
C2
E2
C3
B3
B2
E3
D3
D2
B3
C3
F3
C2
F2
E2
B2
G3
E3
D3
D2
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBA_D<24>
24
FBA_D<25>
25
FBA_D<26>
26
FBA_D<27>
27
FBA_D<28>
28
FBA_D<29>
29
FBA_D<30>
30
FBA_D<31>
31
FBA_DQM<3>
FBA_DQS_RN<3>
FBA_DQS_WP<3>
FBA_D<56>
56
FBA_D<57>
57
FBA_D<58>
58
FBA_D<59> L10
59
FBA_D<60>
60
FBA_D<61>
61
FBA_D<62>
62
FBA_D<63>
63
FBA_DQM<7>
FBA_DQS_RN<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBA Partition
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBA_D<0>
0
FBA_D<1>
1
FBA_D<2>
2
FBA_D<3>
3
FBA_D<4>
4
FBA_DQM<0>
0
FBA_DQM<1>
1
FBA_DQM<2>
2
FBA_DQM<3>
3
FBA_DQM<4>
4
FBA_DQM<5>
5
FBA_DQM<6>
6
FBA_DQM<7>
7
FBA_DQS_RN<0>
0
FBA_DQS_RN<1>
1
FBA_DQS_RN<2>
2
FBA_DQS_RN<3>
3
FBA_DQS_RN<4>
4
FBA_DQS_RN<5>
5
FBA_DQS_RN<6>
6
FBA_DQS_RN<7>
7
FBA_DQS_WP<0>
0
FBA_DQS_WP<1>
1
FBA_DQS_WP<2>
2
FBA_DQS_WP<3>
3
FBA_DQS_WP<4>
4
FBA_DQS_WP<5>
5
FBA_DQS_WP<6>
6
FBA_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBA_D<5>
FBA_D<6>
FBA_D<7>
FBA_DQM<0>
FBA_DQS_RN<0>
FBA_DQS_WP<0>
FBA_D<32>
FBA_D<33>
FBA_D<34>
FBA_D<35>
FBA_D<36>
FBA_D<37>
FBA_D<38>
FBA_D<39>
FBA_DQM<4>
FBA_DQS_RN<4>
FBA_DQS_WP<4>
L10
T10
M10
R11
T11
R10
N11
M11
N10
P10
P11
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L3
R3
T3
M3
M2
N2
T2
R2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBA_D<8>
FBA_D<9>
FBA_D<10>
FBA_D<11>
FBA_D<12>
FBA_D<13>
FBA_D<14>
FBA_D<15>
FBA_DQM<1>
FBA_DQS_RN<1>
FBA_DQS_WP<1>
FBA_D<40>
FBA_D<41>
FBA_D<42>
FBA_D<43>
FBA_D<44>
FBA_D<45>
FBA_D<46>
FBA_D<47>
FBA_DQM<5>
FBA_DQS_RN<5>
FBA_DQS_WP<5>
M6
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
R3
T2
R2
N2
T3
M3
M2
L3
N3
P3
P2
M7
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B10
E11
F11
C10
C11
G10
F10
B11
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBA_D<16>
FBA_D<17>
FBA_D<18>
FBA_D<19>
FBA_D<20>
FBA_D<21>
FBA_D<22>
FBA_D<23>
FBA_DQM<2>
FBA_DQS_RN<2>
FBA_DQS_WP<2>
FBA_D<48>
FBA_D<49>
FBA_D<50>
FBA_D<51>
FBA_D<52>
FBA_D<53>
FBA_D<54>
FBA_D<55>
FBA_DQM<6>
FBA_DQS_RN<6>
FBA_DQS_WP<6>
www.vinafix.vn
9<>
Decoupling
for FBA Lo
Decoupling
for FBA Hi
FBVDD
C624
.1UF
10V
10%
X5R
0402
COMMON
C647
1UF
16V
10%
X5R
0603
COMMON
C576
4.7UF
6.3V
10%
X5R
0805
COMMON
C595
.1UF
10V
10%
X5R
0402
COMMON
C646
1UF
16V
10%
X5R
0603
COMMON
C623
4.7UF
6.3V
10%
X5R
0805
COMMON
C608
.1UF
10V
10%
X5R
0402
COMMON
C587
1UF
16V
10%
X5R
0603
COMMON
C632
4.7UF
6.3V
10%
X5R
0805
COMMON
C629
.1UF
10V
10%
X5R
0402
COMMON
C617
1UF
16V
10%
X5R
0603
COMMON
C577
4.7UF
6.3V
10%
X5R
0805
COMMON
C597
C598
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C641
C614
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C574
4.7UF
6.3V
10%
X5R
0805
COMMON
C600
C637
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
04020402
COMMON
COMMON
C581C642
1UF
1UF
16V
16V
10%
10%
X5R
X5R
06030603
COMMON
COMMON
C579
4.7UF
6.3V
10%
X5R
0805
COMMON
C636
.1UF
10V
10%
X5R
0402
Place 1uF caps at
center of memory
C585
.1UF
10V
10%
X5R
0402
NO STUFF
C601
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C633
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C580
C584
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C627
C609
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C638
C589
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C599
C625
C630
.1UF
10V
10%
X5R
0402
COMMON
C586
.1UF
10V
10%
X5R
0402
NO STUFF
C628
.1UF
10V
10%
X5R
0402
COMMON
C582
.1UF
10V
10%
X5R
0402
NO STUFF
C631
.1UF
10V
10%
X5R
0402
COMMON
C635
.1UF
10V
10%
X5R
0402
NO STUFF
C596
.1UF
10V
10%
X5R
0402
COMMON
C588
.1UF
10V
10%
X5R
0402
NO STUFF
C602
.1UF
10V
10%
X5R
0402
COMMON
C640
.1UF
10V
10%
X5R
0402
NO STUFF
C626
.1UF
10V
10%
X5R
0402
COMMON
C583
.1UF
10V
10%
X5R
0402
NO STUFF
5 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
R605
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
0402
R603
0402
R594
0402
R584
0402
R614
0402
R610
0402
R612
0402
R607
0402
COMMON
1.33K
COMMON
R114
549
0402
R113
04020402
1%
1%
1%
1%
1%
1%
1%
1%
FBVDD
1%
1%
GND
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
R1
R2
FBVDD
C136
.1UF
10V
X5R
0402
COMMON
9<>
Page6: FBB Partition
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6> CMD21
A<7>
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD16
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R613
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
3> 9>
3> 9>
R609
COMMON
FBB_CLK0_MIDPT
243
0402
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
R104
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
VERSION=BGA136
CHANGED
R611
243
0402
COMMON
C659
.01UF
25V
10%
X7R
0402
COMMON
FBB_CMD<28..0>
1%
9<>
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
14
15
R608
10K
5%
0402
COMMON
FBB_CMD<1>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<8>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<23>
FBB_CMD<20>
FBB_CMD<17>
FBB_CMD<9>
FBB_CMD<12>
FBB_CMD<3>
FBB_CMD<7>
FBB_CMD<18>
FBB_CLK0
FBB_CLK0*
SNN_FBB_NC0
FBB_CMD<14>
GND
FBB_CMD<15>
GND
FBB_ZQ0
R606
10K
5%
0402
COMMON
6< 3> 9>
1%
GND
GND
FBVDD
C109
.047UF
16V
10%
X7R
0402
COMMON
C129
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF0
FBB_VREF2
FBVDD
GND
GND
FBVDD
R105
549
1%
0402
COMMON
R106
1.33K
1%
0402 0402
COMMON
GND
GND
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
A<8> CMD23
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
FBVDD
R107
549
R1
9<>
C108
.1UF
R2
10V
X5R
0402
COMMON
0402
COMMON
R108
1.33K
COMMON
R1
1%
R2
1%
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
9>
R586
121
1%
0402
NO STUFF
FBB_CLK1_MIDPT
C128
.1UF
10V
10%10%
X5R
0402
COMMON
3> 9>
3>
R596
243
0402
COMMON
3> 6< 9>
1%
9<>
GND
R600
243
0402
COMMON
C610
.01UF
25V
10%
X7R
0402
COMMON
1%
FBB_CMD<28..0>
FBVDD
9<>
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
14
15
FBVDD
GND
C130
.047UF
16V
10%
X7R
0402
COMMON
FBB_CMD<7>
FBB_CMD<8>
FBB_CMD<18>
FBB_CMD<10>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<21>
FBB_CMD<20>
FBB_CMD<19>
FBB_CMD<25>
FBB_CMD<4>
FBB_CMD<9>
FBB_CMD<17>
FBB_CMD<6>
FBB_CMD<23>
FBB_CMD<16>
FBB_CMD<3>
FBB_CMD<12>
FBB_CMD<1>
FBB_CMD<11>
FBB_CLK1
FBB_CLK1*
SNN_FBB_NC1
FBB_CMD<14>
GND
FBB_CMD<15>
FBB_ZQ1
GND
R121
243
1%
0402
COMMON
C141
.047UF
16V
10%
X7R
0402
COMMON
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
V9
A9
A4
K1
K12
J1
J12
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBB_VREF1
FBB_VREF3
FBVDD
FBVDD
GND
GND
R118
549
0402
COMMON
R117
1.33K
COMMON
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C144
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
FBB_CMD<4>
FBB_CMD<6>
FBB_CMD<5>
FBB_CMD<13>
FBB_CMD<22>
FBB_CMD<24>
FBB_CMD<0>
FBB_CMD<2>
9<>
9<>
3<>
3> 9>
3< 9<
3> 9>
FBB_D<63..0>
FBB_DQM<7..0>
FBB_DQS_RN<7..0>
FBB_DQS_WP<7..0>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBB_D<0>
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_DQM<0>
0
FBB_DQM<1>
1
FBB_DQM<2>
2
FBB_DQM<3>
3
FBB_DQM<4>
4
FBB_DQM<5>
5
FBB_DQM<6>
6
FBB_DQM<7>
7
FBB_DQS_RN<0>
0
FBB_DQS_RN<1>
1
FBB_DQS_RN<2>
2
FBB_DQS_RN<3>
3
FBB_DQS_RN<4>
4
FBB_DQS_RN<5>
5
FBB_DQS_RN<6>
6
FBB_DQS_RN<7>
7
FBB_DQS_WP<0>
0
FBB_DQS_WP<1>
1
FBB_DQS_WP<2>
2
FBB_DQS_WP<3>
3
FBB_DQS_WP<4>
4
FBB_DQS_WP<5>
5
FBB_DQS_WP<6>
6
FBB_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBB_D<5>
FBB_D<6>
FBB_D<7>
FBB_DQS_RN<0>
FBB_DQS_WP<0>
FBB_D<32>
FBB_D<33>
FBB_D<34>
FBB_D<35>
FBB_D<36>
FBB_D<37>
FBB_D<38>
FBB_D<39>
FBB_DQM<4>
FBB_DQS_RN<4>
FBB_DQS_WP<4>
L10
R10
M10
R11
T11
T10
M11
N11
N10FBB_DQM<0>
P10
P11
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L3
R3
T3
M2
M3
T2
R2
N2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBB_D<8>
FBB_D<9>
FBB_D<10>
FBB_D<11>
FBB_D<12>
FBB_D<13>
FBB_D<14>
FBB_D<15>
FBB_DQM<1>
FBB_DQS_RN<1>
FBB_DQS_WP<1>
FBB_D<40>
FBB_D<41>
FBB_D<42>
FBB_D<43>
FBB_D<44>
FBB_D<45>
FBB_D<46>
FBB_D<47>
FBB_DQM<5>
FBB_DQS_RN<5>
FBB_DQS_WP<5>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
T3
R2
N2
R3
T2
M3
L3
N3
P3
P2
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
F10
E11
F11
B10
B11
C10
G10
C11
E10
D10
D11
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_DQM<2>
FBB_DQS_RN<2>
FBB_DQS_WP<2>
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50> T10
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_DQM<6>
FBB_DQS_RN<6>
FBB_DQS_WP<6>
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
G3
C3
B3
E2
F3
C2
B2
F2
E3
D3
D2
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
R11
R10
N11
M10
T11
M11
L10
N10
P10
P11
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_DQM<3>
FBB_DQS_RN<3>
FBB_DQS_WP<3>
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DQM<7>
FBB_DQS_RN<7>
FBB_DQS_WP<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBB Partition
M5
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E11
B11
F11
C11
B10
C10
G10
F10
E10
D10
D11
M8
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E2
C2
G3
F2
B3
F3
B2
C3
E3
D3
D2
www.vinafix.vn
Decoupling
for FBB Lo
Decoupling
for FBB Hi
FBVDD
C666
.1UF
10V
10%
X5R
0402
COMMON
C645
1UF
16V
10%
X5R
0603
COMMON
C672
4.7UF
6.3V
10%
X5R
0805
COMMON
C590
.1UF
10V
10%
X5R
0402
COMMON
C591
1UF
16V
10%
X5R
0603
COMMON
C572
4.7UF
6.3V
10%
X5R
COMMON
C656
.1UF
10V
10%
X5R
0402
COMMON
C665
1UF
16V
10%
X5R
0603
COMMON
C644
4.7UF
6.3V
10%
X5R
0805
COMMON
C618
.1UF
10V
10%
X5R
0402
COMMON
C649
1UF
16V
10%
X5R
0603
COMMON
C605
4.7UF
6.3V
10%
X5R
08050805
COMMON
C652
C661
.1UF
.1UF
10V10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C669
C663
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C664
4.7UF
6.3V
10%
X5R
0805
COMMON
C634
C613
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
04020402
COMMON
COMMON
C620 C621
1UF
1UF
16V
16V
10%
10%
X5R
X5R
06030603
COMMON
COMMON
C603
4.7UF
6.3V
10%
X5R
0805
COMMON
C660
.1UF
10V
10%
X5R
0402
Place 1uF caps at
center of memory
C654
.1UF
10V
10%
X5R
0402
NO STUFF
C607
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C612
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C668
C651
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C606
C639
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C619
C611
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C655
C667
C657
.1UF
10V
10%
X5R
0402
COMMON
C658
.1UF
10V
10%
X5R
0402
NO STUFF
C643
.1UF
10V
10%
X5R
0402
COMMON
C604
.1UF
10V
10%
X5R
0402
NO STUFF
C653
.1UF
10V
10%
X5R
0402
COMMON
C648
.1UF
10V
10%
X5R
0402
NO STUFF
C622
.1UF
10V
10%
X5R
0402
COMMON
C573
.1UF
10V
10%
X5R
0402
NO STUFF
C650
.1UF
10V
10%
X5R
0402
COMMON
C662
.1UF
10V
10%
X5R
0402
NO STUFF
C575
.1UF
10V
10%
X5R
0402
COMMON
C578
.1UF
10V
10%
X5R
0402
NO STUFF
6 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page7: FBC Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7> CMD16
A<8>
A<9>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD23
CMD20
CMD17
CMD9
CMD18
CMD15
FBVDD
R659
121
1%
0402
NO STUFF
FBC_CLK0_MIDPT
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
9> 4>
9> 4>
4> 7< 9>
R658
243
0402
COMMON
1%
FBC_CMD<28..0>
R655
243
1%
0402
COMMON
C864
.01UF
25V
10%
X7R
0402
COMMON
9<>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
FBC_CMD<1>
1
FBC_CMD<10>
10
FBC_CMD<11>
11
FBC_CMD<8>
8
FBC_CMD<19>
19
FBC_CMD<25>
25
FBC_CMD<22>
22
FBC_CMD<24>
24
FBC_CMD<0>
0
FBC_CMD<2>
2
FBC_CMD<21>
21
FBC_CMD<16>
16
FBC_CMD<23>
23
FBC_CMD<20>
20
FBC_CMD<17>
17
FBC_CMD<9>
9
FBC_CMD<12>
12
FBC_CMD<3>
3
FBC_CMD<7>
7
FBC_CMD<18>
18
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1
FBC_CMD<14>
14
GND
15
FBC_CMD<15>
V9
A9
A4
GND
FBC_ZQ0
GND
R635
10K
5%
0402
COMMON
10K
5%
0402
COMMON
243
1%
0402
COMMON
R93
R640
GND
FBVDD
C86
.047UF
16V
10%
X7R
0402
COMMON
C87
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
GND
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
FBC_VREF0
FBC_VREF2
GND
GND
FBVDD
R95
549
R1
1%
0402
COMMON
R97
1.33K
R2
1%
COMMON
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD00A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
R623
121
1%
0402
NO STUFF
4>
9>
4>
9>
FBC_CLK1_MIDPT
Minimize STUB length!
FBVDD
R94
549
R1
1%
0402
9<>
C84
.1UF
10V
10% 10%
X5R
0402
COMMON
COMMON
R96
1.33K
04020402
COMMON
R2
1%
C83
.1UF
10V
X5R
0402
COMMON
9<>
GND
R621
243
0402
COMMON
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R102
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
4> 7< 9>
FBC_CMD<28..0>
R625
243
1%
1%
0402
COMMON
FBVDD
C703
.01UF
25V
10%
X7R
0402
COMMON
9<>
FBC_CMD<7>
7
FBC_CMD<8>
8
FBC_CMD<18>
18
FBC_CMD<10>
10
FBC_CMD<5>
5
FBC_CMD<13>
13
FBC_CMD<21>
21
FBC_CMD<20>
20
FBC_CMD<19>
19
FBC_CMD<25>
25
FBC_CMD<4>
4
FBC_CMD<9>
9
FBC_CMD<17>
17
FBC_CMD<6>
6
FBC_CMD<23>
23
FBC_CMD<16>
16
FBC_CMD<3>
3
FBC_CMD<12>
12
FBC_CMD<1>
1
FBC_CMD<11>
11
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
FBC_CMD<14>
14
GND
FBC_CMD<15>
15
FBC_ZQ1
GND
GND
FBVDD
C100
.047UF
16V
10%
X7R
0402
COMMON
C98
.047UF
16V
10%
X7R
0402
COMMON
GND
FBVDD
FBVDD
FBC_VREF1
FBC_VREF3
GND
GND
R101
549
0402
COMMON
R99
1.33K
COMMON
FBC_CMD<4>
FBC_CMD<6>
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
VREF = 0.70 * FBVDDQ
GDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R1
1%
C103
.1UF
R2
1%
10V
10% 10%
X5R
0402
COMMON
GND
9<>
R632
0402
R631
0402
R622
0402
R627
0402
R654
0402
R648
0402
R653
0402
R657
0402
FBVDD
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
FBVDD
R100
549
R1
1%
0402
COMMON
R98
1.33K
04020402
COMMON
C102
.1UF
R2
1%
10V
X5R
0402
COMMON
9<>
GND
9<>
4<>
4> 9>
4< 9<
4> 9>
FBC_D<63..0>
FBC_DQM<7..0>
FBC_DQS_RN<7..0>
FBC_DQS_WP<7..0>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBC_D<0>
0
FBC_D<1>
1
FBC_D<2>
2
FBC_D<3>
3
FBC_D<4>
4
FBC_DQM<0>
0
FBC_DQM<1>
1
FBC_DQM<2>
2
FBC_DQM<3>
3
FBC_DQM<4>
4
FBC_DQM<5>
5
FBC_DQM<6>
6
FBC_DQM<7>
7
FBC_DQS_RN<0>
0
FBC_DQS_RN<1>
1
FBC_DQS_RN<2>
2
FBC_DQS_RN<3>
3
FBC_DQS_RN<4>
4
FBC_DQS_RN<5>
5
FBC_DQS_RN<6>
6
FBC_DQS_RN<7>
7
FBC_DQS_WP<0>
0
FBC_DQS_WP<1>
1
FBC_DQS_WP<2>
2
FBC_DQS_WP<3>
3
FBC_DQS_WP<4>
4
FBC_DQS_WP<5>
5
FBC_DQS_WP<6>
6
FBC_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBC_D<5>
FBC_D<6>
FBC_D<7>
FBC_DQM<0>
FBC_DQS_RN<0>
FBC_DQS_WP<0>
FBC_D<32>
FBC_D<33>
FBC_D<34>
FBC_D<35>
FBC_D<36>
FBC_D<37>
FBC_D<38>
FBC_D<39>
FBC_DQM<4>
FBC_DQS_RN<4>
FBC_DQS_WP<4>
B11
C11
F11
G10
C10
E11
F10
B10
E10
D10
D11
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
R3
T3
M3
L3
N2
R2
T2
N3
P3
P2
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
FBC_DQM<1>
FBC_DQS_RN<1>
FBC_DQS_WP<1>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_DQM<5>
FBC_DQS_RN<5>
FBC_DQS_WP<5>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
T2
R2
N2
R3
T3
L3
M3
N3
P3
P2
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B10
E11
F11
C11
B11
G10
F10
C10
E10
D10
D11
16
FBC_D<17>
17
FBC_D<18>
18
FBC_D<19>
19
FBC_D<20>
20
FBC_D<21>
21
FBC_D<22>
22
FBC_D<23>
23
FBC_DQM<2>
FBC_DQS_RN<2>
FBC_DQS_WP<2>
FBC_D<48>
48
FBC_D<49>
49
FBC_D<50> R11
50
FBC_D<51>
51
FBC_D<52>
52
FBC_D<53>
53
FBC_D<54>
54
FBC_D<55>
55
FBC_DQM<6>
FBC_DQS_RN<6>
FBC_DQS_WP<6>
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
C2FBC_D<16>
G3
F3
E2
F2
B2
B3
C3
E3
D3
D2
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10
M11
T11
R10
M10
N11
T10
N10
P10
P11
24
FBC_D<25>
25
FBC_D<26>
26
FBC_D<27>
27
FBC_D<28>
28
FBC_D<29>
29
FBC_D<30>
30
FBC_D<31>
31
FBC_DQM<3>
FBC_DQS_RN<3>
FBC_DQS_WP<3>
FBC_D<56>
56
FBC_D<57>
57
FBC_D<58> G3
58
FBC_D<59>
59
FBC_D<60>
60
FBC_D<61>
61
FBC_D<62>
62
FBC_D<63>
63
FBC_DQM<7>
FBC_DQS_RN<7>
FBC_DQS_WP<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBC Partition
M3
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10FBC_D<24>
M10
N11
R10
T11
R11
M11
T10
N10
P10
P11
M4
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
E2
B2
C2
C3
F2
B3
F3
E3
D3
D2
www.vinafix.vn
Decoupling
for FBC Lo
Decoupling
for FBC Hi
FBVDD
C835
.1UF
10V
10%
X5R
0402
COMMON
C882
1UF
16V
10%
X5R
0603
COMMON
C893
4.7UF
6.3V
10%
X5R
0805
COMMON
C685
.1UF
10V
10%
X5R
0402
COMMON
C690
1UF
16V
10%
X5R
0603
COMMON
C691
4.7UF
6.3V
10%
X5R
0805
COMMON
C850
.1UF
10V
10%
X5R
0402
COMMON
C838
1UF
16V
10%
X5R
0603
COMMON
C883
4.7UF
6.3V
10%
X5R
0805
COMMON
C742
.1UF
10V
10%
X5R
0402
COMMON
C689
1UF
16V
10%
X5R
0603
COMMON
C738
4.7UF
6.3V
10%
X5R
0805
COMMON
C836
.1UF
10V
10%
X5R
0402
COMMON
C880
1UF
16V
10%
X5R
COMMON
C840
4.7UF
6.3V
10%
X5R
0805
COMMON
C726
.1UF
10V
10%
X5R
COMMON
1UF
16V
10%
X5R
COMMON
C678
4.7UF
6.3V
10%
X5R
0805
COMMON
C847
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
C813
1UF
Place 1uF caps at
16V
center of memory
10%
X5R
06030603
COMMON
C888
.1UF
10V
10%
X5R
0402
NO STUFF
C695
C749
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
04020402
COMMON
COMMON
C741C766
1UF
Place 1uF caps at
16V
center of memory
10%
X5R
06030603
COMMON
C696
.1UF
10V
10%
X5R
0402
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMONCOMMON
C851
C875
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C740
C684
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C725
C683
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFFNO STUFF
600-10393-0004-100 A
p393_a01
whill
C878
C887
C834
C876
.1UF
10V
10%
X5R
0402
COMMON
C846
.1UF
10V
10%
X5R
0402
NO STUFF
C739
.1UF
10V
10%
X5R
0402
COMMON
C748
.1UF
10V
10%
X5R
0402
NO STUFF
C830
.1UF
10V
10%
X5R
0402
COMMON
C886
.1UF
10V
10%
X5R
0402
NO STUFF
C686
.1UF
10V
10%
X5R
0402
COMMON
C693
.1UF
10V
10%
X5R
0402
NO STUFF
C889
.1UF
10V
10%
X5R
0402
COMMON
C829
.1UF
10V
10%
X5R
0402
NO STUFF
C694
.1UF
10V
10%
X5R
0402
COMMON
C717
.1UF
10V
10%
X5R
0402
NO STUFF
7 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page8: FBD Partition
OUT
OUT
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
ININININOUT
OUT
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
136BGA CMD Mapping
ADDR
RAS*
CAS*
WE*
CS0*
BA2
BA0
BA1
A<12>
A<0>
A<1>
0A<2>
0A<3>
0A<4>
0A<5>
1A<2>
1A<3>
1A<4>
1A<5>
A<6>
A<7> CMD16
A<8>
A<10>
A<11>
CKE
RST
136MAP
CMD1
CMD10
CMD11
CMD8
CMD7
CMD12
CMD3
CMD14
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD23
CMD20A<9>
CMD17
CMD9
CMD18
CMD15
FBVDD
R706
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
4>
9>
4>
9>
FBD_CLK0_MIDPT
R709
243
0402
COMMON
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
R28
243
1%
0402
COMMON
H11
K10
K11
H10
J11
J10
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
GND
R707
243
0402
COMMON
C958
.01UF
25V
10%
X7R
0402
COMMON
FBD_CMD<28..0>
1%
9<>
FBD_CMD<1>
1
FBD_CMD<10>
10
FBD_CMD<11>
11
FBD_CMD<8>
8
FBD_CMD<19>
19
FBD_CMD<25>
25
FBD_CMD<22>
22
FBD_CMD<24>
24
FBD_CMD<0>
0
FBD_CMD<2>
2
FBD_CMD<21>
21
FBD_CMD<16>
16
FBD_CMD<23>
23
FBD_CMD<20>
20
FBD_CMD<17>
17
FBD_CMD<9>
9
FBD_CMD<12>
12
FBD_CMD<3>
3
FBD_CMD<7>
7
FBD_CMD<18>
18
FBD_CLK0
FBD_CLK0*
SNN_FBD0_NC1
FBD_CMD<14>
14
FBD_CMD<15>
15
FBD_ZQ0
R694
R690
10K
10K
5%
5%
0402
0402
COMMON COMMON
GND
GND
4> 8< 9>
1%
GND
FBVDD
C43
.047UF
16V
10%
X7R
0402
COMMON
C57
.047UF
16V
10%
X7R
0402
COMMON
K12
J12
K1
J1
FBVDD
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBD_VREF0
FBD_VREF2
FBVDD
GND
GND
R42
549
0402
COMMON
R47
1.33K
COMMON
1%
1%
GND
136BGA CMD Mapping
136MAPADDR
CMD1
RAS*
CMD10
CAS*
CMD11
WE*
CMD8
CS0*
CMD7
BA2
CMD12
BA0
CMD3
BA1
CMD14
A<12>
CMD19
A<0>
CMD25
A<1>
CMD22
0A<2>
CMD24
0A<3>
CMD0
0A<4>
CMD2
0A<5>
CMD4
1A<2>
CMD6
1A<3>
CMD5
1A<4>
CMD13
1A<5>
CMD21
A<6>
CMD16
A<7>
CMD23A<8>
CMD20
A<9>
CMD17
A<10>
CMD9
A<11>
CMD18
CKE
CMD15
RST
FBVDD
R682
121
1%
0402
NO STUFF
Clock Term MUST BE PLACED as close
as possible to the BGA memory on
the line AFTER the memory pin!
Minimize STUB length!
R26
549
0402
COMMON
R27
1.33K
04020402
COMMON
FBVDD
1%
1%
GND
FBVDD
R1
C55
.1UF
R2
10V
10% 10%
X5R
0402
COMMON
GND
VREF = 0.70 * FBVDDQGDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
9<>
4> 9>
4> 9>
FBD_CLK1_MIDPT
R1
R2
C42
.1UF
10V
X5R
0402
COMMON
R678
243
0402
COMMON
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
H11
K10
K11
H10
J11
J10
K12
J12
CHANGED
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
K2
L4
G4
G9
H4
J2
J3
V4
V9
A9
A4
K1
J1
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
FBVDD
R676
243
0402
COMMON
C929
.01UF
25V
10%
X7R
0402
COMMON
1%
FBD_CMD<28..0>
FBVDD
9<>
FBD_CMD<7>
7
FBD_CMD<8>
8
FBD_CMD<18>
18
FBD_CMD<10>
10
FBD_CMD<5>
5
FBD_CMD<13>
13
FBD_CMD<21>
21
FBD_CMD<20>
20
FBD_CMD<19>
19
FBD_CMD<25>
25
FBD_CMD<4>
4
FBD_CMD<9>
9
FBD_CMD<17>
17
FBD_CMD<6>
6
FBD_CMD<23>
23
FBD_CMD<16>
16
FBD_CMD<3>
3
FBD_CMD<12>
12
FBD_CMD<1>
1
FBD_CMD<11>
11
FBD_CLK1
FBD_CLK1*
SNN_FBD1_NC1
FBD_CMD<14>
14
GND
FBD_CMD<15>
15
FBD_ZQ1
R69
243
1%
0402
COMMON
4> 8< 9>
1%
GND
GND
9<>
FBVDD
C68
.047UF
16V
10%
X7R
0402
COMMON
C59
.047UF
16V
10%
X7R
0402
COMMON
GND
FBD_VREF1
FBD_VREF3
FBVDD
FBVDD
GND
GND
FBD_CMD<4>
FBD_CMD<6>
FBD_CMD<5>
FBD_CMD<13>
FBD_CMD<22>
FBD_CMD<24>
FBD_CMD<0>
FBD_CMD<2>
VREF = 0.70 * FBVDDQ
GDDR3:
1.41V = 2.0V * 1.33K/(549 + 1.33K)
FBVDD
R59
549
R1
1%
0402
COMMON
R51
1.33K
R2
1%
0402 0402
COMMON
C64
.1UF
10V
X5R
0402
COMMON
GND
R79
549
0402
COMMON
R76
1.33K
COMMON
R679
0402
R684
0402
R685
0402
R687
0402
R705
0402
R701
0402
R703
0402
R710
0402
FBVDD
1%
1%
GND
9<>
FBVDD
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
121
COMMON
1%
R1
9<>
C70
R2
.1UF
10V
10%10%
X5R
0402
COMMON
9<
4<>
4> 9>
4<
4> 9>
FBD_D<63..0>
FBD_DQM<7..0>
FBD_DQS_RN<7..0>
FBD_DQS_WP<7..0>
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M10
T10
L10
M11
T11
R11
N11
R10
N10
P10
P11
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
B2
C3
C2
E2
G3
F2
F3
E3
D3
D2FBD_DQS_WP<7>
E2
F3
C3
F2
G3
B2
B3
C2
E3
D3
D2
R3
T3
R2
T2
N2
L3
M3
M2
N3
P3
P2
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBD_D<24>
24
FBD_D<25>
25
FBD_D<26>
26
FBD_D<27>
27
FBD_D<28>
28
FBD_D<29>
29
FBD_D<30>
30
FBD_D<31>
31
FBD_DQM<3>
FBD_DQS_RN<3>
FBD_DQS_WP<3>
FBD_D<56>
56
FBD_D<57>
57
FBD_D<58>
58
FBD_D<59> B3
59
FBD_D<60>
60
FBD_D<61>
61
FBD_D<62>
62
FBD_D<63>
63
FBD_DQM<7>
FBD_DQS_RN<7>
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FBD Partition
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
FBD_D<0>
0
FBD_D<1>
1
FBD_D<2>
2
FBD_D<3>
3
FBD_D<4>
4
FBD_DQM<0>
0
FBD_DQM<1>
1
FBD_DQM<2>
2
FBD_DQM<3>
3
FBD_DQM<4>
4
FBD_DQM<5>
5
FBD_DQM<6>
6
FBD_DQM<7>
7
FBD_DQS_RN<0>
0
FBD_DQS_RN<1>
1
FBD_DQS_RN<2>
2
FBD_DQS_RN<3>
3
FBD_DQS_RN<4>
4
FBD_DQS_RN<5>
5
FBD_DQS_RN<6>
6
FBD_DQS_RN<7>
7
FBD_DQS_WP<0>
0
FBD_DQS_WP<1>
1
FBD_DQS_WP<2>
2
FBD_DQS_WP<3>
3
FBD_DQS_WP<4>
4
FBD_DQS_WP<5>
5
FBD_DQS_WP<6>
6
FBD_DQS_WP<7>
7
5
6
7
32
33
34
35
36
37
38
39
FBD_D<5>
FBD_D<6>
FBD_D<7>
FBD_DQM<0>
FBD_DQS_RN<0>
FBD_DQS_WP<0>
FBD_D<32>
FBD_D<33>
FBD_D<34>
FBD_D<35>
FBD_D<36>
FBD_D<37>
FBD_D<38>
FBD_D<39>
FBD_DQM<4>
FBD_DQS_RN<4>
FBD_DQS_WP<4>
C11
E11
F11
G10
B11
F10
C10
B10
E10
D10
D11
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
L10
R10
T10
N11
T11
M10
M11
R11
N10
P10
P11
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
FBD_D<8>
FBD_D<9>
FBD_D<10>
FBD_D<11>
FBD_D<12>
FBD_D<13>
FBD_D<14>
FBD_D<15>
FBD_DQM<1>
FBD_DQS_RN<1>
FBD_DQS_WP<1>
FBD_D<40>
FBD_D<41>
FBD_D<42>
FBD_D<43>
FBD_D<44>
FBD_D<45>
FBD_D<46>
FBD_D<47>
FBD_DQM<5>
FBD_DQS_RN<5>
FBD_DQS_WP<5>
M1
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
N2
T2
R2
R3
T3
M2
L3
M3
N3
P3
P2
M2
HYB18H512321BF-10
PACK_TYPE=BGA136_V2
VERSION=BGA136
CHANGED
C10
F11
E11
B11
C11
G10
F10
B10
E10
D10
D11
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBD_D<16>
FBD_D<17>
FBD_D<18>
FBD_D<19>
FBD_D<20>
FBD_D<21>
FBD_D<22>
FBD_D<23>
FBD_DQM<2>
FBD_DQS_RN<2>
FBD_DQS_WP<2>
FBD_D<48>
FBD_D<49>
FBD_D<50>
FBD_D<51>
FBD_D<52>
FBD_D<53>
FBD_D<54>
FBD_D<55>
FBD_DQM<6>
FBD_DQS_RN<6>
FBD_DQS_WP<6>
www.vinafix.vn
9<>
Decoupling
for FBD Lo
Decoupling
for FBD Hi
FBVDD
C950
.1UF
10V
10%
X5R
0402
COMMON
C967
1UF
16V
10%
X5R
0603
COMMON
C977
4.7UF
6.3V
10%
X5R
0805
COMMON
C934
.1UF
10V
10%
X5R
0402
COMMON
C908
1UF
16V
10%
X5R
0603
COMMON
C933
4.7UF
6.3V
10%
X5R
0805
COMMON
C969
.1UF
10V
10%
X5R
0402
COMMON
C938
1UF
16V
10%
X5R
0603
COMMON
C962
4.7UF
6.3V
10%
X5R
0805
COMMON
C930
.1UF
10V
10%
X5R
0402
COMMON
C941
1UF
16V
10%
X5R
0603
COMMON
C910
4.7UF
6.3V
10%
X5R
0805
COMMON
C943
C961
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C952
C949
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603 0603
COMMON
COMMON
C965
4.7UF
6.3V
10%
X5R
0805
COMMON
C937
C935
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C920
C925
1UF
1UF
16V
16V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
C942
4.7UF
6.3V
10%
X5R
0805
COMMON
C972
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C974
.1UF
10V
10%
X5R
0402
NO STUFF
C927
.1UF
10V
10%
X5R
0402
COMMON
Place 1uF caps at
center of memory
C936
.1UF
10V
10%
X5R
0402
NO STUFF
p393_a01
whill
.1UF
.1UF
10V10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C963
C944
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
C924
C931
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C932
C926
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
NO STUFF
NO STUFF
600-10393-0004-100 A
C957
C948
C953
.1UF
10%
X5R
0402
COMMON
C971
.1UF
10V
10%
X5R
0402
NO STUFF
C928
.1UF
10V
10%
X5R
0402
COMMON
C914
.1UF
10V
10%
X5R
0402
NO STUFF
C947
.1UF
10V10V
10%
X5R
0402
COMMON
C956
.1UF
10V
10%
X5R
0402
NO STUFF
C919
.1UF
10V
10%
X5R
0402
COMMON
C939
.1UF
10V
10%
X5R
0402
NO STUFF
C940
.1UF
10V
10%
X5R
0402
COMMON
C955
.1UF
10V
10%
X5R
0402
NO STUFF
C916
.1UF
10V
10%
X5R
0402
COMMON
C923
.1UF
10V
10%
X5R
0402
NO STUFF
8 OF 27
28-SEP-2007
GND
GND
GND
GND
GND
GND
Page9: FrameBuffer Net Rules
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUTINOUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI
OUTINOUT
OUT
OUT
OUT
OUT
OUTBIOUTINOUT
OUT
OUT
OUT
OUT
OUT
NET RULES for FrameBuffer A/B
5<>
5<>
5<>
5<>
5<
5<
5<
5<
5<
3<>
3>
3>
3>
3>
3>
3>
3<
3>
NET
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1* 1
FBA_CMD<28..0>
FBA_DQS_WP<7..0>
FBA_DQS_RN<7..0>
FBA_DQM<7..0>
FBA_D<63..0>
NET
6<
3>
6<
3>
6<
3>
6<
3>
6<
3>
3> 6<>
6<>
6<>
6<>
3<>
3<>
3<>
3<
3>
FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_CMD<28..0>
FBB_DQS_WP<7..0> 1
FBB_DQS_RN<7..0>
FBB_DQM<7..0>
FBB_D<63..0>
FBA_DEBUG
FBB_DEBUG
NET VOLTAGE
3<>
FBAB_PLLAVDD
NV_CRITICAL
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1.2V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
MAX_CURRENT MIN_WIDTH NET VOLTAGE
0.02A
12MIL
NET RULES for FrameBuffer C/D
7<>
8<>
7<
7<
7<
7<
7<
7<>
7<>
7<>
8<
8<
8<
8<
8<
8<>
8<>
4<>
4<>
4<>
4<>
4<>
4>
4>
4>
4>
4>
4>
4<
4>
4>
4>
4>
4>
4>
4> 8<>
4<
4>
NET
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_CMD<28..0>
FBC_DQS_WP<7..0>
FBC_DQS_RN<7..0>
FBC_DQM<7..0>
FBC_D<63..0>
NET
FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
FBD_CMD<28..0>
FBD_DQS_WP<7..0> 1
FBD_DQS_RN<7..0>
FBD_DQM<7..0>
FBD_D<63..0>
FBC_DEBUG
FBD_DEBUG
FBCD_PLLAVDD
NV_CRITICAL
1
1
1
1
1
1
1
1
1
NV_CRITICAL
1
1
1
1
1
1
1
1
1
1
1.2V
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
NV_IMPEDANCE DIFFPAIR
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
40OHM
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
MAX_CURRENT MIN_WIDTH
0.02A
12MIL
5>
5>
5>
5>
5<
5<
6>
6>
6>
6>
6<
6<
FBA_VREF0
FBA_VREF1
FBA_VREF2
FBA_VREF3
FBA_ZQ0
FBA_ZQ1
FBB_VREF0
FBB_VREF1
FBB_VREF2
FBB_VREF3
FBB_ZQ0
FBB_ZQ1
3<>
3<>
FB_VREF1
FB_VREF2
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A 12MIL
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
7>
7>
7>
7>
7<
7<
8>
8>
8>
8>
8<
8<
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBC_ZQ0
FBC_ZQ1
FBD_VREF0
FBD_VREF1
FBD_VREF2
FBD_VREF3
FBD_ZQ0
FBD_ZQ1
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
1.40V
1.40V
1.40V
1.40V
2.0V
2.0V
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
0.02A
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
12MIL
P393 G92-270 512MB GDDR3 16Mx32 DVI-I+DVI-I+HDTV
FrameBuffer Net Rules
www.vinafix.vn
600-10393-0004-100 A
p393_a01
whill
9 OF 27
28-SEP-2007
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