MSI MS-V102 Schematic
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
ASSEMBLYNVPNVARIANT
B
1
2
SKU
3
4
5
6
12
13
14
7
8
9
10
11
15
P402-A02 DESIGN -- G84/G86, 540/702 128/256 MB DDR3, VGA, DVI-I, SD/HDTV
BASE
SKU0000
SKU0010
SKU0500
SKU9100
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
600-10402-base-sch
600-10402-0000-200
600-10402-0010-200
600-50402-0500-200
600-10402-9100-200
<UNDEFINED>
<UNDEFINED> <UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
G86-400-500/700Mhz 256/128 MB 16Mx32 BGA135 GDDR3 DVI+VGA_HDTV-Out
G84-875, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
<UNDEFINED>
<UNDEFINED><UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
PAGE SUMMARY:
Page 1: TABLE OF CONTENTS & REVISION HISTORY
Page 2: PCI EXPRESS 16X, NVVDD DECOUPLING CAPS,PEX_IOVDD/Q DECOUPLING CAPS
Page 3: FBA MEMORY INTERFACE, GPU FBVDD/Q DECOUPLING CAPS
Page 4: FBA 8Mx32 DDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS
Page 5: FBA MEMORY FBVDD/Q DECOUPLING CAPS
Page 6: FBC MEMORY INTERFACE, GPU FBVTT
Page 7: FBC 8MX32 DDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS
Page 8: FBC MEMORY FBVDD/Q DECOUPLING CAPS, GPU GND CONNECTIONS
Page 9: DACA FILTERS, DACA SYNC BUFFERS & DB15 SOUTH
Page 10: DACC FILTERS, DACC SYNC BUFFERS & DB15 MID
Page 11: TMDS LINK A/B & PU's, TMDS IO BACKDRIVE PREVENTION,DVI CONNECTOR SOUTH
Page 12: TMDS LINK C/D & PU's,DVI CONNECTOR MID
Page 13: MIOA & MIOB, SLI CONNECTOR
Page 14: DACB FILTERS, MINIDIN CONNECTOR NORTH, COMPONENT VIDEO OUTPUT CONNECTOR
Page 15: SPDIF-IN HEADER, XTAL
Page 16: EXTERNAL THERMAL SENSOR, 2PIN / 4PIN FAN CONTROL, GPIO
Page 17: BIOS ROM, HDCP ROM
Page 18: BIOS STRAPS & MECHANICALS
Page 19: POWER SUPPLY LINEARS: DDC5V, TMDS PLLVDD, DACB VDD, MIOA_VDDQ
Page 20: POWER SUPPLY: 5V, TMDSIOVDD, PEX1V2 AND FBVDDQ SWITCHER
Page 21: POWER SUPPLY: SINGLE PHASE NVVDD, NVVDD SET CONTROL
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
TABLE OF CONTENTS & REVISION HISTORY
www.vinafix.vn
600-10402-0000-200 H
p402
broth
1 OF 21
03-APR-2007
PEX3V3
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIININININOUT
OUT
OUT
OUT
IN
1/14 PCI_EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
VDD
VDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_LP
VDD_LP
VDD_LP
VDD_LP
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD_LP
VDD_LP
VDD_SENSE
GND_SENSE
VDD33
VDD33
PEX_PLLGND
PEX_PLLDVDD
PEX_PLLAVDD
SPDIF
PEX_RST
RFU
RFU
PEX_RX1
PEX_TX1
PEX_TX1
PEX_RX0
PEX_RX0
PEX_TX0
PEX_TX0
PEX_REFCLK
PEX_REFCLK
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_RX1
PEX_TX2
PEX_RX4
PEX_RX4
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_TX3
PEX_TX3
PEX_RX2
PEX_RX2
PEX_TX2
PEX_TX5
PEX_TX5
PEX_RX5
PEX_TX8
PEX_TX8
PEX_RX7
PEX_RX7
PEX_TX7
PEX_TX7
PEX_RX6
PEX_RX6
PEX_TX6
PEX_TX6
PEX_RX5
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_RX10
PEX_RX10
PEX_TX10
PEX_TX10
PEX_RX9
PEX_RX9
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX15
PEX_TX15
PEX_RX14
PEX_RX14
PEX_TX14
PEX_TX14
PEX_RX13
PEX_RX13
PEX_TX13
PEX_TX13
PEX_RX15
PEX_RX15
IN
BI
END OF X8
END OF X16
END OF X1
END OF X4
TCLK JTAG2
TMS JTAG5
TDO JTAG4
TDI JTAG3
WAKE
SMDAT
SMCLK
PERN0
PERP0
REFCLK
PERST
REFCLK
PETN1
PERP2
PETN0
PERP1
PERN1
PETP0
PETP1
PERN3
PETP3
PETN3
PETP2
PERP3
PETN2
PERN2
PERP4
PERN4
PETN4
PERP5
PETP4
PERN5
PETP5
PETP6
PERN6
PERP6
PETN5
PERP7
PETN6
PERN7
PETN8
PETP8
PERP8
PETN7
PETP7
PERN8
PERN9
PERP9
PERP10
PERN10
PETP10
PETP9
PETN9
PETN10
PETN11
PERP12
PERN12
PERP11
PERN11
PETP11
PETN12
PETP12
PETN13
PERP13
PERN13
PETP13
PERP14
PERN15
PETP15
PETN15
PERN14
PETN14
PETP14
PERP15
TRST* JTAG1+12V
+12V/RSVD
+3V3AUX
+12V
+12V
+12V
+3V3
+3V3
+3V3
PRSNT2
PRSNT1
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
GND
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
C849
.01UF
16V
10%
X7R
0402
COMMON
3V3AUX
GND
Place Close to fingers
C848
.1UF
16V
10%
X7R
0402
COMMON
PEX12V
PEX3V3
3V3AUX
PRSNT
SNN_PE_PRSNT2_A
SNN_PE_RSVD2
SNN_PE_PRSNT2_B
SNN_PE_RSVD3
SNN_PE_RSVD4
SNN_PE_RSVD5
SNN_PE_PRSNT2_C
SNN_PE_RSVD6
PRSNT
SNN_PE_RSVD7
SNN_PE_RSVD8
C32
.1UF
16V
10%
X5R
0402
COMMON
C846
10UF
16V
20%
X5R
1206
COMMON
GND
GND
GND
GND
GND
A10
B10
B17
B12
A12
B13
A15
B16
B18
A18
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
B1
B2
A2
A3
B3
B8
A9
A1
B4
A4
B7
CN2
CON_X16
CON_PCIEXP_X16_EDGE
COMMON
PEX12V
C28
.01UF
25V
10%
X7R
0402
COMMON
NONPHY-X16
C29
.1UF
16V
10%
X7R
0603
COMMON
B9
A5
A6
A7
A8
B5
B6
B11
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
C30
10UF
16V
20%
X5R
1206
COMMON
GND
PEX_R_JTAG_TRST*
PEX_R_JTAG_TCLK
PEX_R_JTAG_TDI
PEX_R_JTAG_TDO
PEX_R_JTAG_TMS
I2CS_SCL_PRS
I2CS_SDA_PRS
SNN_PEX_WAKE*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*A36
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
R635
0
5%
0402
NO STUFF
R_0402-05116WROHSRDP-0A
R10
0402
5%
R_0402-05116WROHSRDP-0A
0
R11
NO STUFF
0402
5%
0
NO STUFF
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
I2CS_SCL
I2CS_SDA
X7R
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7R
X7RCOMMON
X7R
X7RCOMMON
R_PAK_0402X4-0005R_MAX120WB
NO STUFF
RP501
R_PAK_0402X4-0005R_MAX120WB
NO STUFF
RP501
R_PAK_0402X4-0005R_MAX120WB
1
R_PAK_0402X4-0005R_MAX120WB
NO STUFF
RP501
NO STUFF
RP501
3
R632
0402
5%
NO STUFF
PEX_PWRGD*
.1UF
C791
16V
040210%
.1UF
C778
16V
040210%
.1UF
C764
16V
0402
10%
.1UF
C750
16V
0402
10%
.1UF
C731
16V
0402
10%
.1UF
C720
16V
0402
10%
.1UF
C709
16V
040210%
.1UF
C699
16V
10%X7R 0402COMMON
.1UF
C688
16V
040210%
.1UF
C677
16V
0402
10%
.1UF
C653
16V
0402
10%
.1UF
C641
16V
0402
10%
.1UF
C635
16V
0402
10%
.1UF
C632
16V
040210%
.1UF
C622
16V
0402
10%
.1UF
C615
16V
0402
10%
JTAG_TRST*
702
JTAG_TCLK
0
8
JTAG_TDI
504
JTAG_TDO
0
R_0402-05116WROHSRDP-0A
6
JTAG_TMS
0
16<
16<>
R603
0402
PEX_TEST_PLLCLK_OUT
PEX_TEST_PLLCLK_OUT_N
.1UF
C785
16V0402
.1UF
C773
16V0402
.1UF
C756
16V
0402
.1UF
C739
16V
0402
.1UF
C727
16V
0402
.1UF
C712
16V
0402
.1UF
C702
16V0402
.1UF
C694
0402 X7R16V 10% COMMON
.1UF
C683
16V0402
.1UF
C667
16V
0402
.1UF
C650
16V
0402
.1UF
C638
16V
0402
.1UF
C633
16V
0402
.1UF
C630
16V0402
.1UF
C620
16V
0402
.1UF
C611
16V
0402
16X PEX INTERFACE
16>
16>
16>
16<
16>
17<
R_0402-05116WROHSRDP-0A
PEX_PWRGD_GPU*
0
COMMON
5%
SNN_PEXCAPD_VDDQ
SNN_PEXCALPD_GND
200
R31
0402 COMMON
5%
PEX_TX0
PEX_TX0*
X7R COMMON
10%
PEX_TX1
PEX_TX1*
X7R
COMMON10%
PEX_TX2
PEX_TX2*
X7R
COMMON
10%
PEX_TX3
PEX_TX3*
X7R COMMON
10%
PEX_TX4
PEX_TX4*
X7R
COMMON10%
PEX_TX5
PEX_TX5*
X7R
COMMON
10%
PEX_TX6
PEX_TX6*
X7R COMMON
10%
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
X7R
COMMON10%
PEX_TX9
PEX_TX9*
X7R
COMMON
10%
PEX_TX10
PEX_TX10*
X7R COMMON
10%
PEX_TX11
PEX_TX11*
X7R
COMMON10%
PEX_TX12
PEX_TX12*
X7R
COMMON
10%
PEX_TX13
PEX_TX13*
X7R COMMON
10%
PEX_TX14
PEX_TX14*
X7R
COMMON10%
PEX_TX15
PEX_TX15*
X7R COMMON
10%
U_GPU_G3_128_8X_BGA820-G84-300B
G1
G84-300-A1
BGA820
COMMON
1
AH15
AG12
AH13
AM12
AM11
AH14
AJ14
AJ15
AK15
AK13
AK14
AH16
AG16
AM14
AM15
AG17
AH17
AL15
AL16
AG18
AH18
AK16
AK17
AK18
AJ18
AL17
AL18
AJ19
AH19
AM18
AM19
AG20
AH20
AK19
AK20
AG21
AH21
AL20
AL21
AK21
AJ21
AM21
AM22
AJ22
AH22
AK22
AK23
AG23
AH23
AL23
AL24
AK24
AJ24
AM24
AM25
AJ25
AH25
AK25
AK26
AH26
AG26
AL26
AL27
AK27
AJ27
AM27
AM28
AJ28
AH27
AL28
AL29
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
PCI EXPRESS 16X, NVVDD DECOUPLING CAPS,PEX_IOVDD/Q DECOUPLING CAPS
www.vinafix.vn
AD23
AF23
AF24
AF25
AG24
AG25
AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22
K16
K17
N13
N14
N16
N17
N19
P13
P14
P16
P17
P19
R16
R17
T13
T14
T15
T18
T19
U13
U14
U15
U18
U19
V16
V17
W13
W14
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
P20
T20
T23
U20
U23
W20
N20
M21
AC11
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
L10
L7
L8
M10
AF15
AE15
AE16
J6
600mA
NVVDD_SENSE
GND_SENSE
GND
F_SPDIFIN
6MIL
Place near balls
C674
.022UF
16V
10%
X7R
0402
COMMON
2A
C698
.022UF
16V
10%
X7R
0402
COMMON
VALUES TBD
6MIL
R576
0402
5%
2<>
VALUES TBD
C658
.022UF
16V
10%
X7R
0402
COMMON
VALUES TBD
Place near balls
C724
.022UF
16V
10%
X7R
0402
COMMON
C696
.47UF
6.3V
10%
X5R
0402
COMMON
C713
.1UF
16V
10%
X7R
0402
COMMON
C714
.47UF
6.3V
10%
X5R
0402
COMMON
C663
.47UF
6.3V
10%
0402
COMMON
0
COMMON
C679
.1UF
16V
10%
X7R
0402
COMMON
C710
.1UF
16V
10%
X7R
0402
COMMON
C695
.1UF
16V
10%
X7R
0402
COMMON
C678
.1UF
16V
10%
X7RX5R
0402
COMMON
C666
1000PF
50V
10%
X7R
0402
GND
270mA
Place near balls
20mA
15>
C686
.01UF
16V
10%
X7R
0402
COMMON
C690
.01UF
16V
10%
X7R
0402
COMMON
Place near balls
C664
.47UF
6.3V
10%
X5R
0402
COMMON
C660
.47UF
6.3V
10%
X5R
0402
COMMON
C689
.1UF
16V
10%
X7R
0402
COMMON
C682
.1UF
16V
10%
0402
COMMON
COMMON
21<
2<>
Place near balls
C768
C736
4700PF
.1UF
25V
10V
10%
10%
X7R
X5R
0402
0402
COMMONCOMMON
C754
C729
4700PF
.1UF
25V
10V
10%
10%
X7RX5R
0402
0402
COMMON
COMMON
Place near balls
PEX_PLL_VDD
C711
.1UF
10%
16V
X7R
0402
COMMON
C722
4700PF
10%
25V
X7R
0402
COMMON
15<
C721
.01UF
16V
10%
X7R
0402
COMMON
C723
470PF
16V
10%
X7R
0402
COMMON
Place Close to GPU
C623
4.7UF
10%6.3V
X5R
0603
COMMON
Place Close to GPU
C701
.01UF
16V
10%
X7R
0402
COMMON
C732
.47UF
6.3V
10%
X5R X5RX7RX7R
0402
COMMON
C652
.022UF
16V
10%
X7R
0402
COMMON
C740
.022UF
16V
10%
X7R
0402
COMMON
C719
.47UF
6.3V
10%
X5R
0402
COMMON
C718
.1UF
16V
10%
X7R
0402
COMMON
C726
.47UF
6.3V
10%
X5R
0402
COMMON
C700
.1UF
16V
10%
X7R
0402
COMMON
C730
.47UF
6.3V
10%
X5R
0402
COMMON
C715
.47UF
6.3V
10%
X5R
0402
COMMON
Place Near BGA
PEX1V2
C624
4.7UF
6.3V
X5R
0603
COMMON
C681
22UF
20%
6.3V
X5R
0805
COMMON
C717
.1UF
16V
10%
X7R
0402
COMMON
C735
10UF
6.3V
20%
X5R
0805
COMMON
C703
10UF
6.3V
20%
X5R
0805
COMMON
C704
.1UF
16V
10%
0402
COMMON
C779
.022UF
16V
10%
X7R
0402
COMMON
C647
.022UF
16V
10%
X7R
0402
COMMON
Place Near BGA
C706
.47UF
6.3V
10%
0402
COMMON
GND
GND
180R@100MHz
LB503
C708
4.7UF
10%
6.3V
X5R
0603
COMMON
GND
C796
1UF
6.3V
10%
X7R
0603
COMMON
COMMONBEAD_0603
GND
10%
PEX1V2
C625
22UF
X5R
0805
COMMON
C693
10UF
6.3V
20%
X5R
0805
COMMON
C705
.1UF
16V
10%
X7R
0402
COMMON
PEX3V3
20%6.3V
C733
.1UF
16V
10%
X7R
0402
COMMON
GND
GND
PEX1V2
GND
NVVDD
GND
GND
C676
4.7UF
6.3V
X5R
0603
COMMON
PEX_REFCLK
PEX_REFCLK*
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
PEX_TXX0
PEX_TXX0*
PEX_TXX1
PEX_TXX1*
PEX_TXX2
PEX_TXX2*
PEX_TXX3
PEX_TXX3*
PEX_TXX4
PEX_TXX4*
PEX_TXX5
PEX_TXX5*
PEX_TXX6
PEX_TXX6*
PEX_TXX7
PEX_TXX7*
PEX_TXX8
PEX_TXX8*
PEX_TXX9
PEX_TXX9*
PEX_TXX10
PEX_TXX10*
PEX_TXX11
PEX_TXX11*
PEX_TXX12
PEX_TXX12*
PEX_TXX13
PEX_TXX13*
PEX_TXX14
PEX_TXX14*
PEX_TXX15
PEX_TXX15*
PEX_RX0
PEX_RX0*
PEX_RX1
PEX_RX1*
PEX_RX2
PEX_RX2*
PEX_RX3
PEX_RX3*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_RX14
PEX_RX14*
PEX_RX15
2> 21<
2>
PEX3V3
PEX12V
PEX_RX15*
NVVDD_SENSE
GND_SENSE
PEX3V3
PEX12V
NV_PLLAVDD
PEX_PLL_VDD
10%
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_TX1
PEX_TX1
PEX_TX2
PEX_TX2
PEX_TX3
PEX_TX3
PEX_TX4
PEX_TX4
PEX_TX5
PEX_TX5
PEX_TX6
PEX_TX6
PEX_TX7
PEX_TX7
PEX_TX8
PEX_TX8
PEX_TX9
PEX_TX9
PEX_TX10
PEX_TX10
PEX_TX11
PEX_TX11
PEX_TX12
PEX_TX12
PEX_TX13
PEX_TX13
PEX_TX14
PEX_TX14
PEX_TX15
PEX_TX15
PEX_TXX0
PEX_TXX0
PEX_TXX1
PEX_TXX1
PEX_TXX2
PEX_TXX2
PEX_TXX3
PEX_TXX3
PEX_TXX4
PEX_TXX4
PEX_TXX5
PEX_TXX5
PEX_TXX6
PEX_TXX6
PEX_TXX7
PEX_TXX7
PEX_TXX8
PEX_TXX8
PEX_TXX9
PEX_TXX9
PEX_TXX10
PEX_TXX10
PEX_TXX11
PEX_TXX11
PEX_TXX12
PEX_TXX12
PEX_TXX13
PEX_TXX13
PEX_TXX14
PEX_TXX14
PEX_TXX15
PEX_TXX15
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
NV_SOURCE_POWER_NET
NV_SOURCE_POWER_NET
NV_CRITICALNV_IMPEDANCEDIFFPAIRNET
100DIFF
100DIFF 1
100DIFF 1
100DIFF 1
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
100DIFF
VOLTAGEMIN_LINE_WIDTH
10MIL
10MIL
12MIL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100DIFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.2V
1.2V
1.2V
3.3V
12V35MIL
0V
3A
5.5A
GND
600-10402-0000-200 H
p402
broth
2 OF 21
03-APR-2007
BIBIOUT
OUT
OUT
OUT
OUT
BI
2/14 FBA
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD2
FBA_CMD3
FBVDDQ
FBA_CMD1
FBA_CMD4
FBA_CMD5
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD11
FBA_CMD13
FBA_CMD15
FBA_CMD16
FBA_CMD19
FBA_CMD21
FBA_CMD22
FBA_CMD24
FBA_CMD25
FBA_CMD20
FBA_CMD17
FBA_CMD14
FBA_CMD10
FBA_CMD6
FBA_CMD12
FBA_CMD18
FBA_CMD23
FBA_CMD26
FBA_DEBUG
FBA_CLK0
FBA_PLLAVDD
H_PLLAVDD
FBA_CLK1
FBA_CLK1
FBA_CLK0
FBA_CMD28
FBA_CMD27
NC1
NC2
FBA_PLLGND
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD44
FBAD47
FBAD49
FBAD51
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD45
FBAD46
FBAD48
FBAD50
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN7
FBADQS_RN6
FBADQS_RN5
FB_VREF1
OUTBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
Rtop
Rbot
FBVDDQ
590
R5611.27K
R562
GND
4<>
4<>
NO STUFF
1%
0402
NO STUFF
1%
0402
4<>
4<>
FBAD<63..0>
FBADQM<7..0>
FBADQS_WP<7..0>
FBADQS_RN<7..0>
C627
.1UF
16V
10%
X7R
0402
COMMON
VREF = FBVDDQ * Rbot/(Rtop + Rbot)
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)DDR3:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBAD<0>
FBAD<1>
FBAD<2>
FBAD<3>
FBAD<4>
FBAD<5>
FBAD<6>
FBAD<7>
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30> E28
FBAD<31>
FBAD<32>
FBAD<33>
FBAD<34>
FBAD<35>
FBAD<36>
FBAD<37>
FBAD<38>
FBAD<39>
FBAD<40> AM30
FBAD<41>
FBAD<42>
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBAD<48>
FBAD<49>
FBAD<50>
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<0>
FBADQM<1>
FBADQM<2>
FBADQM<3>
FBADQM<4>
FBADQM<5>
FBADQM<6>
FBADQM<7>
FBADQS_WP<0>
FBADQS_WP<1>
FBADQS_WP<2>
FBADQS_WP<3>
FBADQS_WP<4>
FBADQS_WP<5>
FBADQS_WP<6>
FBADQS_WP<7>
FBADQS_RN<0>
FBADQS_RN<1>
FBADQS_RN<2>
FBADQS_RN<3>
FBADQS_RN<4>
FBADQS_RN<5>
FBADQS_RN<6>
FBADQS_RN<7>
U_GPU_G3_128_8X_BGA820-G84-300B
G1
G84-300-A1
BGA820
COMMON
N27
M27
N28
L29
K27
K28
J29
J28
P30
N31
N30
N32
L31
L30
J30
L32
H30
K30
H31
F30
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29FBAD<60>
AD27
AF27
AE28
M29
M30
G30
F29
AA29
AK30
AC30
AG30
L28
K31
G32
G28
AB28
AL32
AF32
AH30
M28
K32
G31
G27
AA28
AL31
AF31
AH29
E32FBA_VREF
A12
A18
A21
A24
A27
A3
A30
A6
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32
AA25
AA26
AB25
AB26
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
M26
R25
R26
V25
V26
P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32
Y30
V32
P28
R28
Y27
AA27
AC27
G23
FBA_CMD<0>
FBA_CMD<1>
FBA_CMD<2>
FBA_CMD<3>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
FBA_CMD<7>
FBA_CMD<8>
FBA_CMD<9>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<12>
FBA_CMD<13>
SNN_FBA_CMD<14>
FBA_CMD<15>
FBA_CMD<16>
FBA_CMD<17>
FBA_CMD<18>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<21>
FBA_CMD<22>
FBA_CMD<23>
FBA_CMD<24>
FBA_CMD<25>
SNN_FBA_CMD<26>
SNN_FBA_CMD<27>
SNN_FBA_CMD<28>
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
LTP_FBA_DEBUG
PLLAVDD
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
NO STUFF
TP505
FBA_CMD<26..0>
G25
G24
GND
SNN_GPU_NC1
D31
SNN_GPU_NC2
D32
C645
.47UF
6.3V
10%
X5R
0402
COMMON
C697
.1UF
16V
10%
X7R
0402
COMMON
C687
.1UF
16V
10%
X7R
0402
COMMON
C684
.47UF
6.3V
10%
X5R
0402
COMMON
C659
.1UF
16V
10%
X7R
0402
COMMON
C725
.47UF
6.3V
10%
X5R
0402
COMMON
C749
.1UF
16V
10%
X7R
0402
COMMON
C642
1UF
6.3V
10%
X7R
0603
COMMON
C661
.47UF
6.3V
10%
X5R
0402
COMMON
C675
.1UF
16V
10%
X7R
0402
COMMON
PLACE BELOW GPU
4< 4<>
4<
4<
4<
4<
PLACE close to balls
C671
.01UF
16V
10%
X7R
0402
COMMON
C670
.1UF
16V
10%
X7R
0402
COMMON
C654
.1UF
16V
10%
X7R
0402
COMMON
GND
C716
.1UF
16V
10%
X7R
0402
COMMON
C691
.1UF
16V
10%
X7R
0402
COMMON
C757
.1UF
16V
10%
X7R
0402
COMMON
C680
.1UF
16V
10%
X7R
0402
COMMON
FBVDDQ
NET
PLLAVDD
FBA_PLLAVDD_R
MIN_LINE_WIDTH
10MIL
10MIL
GND
C707
C662
1UF
.1UF
6.3V
16V
10%
X7R
0402
COMMON
C692
.47UF
6.3V
10%
X5R
0402
COMMON
10%
X7R
0603
COMMON
C646
.47UF
6.3V
10%
X5R
0402
COMMON
GND
GND
GND
PEX1V2
240R@100MHz
LB502
C669
1UF
6.3V
10%
X5R
0603
COMMON
GND
COMMONBEAD_0402
FBVDDQ
C601
10UF
6.3V
20%
X5R
0805
COMMON
C602
10UF
6.3V
20%
X5R
0805
COMMON
C607
10UF
6.3V
20%
X5R
0805
COMMON
PLACE MIDWAY BETWEEN GPU AND MEMORY
GND
C840
10UF
6.3V
20%
X5R
0805
COMMON
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
FBA MEMORY INTERFACE, GPU FBVDD/Q DECOUPLING CAPS
www.vinafix.vn
600-10402-0000-200 H
p402
broth
3 OF 21
03-APR-2007
ININININBIBIBIBIBIBIBIBIBI
IN
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
FrameBuffer: Partition A 8Mx32 BGA136 DDR3
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
A-CS0-LOW-32bit
M3
GDDR3_16MX32
GND
H11
K10
K11
H10
J11
J10
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
L4
G4
G9
H4
J2
J3
V4
V9
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
3> 4< 4<>
3> 4<
3> 4<
FBA_CMD<26..0>
Low Sub-Partition
FBA_CLK0
FBA_CLK0*
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
FBA_CMD<1>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<8>
CS0
FBA_CMD<19>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<24>
FBA_CMD<0>
FBA_CMD<2>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<23>
FBA_CMD<20>
FBA_CMD<17>
FBA_CMD<9>
FBA_CMD<12>
FBA_CMD<3>
FBA_CMD<7>
FBA_CMD<18>
FBA_CMD<15>
SNN_FBA0_NC1
SNN_FBA0_NC2
A9
A4
FBA_ZQ0
R547
R552
10K
ZQ = 6x desired output
DDR3:
Impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
DDR3: CKE DETERMINES THE ODT VALUE FOR CMD PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
FBVDDQ
10K
5%
5%
0402
0402
COMMON
COMMON
GND
C525
.047UF
16V
10%
X7R
0402
COMMON
GND
3<>
4<>
3>
4<>
3<>
4<>
3<>
4<>
GND
C598
.047UF
16V
10%
X7R
0402
COMMON
FBAD<63..0>
FBADQM<7..0>
FBADQS_RN<7..0>
FBADQS_WP<7..0>
R550
243
1%
0402
COMMON
K12
J12
K1
J1
DDR3:
FBADQM<0>
0
FBADQM<1>
1
FBADQM<2>
2
FBADQM<3>
3
FBADQM<4>
4
FBADQM<5>
5
FBADQM<6>
6
FBADQM<7>
7
FBADQS_RN<0>
0
FBADQS_RN<1>
1
FBADQS_RN<2>
2
FBADQS_RN<3>
3
FBADQS_RN<4>
4
FBADQS_RN<5>
5
FBADQS_RN<6>
6
FBADQS_RN<7>
7
FBADQS_WP<0>
0
FBADQS_WP<1>
1
FBADQS_WP<2>
2
FBADQS_WP<3>
3
FBADQS_WP<4>
4
FBADQS_WP<5>
5
FBADQS_WP<6>
6
FBADQS_WP<7>
7
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4K2
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.3K/(511 + 1.3K)
FBA Partition
136BGA CMD Mapping
CMD
CMD1
CMD10
CMD11
CMD18
CMD15
CMD8
CMD19
CMD25
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD12
CMD3
CMD7
GND
FBA_VREF0
FBA_VREF1H12
1.4V = 2.0V * 1.3K/(511 + 1.3K)
FBAD<0>
0
FBAD<1>
1
FBAD<2>
2
FBAD<3>
3
FBAD<4>
4
FBAD<5>
5
FBAD<6>
6
FBAD<7>
7
FBADQM<0>
FBADQS_RN<0>
FBADQS_WP<0>
FBAD<32>
32
FBAD<33>
33
FBAD<34>
34
FBAD<35>
35
FBAD<36>
36
FBAD<37>
37
FBAD<38>
38
FBAD<39>
39
FBADQM<4>
FBADQS_RN<4>
FBADQS_WP<4>
ADDR
RAS*
CAS*
WE*
CKE
RESET
CS0*
A<0>
A<1>
A<2>
Low Sub-Partition
A<3>
A<4>
A<5>
A<2>
Hi Sub-Partition
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10
A<11>
BA0
BA1
BA2
FBVDDQ
R556
590
R1
1%
0402
COMMON
R557
1.27K
R2
1%
0402
COMMON
GND
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M3
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R11
T11
R10
T10
N11
M11
L10
M10
N10
P10
P11
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M4
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
L3
M2
M3
N2
T3
R2
T2
R3
N3
P3
P2
C597
.1UF
16V
10%
X7R
0402
COMMON
R34
590
0402
COMMON
R35
1.27K
0402
COMMON
8
9
10
11
12
13
14
15
40
41
42
43
44
45
46
47
1%
FBA_CMD<26..0>
3> 4< 4<>
Hi Sub-Partition
3> 4<
3> 4<
FBVDDQ
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
FBVDDQ
C599
.047UF
R1
C51
.1UF
R2
16V1%
10%
X7R
0402
COMMON
GND
FBAD<8>
FBAD<9>
FBAD<10>
FBAD<11>
FBAD<12>
FBAD<13>
FBAD<14>
FBAD<15>
FBADQM<1>
FBADQS_RN<1>
FBADQS_WP<1>
FBAD<40>
FBAD<41>
FBAD<42> F10
FBAD<43>
FBAD<44>
FBAD<45>
FBAD<46>
FBAD<47>
FBADQM<5>
FBADQS_RN<5>
FBADQS_WP<5>
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M3
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
T3
R2
R3
T2
M2
N2
L3
M3
N3
P3
P2
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M4
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B10
G10
E11
F11
C10
C11
B11
E10
D10
D11
16V
10%
X7R
0402
COMMON
GND
16
17
18
19
20
21
22
23
48
49
50
51
52
53
54
55
FBA_CMD<7>
7
FBA_CMD<8>
CS0
8
FBA_CMD<18>
18
FBA_CMD<10>
10
FBA_CMD<5>
5
FBA_CMD<13>
13
FBA_CMD<21>
21
FBA_CMD<20>
20
FBA_CMD<19>
19
FBA_CMD<25>
25
FBA_CMD<4>
4
FBA_CMD<9>
9
FBA_CMD<17>
17
FBA_CMD<6>
6
FBA_CMD<23>
23
FBA_CMD<16>
16
FBA_CMD<3>
3
FBA_CMD<12>
12
FBA_CMD<1>
1
FBA_CMD<11>
11
FBA_CLK1
FBA_CLK1*
SNN_FBA1_NC1
SNN_FBA1_NC2
FBA_CMD<15>
15
FBA_ZQ1
R543
243
1%
0402
COMMON
GND
C52
.047UF
16V
10%
X7R
0402
COMMON
FBAD<16>
FBAD<17>
FBAD<18>
FBAD<19>
FBAD<20>
FBAD<21>
FBAD<22>
FBAD<23>
FBADQM<2>
FBADQS_RN<2>
FBADQS_WP<2>
FBAD<48>
FBAD<49>
FBAD<50> R11
FBAD<51>
FBAD<52>
FBAD<53>
FBAD<54>
FBAD<55>
FBADQM<6>
FBADQS_RN<6>
FBADQS_WP<6>
B2
E2
C2
B3
C3
F3
G3
F2
E3
D3
D2
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
A-CS0-HI-32bit
M4
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
K1
K12
J1
J12
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M3
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M4
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
R10
M11
T11
N11
T10
M10
L10
N10
P10
P11
24
25
26
27
28
29
30
31
56
57
58
59
60
61
62
63
FBAD<24>
FBAD<25>
FBAD<26>
FBAD<27>
FBAD<28>
FBAD<29>
FBAD<30>
FBAD<31>
FBADQM<3>
FBADQS_RN<3>
FBADQS_WP<3>
FBAD<56>
FBAD<57>
FBAD<58>
FBAD<59>
FBAD<60>
FBAD<61>
FBAD<62>
FBAD<63>
FBADQM<7>
FBADQS_RN<7>
FBADQS_WP<7>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
GND
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBA_VREF2
H1
FBA_VREF3
H12
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M3
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
F11
F10
B11
B10
C11
E11
G10
C10
E10
D10
D11
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M4
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B3
F3
C2
C3
F2
E2
B2
G3
E3
D3
D2
R37
590
0402
COMMON
R36
1.27K
0402
COMMON
4<> 3> 4<
FBVDDQ
1%
1%
GND
R1
R2
4<>
4<>
4< 3>
4<> 3<>
4< 3>
3<>
3>
3<> 4<>
C53
.1UF
16V
10%
X7R
0402
COMMON
3> 4<
3> 4<
3> 4<
FBA_CMD<26:0>
FBA_VREF0
FBA_VREF1
FBA_VREF2
FBA_VREF3
FBADQS_WP<7:0>
R559
590
1%
0402
COMMON
R558
1.27K
1%
0402
COMMON
FBA_CMD<26..0>
DIFFPAIRNET
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBAD<63..0>
FBADQM<7..0>
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
NV_IMPEDANCE
40OHM 1
FBADQS_RN<7:0>
FBVDDQ
R1
C595
.1UF
R2
16V
10%
X7R
0402
COMMON
Termination for Sub-Partition and CLK
GND
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBA_CMD<2>
2
0
24
22
13
4
5
6
FBA_CMD<0>
FBA_CMD<24>
FBA_CMD<22>
FBA_CMD<13>
FBA_CMD<4>
FBA_CMD<5>
FBA_CMD<6>
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
121
COMMON
121
121
COMMON
121
COMMON
R539
0402
5%
R545
0402
5%
R551
0402
5%
R546
0402
5%
R542
0402
5%
R548
0402
5%
R544
0402
5%
R549
0402
5%
R540
0402
1%
R541
0402COMMON
1%
R555
0402
1%
R553
0402
1%
NV_IMPEDANCE
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
12MIL
DIFFPAIR
FBVDDQ
FBA_CLK0_PU
FBA_CLK1_PU
NV_CRITICAL_NET
1
1
1
1
1
1
1
NV_CRITICAL_NET
140OHM
FBVDDQ
R538
80.6
1%
0402
NO STUFF
C_0402-01UFX7R1063VNAB
C527
.01UF
6.3V
10%
X7R
0402
COMMON COMMON
GND
R554
80.6
1%
0402
NO STUFF
C_0402-01UFX7R1063VNAB
C573
.01UF
6.3V
10%
X7R
0402
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
FBA 8Mx32 DDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA CLK TERMS
www.vinafix.vn
600-10402-0000-200 H
p402
broth
4 OF 21
03-APR-2007
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
FRAME BUFFER: PARTITION A DECOUPLING
Decoupling for FBA 0..31
PLACE NEAR MEMORY FBVDDQ PINS
Decoupling for FBA 32..63
FBVDDQ
PLACE NEAR MEMORY FBVDD PINS
FBVDDQ
C548
.1UF
16V
10%
X7R
0402
COMMON
C543C529
.1UF
16V
10%
X7R
0402
COMMON
C582
.47UF
6.3V
10%
X5R
0402
COMMON
C565
.1UF
16V
10%
X7R
0402
COMMON
C584
.01UF
25V
10%
X7R
0402
COMMON
C558
.01UF
25V
10%
X7R
0402
COMMON
.1UF
16V
10%
X7R
0402
COMMON
C589
C557
.01UF
.01UF
16V
25V
10%10%
X7R
X7R
0402
0402
COMMON COMMON
C586
C585
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON COMMON
C572
C542
.1UF
.01UF
16V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C534
C571
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
.1UF
16V
10%
X7R
0402
COMMON
C577
.1UF
16V
10%
X7R
0402
COMMON
C549
.1UF
16V
10%
X7R
0402
COMMON
C568
.01UF
25V
10%
X7R
0402
COMMON
.1UF
16V
10%
X7R
0402
COMMON
C587C566 C556
.47UF
6.3V
10%
X5R
0402
COMMON
C560
.01UF
25V
10%
X7R
0402
COMMON
C567
.01UF
25V
10%
X7R
0402
COMMON
C583
.01UF
25V
10%
X7R
0402
COMMON
C530
.01UF
25V
10%
X7R
0402
COMMON
C588
.01UF
25V
10%
X7R
0402
COMMON
C532
.01UF
25V
10%
X7R
0402
COMMON
C533
.01UF
25V
10%
X7R
0402
COMMON
C531
.01UF
25V
10%
X7R
0402
COMMON
C559
.01UF
25V
10%
X7R
0402
COMMON
C570 C553C541
.01UF
25V
10%
X7R
0402
COMMON
C552
.01UF
25V
10% 10%
X7R
0402
COMMON
C574
.1UF
16V
10%
X7R
0402
COMMON
C539
.01UF
25V
10%
X7R
0402
COMMON
C564
.01UF
25V
10%
X7R
0402
COMMON
.01UF
25V
10%
X7R
0402
COMMON
C569
.01UF
25V
X7R
0402
COMMON
C546
.1UF
16V
10%
X7R
0402
COMMON
C544
.1UF
16V
10%
X7R
0402
COMMON
C593
.01UF
25V
10%
X7R
0402
COMMON
.01UF
25V
10%
X7R
0402
COMMON
C592
.01UF
25V
10%
X7R
0402
COMMON
C594
.01UF
25V
10%
X7R
0402
COMMON
C551
.47UF
6.3V
10%
X5R
0402
COMMON
C580
.01UF
25V
10%
X7R
0402
COMMON
C537
.1UF
16V
10%
X7R
0402
COMMON
C578
.1UF
16V
10%
X7R
0402
COMMON
C536
.01UF
25V
10%
X7R
0402
COMMON
C563
.01UF
25V
10%
X7R
0402
COMMON
C562
.01UF
25V
10%
X7R
0402
COMMON
.01UF
16V
10%
X7R
0402
COMMON
C590
.01UF
25V
10%
X7R
0402
COMMON
C561
.01UF
25V
10%
X7R
0402
COMMON
C538
.01UF
25V
10%
X7R
0402
COMMON
C554
.01UF
25V
10%
X7R
0402
COMMON
C591C535
.01UF
25V
10%
X7R
0402
COMMON
C579
.01UF
25V
10%
X7R
0402
COMMON
C555
.01UF
25V
10%
X7R
0402
COMMON
C581
.01UF
25V
10%
X7R
0402
COMMON
C540
.01UF
25V
10%
X7R
0402
COMMON
FBVDDQ
C547
4.7UF
6.3V
10%
X5R
0603
COMMON
C576
4.7UF
6.3V
10%
X5R
0603
COMMON
C550
1UF
6.3V
10%
X7R
0603
COMMON
C596
1UF
6.3V
10%
X7R
0603
COMMON
GND
GND
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
FBA MEMORY FBVDD/Q DECOUPLING CAPS
www.vinafix.vn
FBVDDQ
C575
4.7UF
6.3V
10%
X5R
0603
COMMON
C545
4.7UF
6.3V
10%
X5R
0603
COMMON
C528
1UF
6.3V
10%
X7R
0603
COMMON
GND
C600
1UF
6.3V
10%
X7R
0603
COMMON
GND
600-10402-0000-200 H
p402
broth
5 OF 21
03-APR-2007
BIBIBI
OUT
OUT
OUT
OUT
OUT
BI
3/14 FBC
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBC_CMD0
FBC_CMD4
FBC_CMD3
FBC_CMD2
FBC_CMD1
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_PLLAVDD
FBC_PLLVDD
FBC_DEBUG
FBC_CLK1
FBC_CLK1
FBC_CLK0
FBC_CLK0
FBC_CMD28
FBC_CMD27
FBCAL_TERM_GND
FBCAL_PU_GND
FBCAL_PD_VDDQ
FBC_PLLGND
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN7
FBCDQS_RN6
FBCDQS_RN5
FB_VREF2
OUTBIBI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
CB
2
1
A
5
4
3
HFD GEBA C
7<>
7<>
7<>
7<>
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_WP<7..0>
FBCDQS_RN<7..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
FBCDQS_WP<1>
1
FBCDQS_WP<2>
2
FBCDQS_WP<3>
3
FBCDQS_WP<4> A29
4
FBCDQS_WP<5>
5
FBCDQS_WP<6>
6
FBCDQS_WP<7>
7
FBCDQS_RN<0>
0
FBCDQS_RN<1>
1
FBCDQS_RN<2>
2
FBCDQS_RN<3>
3
FBCDQS_RN<4>
4
FBCDQS_RN<5>
5
FBCDQS_RN<6>
6
FBCDQS_RN<7>
7
SNN_FBC_VREF_A28
FBCD<0>
FBCD<1>
FBCD<2>
FBCD<3>
FBCD<4>
FBCD<5>
FBCD<6>
FBCD<7>
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<24>
FBCD<25>
FBCD<26>
FBCD<27>
FBCD<28>
FBCD<29>
FBCD<30>
FBCD<31>
FBCD<32>
FBCD<33>
FBCD<34>
FBCD<35>
FBCD<36>
FBCD<37>
FBCD<38>
FBCD<39> A31
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBCD<56>
FBCD<57>
FBCD<58>
FBCD<59>
FBCD<60>
FBCD<61>
FBCD<62>
FBCD<63>
FBCDQM<0>
FBCDQM<1>
FBCDQM<2>
FBCDQM<3>
FBCDQM<4>
FBCDQM<5>
FBCDQM<6>
FBCDQM<7>
U_GPU_G3_128_8X_BGA820-G84-300B
G1
G84-300-A1
BGA820
COMMON
B7
A7
C7
A2
B2
C4
A5
B5
F9
F10
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
D3
E4
C3
B4
C10
B10
C8
A10
C11
C12
A11
B11
B28
C27
C26
B26
C30
B31
C29
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C25
C23
A22
C22
C21
B22
E22
D22
D21
E21
E18
D19
D18
E19
A4
E11
F5
C9
C28
F24
C24
E20
C5FBCDQS_WP<0>
E10
E5
B8
D25
B25
F20
C6
E9
E6
A8
B29
E25
A25
F21
A28
3
AA23
AB23
H16
H17
J10
J23
J24
J9
K11
K12
K21
K22
K24
K9
L23
M23
T25
U25
C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20
C20
E13
F13
F18
E17
F12
G8
SNN_FBVTT_AA23
SNN_FBVTT_AB23
SNN_FBVTT_H16
SNN_FBVTT_H17
SNN_FBVTT_J10
SNN_FBVTT_J23
SNN_FBVTT_J24
SNN_FBVTT_J9
SNN_FBVTT_K11
SNN_FBVTT_K12
SNN_FBVTT_K21
SNN_FBVTT_K22
SNN_FBVTT_K24
SNN_FBVTT_K9
SNN_FBVTT_L23
SNN_FBVTT_M23
SNN_FBVTT_T25
SNN_FBVTT_U25
FBC_CMD<0>
FBC_CMD<1>
FBC_CMD<2>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<5>
FBC_CMD<6>
FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<12>
FBC_CMD<13>
SNN_FBC_CMD<14>
FBC_CMD<15>
FBC_CMD<16>
FBC_CMD<17>
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<21>
FBC_CMD<22>
FBC_CMD<23>
FBC_CMD<24>
FBC_CMD<25>
SNN_FBC_CMD<26>
SNN_FBC_CMD<27>
SNN_FBC_CMD<28>A15
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
LTP_FBC_DEBUG
SNN_FBC_PLLVDD_G8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
G10
G9
GND
FBCAL_PD
K26
H26
J26
FBCAL_PU
FBCAL_TERM
R573
0402
R575
0402
R572
0402
FBC_CMD<26..0>
7<
7<
7<
7<
TP3
NO STUFF
7<
FBC_PLLAVDD
FBVDDQ
43.2
COMMON
1%
40.2
COMMON
1%
40.2
COMMON
1%
GND
Place close to balls
.01UF .1UF 1UF
16V
10%
X7R
COMMON
16V
10%
X7R
04020402
C741C742C743
6.3V
10%
X5R
0402
COMMONCOMMON
L_BEAD_0402-240R100MHZFERRITB
240R@100MHz
LB504
COMMON
BEAD_0402
GND
C746
4.7UF
6.3V
10%
X5R
0603
COMMON
PEX1V2
FBC_PLLVDD
FBC_PLLAVDD
FBC_PLLAVDD_R
MIN_LINE_WIDTHNET
10MIL
10MIL
10MIL
www.vinafix.vn
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
FBC MEMORY INTERFACE, GPU FBVTT
600-10402-0000-200 H
p402
broth
6 OF 21
03-APR-2007
ININININBIBIINBIBIBIBIBIBI
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
IN
IN
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
WDQS
RDQS
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQM
DQ7
DQ6
INININ
MIRROR
*CS1 is required 32Mx32 Memories
NONMIRROR
VDD
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSS
VREF
VREF
VSS
CKE
BA2
CAS
WE
CS0
RAS
BA0
BA1
A7
A8/AP
A3
A10
A11
A2
A1
A0
A9
A6
A5
A4
NC/CS1
RAS
CAS
CS0
A0
WE
A5
A4
A3
A2
A1
A8/AP
A10
A11
BA0
BA1
A7
A6
A9
BA2
NC/CS1
CKE
CLK
CLK
NC/RFU
SEN (GND)
MIRROR
RESET
ZQ
VDDA
VDDA
VSSA
VSSA
BIBIBI
BI
2
3
4
5
1
HGF
DATE
PAGE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
NAME
ID
NV_PN
D E
PAGE DETAIL
ASSEMBLY
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
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CB
2
1
A
5
4
3
HFD GEBA C
FRAMEBUFFER: PARTITION C 8Mx32 BGA136 DDR3
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
A-CS0-LOW-32bit
M1
GDDR3_16MX32
PACK_TYPE=BGA136
H11
K10
K11
H10
J11
J10
GND
H3
F4
H9
F9
K4
H2
K3
M4
K9
L9
M9
L4
G4
G9
H4
J2
J3
V4
V9FBC_CMD<15>
VERSION=BGA136
COMMON
7< 6>
FBC_CMD<26..0>
Low Sub-Partition
6>
7<
6>
7<
1
10
11
8
19
25
22
24
0
2
21
16
23
20
17
9
12
3
7
18
15
CS0
FBC_CMD<22>
FBC_CMD<24>
FBC_CMD<0>
FBC_CMD<2>
FBC_CMD<18>
FBC_CLK0
FBC_CLK0*
SNN_FBC0_NC1
SNN_FBC0_NC2
FBC_CMD<1>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<8>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<23>
FBC_CMD<20>
FBC_CMD<17>
FBC_CMD<9>
FBC_CMD<12>
FBC_CMD<3>
FBC_CMD<7>
A9
R577
FBC_ZQ0
R615
243
1%
0402
COMMON
GND
C792
.047UF
16V
10%
X7R
0402
COMMON
FBCD<63..0>
FBCDQM<7..0>
FBCDQS_RN<7..0>
FBCDQS_WP<7..0>
K12
J12
A4
K1
J1
FBCDQM<0>
0
FBCDQM<1>
1
FBCDQM<2>
2
FBCDQM<3>
3
FBCDQM<4>
4
FBCDQM<5>
5
FBCDQM<6>
6
FBCDQM<7>
7
FBCDQS_RN<0>
0
FBCDQS_RN<1>
1
FBCDQS_RN<2>
2
FBCDQS_RN<3>
3
FBCDQS_RN<4>
4
FBCDQS_RN<5>
5
FBCDQS_RN<6>
6
FBCDQS_RN<7>
7
FBCDQS_WP<0>
0
FBCDQS_WP<1>
1
FBCDQS_WP<2>
2
FBCDQS_WP<3>
3
FBCDQS_WP<4>
4
FBCDQS_WP<5>
5
FBCDQS_WP<6>
6
FBCDQS_WP<7>
7
ZQ = 6x desired output
DDR3:
Impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
DDR3: CKE DETERMINES THE ODT VALUE FOR CMD PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
FBVDDQ
GND
C789
.047UF
16V
10%
X7R
0402
COMMON
7<>
7<>
7<>
7<>
R578
10K
5%
0402
COMMON
6<>
6>
6<>
6<>
10K
5%
0402
COMMON
GND
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4K2
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
H1
H12
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
GND
FBC_VREF0
FBC_VREF1
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
FBCD<0>
0
FBCD<1>
1
FBCD<2>
2
FBCD<3>
3
FBCD<4>
4
FBCD<5>
5
FBCD<6>
6
FBCD<7>
7
FBCDQM<0>
FBCDQS_RN<0>
FBCDQS_WP<0>
FBCD<32>
32
FBCD<33>
33
FBCD<34>
34
FBCD<35>
35
FBCD<36>
36
FBCD<37>
37
FBCD<38>
38
FBCD<39>
39
FBCDQM<4>
FBCDQS_RN<4>
FBCDQS_WP<4>
FBA Partition
136BGA CMD Mapping
ADDR
CMD
RAS*
CMD1
CAS*
CMD10
WE*
CMD11
CKE
CMD18
RESET
CMD15
CS0*
CMD8
A<0>
CMD19
A<1>
CMD25
A<2>
CMD22
CMD24
CMD0
CMD2
CMD4
CMD6
CMD5
CMD13
CMD21
CMD16
CMD23
CMD20
CMD17
CMD9
CMD12
CMD3
CMD7
FBVDDQ
R605
590
1%
R1
0402
COMMON
R601
R2
1.27K
1%
0402
COMMON
GND
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M1
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B2
C2
E2
F2
G3
F3
C3
B3
E3
D3
D2
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M2
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E11
F11
F10
G10
B11
C10
C11
B10
E10
D10
D11
A<4>
A<5>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10
A<11>
BA0
BA1
BA2
Low Sub-PartitionA<3>
Hi Sub-Partition
C798
.1UF
16V
10%
X7R
0402
COMMON
FBC_CMD<26..0>
Hi Sub-Partition
6>
7<
6>
7<
FBVDDQ
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
FBVDDQ
FBVDDQ
R29
590
1%
0402
R1
COMMON
R2
FBCD<8>
FBCD<9>
FBCD<10>
FBCD<11>
FBCD<12>
FBCD<13>
FBCD<14>
FBCD<15>
FBCD<40>
FBCD<41>
FBCD<42>
FBCD<43>
FBCD<44>
FBCD<45>
FBCD<46>
FBCD<47>
C39
.1UF
16V
10%
X7R
0402
COMMON
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M1
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M11
T10
R11
N11
T11
R10
L10
M10
N10FBCDQM<1>
P10
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M2
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
E2
B2
B3
F3
F2
C3
C2
G3
E3
D3
D2
R30
1.27K
1%
0402
COMMON
GND
8
9
10
11
12
13
14
15
FBCDQS_RN<1>
FBCDQS_WP<1> P11
40
41
42
43
44
45
46
47
FBCDQM<5>
FBCDQS_RN<5>
FBCDQS_WP<5>
7
8
18
10
5
13
21
20
19
25
4
9
17
6
23
16
3
12
1
11
15
C634
.047UF
16V
10%
X7R
0402
COMMON
GND
16
17
18
19
20
21
22
23
FBCDQM<2>
FBCDQS_RN<2>
FBCDQS_WP<2>
48
49
50
51
52
53
54
55
FBCDQM<6>
FBCDQS_RN<6>
FBCDQS_WP<6>
CS0
FBC_CMD<5>
FBC_CMD<13>
FBC_CMD<4>
FBC_CMD<6>
FBCD<16>
FBCD<17>
FBCD<18>
FBCD<19>
FBCD<20>
FBCD<21>
FBCD<22>
FBCD<23>
FBCD<48>
FBCD<49>
FBCD<50>
FBCD<51>
FBCD<52>
FBCD<53>
FBCD<54>
FBCD<55>
FBC_CMD<7>
FBC_CMD<8>
FBC_CMD<18>
FBC_CMD<10>
FBC_CMD<21>
FBC_CMD<20>
FBC_CMD<19>
FBC_CMD<25>
FBC_CMD<9>
FBC_CMD<17>
FBC_CMD<23>
FBC_CMD<16>
FBC_CMD<3>
FBC_CMD<12>
FBC_CMD<1>
FBC_CMD<11>
FBC_CLK1
FBC_CLK1*
SNN_FBC1_NC1
SNN_FBC1_NC2
FBC_CMD<15>
FBC_ZQ1
R560
243
1%
0402
COMMON
GND
C40
.047UF
16V
10%
X7R
0402
COMMON
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M1
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
B10
G10
F11
F10
C11
E11
B11
C10
E10
D10
D11
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M2
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
T10
T11
M11
R11
N11
R10
L10
M10
N10
P10
P11
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
A-CS0-HI-32bit
M2
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
H3
F4
H9
F9
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
H10
H4
J11
J10
J2
J3
V4
GND
V9
A9
A4
K1
K12
J1
J12
FBCD<24>
24
FBCD<25>
25
FBCD<26>
26
FBCD<27>
27
FBCD<28>
28
FBCD<29>
29
FBCD<30>
30
FBCD<31>
31
FBCDQM<3>
FBCDQS_RN<3>
FBCDQS_WP<3>
FBCD<56>
56
FBCD<57>
57
FBCD<58>
58
FBCD<59>
59
FBCD<60>
60
FBCD<61>
61
FBCD<62>
62
FBCD<63>
63
FBCDQM<7>
FBCDQS_RN<7>
FBCDQS_WP<7>
FBVDDQ
F1
M1
A2
V2
A11
V11
F12
M12
A1
C1
E1
N1
R1
V1
C4
E4
J4
N4
R4
C9
E9
J9
N9
R9
A12
C12
E12
N12
R12
V12
B1
D1
P1
T1
G2
GND
L2
B4
D4
P4
T4
B9
D9
P9
T9
G11
L11
B12
D12
P12
T12
G1
L1
A3
V3
A10
V10
G12
L12
FBC_VREF2
H1
FBC_VREF3
H12
VREF = FBVDDQ * R2/(R1 + R2)
VREF = 0.70 * FBVDDQDDR3:
1.26V = 1.8V * 1.3K/(511 + 1.3K)
1.4V = 2.0V * 1.3K/(511 + 1.3K)
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M1
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
M2
N2
L3
M3
R2
R3
T2
T3
N3
P3
P2
U_MEM_SD_DDR3_X32_BGA136-GDDR3B
M2
GDDR3_16MX32
PACK_TYPE=BGA136
VERSION=BGA136
COMMON
N2
M2
L3
M3
R2
R3
T2
T3
N3
P3
P2
R33
590
0402
COMMON
R32
1.27K
0402
COMMON
FBVDDQ
1%
1%
6<>
7<>
6>
7<>
7<>
7<>
R1
R2
GND
FBC_CMD<26..0>
6> 7<
6> 7<
6> 7<
6> 7<
6> 7<
6<>
6<>
C41
.1UF
16V
10%
X7R
0402
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
120
COMMON
121
COMMON
121
COMMON
121
COMMON
121
COMMON
C629
.1UF
16V
10%
X7R
0402
COMMON
5%
5%
5%
5%
5%
5%
5%
5%
1%
1%
1%
1%
DIFFPAIR
R599
0402
R597
0402
R590
0402
R594
0402
R565
0402
R566
0402
R567
0402
R568
0402
R600
0402
R596
0402
R570
0402
R569
0402
NET
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBCD<63..0>
FBCDQM<7..0>
FBC_CMD<26..0>
FBC_VREF0
FBC_VREF1
FBC_VREF2
FBC_VREF3
FBCDQS_WP<7:0>
FBCDQS_RN<7:0>
FBVDDQ
R564
590
1%
R1
0402
COMMON
R563
1.27K
1%
R2
0402
COMMON
GND
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY pin!!
Minimize the stub length!!
FBC_CMD<2>
2
FBC_CMD<0>
0
FBC_CMD<24>
24
FBC_CMD<22>
22
FBC_CMD<13>
13
FBC_CMD<4>
4
FBC_CMD<5>
5
FBC_CMD<6>
6
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
80DIFF
80DIFF
80DIFF
80DIFF
40OHM
40OHM
40OHM
MIN_LINE_WIDTH
12MIL
12MIL
12MIL
12MIL
DIFFPAIRNV_IMPEDANCE NV_CRITICAL_NET
40OHM 1
40OHM
FBVDDQ
G73 - STUFF 0.01uf CAPS
NV43 - STUFF 0 OHM PUs
R598
80.6
1%
0402
NO STUFF
FBC_CLK0_PU
FBC_CLK1_PU
C_0402-01UFX7R1063VNAB
C804
.01UF
6.3V
10%
X7R
0402
COMMON
FBVDDQ
NV_CRITICAL_NETNV_IMPEDANCE
1
1
1
1
1
1
1
1
R571
80.6
1%
0402
NO STUFF
C_0402-01UFX7R1063VNAB
C644
.01UF
6.3V
10%
X7R
0402
COMMON
GND
G84-300, 600/700MHz 256MB 16Mx32 BGA135 GDDR3 DVI+DVI+HDTV-Out
FBC 8MX32 DDR3 MEMORIES, FBC CMD BUS PU'S, FBC CLK TERMS
www.vinafix.vn
600-10402-0000-200 H
p402
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7 OF 21
03-APR-2007
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