ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUS T RY S TA NDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRAN T I ES INCLUDING, WIT H O UT LIMITATI O N, THE WARRANTIES O F D ESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P381: G72/G3-64, 32 BIT DDR2 MEMORY, VGA+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA+SDTV
P381: G72/G3-64, 32 BIT DDR2 MEMORY, DVI+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, DVI+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA+DVI+SDTV
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
ASSEMBLY
PAGE DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P381 Overvie w
EGC
Micro-Star International Co., LTD.
V056-0A
Size Document NumberRev
Custom
Date:
Thursday, D ec ember 15, 2005
1
Sheetof
3
4
5
00A
14
www.vinafix.vn
PEX-Interface
PLACE NEAR FINGERS
3V3
C23
C21
.1UF
10V
10%
X5R
0402
COMMON
C22
.01UF
25V
10%
X7R
0402
COMMON
1UF
1
10V
10%
X5R
0603
COMMON
GND
Net Name
PEX_TSTCLK
IN
PEX_TSTCLK*
IN
PEX_TX0
IN
2
3
4
5
PEX_TX0*
IN
PEX_TX1
IN
PEX_TX1*
IN
PEX_TX2
IN
PEX_TX2*
IN
PEX_TX3
IN
PEX_TX3*
IN
PEX_TX4
IN
PEX_TX4*
IN
PEX_TX5
IN
PEX_TX5*
IN
PEX_TX6
IN
PEX_TX6*
IN
PEX_TX7
IN
PEX_TX7*
IN
PEX_TX8
IN
PEX_TX8*
IN
PEX_TX9
IN
PEX_TX9*
IN
PEX_TX10
IN
PEX_TX10*
IN
PEX_TX11
IN
PEX_TX11*
IN
PEX_TX12
IN
PEX_TX12*
IN
PEX_TX13
IN
PEX_TX13*
IN
PEX_TX14
IN
PEX_TX14*
IN
PEX_TX15
IN
PEX_TX15*
IN
PEX_TXX0
IN
PEX_TXX0*
IN
PEX_TXX1
IN
PEX_TXX1*
IN
PEX_TXX2
IN
PEX_TXX2*
IN
PEX_TXX3
IN
PEX_TXX3*
IN
PEX_TXX4
IN
PEX_TXX4*
IN
PEX_TXX5
IN
PEX_TXX5*
IN
PEX_TXX6
IN
PEX_TXX6*
IN
PEX_TXX7
IN
PEX_TXX7*
IN
PEX_TXX8
IN
PEX_TXX8*
IN
PEX_TXX9
IN
IN
PEX_TXX10
IN
PEX_TXX10*
IN
PEX_TXX11
IN
PEX_TXX11*
IN
PEX_TXX12
IN
PEX_TXX12*
IN
PEX_TXX13
IN
PEX_TXX13*
IN
PEX_TXX14
IN
PEX_TXX14*
IN
PEX_TXX15
IN
PEX_TXX15*
IN
PEX_RX0
IN
PEX_RX0*
IN
PEX_RX1
IN
PEX_RX1*
IN
PEX_RX2
IN
PEX_RX2*
IN
PEX_RX3
IN
PEX_RX3*
IN
PEX_RX4
IN
PEX_RX4*
IN
PEX_RX5
IN
PEX_RX5*
IN
PEX_RX6
IN
PEX_RX6*
IN
PEX_RX7
IN
PEX_RX7*
IN
PEX_RX8
IN
PEX_RX8*
IN
PEX_RX9
IN
PEX_RX9*
IN
PEX_RX10
IN
PEX_RX10*
IN
PEX_RX11
IN
PEX_RX11*
IN
PEX_RX12
IN
PEX_RX12*
IN
PEX_RX13
IN
PEX_RX13*
IN
PEX_RX14
IN
PEX_RX14*
IN
PEX_RX15
IN
PEX_RX15*
IN
PEX_REFCLK
IN
PEX_REFCLK*
IN
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUS T RY S TA NDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRAN T I ES INCLUDING, WIT H O UT LIMITATI O N, THE WARRANTIES O F D ESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUS T RY S TA NDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRAN T I ES INCLUDING, WIT H O UT LIMITATI O N, THE WARRANTIES O F D ESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Frame Buffer Interface
C526
.1UF
10V
10%
X5R
0402
COMMON
C528
C523
.022UF
.1UF
16V
10V
10%
10%
X5R
X7R
0402
0402
COMMON
COMMON
C524
.022UF
16V
10%
X7R
0402
COMMON
NVVDD
GND
EGC
C542
4700PF
25V
10%
X7R
0402
COMMON
C543
4700PF
25V
10%
X7R
0402
COMMON
Rmoved two 0.022uf, and two 0.1uf
FBADQS1
TP5
FBADQSN1
TP6
C538
.1UF
10V
10%
X5R
0402
COMMON
C527
.022UF
16V
10%
X7R
0402
COMMON
C525
.1UF
10V
10%
X5R
0402
COMMON
FBVDDQ
GND
GND
FBA CMD/ADDR TERMINATIONS:
FBVDDQ
150
150
COMMON
COMMONRPAK_PAR_4_2010
150
COMMONRPAK_PAR_4_2010
150
COMMON
150
COMMONRPAK_PAR_4_2010
150
FBVDDQ
FBACMD2
150
FBACMD3
150
COMMON
GND
FBVDDQ
FBACMD6
FBACMD8
GND
FBVDDQ
FBACMD13
FBACMD14
GND
FBACMD17
18
27
RPAK_PAR_4_2010COMMON
FBACMD18
36
RPAK_PAR_4_2010COMMON
45
RPAK_PAR_4_2010
GND
FBACMD0
RP7D 150
45
RPAK_PAR_4_2010COMMON
+/-5%
RP7C
36
RPAK_PAR_4_2010COMMON
+/-5%
FBACMD1
RP3B
27
RPAK_PAR_4_2010
+/-5%
RP3A 150
18
RPAK_PAR_4_2010COMMON
+/-5%
FBACMD4
RP501A
18
RPAK_PAR_4_2010COMMON
+/-5%
RP501B
27
RPAK_PAR_4_2010
+/-5%
FBACMD5
RP10C 150
36
FBACMD9
+/-5%
RP10D
45
RPAK_PAR_4_2010COMMON
+/-5%
RP6A 150
18
+/-5%
RP6B
27
RPAK_PAR_4_2010
+/-5%
RP5B
27
+/-5%
RP5A
18
RPAK_PAR_4_2010COMMON
+/-5%
C533
1UF
6.3V
10%
X5R
0402
COMMON
FBACMD10
GND
FBACMD15
RP6D
150
FBACMD16
45
RPAK_PAR_4_2010COMMON
+/-5%
RP6C
150
36
COMMON
RPAK_PAR_4_2010
+/-5%
RP10B 150
27
RPAK_PAR_4_2010COMMON
+/-5%
RP10A
150
18
RPAK_PAR_4_2010COMMON
+/-5%
C544
1UF
6.3V
10%
X5R
0402
COMMON
FBVDDQ
FBACMD23
FBACMD24
FBACMD19
FBACMD20
RP3D 150
45
RPAK_PAR_4_2010
RP3C 150
36
RP11C
36
RPAK_PAR_4_2010
RP11D
45
RPAK_PAR_4_2010
RP1D
45
RPAK_PAR_4_2010COMMON
+/-5%
RP1C 150
36
RPAK_PAR_4_2010COMMON
+/-5%
RP2B
27
RPAK_PAR_4_2010COMMON
+/-5%
RP2A
18
+/-5%
FBACMD21
COMMON
+/-5%
COMMONRPAK_PAR_4_2010
+/-5%
150
COMMON
+/-5%
150
COMMON
+/-5%
FBVDDQ
150
150
150
COMMONRPAK_PAR_4_2010
GND
45
36
RPAK_PAR_4_2010
FBACMD22
36
RPAK_PAR_4_2010COMMON
45
RPAK_PAR_4_2010COMMON
GND
FBACMD25
FBACMD7
RP8D
45
RP8C 150
36
RPAK_PAR_4_2010
RP8B 150
27
RPAK_PAR_4_2010
RP8A 150
18
RPAK_PAR_4_2010COMMON
RP11A
18
RPAK_PAR_4_2010
+/-5%
RP11B
27
RPAK_PAR_4_2010COMMON
+/-5%
RP7B
27
RPAK_PAR_4_2010COMMON
+/-5%
RP7A
18
+/-5%
RP4A
18
RPAK_PAR_4_2010COMMON
+/-5%
RP4B 150
27
RPAK_PAR_4_2010COMMON
+/-5%
RP501C 150
36
RPAK_PAR_4_2010COMMON
+/-5%
RP501D 150
45
RPAK_PAR_4_2010COMMON
+/-5%
RP1A 150
COMMONRPAK_PAR_4_2010
+/-5%
RP1B 150
+/-5%
RP9C 150
+/-5%
RP9D 150
COMMON
+/-5%
RP4D
150
COMMONRPAK_PAR_4_2010
+/-5%
RP4C 150
COMMON
+/-5%
RP2C
150
+/-5%
RP2D 150
+/-5%
RP9A
18
RPAK_PAR_4_2010COMMON
+/-5%
RP9B
27
RPAK_PAR_4_2010COMMON
+/-5%
RP5D
45
RPAK_PAR_4_2010COMMON
+/-5%
RP5C
36
RPAK_PAR_4_2010COMMON
+/-5%
FBVDDQ
150
COMMONRPAK_PAR_4_2010
+/-5%
COMMON
+/-5%
COMMON
+/-5%
+/-5%
GND
FBVDDQ
150
COMMON
150
150
150
COMMONRPAK_PAR_4_2010
GND
FBVDDQ
150
GND
FBVDDQ
GND
FBVDDQ
GND
FBVDDQ
150
150
150
150
GND
1
2
3
4
FBVDDQ
R40
10K
5%
0402
COMMON
R39
10K
5%
0402
GND
NS
PD REQUIRED FOR INITIALIZATION OF DDR2
3,4,4,4,5,5
OUT
5
RESET
FBACMD12
Micro-Star International Co., LTD.
V056-0A
Size Document NumberRev
Custom
Date:
Thursday, December 15, 2005
Sheetof
00A
3
14
www.vinafix.vn
Memory Bit 0..31
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
1
3,3,4,4,5,5
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUS T RY S TA NDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRAN T I ES INCLUDING, WIT H O UT LIMITATI O N, THE WARRANTIES O F D ESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
Memory 1st bank 0..31
COMMON
GND
FBVDDQ
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VDD
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
J1
VDDL
A3
VSS
E3
VSS
J3
VSS
GND
N1
VSS
P9
VSS
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
J7
VSSL
J2
Vref
C506
.047UF
16V
10%
X7R
0402
COMMON
GND
EGC
HGFEDCBA
DIFFPAIRNETNV_IMPEDANCENV_CRITICAL_NET
FBACLK0
3,4,4,4
IN
FBACLK0*
3,4,4,4
IN
FBAD[63..0]
3,3,4,5
IN
FBADQS0
0
FBADQS[7..0]
3,4,5,5
IN
3,4,5,5
FBADQSN[7..0]
IN
FBVDDQ
GND
FBVDDQ
GND
FBVDDQ
GND
FBVDDQ
GND
3,4,5
3,3,4,4,5,5
IN
IN
IN
C513
.1UF
10V
10%
X5R
0402
COMMON
C512
.1UF
10V
10%
X5R
0402
COMMON
C508
.1UF
10V
10%
X5R
0402
COMMON
C514
.1UF
10V
10%
X5R
0402
COMMON
FBADQSN0
0
1
1
2
2
3
3
FBADQM[7..0]
FBACMD[25..0]
FBADQS0100DIFF1
FBADQS1
FBADQSN1
FBADQS2
FBADQSN2
FBADQS2100DIFF1
FBADQS3
FBADQSN3
FBADQS3100DIFF1
FBA_ODT
C46
.1UF
10V
10%
X5R
0402
COMMON
C44
.1UF
10V
10%
X5R
0402
COMMON
C41
.1UF
10V
10%
X5R
0402
COMMON
C515
.1UF
10V
10%
X5R
0402
COMMON
C47
1UF
6.3V
10%
X5R
0402
COMMON
100DIFF1FBACLK0
100DIFFFBACLK01
50OHM1
100DIFF1FBADQS0
100DIFF1FBADQS1
100DIFFFBADQS31
50OHM1
50OHM1
C52
C57
1UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0603
COMMON
COMMON
C58
4.7UF
6.3V
10%
X5R
0603
COMMON
1FBADQS1100DIFF
1100DIFFFBADQS2
150OHM
1
2
3
X-cap for CMD
FBVDDQ
GND
FBVDDQ
GND
C62
.01UF
25V
10%
X7R
0402
COMMON
C60
.01UF
25V
10%
X7R
0402
COMMON
C505
.01UF
25V
10%
X7R
0402
COMMON
C502
.01UF
25V
10%
X7R
0402
COMMON
C64
.01UF
25V
10%
X7R
0402
COMMON
C63
.01UF
25V
10%
X7R
0402
COMMON
C501
.01UF
25V
10%
X7R
0402
COMMON
C61
.01UF
25V
10%
X7R
0402
COMMON
C56
.01UF
25V
10%
X7R
0402
COMMON
C503
.01UF
25V
10%
X7R
0402
COMMON
4
5
Micro-Star International Co., LTD.
V056-0A
Size Document NumberRev
Custom
Date:
Thursday, December 15, 2005
Sheetof
00A
4
14
www.vinafix.vn
Memory Bit 32..63
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
FBACMD[25..0]
3,3,4,4,4,5
1
IN
FBACMD15FBACMD15
15
FBACMD25FBACMD25
25
FBACMD9FBACMD9
9
FBACMD8FBACMD8
8
FBACMD1FBACMD1
1
FBACMD3FBACMD3
3
FBACMD13FBACMD13
13
FBACMD4FBACMD4
4
FBACMD5FBACMD5
SUBPARTITION BITS ---->
2
USED ONLY FOR 1GB DEVICES ---->
3,5,5,5
3,5,5,5
3
5
FBACMD6FBACMD6
6
FBACLK1FBACLK1
IN
FBACLK1*FBACLK1*
IN
3,3,4,4,4,5
3,4,4,5
FBACMD21FBACMD21
21
FBACMD23FBACMD23
23
FBACMD19FBACMD19
19
FBACMD20FBACMD20
20
FBACMD17FBACMD17
17
FBACMD16FBACMD16
16
FBACMD14FBACMD14
14
SNN_FBA3_NC_R8
SNN_FBA3_NC_R3
SNN_FBA3_NC_R7
FBACMD10FBACMD10
10
FBACMD18FBACMD18
18
FBACMD7FBACMD7
7
FBACMD11FBACMD11
11
FBACMD12FBACMD12
IN
SNN_FBA3_NC_A2
SNN_FBA3_NC_E2
3,3,4,4
3,4,4
FBAD[63..0]
BI
FBADQM[7..0]
IN
FBADQS[7..0]
IN
4
3,4,4,5
FBADQSN[7..0]
IN
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUS T RY S TA NDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRAN T I ES INCLUDING, WIT H O UT LIMITATI O N, THE WARRANTIES O F D ESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.