MSI MS-V045 Schematic 10
V045 -- NV43, 128/256 MB DDR3, VGA, DVI-I, SD/HDTV, VIVO
HGFEDCBA
1
1
SUMMARY:
1. Base on V023 to Modify
2. BGA-136 DDRIII
3. Add G73 2V5 Power
2
3
2
3
4
SKU
VARIANT ASSEMBLY
BASE
B
000
1
2
001
002
3
003
4
<UNDEFINED>
5
<UNDEFINED>
6
<UNDEFINED>
7
<UNDEFINED>
8
<UNDEFINED>
9
<UNDEFINED>
10
<UNDEFINED>
11
<UNDEFINED>
12
<UNDEFINED>
13
<UNDEFINED>
5
14
15
<UNDEFINED>
NVPN
600-10216-base-sch
602-10216-0000-200
602-10216-0001-200
602-10216-0002-200
602-10216-0003-200
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
X01
ASSEMBLY
PAGE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
TABLE OF CONTENTS & R EV ISION
HISTORY
E GC
www.vinafix.vn
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
NV43-U 500/500MHz 128MB DDR3 8MX32
DVI+VGA+HDTVOUT
NV43-U 500/500MHZ 128MB DDR3 8MX32
DVI+VGA+HD/VIVO
NV43-U 350/350MHZ 128MB DDR3 8MX32
DVI+VGA+HDTVOUT
NV43-U 400/400MHZ 128MB DDR3 8MX32
DVI+VGA+HDTVOUT
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Date:
Custom
Tuesday, Nove mber 22 , 2005
1
Sheet of
4
5
10
22
3V3
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
C949
.01UF
16V
10%
X7R
0402
COMMON
3V3AUX
GND
Place Close to fingers
C94
.100UF
25V
10%
X7R
0603
COMMON
C95
C916
.1UF
10UF
16V
10V
20%
10%
X5R
X5R
0402
1206
COMMON
COMMON
CN2
CON_3GIO_164_FINGER
A10
B10
B17
B12
A12
B13
A15
B16
B18
A18
B1
B2
A2
A3
B3
B8
A9
A1
B4
A4
B7
COMMON
+12V
+12V
+12V
+12V
+12V/RSVD
+3V3
+3V3
+3V3
+3V3AUX
PRSNT1
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
12V
3V3
3V3AUX
PRSNT
NTP_PE_PRSNT2_A
NTP_PE_RSVD2
GND
NTP_PE_PRSNT2_B
NTP_PE_RSVD3
NTP_PE_RSVD4
NTP_PE_RSVD5
NTP_PE_PRSNT2_C
NTP_PE_RSVD6
NTP_PE_RSVD7
NTP_PE_RSVD8
B31
PRSNT2
A19
RSVD
B30
RSVD
A32
RSVD
A20
GND
B21
GND
B22
GND
A23
GND
A24
GND
B25
GND
B26
GND
A27
GND
A28
GND
B29
GND
A31
GND
B32
GND
GND
B48
PRSNT2
A33
RSVD
A34
GND
B35
GND
B36
GND
A37
GND
A38
GND
B39
GND
B40
GND
A41
GND
A42
GND
B43
GND
B44
GND
A45
GND
A46
GND
B47
GND
B49
GND
A49
GND
GND
B81
PRSNT2
A50
RSVD
B82
RSVD
A51
GND
B52
GND
B53
GND
A54
GND
A55
GND
B56
GND
B57
GND
A58
GND
A59
GND
B60
GND
B61
GND
A62
GND
A63
GND
B64
GND
B65
GND
A66
GND
A67
GND
B68
GND
B69
GND
A70
GND
A71
GND
B72
GND
B73
GND
A74
GND
A75
GND
B76
GND
B77
GND
A78
GND
A79
GND
B80
GND
A82
GND
GND
AB D F H
END OF X1
END OF X4
END OF X8
END OF X16
12V
C950
.01UF
25V
10%
X7R
0402
COMMON
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
C915
.1UF
16V
10%
X7R
0603
COMMON
B9
A5
A6
A7
A8
this resistor stradles the TDI/TDO pair
B5
B6
B11
WAKE
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
GND
NTP_JTAG_TRST*
NTP_JTAG_TCLK
JTAG_TDI_TDO
NTP_JTAG_TMS
NTP_PEX_SMCLK
NTP_PEX_SMDAT
NTP_PEX_WAKE*
PEX_PWRGD*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
C93
10UF
16V
20%
X5R
1206
COMMON
VALUES
TBD
Place near balls
PEX_IO_VDD
C846
.022UF
16V
10%
X7R
0402
COMMON
2A
PEX_IO_VDDQ
C849
.022UF
16V
10%
X7R
0402
COMMON
C985
.1UF
10V
10%
X5R
0402
COMMON
GND
C747
0.47UF
6.3V
10%
X5R
0402
COMMON
C675
.1UF
10V
10%
X5R
0402
COMMON
C804
0.47UF
6.3V
10%
X5R
0402
COMMON
C773
0.47UF
6.3V
10%
X5R
0402
COMMON
VALUES
TBD
R6295%0
COMMON0402
VDD33
PEX_PLL_VDD
C845
.022UF
16V
10%
X7R
0402
COMMON
Place near balls
C857
.022UF
16V
10%
X7R
0402
COMMON
150-220R@100MHz
150-220R@100MHz
GND
R7042
3V3
5
1
2
3
GND
0402
0
C948
.1UF
0402X5R 10% 10V
C946
.1UF
0402X5R 10% 10V
C944
.1UF
0402X5R 10% 10V
C942
.1UF
0402X5R 10% 10V
C940
.1UF
0402X5R 10% 10V
C938
.1UF
0402X5R 10% 10V
C936
.1UF
0402X5R 10% 10V
C934
.1UF
0402X5R 10% 10V
C932
.1UF
0402X5R 10% 10V
C930
.1UF
0402X5R 10% 10V
C928
.1UF
0402X5R 10% 10V
C926
.1UF
0402X5R 10% 10V
C924
.1UF
0402X5R 10% 10V
C922
.1UF
0402X5R 10% 10V
C920
.1UF
0402X5R 10% 10V
C918
.1UF
0402X5R 10% 10V
C97
1UF
6.3V
10%
X5R
0402
COMMON
R704
0
5%
0402
NS
3.5MIL
R7041
3.5MIL
3.5MIL
0402
0
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
16X PCIe Interface
short duration contention possible
3.3V^2/100 =
108mW
U14
UNNAMED_2_R_I543_1
R110
100
4
0402
COMMON
5%
SC70-5
COMMON
1/16W
R83 0
0402 COMM ON
5%
BYPASS
TP_PEXCAPD_VDDQ
TP_PEXCALPD_GND
R102
04025%COMMON
PEX_TEST_PLLCLK_OUT
PEX_TEST_PLLCLK_OUT_N
GPU_PEX_REFCLK
GPU_PEX_REFCLK*
C947
.1UF
3.5MIL
3.5MIL
0402 10% X5 R10V
C945 .1UF
0402 10%10V X5R C OMMON
C943 .1UF
0402 10%10V X5R C OMMON
C941
0402 X5R10%10V
C939
0402 X5R10%10V
C937
0402 X5R10%10V
C935
0402 X5R10%10V
C933
0402 X5R10%10V
C931
0402 X5R10%10V
C929
0402 X5R10%10V
C927
0402 X5R10%10V
C925
0402 X5R10%10V
C923
0402 X5R10%10V
C921
0402 X5R10%10V
C919
0402 X5R10%10V
C917
0402 X5R10%10V
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
.1UF
3.5MIL
3.5MIL
COMMON
200
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
R111
10K
5%
0402
COMMON
GND
AH15
PEX_PWRGD_BUF*
AG12
AH13
AM12
AM11
AH14
AJ14
AJ15
AK15
AK13
AK14
AH16
AG16
AM14
AM15
AG17
AH17
AL15
AL16
AG18
AH18
AK16
AK17
AK18
AJ18
AL17
AL18
AJ19
AH19
AM18
AM19
AG20
AH20
AK19
AK20
AG21
AH21
AL20
AL21
AK21
AJ21
AM21
AM22
AJ22
AH22
AK22
AK23
AG23
AH23
AL23
AL24
AK24
AJ24
AM24
AM25
AJ25
AH25
AK25
AK26
AH26
AG26
AL26
AL27
AK27
AJ27
AM27
AM28
AJ28
AH27
AL28
AL29
U11A
BGA820_P10_33X33MM
COMMON
1/14 PCI_EXPRESS
PEX_RST
RFU
RFU
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX10
PEX_TX10
PEX_RX10
PEX_RX10
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX14
PEX_TX14
PEX_RX14
PEX_RX14
PEX_TX15
PEX_TX15
PEX_RX15
PEX_RX15
ASSEMBLY
PAGE
DETAIL
600mA
AD23
PEX_IOVDD
AF23
PEX_IOVDD
AF24
PEX_IOVDD
AF25
PEX_IOVDD
AG24
PEX_IOVDD
AG25
PEX_IOVDD
AC16
PEX_IOVDDQ
AC17
PEX_IOVDDQ
AC21
PEX_IOVDDQ
AC22
PEX_IOVDDQ
AE18
PEX_IOVDDQ
AE21
PEX_IOVDDQ
AE22
PEX_IOVDDQ
AF12
PEX_IOVDDQ
AF18
PEX_IOVDDQ
AF21
PEX_IOVDDQ
AF22
PEX_IOVDDQ
K16
VDD
K17
VDD
N13
VDD
N14
VDD
N16
VDD
N17
VDD
N19
VDD
P13
VDD
P14
VDD
P16
VDD
P17
VDD
P19
VDD
R16
VDD
R17
VDD
T13
VDD
T14
VDD
T15
VDD
T18
VDD
T19
VDD
U13
VDD
U14
VDD
U15
VDD
U18
VDD
U19
VDD
V16
VDD
V17
VDD
W13
VDD
W14
VDD
W16
VDD
W17
VDD
W19
VDD
Y13
VDD
Y14
VDD
Y16
VDD
Y17
VDD
Y19
VDD
Y20
VDD
P20
VDD_LP
T20
VDD_LP
T23
VDD_LP
U20
VDD_LP
U23
VDD_LP
W20
VDD_LP
NVVDD_SENSE
N20
VDD_SENSE
GND_SENSE
PEX_PLLAVDD
PEX_PLLDVDD
PEX_PLLGND
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
GND_SENSE
M21
AC11
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
L10
L7
L8
M10
AF15
AE15
AE16
GND
NTP_GPU_AM10_NC
AM8
NC
NTP_GPU_AM8_NC
AM9
NC
NTP_GPU_AM9_NC
B32
NC
NTP_GPU_B32_NC
J6
NC
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
PCI EXPRESS 16X, NVVDD DECOUPLING CAPS,PEX_IOVDD/Q
DECOUPLING CAPS
E GC
VALUES
TBD
C847
.01UF
16V
10%
X7R
0402
COMMON
LB535
0603 COMMO N
LB536
0603 COMMO N
C780
.1UF
10V
10%
X5R
0402
COMMON
C781
.1UF
10V
10%
X5R
0402
COMMON
C756
.1UF
10V
10%
X5R
0402
COMMON
C796
.1UF
10V
10%
X5R
0402
COMMON
C751
.001UF
COMMON
50V
10%
X7R
0402
OUT
Place near balls
C826
.1UF
10V
10%
X5R
0402
COMMON
C853
.1UF
10V
10%
X5R
0402
COMMON
Place near balls
180mA
C833
.1UF
10V 10%
X5R
0402
COMMON
Place near balls
20mA
C842
4700PF
25V
10%
X7R
0402
COMMON
C786
0.47UF
6.3V
10%
X5R
0402
COMMON
C801
0.47UF
6.3V
10%
X5R
0402
COMMON
C798
.1UF
10V
10%
X5R
0402
COMMON
C762
.1UF
10V
10%
X5R
0402
COMMON
C738
4700PF
25V
10%
X7R
0402
COMMON
C745
4700PF
25V
10%
X7R
0402
COMMON
C831
470PF
16V
10%
X7R
0402
COMMON
C848
.01UF
16V
10%
X7R
0402
COMMON
22.2G< 2.5G<>
C825
.01UF
16V
10%
X7R
0402
COMMON
Place Close to GPU
220R@100MHz
LB530
0805 COMMON
C883
4.7UF
6.3V
10%
X5R
0603
COMMON
Place Close to GPU
C850
.01UF
16V
10%
X7R
0402
COMMON
NVVDD
C799
C794
.1UF
0.47UF
6.3V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C758
C777
0.47UF
.1UF
6.3V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C727
C746
0.47UF
0.47UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C744
C790
.1UF
0.47UF
10V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
3V3
LB531
120R@100MHz
NS
0603
C844
.022UF
16V
10%
X7R
0402
COMMON
C854
.022UF
16V
10%
X7R
0402
COMMON
Place Near
BGA
0.02R3A
220R@100MHz
3A
LB9
0805
C96
4.7UF
6.3V
X5R
0603
COMMON
Place near balls
C721
.022UF
16V
10%
X7R
0402
COMMON
C843
.022UF
16V
10%
X7R
0402
COMMON
Place Near
BGA
150-220R@100MHz
LB524
0603 COMMO N
C828
4.7UF
10%6.3V
X5R
0603
COMMON
PEX1V2
C894
4.7UF
6.3V
X5R
0603
COMMON
0.02R
COMMON
10%
PEX1V2
C757
.1UF
10V
10%
X5R
0402
COMMON
C784
10UF
6.3V
20%
X5R
0805
COMMON
C742
10UF
6.3V
20%
X5R
0805
COMMON
C797
0.47UF
6.3V
10%
X5R
0402
COMMON
A3V3
LB532
120R@100MHz
COMMON
0603
C734
1UF
10V
10%
X7R
0603
COMMON
GND
GND
22.2G< 2.3F>
HGFEDCBA
10%
GND
PEX1V2
C908
21.3B< 2.2C>
10UF
20%
6.3V
X5R
0805
21.3G> 2.2C<
COMMON
GND
NVVDD
C783
10UF
6.3V
20%
X5R
0805
COMMON
C659
.1UF
GND
10V
10%
X5R
0402
COMMON
C769
.1UF
GND
10V
10%
X5R
0402
COMMON
GND
GND
PEX1V2
GND
C812
4.7UF
6.3V 10%
X5R
0603
COMMON
PEX_REFCLK
PEX_REFCLK*
BI
GPU_PEX_REFCLK
BI
GPU_PEX_REFCLK*
BI
BI
PEX_TX0
BI
PEX_TX0*
BI
PEX_TX1
BI
PEX_TX1*
BI
PEX_TX2
BI
PEX_TX2*
BI
PEX_TX3
BI
PEX_TX3*
BI
PEX_TX4
BI
PEX_TX4*
BI
PEX_TX5
BI
PEX_TX5*
BI
PEX_TX6
BI
PEX_TX6*
BI
PEX_TX7
BI
PEX_TX7*
BI
PEX_TX8
BI
PEX_TX8*
BI
PEX_TX9
BI
PEX_TX9*
BI
PEX_TX10
BI
PEX_TX10*
BI
PEX_TX11
BI
PEX_TX11*
BI
PEX_TX12
BI
PEX_TX12*
BI
PEX_TX13
BI
PEX_TX13*
BI
PEX_TX14
BI
PEX_TX14*
BI
PEX_TX15
BI
PEX_TX15*
BI
PEX_TXX0
PEX_TXX0*
BI
PEX_TXX1
BI
PEX_TXX1*
BI
PEX_TXX2
BI
PEX_TXX2*
BI
PEX_TXX3
BI
PEX_TXX3*
BI
PEX_TXX4
BI
PEX_TXX4*
BI
PEX_TXX5
BI
PEX_TXX5*
BI
PEX_TXX6
BI
PEX_TXX6*
BI
PEX_TXX7
BI
PEX_TXX7*
BI
PEX_TXX8
BI
PEX_TXX8*
BI
PEX_TXX9
BI
PEX_TXX9*
BI
PEX_TXX10
BI
PEX_TXX10*
BI
PEX_TXX11
BI
PEX_TXX11*
BI
PEX_TXX12
BI
PEX_TXX12*
BI
PEX_TXX13
BI
PEX_TXX13*
BI
PEX_TXX14
BI
PEX_TXX14*
BI
PEX_TXX15
BI
PEX_TXX15*
BI
BI
PEX_RX0
BI
PEX_RX0*
BI
PEX_RX1
BI
PEX_RX1*
BI
PEX_RX2
BI
PEX_RX2*
BI
PEX_RX3
BI
PEX_RX3*
BI
PEX_RX4
BI
PEX_RX4*
BI
PEX_RX5
BI
PEX_RX5*
BI
PEX_RX6
BI
PEX_RX6*
BI
PEX_RX7
BI
PEX_RX7*
BI
PEX_RX8
BI
PEX_RX8*
BI
PEX_RX9
BI
PEX_RX9*
BI
PEX_RX10
BI
PEX_RX10*
BI
PEX_RX11
BI
PEX_RX11*
BI
PEX_RX12
BI
PEX_RX12*
BI
PEX_RX13
BI
PEX_RX13*
BI
PEX_RX14
BI
PEX_RX14*
BI
PEX_RX15
BI
PEX_RX15*
BI
NVVDD_SENSE
BI
GND_SENSE
BI
BI
GND
V045 base on P216 Modify
Size Document Number Rev
Custom
Date:
DIFFPAIRNET
NET_SPACING_RULE
20MIL_G2G_30MIL_USER_DIFFPEX_REFCLK
GPU_PEX_REFCLK 20MIL_G2G_30MIL_USER_DIFF
GPU_PEX_REFCLK 20MIL_G2G_30MIL_USER_DIFF
PEX_TX0 20MIL_G2G_30MIL_USER_DIFF
PEX_TX0 20MIL_G2G_30MIL_USER_DIFF
PEX_TX5 20MIL_G2G_30MIL_USER_DIFF
PEX_TX7 20MIL_G2G_30MIL_USER_DIFF
PEX_TX8 20MIL_G2G_30MIL_USER_DIFF
PEX_TX9 20MIL_G2G_30MIL_USER_DIFF
PEX_TX13 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX7 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX7 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX8 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX9 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX10 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX11 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX12 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX13 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX14 20MIL_G2G_30MIL_USER_DIFF
PEX_TXX14 20MIL_G2G_30MIL_USER_DIFF
PEX_RX0 20MIL_G2G_30MIL_USER_DIFF
PEX_RX8 20MIL_G2G_30MIL_USER_DIFF
PEX_RX9 20MIL_G2G_30MIL_USER_DIFF
PEX_RX9 20MIL_G2G_30MIL_USER_DIFF
PEX_RX10 20MIL_G2G_30MIL_USER_DIFF
PEX_RX10 20MIL_G2G_30MIL_USER_DIFF
PEX_RX15 20MIL_G2G_30MIL_USER_DIFF
PEX_RX15 20MIL_G2G_30MIL_USER_DIFF
PEX_PLL_VDD
20MIL_G2G_30MIL_USER_DIFFPEX_REFCLK
20MIL_G2G_30MIL_USER_DIFFPEX_TX1
20MIL_G2G_30MIL_USER_DIFFPEX_TX1
20MIL_G2G_30MIL_USER_DIFFPEX_TX2
20MIL_G2G_30MIL_USER_DIFFPEX_TX2
20MIL_G2G_30MIL_USER_DIFFPEX_TX3
20MIL_G2G_30MIL_USER_DIFFPEX_TX3
20MIL_G2G_30MIL_USER_DIFFPEX_TX4
20MIL_G2G_30MIL_USER_DIFFPEX_TX4
20MIL_G2G_30MIL_USER_DIFFPEX_TX5
20MIL_G2G_30MIL_USER_DIFFPEX_TX6
20MIL_G2G_30MIL_USER_DIFFPEX_TX6
20MIL_G2G_30MIL_USER_DIFFPEX_TX7
20MIL_G2G_30MIL_USER_DIFFPEX_TX8
20MIL_G2G_30MIL_USER_DIFFPEX_TX9
20MIL_G2G_30MIL_USER_DIFFPEX_TX10
20MIL_G2G_30MIL_USER_DIFFPEX_TX10
20MIL_G2G_30MIL_USER_DIFFPEX_TX11
20MIL_G2G_30MIL_USER_DIFFPEX_TX11
20MIL_G2G_30MIL_USER_DIFFPEX_TX12
20MIL_G2G_30MIL_USER_DIFFPEX_TX12
20MIL_G2G_30MIL_USER_DIFFPEX_TX13
20MIL_G2G_30MIL_USER_DIFFPEX_TX14
20MIL_G2G_30MIL_USER_DIFFPEX_TX14
20MIL_G2G_30MIL_USER_DIFFPEX_TX15
20MIL_G2G_30MIL_USER_DIFFPEX_TX15
20MIL_G2G_30MIL_USER_DIFFPEX_TXX0
20MIL_G2G_30MIL_USER_DIFFPEX_TXX0
20MIL_G2G_30MIL_USER_DIFFPEX_TXX1
20MIL_G2G_30MIL_USER_DIFFPEX_TXX1
20MIL_G2G_30MIL_USER_DIFFPEX_TXX2
20MIL_G2G_30MIL_USER_DIFFPEX_TXX2
20MIL_G2G_30MIL_USER_DIFFPEX_TXX3
20MIL_G2G_30MIL_USER_DIFFPEX_TXX3
20MIL_G2G_30MIL_USER_DIFFPEX_TXX4
20MIL_G2G_30MIL_USER_DIFFPEX_TXX4
20MIL_G2G_30MIL_USER_DIFFPEX_TXX5
20MIL_G2G_30MIL_USER_DIFFPEX_TXX5
20MIL_G2G_30MIL_USER_DIFFPEX_TXX6
20MIL_G2G_30MIL_USER_DIFFPEX_TXX6
20MIL_G2G_30MIL_USER_DIFFPEX_TXX8
20MIL_G2G_30MIL_USER_DIFFPEX_TXX9
20MIL_G2G_30MIL_USER_DIFFPEX_TXX10
20MIL_G2G_30MIL_USER_DIFFPEX_TXX11
20MIL_G2G_30MIL_USER_DIFFPEX_TXX12
20MIL_G2G_30MIL_USER_DIFFPEX_TXX13
20MIL_G2G_30MIL_USER_DIFFPEX_TXX15
20MIL_G2G_30MIL_USER_DIFFPEX_TXX15
20MIL_G2G_30MIL_USER_DIFFPEX_RX0
20MIL_G2G_30MIL_USER_DIFFPEX_RX1
20MIL_G2G_30MIL_USER_DIFFPEX_RX1
20MIL_G2G_30MIL_USER_DIFFPEX_RX2
20MIL_G2G_30MIL_USER_DIFFPEX_RX2
20MIL_G2G_30MIL_USER_DIFFPEX_RX3
20MIL_G2G_30MIL_USER_DIFFPEX_RX3
20MIL_G2G_30MIL_USER_DIFFPEX_RX4
20MIL_G2G_30MIL_USER_DIFFPEX_RX4
20MIL_G2G_30MIL_USER_DIFFPEX_RX5
20MIL_G2G_30MIL_USER_DIFFPEX_RX5
20MIL_G2G_30MIL_USER_DIFFPEX_RX6
20MIL_G2G_30MIL_USER_DIFFPEX_RX6
20MIL_G2G_30MIL_USER_DIFFPEX_RX7
20MIL_G2G_30MIL_USER_DIFFPEX_RX7
20MIL_G2G_30MIL_USER_DIFFPEX_RX8
20MIL_G2G_30MIL_USER_DIFFPEX_RX11
20MIL_G2G_30MIL_USER_DIFFPEX_RX11
20MIL_G2G_30MIL_USER_DIFFPEX_RX12
20MIL_G2G_30MIL_USER_DIFFPEX_RX12
20MIL_G2G_30MIL_USER_DIFFPEX_RX13
20MIL_G2G_30MIL_USER_DIFFPEX_RX13
20MIL_G2G_30MIL_USER_DIFFPEX_RX14
20MIL_G2G_30MIL_USER_DIFFPEX_RX14
MIN_LINE_WIDTH
10MIL
10MIL
10MIL
Micro-Star International Co., LTD.
Tuesday, Nove mber 22 , 2005
Sheet of
1
2
3
4
5
10
2
22
www.vinafix.vn
HGFEDCBA
4.4B<> 4.1G<> >4,6>
1
2
3
4.4B<> 4.1G<> >4,6>
4.5B<> 4.1G<> >4,6>
4.4B<> 4.1G<> >4,6>
FBVDD
4
Rtop
COMMON
1%
0402
R602 1K
Rbot
COMMON0402
1%
R607 1K
GND
5
BI
OUT
BI
BI
C652
.1UF
10V
10%
X5R
0402
NS
C660
.1UF
10V
10%
X5R
0402
COMMON
VREF = FBVDDQ * Rbot/(Rtop + Rbot)
VREF = 0.70 *
FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)
DDR3:
FBAD[63..0]
FBADQM[7..0]
FBADQS_WP[7..0]
FBADQS_RN[7..0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
FBA_VREF
U11B
BGA820_P10_33X33MM
COMMON
2/14 FBA
N27
FBAD0
M27
FBAD1
N28
FBAD2
L29
FBAD3
K27
FBAD4
K28
FBAD5
J29
FBAD6
J28
FBAD7
P30
FBAD8
N31
FBAD9
N30
FBAD10
N32
FBAD11
L31
FBAD12
L30
FBAD13
J30
FBAD14
L32
FBAD15
H30
FBAD16
K30
FBAD17
H31
FBAD18
F30
FBAD19
H32
FBAD20
E31
FBAD21
D30
FBAD22
E30
FBAD23
H28
FBAD24
H29
FBAD25
E29
FBAD26
J27
FBAD27
F27
FBAD28
E27
FBAD29
E28
FBAD30
F28
FBAD31
AD29
FBAD32
AE29
FBAD33
AD28
FBAD34
AC28
FBAD35
AB29
FBAD36
AA30
FBAD37
Y28
FBAD38
AB30
FBAD39
AM30
FBAD40
AF30
FBAD41
AJ31
FBAD42
AJ30
FBAD43
AJ32
FBAD44
AK29
FBAD45
AM31
FBAD46
AL30
FBAD47
AE32
FBAD48
AE30
FBAD49
AE31
FBAD50
AD30
FBAD51
AC31
FBAD52
AC32
FBAD53
AB32
FBAD54
AB31
FBAD55
AG27
FBAD56
AF28
FBAD57
AH28
FBAD58
AG28
FBAD59
AG29
FBAD60
AD27
FBAD61
AF27
FBAD62
AE28
FBAD63
M29
FBADQM0
M30
FBADQM1
G30
FBADQM2
F29
FBADQM3
AA29
FBADQM4
AK30
FBADQM5
AC30
FBADQM6
AG30
FBADQM7
L28
FBADQS_WP0
K31
FBADQS_WP1
G32
FBADQS_WP2
G28
FBADQS_WP3
AB28
FBADQS_WP4
AL32
FBADQS_WP5
AF32
FBADQS_WP6
AH30
FBADQS_WP7
M28
FBADQS_RN0
K32
FBADQS_RN1
G31
FBADQS_RN2
G27
FBADQS_RN3
AA28
FBADQS_RN4
AL31
FBADQS_RN5
AF31
FBADQS_RN6
AH29
FBADQS_RN7
E32
FB_VREF1
ALL FBVDD PINS ARE NC ON
NV43 DESKTOP G3 PACKAGE
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDD
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
RFU
RFU
FBA_DEBUG
FBA_REFCLK
FBA_REFCLK
FBA_PLLVDD
FBA_PLLAVDD
FBA_PLLGND
A12
A15
A18
A21
A24
A27
A3
A30
A6
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32
V32
AA25
AA26
AB25
AB26
G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
M26
R25
R26
V25
V26
P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32
P28
R28
Y27
AA27
Y30
AC26
AC27
D32
D31
G23
G25
G24
NTP_GPU_A12
NTP_GPU_A15
NTP_GPU_A18
NTP_GPU_A21
NTP_GPU_A24
NTP_GPU_A27
NTP_GPU_A3
NTP_GPU_A30
NTP_GPU_A6
NTP_GPU_A9
NTP_GPU_AA32
NTP_GPU_AD32
NTP_GPU_AG32
NTP_GPU_AK32
NTP_GPU_C32
NTP_GPU_F32
NTP_GPU_J32
NTP_GPU_M32
NTP_GPU_R32
NTP_GPU_V32
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
NTP_FBA_CMD<26>
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
TP
NOW
TP_FBA_DBI1
FBA_PLLAVDD
GND
TP_FBA_DBI0
TP_FBA_DEBUG
FBA_REFCLK
FBA_REFCLK*
FBA_CMD[26..0]
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PLACE close to
24
25
GPU
4.1G<
OUT
4.2A<
OUT
4.1G<
OUT
4.2D<
OUT
PLACE BELOW
GPU
OUT
R7146
0R
0402
1%
R7147
COMMON
0R
0402
1%
COMMON
FBVDD
>4,6>
R596
>4,6>
100
1%
0402
COMMON
FBA_REFCLK*
R593
100
1%
0402
COMMON
GND
C792
.1UF
10V
10%
X5R
0402
COMMON
FBVDD
C708
0.47UF
6.3V
10%
X5R
0402
COMMON
C707
.1UF
10V
10%
X5R
0402
COMMON
C722
0.47UF
6.3V
10%
X5R
0402
COMMON
C806
.1UF
10V
10%
X5R
0402
COMMON
C755
.1UF
10V
10%
X5R
0402
COMMON
C800
0.47UF
6.3V
10%
X5R
0402
COMMON
C730
.1UF
10V
10%
X5R
0402
COMMON
C5
.1UF
10V
10%
X5R
0402
COMMON
C6
.1UF
10V
10%
X5R
0402
COMMON
C50
.1UF
10V
10%
X5R
0402
COMMON
C68
.1UF
10V
10%
X5R
0402
COMMON
C824
1UF
10V
10%
X7R
0603
COMMON
C697
1UF
10V
10%
X7R
0603
COMMON
GND
GND
GND
GND
C705
0.47UF
6.3V
10%
X5R
0402
COMMON
C704
.1UF
10V
10%
X5R
0402
COMMON
C754
0.47UF
6.3V
10%
X5R
0402
COMMON
C750
0.47UF
6.3V
10%
X5R
0402
COMMON
C698
.1UF
10V
10%
X5R
0402
COMMON
GND
4.1G< 4.1A< >4,6>
14.3A< >4>
OUT
14.3A< >6>
OUT
R599
100
1%
0402
COMMON
R601
100
1%
0402
COMMON
PLACE close to balls
FBA_PLLVDD
C689
C685
.01UF
.1UF
16V
10V
10%
10%
X7R
X5R
0402
0402
COMMON
COMMON
C710
.01UF
16V
10%
X7R
0402
COMMON
C692
.1UF
10V
10%
X5R
0402
COMMON
FB_DLLVDD
ON NV3x version's of G3
FB_DLLVDD will be routed on
FB_PLLVDD
150-220R@100MHz
LB507
0603 COMMO N
C674
1UF
6.3V
10%
X5R
0402
COMMON
150-220R@100MHz
LB509
0603 COMMON
C672
1UF
6.3V
10%
X5R
0402
COMMON
150-220R@100MHz
LB537
0603 COMMON
NVVDD
GND
C662
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
FBA_AVDD is TBD. This may not be hooked up on the Package.
C654
4.7UF
6.3V
10%
X5R
0603
COMMON
C986
4.7UF
6.3V
10%
X5R
0603
COMMON
FBVDD
PLACE MIDWAY BETWEEN GPU AND
MEMORY
A3V3
GND
PEX1V2
IN
IN
IN
IN
C740
10UF
6.3V
20%
X5R
0805
COMMON
FBA_REFCLK
FBA_REFCLK*
FBA_PLLVDD
FBA_PLLAVDD
C856
10UF
6.3V
20%
X5R
0805
COMMON
MIN_LINE_WIDTHNET
4MIL 10MIL
10MIL
10MIL
C597
10UF
6.3V
20%
X5R
0805
COMMON
C594
10UF
6.3V
20%
X5R
0805
COMMON
DIFFPAIR
GND
PLACE NEAR
GPU
R7240
10K
?
0402
COMMON
FBA_CMD11
FBA_CMD12
GND
CKE Stuff options for DDR3 configation for
on-die terminations at the memory
IMPORTANT FOR POWER ON INITIALIZATION OF
DDR3 MEMS
DDR3: DETERMINES THE ODT VALUE FOR ADDR AND
CONTROL PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
NET_SPACING_RULE
10MIL4MIL
FBVDD
R638
10K
5%
0402
NS
R640
10K
5%
0402
COMMON
GND
1
2
3
4
5
ASSEMBLY
PAGE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
FBA MEMORY INTERFA CE , GPU FBVDD/Q
DECOUPLING CAPS
E GC
www.vinafix.vn
Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Date:
Custom
Tuesday, Nove mber 22 , 2005
3
Sheet of
10
22
1
5 FrameBuffer: Partition A
8Mx32 BGA136 DDR3
2
3
4
5
6
7
8
HGFEDCBA
FBA_CMD[26..0]
20.5G> >3>
FBVDD
C988
.1UF
10V
10%
X5R
0402
COMMON
R7159
60.4R
1%
0402
COMMON
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)
FBAD[63..0]
IN
Low Sub-Partition
GND
C953
R7163
.1UF
10V
10%
COMMON
X5R
0402
NS
R7166
C956
.1UF
10V
10%
COMMON
X5R
0402
COMMON
R7165
2.37K
1%
0402
COMMON
R7168
5.49K
1%
0402
COMMON
FBVDD
GND
U508
T3
DQ31 | DQ23
T2
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8
BA2 | RAS
BA1 | BA0
BA0 | BA1
A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4
CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK
CK
RDQS3 | RDQS2
RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1
WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1
DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1
RESET
ZQ
VREF
VREF#H12
VDDQ#A12
VDDQ#C1
VDDQ#C4
VDDQ#C9
VDDQ#C12
VDDQ#E1
VDDQ#E4
VDDQ#E9
VDDQ#E12
VDDQ#N1
VDDQ#N4
VDDQ#N9
VDDQ#N12
VDDQ#R1
VDDQ#R4
VDDQ#R9
VDDQ#R12
VDDQ#V1
VDDQ#V12
VSSQ#B12
VSSQ#D12
VSSQ#G2
VSSQ#G11
VSSQ#L11
VSSQ#P12
VSSQ#T12
VDDA#K12
VSSA#J12
GND | VDD
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11
G3
F2
F3
E2
C3
C2
B3
B2
H10
G9
G4
L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4
CS0
F9
H9
H3
F4
H4
J10
J11
P3
P10
D10
D3
P2
P11
D11
D2
N3
N10
E10
E3
U9
A4
H1
H12
136BALL-GDDR3
C955
.1UF
10V
R1
10%
X5R
0402
NS
C958
.1UF
R2
10V
10%
X5R
0402
COMMON
FBAD58
63
FBAD62
62
FBAD56
61
FBAD59
60
C952
.1UF
10V
10%
X5R
0402
NS
C954
.1UF
10V
10%
X5R
0402
COMMON
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
18
10
16
17
20
19
23
21
6
5
4
13
3
1
8
9
15
25
11
R7160
240
1%
0603
COMMON
FBAD57
FBAD60
FBAD63
FBAD61
FBAD38
FBAD39
FBAD37
FBAD36
FBAD35
FBAD32
FBAD33
FBAD34
FBAD55
FBAD52
FBAD54
FBAD53
FBAD49
FBAD51
FBAD48
FBAD50
FBAD45
FBAD46
FBAD40
FBAD47
FBAD41
FBAD43
FBAD42
FBAD44
FBA_CMD7_0
FBA_CMD18
FBA_CMD10
FBA_CMD16
FBA_CMD17
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD21
FBA_CMD6
FBA_CMD5
FBA_CMD4
FBA_CMD13
FBA_CMD3
FBA_CMD1
FBA_CMD8
FBA_CMD9
FBA_CMD15
FBA_CMD25
FBA_CMD11
FBA_CLK1*
FBA_CLK1
FBADQS_RN7
FBADQS_RN4
FBADQS_RN6
FBADQS_RN5
FBADQS_WP7
FBADQS_WP4
FBADQS_WP6
FBADQS_WP5
FBADQM7
FBADQM4
FBADQM6
FBADQM5
FBA_CMD12
FBA_ZQ1
FBA_VREF_ADDR1
FBA_VREF_DATA1
FBA_ZQ0
R7167
0402
COMMON
R7169
0402
COMMON
U509
T3
DQ31 | DQ23
T2
DQ30 | DQ22
R3
DQ29 | DQ21
R2
DQ28 | DQ20
M3
DQ27 | DQ19
N2
DQ26 | DQ18
L3
DQ25 | DQ17
M2
DQ24 | DQ16
T10
DQ23 | DQ31
T11
DQ22 | DQ30
R10
DQ21 | DQ29
R11
DQ20 | DQ28
M10
DQ19 | DQ27
N11
DQ18 | DQ26
L10
DQ17 | DQ25
M11
DQ16 | DQ24
G10
DQ15 | DQ7
F11
DQ14 | DQ6
F10
DQ13 | DQ5
E11
DQ12 | DQ4
C10
DQ11 | DQ3
C11
DQ10 | DQ2
B10
DQ9 | DQ1
B11
DQ8 | DQ0
G3
DQ7 | DQ15
F2
DQ6 | DQ14
F3
DQ5 | DQ13
E2
DQ4 | DQ12
C3
DQ3 | DQ11
C2
DQ2 | DQ10
B3
DQ1 | DQ9
B2
DQ0 | DQ8
H10
BA2 | RAS
G9
BA1 | BA0
G4
BA0 | BA1
L4
A11 | A7
K2
A10 | A8
M9
A9 | A3
K11
A8/AP | A10
L9
A7 | A11
K10
A6 | A2
H11
A5 | A1
K9
A4 | A0
M4
A3 | A9
K3
A2 | A6
H2
A1 | A5
K4
A0 | A4
CS0
F9
CS | CAS
H9
WE | CKE
H3
RAS | BA2
F4
CAS | CS
H4
CKE | WE
J10
CK
J11
CK
P3
RDQS3 | RDQS2
P10
RDQS2 | RDQS3
D10
RDQS1 | RDQS0
D3
RDQS0 | RDQS1
P2
WDQS3 | WDQS2
P11
WDQS2 | WDQS3
D11
WDQS1 | WDQS0
D2
WDQS0 | WDQS1
N3
DM3 | DM2
N10
DM2 | DM3
E10
DM1 | DM0
E3
DM0 | DM1
U9
RESET
A4
ZQ
H1
VREF
H12
VREF#H12
VDDQ#A12
VDDQ#C1
VDDQ#C4
VDDQ#C9
VDDQ#C12
VDDQ#E1
VDDQ#E4
VDDQ#E9
VDDQ#E12
VDDQ#J4
VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9
VDDQ#N12
VDDQ#R1
VDDQ#R4
VDDQ#R9
VDDQ#R12
VDDQ#V1
VDDQ#V12
VDD#A11
VDD#F1
VDD#F12
VDD#M1
VDD#M12
VDD#V2
VDD#V11
VSSQ#B4
VSSQ#B9
VSSQ#B12
VSSQ#D1
VSSQ#D4
VSSQ#D9
VSSQ#D12
VSSQ#G2
VSSQ#G11
VSSQ#L2
VSSQ#L11
VSSQ#P1
VSSQ#P4
VSSQ#P9
VSSQ#P12
VSSQ#T1
VSSQ#T4
VSSQ#T9
VSSQ#T12
VSS#A10
VSS#G1
VSS#G12
VSS#L1
VSS#L12
VSS#V3
VSS#V10
VDDA#K12
VSSA#J12
GND | VDD
VDDQ
VDD
VSSQ
VSS
VDDA
VSSA
RFU2
RFU1
RFU0
MF
136BALL-GDDR3
FBVDD
C957
.1UF
10V
2.37K
R1
10%
1%
X5R
0402
NS
C959
5.49K
.1UF
R2
1%
10V
10%
X5R
0402
COMMON
GND
FBAD1
31
FBAD3
30
FBAD0
29
FBAD2
28
FBAD4
27
FBAD5
26
FBAD7
25
FBAD6
24
FBAD30
23
FBAD29
22
FBAD31
21
FBAD26
20
FBAD24
19
FBAD28
18
FBAD25
17
FBAD27
16
FBAD22
15
FBAD21
14
FBAD23
13
FBAD19
12
FBAD17
11
FBAD16
10
FBAD18
9
FBAD20
8
FBAD8
7
FBAD11
6
FBAD9
5
FBAD10
4
FBAD14
3
FBAD12
2
FBAD13
1
FBAD15
0
FBA_CMD7_0
18
FBA_CMD18
10
FBA_CMD10
16
FBA_CMD16
17
FBA_CMD17
20
FBA_CMD20
19
FBA_CMD19
23
FBA_CMD23
21
FBA_CMD21
22
FBA_CMD22
24
FBA_CMD24
0
FBA_CMD0
2
FBA_CMD2
3
FBA_CMD3
1
FBA_CMD1
8
FBA_CMD8
9
FBA_CMD9
FBA_CMD15
15
25
FBA_CMD25
11
FBA_CMD11
FBA_CLK0*
FBA_CLK0
FBADQS_RN0
FBADQS_RN3
FBADQS_RN2
FBADQS_RN1
FBADQS_WP0
FBADQS_WP3
FBADQS_WP2
FBADQS_WP1
FBADQM0
FBADQM3
FBADQM2
12
FBVDD
2.37K
R1
1%
0402
5.49K
R2
1%
0402
GND
R7161
FBADQM1
FBA_CMD12
240
1%
0603
COMMON
FBA_VREF_DATA0
FBA_VREF_ADDR0
FBVDD
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
FBVDD
A2
A11
F1
F12
M1
M12
U2
U11
B1
B4
B9
B12
GND
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
U3
U10
FBVDD
K1
K12
J12
J1
J3
J2
U4
GND
GND
7.1G<>
>3,6>
7.1G<>
>3,6>
7.1G<>
>3,6>
A9
GND
FBA Partition
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY
pin!!
Minimize the stub length!!
FBA_CMD4
FBA_CMD6
FBA_CMD5
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
6.3A>
6.3A>
6.3A>
FBADQM[7..0]
BI
FBADQS_RN[7..0]
BI
FBADQS_WP[7..0]
BI
FBVDD
R7148
120
0402
COMMON
5%
R7149
120
0402COMMON
5%
R7150
120
0402
COMMON
5%
R7151
120
0402
COMMON
5%
R7152
120
0402
COMMON
5%
R7153
120
0402COMMON
5%
R7154
120
0402
COMMON
5%
R7155
120
0402COMMON
5%
20.5G> >3,6>
FBADQM0
0
FBADQM1
1
FBADQM2
2
FBADQM3
3
FBADQM4
4
FBADQM5
5
FBADQM6
6
FBADQM7
7
FBADQS_RN0
0
FBADQS_RN1
1
FBADQS_RN2
2
FBADQS_RN3
3
FBADQS_RN4
4
FBADQS_RN5
5
FBADQS_RN6
6
FBADQS_RN7
7
FBADQS_WP0
0
FBADQS_WP1
1
FBADQS_WP2
2
FBADQS_WP3
3
FBADQS_WP4
4
FBADQS_WP5
5
FBADQS_WP6
6
FBADQS_WP7
7
20.5G> >3,6>
FBA_CMD[26..0]
3.2D> 4.1G< >3,6>
IN
20.5G> >3>
IN
FBVDD
C987
.1UF
10V
10%
X5R
0402
Hi Sub-Partition
COMMON
R7156
R7157
60.4R
60.4R
1%
1%
0402
0402
COMMON
COMMON
IN
IN
12
FBVDD
GND
R7162
2.37K
R1
1%
0402
COMMON
R7164
5.49K
R2
1%
0402
COMMON
GND
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)
VDDQ#J4
VDDQ#J9
VDD#A11
VDD#F1
VDD#F12
VDD#M1
VDD#M12
VDD#V2
VDD#V11
VSSQ#B4
VSSQ#B9
VSSQ#D1
VSSQ#D4
VSSQ#D9
VSSQ#L2
VSSQ#P1
VSSQ#P4
VSSQ#P9
VSSQ#T1
VSSQ#T4
VSSQ#T9
VSS#A10
VSS#G1
VSS#G12
VSS#L1
VSS#L12
VSS#V3
VSS#V10
FBVDD
A1
VDDQ
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
A2
VDD
A11
F1
F12
M1
M12
U2
U11
B1
VSSQ
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
VSS
A10
G1
G12
L1
L12
U3
U10
K1
VDDA
K12
J12
J1
VSSA
J3
RFU2
J2
RFU1
U4
RFU0
A9
MF
FBVDD
GND
FBVDD
GND
GND
GND
1
2
3
4
5
13.1G<> >3,6>
1
A A
BI
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
2
3.2D> 4.1G< >3,6>
R7158
60.4R
1%
0402
COMMON
IN
B B
3
20.5G> >3,6>
IN
20.5G> >3,6>
IN
C C
4
D D
5
ASSEMBLY
PAGE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
1
2
3
DETAIL
4
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
FBA 8Mx32 DDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA
CLK PU'S
E GC
5
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Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Custom
Date:
Tuesday, Nove mber 22 , 2005
6
7
Sheet of
8
10
4
22
FRAME BUFFER: PARTITION A
DECOUPLING
HGFEDCBA
1
Decoupling for FBA 0..31
PLACE NEAR MEMORY
C529
4.7UF
6.3V
10%
X5R
0603
COMMON
FBVDD PINS
C841
.1UF
10V
10%
X5R
0402
COMMON
C718
.01UF
25V
10%
X7R
0402
COMMON
PLACE NEAR MEMORY
FBVDDQ PINS
C642
0.47UF
6.3V
10%
X5R
0402
COMMON
C541
.1UF
10V
10%
X5R
0402
COMMON
C765
.1UF
10V
10%
X5R
0402
COMMON
C678
.01UF
25V
10%
X7R
0402
COMMON
C48
.01UF
25V
10%
X7R
0402
COMMON
C571
.1UF
10V
10%
X5R
0402
COMMON
C725
.01UF
25V
10%
X7R
0402
COMMON
C680
.01UF
16V
10%
X7R
0402
COMMON
C683
.01UF
25V
10%
X7R
0402
COMMON
C691
.1UF
10V
10%
X5R
0402
COMMON
GND
C682
.01UF
25V
10%
X7R
0402
COMMON
C767
0.47UF
6.3V
10%
X5R
0402
COMMON
C706
.01UF
25V
10%
X7R
0402
COMMON
C716
.01UF
25V
10%
X7R
0402
COMMON
C719
.01UF
25V
10%
X7R
0402
COMMON
C717
.01UF
25V
10%
X7R
0402
COMMON
GND
GND
GND
FBVDD
2
C832
1UF
10V
10%
X7R
0603
COMMON
FBVDD
3
4
C887
1UF
10V
10%
X7R
0603
COMMON
C749
1UF
10V
10%
X7R
0603
COMMON
C543
4.7UF
6.3V
10%
X5R
0603
COMMON
C641
4.7UF
6.3V
10%
X5R
0603
COMMON
C681
.1UF
10V
10%
X5R
0402
COMMON
C512
.1UF
10V
10%
X5R
0402
COMMON
C527
.1UF
10V
10%
X5R
0402
COMMON
C712
.1UF
10V
10%
X5R
0402
COMMON
Decoupling for FBA 32..63
PLACE NEAR MEMORY
C544
.1UF
10V
10%
X5R
0402
COMMON
C875
.1UF
10V
10%
X5R
0402
COMMON
FBVDD PINS
C902
C572
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
PLACE NEAR MEMORY
FBVDDQ PINS
C528
.1UF
10V
10%
X5R
0402
COMMON
C668
.1UF
10V
10%
X5R
0402
COMMON
C876
.01UF
25V
10%
X7R
0402
COMMON
C715
.1UF
10V
10%
X5R
0402
COMMON
C859
.01UF
25V
10%
X7R
0402
COMMON
FBVDD
FBVDD
C670
1UF
10V
10%
X7R
0603
COMMON
C562
1UF
10V
10%
X7R
0603
COMMON
C658
4.7UF
6.3V
10%
X5R
0603
COMMON
C578
4.7UF
6.3V
10%
X5R
0603
COMMON
C536
1UF
10V
10%
X7R
0603
COMMON
C542
4.7UF
6.3V
10%
X5R
0603
COMMON
C858
.01UF
16V
10%
X7R
0402
COMMON
C878
.01UF
25V
10%
X7R
0402
COMMON
C726
0.47UF
6.3V
10%
X5R
0402
COMMON
GND
C866
.01UF
25V
10%
X7R
0402
COMMON
C860
.01UF
25V
10%
X7R
0402
COMMON
C877
.01UF
25V
10%
X7R
0402
COMMON
C855
.01UF
25V
10%
X7R
0402
COMMON
C871
.01UF
25V
10%
X7R
0402
COMMON
C861
.01UF
25V
10%
X7R
0402
COMMON
C882
.01UF
25V
10%
X7R
0402
COMMON
C879
.01UF
25V
10%
X7R
0402
COMMON
GND
GND
GND
1
2
3
4
5
ASSEMBLY
PAGE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
FBA MEMORY FBVDD/Q
DECOUPLING CAPS
E GC
www.vinafix.vn
Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Date:
Custom
Tuesday, Nove mber 22 , 2005
5
Sheet of
5
10
22
5 FrameBuffer: Partition A
8Mx32 BGA136 DDR3
HGFEDCBA
FBA_CMD[26..0]
FBVDD
C990
.1UF
10V
10%
X5R
0402
COMMON
R7181
60.4R
1%
0402
COMMON
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)
FBAD[63..0]
Low Sub-Partition
20.5G> >3>
GND
C961
R7185
.1UF
10V
10%
COMMON
X5R
0402
NS
C964
R7188
.1UF
10V
10%
COMMON
X5R
0402
COMMON
FBA_ZQ0
R7189
0402
COMMON
R7191
0402
COMMON
U511
T3
DQ31 | DQ23
T2
DQ30 | DQ22
R3
DQ29 | DQ21
R2
DQ28 | DQ20
M3
DQ27 | DQ19
N2
DQ26 | DQ18
L3
DQ25 | DQ17
M2
DQ24 | DQ16
T10
DQ23 | DQ31
T11
DQ22 | DQ30
R10
DQ21 | DQ29
R11
DQ20 | DQ28
M10
DQ19 | DQ27
N11
DQ18 | DQ26
L10
DQ17 | DQ25
M11
DQ16 | DQ24
G10
DQ15 | DQ7
F11
DQ14 | DQ6
F10
DQ13 | DQ5
E11
DQ12 | DQ4
C10
DQ11 | DQ3
C11
DQ10 | DQ2
B10
DQ9 | DQ1
B11
DQ8 | DQ0
G3
DQ7 | DQ15
F2
DQ6 | DQ14
F3
DQ5 | DQ13
E2
DQ4 | DQ12
C3
DQ3 | DQ11
C2
DQ2 | DQ10
B3
DQ1 | DQ9
B2
DQ0 | DQ8
H10
BA2 | RAS
G9
BA1 | BA0
G4
BA0 | BA1
L4
A11 | A7
K2
A10 | A8
M9
A9 | A3
K11
A8/AP | A10
L9
A7 | A11
K10
A6 | A2
H11
A5 | A1
K9
A4 | A0
M4
A3 | A9
K3
A2 | A6
H2
A1 | A5
K4
A0 | A4
CS1
F9
CS | CAS
H9
WE | CKE
H3
RAS | BA2
F4
CAS | CS
H4
CKE | WE
J10
CK
J11
CK
P3
RDQS3 | RDQS2
P10
RDQS2 | RDQS3
D10
RDQS1 | RDQS0
D3
RDQS0 | RDQS1
P2
WDQS3 | WDQS2
P11
WDQS2 | WDQS3
D11
WDQS1 | WDQS0
D2
WDQS0 | WDQS1
N3
DM3 | DM2
N10
DM2 | DM3
E10
DM1 | DM0
E3
DM0 | DM1
U9
RESET
A4
ZQ
H1
VREF
H12
VREF#H12
VDDQ#A12
VDDQ#C1
VDDQ#C4
VDDQ#C9
VDDQ#C12
VDDQ#E1
VDDQ#E4
VDDQ#E9
VDDQ#E12
VDDQ#J4
VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9
VDDQ#N12
VDDQ#R1
VDDQ#R4
VDDQ#R9
VDDQ#R12
VDDQ#V1
VDDQ#V12
VDD#A11
VDD#F1
VDD#F12
VDD#M1
VDD#M12
VDD#V2
VDD#V11
VSSQ#B4
VSSQ#B9
VSSQ#B12
VSSQ#D1
VSSQ#D4
VSSQ#D9
VSSQ#D12
VSSQ#G2
VSSQ#G11
VSSQ#L2
VSSQ#L11
VSSQ#P1
VSSQ#P4
VSSQ#P9
VSSQ#P12
VSSQ#T1
VSSQ#T4
VSSQ#T9
VSSQ#T12
VSS#A10
VSS#G1
VSS#G12
VSS#L1
VSS#L12
VSS#V3
VSS#V10
VDDA#K12
VSSA#J12
GND | VDD
VDDQ
VDD
VSSQ
VSS
VDDA
VSSA
RFU2
RFU1
RFU0
MF
136BALL-GDDR3
FBVDD
C965
.1UF
10V
2.37K
R1
10%
1%
X5R
0402
NS
C967
.1UF
5.49K
R2
10V
1%
10%
X5R
0402
COMMON
GND
FBAD30
30
FBAD29
29
FBAD31
31
FBAD26
26
FBAD24
24
FBAD28
28
FBAD25
25
FBAD27
27
FBAD1
1
FBAD3
3
FBAD0
0
FBAD2
2
FBAD4
4
FBAD5
5
FBAD7
7
FBAD6
6
FBAD8
8
FBAD11
11
FBAD9
9
FBAD10
10
FBAD14
14
FBAD12
12
FBAD13
13
FBAD15
15
FBAD22
22
FBAD21
21
FBAD23
23
FBAD19
19
FBAD17
17
FBAD16
16
FBAD18
18
FBAD20
20
18
FBA_CMD18
10
FBA_CMD10
16
FBA_CMD16
17
FBA_CMD17
20
FBA_CMD20
19
FBA_CMD19
23
FBA_CMD23
21
FBA_CMD21
22
FBA_CMD22
24
FBA_CMD24
0
FBA_CMD0
2
FBA_CMD2
3
FBA_CMD3
1
FBA_CMD1
FBA_CMD7_1
IN
9
FBA_CMD9
15
FBA_CMD15
25
FBA_CMD25
FBA_CMD11
FBA_CLK0*
FBA_CLK0
FBADQS_RN3
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_WP3
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQM3
FBADQM0
FBADQM1
12
FBVDD
2.37K
R1
1%
0402
5.49K
R2
1%
0402
GND
R7183
FBADQM2
FBA_CMD12
240
1%
0603
COMMON
FBA_VREF_DATA0
FBA_VREF_ADDR0
FBVDD
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
FBVDD
A2
A11
F1
F12
M1
M12
U2
U11
B1
B4
B9
B12
GND
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
U3
U10
FBVDD
K1
K12
J12
J1
J3
J2
U4
GND
GND
7.1G<>
>3,4>
7.1G<>
>3,4>
7.1G<>
>3,4>
A9
GND
ASSEMBLY
PAGE
DETAIL
FBA Partition
Termination for Sub-Partition and CLK
MUST BE PLACED as close as possible to
the BGA memory on the line BEFORE the
MEMORY
pin!!
Minimize the stub length!!
FBA_CMD4
FBA_CMD6
FBA_CMD5
FBA_CMD13
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
6.3A>
6.3A>
6.3A>
FBADQM[7..0]
BI
FBADQS_RN[7..0]
BI
FBADQS_WP[7..0]
BI
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
FBA 8Mx32 DDR3 MEMORIES, FBA COMMAND BUS PU'S, FBA
CLK PU'S
FBADQM0
0
FBADQM1
1
FBADQM2
2
FBADQM3
3
FBADQM4
4
FBADQM5
5
FBADQM6
6
FBADQM7
7
0
1
2
3
4
5
6
7
FBADQS_WP0
0
FBADQS_WP1
1
FBADQS_WP2
2
FBADQS_WP3
3
FBADQS_WP4
4
FBADQS_WP5
5
FBADQS_WP6
6
FBADQS_WP7
7
120
COMMON
5%
120
5%
120
COMMON
5%
120
COMMON
5%
120
COMMON
5%
120
5%
120
COMMON
5%
120
5%
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
R7170
0402
R7171
0402COMMON
R7172
0402
R7173
0402
R7174
0402
R7175
0402COMMON
R7176
0402
R7177
0402COMMON
FBVDD
20.5G> >3,4>
20.5G> >3,4>
E GC
13.1G<> >3,4>
1
BI
ZQ = 6x desired output
DDR3:
impedence of DQ drivers
Impedence = 240 / 6 = 40 ohm
2
3.2D> 4.1G< >3,4>
IN
R7180
60.4R
3
20.5G> >3,4>
IN
20.5G> >3,4>
IN
1%
0402
COMMON
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
1
2
3
4
5
R7187
2.37K
1%
0402
COMMON
R7190
5.49K
1%
0402
COMMON
FBVDD
U510
T3
DQ31 | DQ23
T2
DQ30 | DQ22
DQ29 | DQ21
DQ28 | DQ20
DQ27 | DQ19
DQ26 | DQ18
DQ25 | DQ17
DQ24 | DQ16
DQ23 | DQ31
DQ22 | DQ30
DQ21 | DQ29
DQ20 | DQ28
DQ19 | DQ27
DQ18 | DQ26
DQ17 | DQ25
DQ16 | DQ24
DQ15 | DQ7
DQ14 | DQ6
DQ13 | DQ5
DQ12 | DQ4
DQ11 | DQ3
DQ10 | DQ2
DQ9 | DQ1
DQ8 | DQ0
DQ7 | DQ15
DQ6 | DQ14
DQ5 | DQ13
DQ4 | DQ12
DQ3 | DQ11
DQ2 | DQ10
DQ1 | DQ9
DQ0 | DQ8
BA2 | RAS
BA1 | BA0
BA0 | BA1
A11 | A7
A10 | A8
A9 | A3
A8/AP | A10
A7 | A11
A6 | A2
A5 | A1
A4 | A0
A3 | A9
A2 | A6
A1 | A5
A0 | A4
CS | CAS
WE | CKE
RAS | BA2
CAS | CS
CKE | WE
CK
CK
RDQS3 | RDQS2
RDQS2 | RDQS3
RDQS1 | RDQS0
RDQS0 | RDQS1
WDQS3 | WDQS2
WDQS2 | WDQS3
WDQS1 | WDQS0
WDQS0 | WDQS1
DM3 | DM2
DM2 | DM3
DM1 | DM0
DM0 | DM1
RESET
ZQ
VREF
VREF#H12
VDDQ#A12
VDDQ#C12
VDDQ#E12
VDDQ#N12
VDDQ#R12
VDDQ#V12
VSSQ#B12
VSSQ#D12
VSSQ#G11
VSSQ#L11
VSSQ#P12
VSSQ#T12
VDDA#K12
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11
G3
F2
F3
E2
C3
C2
B3
B2
H10
G9
G4
L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4
CS1
F9
H9
H3
F4
H4
J10
J11
P3
P10
D10
D3
P2
P11
D11
D2
N3
N10
E10
E3
U9
A4
H1
H12
136BALL-GDDR3
C963
.1UF
10V
R1
10%
X5R
0402
NS
C966
.1UF
R2
10V
10%
X5R
0402
COMMON
GND
FBAD38
38
FBAD39
39
FBAD37
37
FBAD36
36
FBAD35
35
FBAD32
32
FBAD33
33
FBAD34
34
FBAD58
58
FBAD62
62
FBAD56
56
FBAD59
59
FBAD57
57
FBAD60
60
FBAD63
63
FBAD61
61
FBAD45
45
FBAD46
46
FBAD40
40
FBAD47
47
FBAD41
41
FBAD43
43
FBAD42
42
FBAD44
44
FBAD55
55
FBAD52
52
FBAD54
54
FBAD53
53
FBAD49
49
FBAD51
51
FBAD48
48
FBAD50
FBA_CMD[26..0]
3.2D> 4.1G< >3,4>
IN
FBVDD
C989
.1UF
10V
10%
X5R
0402
Hi Sub-Partition
COMMON
R7179
R7178
60.4R
1%
0402
COMMON
IN
IN
60.4R
1%
0402
COMMON
20.5G> >3>
12
R7184
0402
COMMON
R7186
0402
COMMON
VREF = FBVDDQ * R2/(R1 + R2)
DDR3:
VREF = 0.70 * FBVDDQ
1.26V = 1.8V * 2.7K/(1.15K + 2.7K)
50
18
FBA_CMD18
10
FBA_CMD10
16
FBA_CMD16
17
FBA_CMD17
20
FBA_CMD20
19
FBA_CMD19
23
FBA_CMD23
21
FBA_CMD21
6
FBA_CMD6
5
FBA_CMD5
4
FBA_CMD4
13
FBA_CMD13
3
FBA_CMD3
1
FBA_CMD1
FBA_CMD7_1
IN
9
FBA_CMD9
FBA_CMD15
15
FBA_CMD25
25
11
FBA_CMD11
FBA_CLK1*
FBA_CLK1
FBADQS_RN4
FBADQS_RN7
FBADQS_RN5
FBADQS_RN6
FBADQS_WP4
FBADQS_WP7
FBADQS_WP5
FBADQS_WP6
FBADQM4
FBADQM7
FBADQM5
FBADQM6
C960
FBA_CMD12
.1UF
10V
FBA_ZQ1
R7182
10%
X5R
0402
240
FBA_VREF_DATA1
NS
FBVDD
GND
1%
0603
COMMON
FBA_VREF_ADDR1
C962
.1UF
10V
10%
X5R
2.37K
R1
0402
1%
COMMON
5.49K
R2
1%
GND
VDDQ#C1
VDDQ#C4
VDDQ#C9
VDDQ#E1
VDDQ#E4
VDDQ#E9
VDDQ#J4
VDDQ#J9
VDDQ#N1
VDDQ#N4
VDDQ#N9
VDDQ#R1
VDDQ#R4
VDDQ#R9
VDDQ#V1
VDD#A11
VDD#F1
VDD#F12
VDD#M1
VDD#M12
VDD#V2
VDD#V11
VSSQ#B4
VSSQ#B9
VSSQ#D1
VSSQ#D4
VSSQ#D9
VSSQ#G2
VSSQ#L2
VSSQ#P1
VSSQ#P4
VSSQ#P9
VSSQ#T1
VSSQ#T4
VSSQ#T9
VSS#A10
VSS#G1
VSS#G12
VSS#L1
VSS#L12
VSS#V3
VSS#V10
VSSA#J12
GND | VDD
FBVDD
A1
VDDQ
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
U1
U12
A2
VDD
A11
F1
F12
M1
M12
U2
U11
B1
VSSQ
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
VSS
A10
G1
G12
L1
L12
U3
U10
K1
VDDA
K12
J12
J1
VSSA
J3
RFU2
J2
RFU1
U4
RFU0
A9
MF
FBVDD
GND
FBVDD
GND
GND
GND
Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Date:
Custom
Tuesday, Nove mber 22 , 2005
Sheet of
10
6
22
www.vinafix.vn
7.1G<> 7.4B<> >8,10>
1
2
7.1G<>
>8,10>
3
7.4B<>
7.5B<> >8,10>
7.2G<>
7.1G<>
7.1G<> 7.2G<> 7.4B<> >8,10>
4
5
FBCD[63..0]
BI
FBCD0
0
FBCD1
1
FBCD2
2
FBCD3
3
FBCD4
4
FBCD5
5
FBCD6
6
FBCD7
7
FBCD8
8
FBCD9
9
FBCD10
10
FBCD11
11
FBCD12
12
FBCD13
13
FBCD14
14
FBCD15
15
FBCD16
16
FBCD17
17
FBCD18
18
FBCD19
19
FBCD20
20
FBCD21
21
FBCD22
22
FBCD23
23
FBCD24
24
FBCD25
25
FBCD26
26
FBCD27
27
FBCD28
28
FBCD29
29
FBCD30
30
FBCD31
31
FBCD32
32
FBCD33
33
FBCD34
34
FBCD35
35
FBCD36
36
FBCD37
37
FBCD38
38
FBCD39
39
FBCD40
40
FBCD41
41
FBCD42
42
FBCD43
43
FBCD44
44
FBCD45
45
FBCD46
46
FBCD47
47
FBCD48
48
FBCD49
49
FBCD50
50
FBCD51
51
FBCD52
52
FBCD53
53
FBCD54
54
FBCD55
55
FBCD56
56
FBCD57
57
FBCD58
58
FBCD59
59
FBCD60
60
FBCD61
61
FBCD62
62
FBCD63
63
FBCDQM[7..0]
OUT
FBCDQS_WP[7..0]
BI
FBCDQS_RN[7..0]
BI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
TP_FBC_VREF
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7
U11C
BGA820_P10_33X33MM
COMMON
3/14 FBC
B7
FBCD0
A7
FBCD1
C7
FBCD2
A2
FBCD3
B2
FBCD4
C4
FBCD5
A5
FBCD6
B5
FBCD7
F9
FBCD8
F10
FBCD9
D12
FBCD10
D9
FBCD11
E12
FBCD12
D11
FBCD13
E8
FBCD14
D8
FBCD15
E7
FBCD16
F7
FBCD17
D6
FBCD18
D5
FBCD19
D3
FBCD20
E4
FBCD21
C3
FBCD22
B4
FBCD23
C10
FBCD24
B10
FBCD25
C8
FBCD26
A10
FBCD27
C11
FBCD28
C12
FBCD29
A11
FBCD30
B11
FBCD31
B28
FBCD32
C27
FBCD33
C26
FBCD34
B26
FBCD35
C30
FBCD36
B31
FBCD37
C29
FBCD38
A31
FBCD39
D28
FBCD40
D27
FBCD41
F26
FBCD42
D24
FBCD43
E23
FBCD44
E26
FBCD45
E24
FBCD46
F23
FBCD47
B23
FBCD48
A23
FBCD49
C25
FBCD50
C23
FBCD51
A22
FBCD52
C22
FBCD53
C21
FBCD54
B22
FBCD55
E22
FBCD56
D22
FBCD57
D21
FBCD58
E21
FBCD59
E18
FBCD60
D19
FBCD61
D18
FBCD62
E19
FBCD63
A4
FBCDQM0
E11
FBCDQM1
F5
FBCDQM2
C9
FBCDQM3
C28
FBCDQM4
F24
FBCDQM5
C24
FBCDQM6
E20
FBCDQM7
C5
FBCDQS_WP0
E10
FBCDQS_WP1
E5
FBCDQS_WP2
B8
FBCDQS_WP3
A29
FBCDQS_WP4
D25
FBCDQS_WP5
B25
FBCDQS_WP6
F20
FBCDQS_WP7
C6
FBCDQS_RN0
E9
FBCDQS_RN1
E6
FBCDQS_RN2
A8
FBCDQS_RN3
B29
FBCDQS_RN4
E25
FBCDQS_RN5
A25
FBCDQS_RN6
F21
FBCDQS_RN7
A28
FB_VREF2
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
RFU
RFU
FBC_DEBUG
FBC_REFCLK
FBC_REFCLK
FBC_PLLVDD
FBC_PLLAVDD
FBC_PLLGND
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
AA23
AB23
H16
H17
J10
J23
J24
J9
K11
K12
K21
K22
K24
K9
L23
M23
T25
U25
C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20
E13
F13
F18
E17
C20
D1
F12
B1
C1
G8
G10
G9
K26
H26
J26
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
NTP_FBC_CMD<26>
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
TP
NOW
TP_FBC_DBI0
TP_FBC_DBI1
TP_FBC_DEBUG
FBC_REFCLK
FBC_REFCLK*
FBC_PLLVDD
FBC_PLLAVDD
GND
FBCAL_PD
FBCAL_PU
FBCAL_TERM
Place near
BGA
Value
TBD
FBC_CMD[26..0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
7.1G< 7.2A< >8,10>
OUT
7.1G< 7.2A< >8,10>
OUT
7.1G< 7.2D< >8,10>
OUT
7.1G< 7.2D< >8,10>
OUT
R624
49.9
04021%COMMON
R621
49.9
0402
COMMON
1%
R625
0
0402 COMM ON
5%
FBVDD
OUT
R7194
0R
0402
1%
COMMON
GND
R7195
0R
0402
1%
COMMON
7.1A<
GND
GND
FBVDD
C782
1UF
10V
10%
X7R
0603
COMMON
7.1G<
>8,10>
OUT
OUT
PLACE close to
GPU
14.3A< >8>
14.3A< >10>
C713
.01UF
16V
10%
X7R
0402
COMMON
C696
.01UF
16V
10%
X7R
0402
COMMON
R45
100
1%
0402
COMMON
R46
100
1%
0402
COMMON
FBVDD
R44
100
1%
0402
COMMON
R43
100
1%
0402
COMMON
GND
C701
C669
.1UF
1UF
10V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C688
C677
.1UF
1UF
10V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
Place close to balls
ASSEMBLY
PAGE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE
BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS
OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE,
TRADE PRACTICE, OR INDUSTRY STANDARDS.
AB D F H
DETAIL
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES
AND BOM NOT FINAL
FBC MEMORY INTERFACE,
GPU FBVTT
E GC
150-220R@100MHz
LB506
0603 COMMO N
150-220R@100MHz
LB508
COMMON0603
150-220R@100MHz
LB538
0603 COMMO N
DIFFPAIR MIN_LINE_WIDTH
NET NET_SPACING_RULE
FBC_REFCLK
IN
FBC_REFCLK*
IN
FBC_PLLVDD
IN
FBC_PLLAVDD
IN
PLACE NEAR
GPU
4MIL 10MIL
10MIL
10MIL
FBVDD
R606
10K
5%
0402
NS
FBC_CMD11FBC_CMD12
R608
R7241
10K
?
0402
COMMON
10K
5%
0402
COMMON
GND
GND
CKE Stuff options for DDR3 configation for
on-die terminations at the memory
IMPORTANT FOR POWER ON INITIALIZATION OF
DDR3 MEMS
DDR3: DETERMINES THE ODT VALUE FOR ADDR AND
CONTROL PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
A3V3
C653
4.7UF
6.3V
10%
X5R
0603
COMMON
NVVDD
GND
C657
4.7UF
6.3V
FBA_AVDD Connection is TBD. This may not be tied on the Package
10%
X5R
0603
COMMON
PEX1V2
C991
4.7UF
6.3V
10%
X5R
0603
COMMON
GND
Micro-Star International Co., LTD.
V045 base on P216 Modify
Size Document Number Rev
Custom
Date:
Tuesday, Nove mber 22 , 2005
HGFEDCBA
10MIL
Sheet of
1
2
3
4
5
10
22
7
www.vinafix.vn
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