MSI ms-7501 Schematic Ver:0C
5
4
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PageTitle
Cover Sheet 1
Block Diagram 2
Device Map
D D
3
GPIO Table 4
Clock Distribution
CPU:AM2R2
DDR2 DIMM(Dual Channel)
NB:RX780/RS780
5
6,7,8,9
10,11,12
13 ~ 17
CLK GEN ICS9LPRS475 18
SB:SB700 19 ~ 23
Giga LAN_BOARDCOM 5754 24
C C
PCIE x 16 , x1 Slots.
PCI Slot1
VGA /THERMAL SENSOR
DVI CONNECTOR / BLEED OFF
SPI ROM / FAN / LPT
USB Conn.
Azalia Codec
SMSC-5327 / TPM
B B
KB / MS / COM / FDD
ACPI Power Controler
25
26
27
28
29
30
31
32
33
34
MS-7500
CPU:
AMD AM2R2+ Socket940
System Chipset:
North Bridge --South Bridge --- AMD-ATI SB700
OnBoard Chipset:
Clock Gen:Seligo P625
AZALIA Codec:ADI1884
LAN(PHY):BOARDCOM 5754
SIO:SMSC 5327
Flash ROM: 32 MB SPI (CHIP)
Main Memory:
DDRII (667/800MHz) * 4 (Dual Channel)
Expansion Slots:
PCI Express (X16) Slot * 1
PCI Express (X1) Slot * 2
PCI Slot * 1
PWM:
Controller:ISL6323 ( 4-Phase 89W )
ACPI:
INTERSIL 6545
0C
AMD-ATI RX780/RS780
BTX(264.16mm X 266.4mm)
( 5764 )
System Regulators
VRM-ISL6323
Front Panel / ATX CONNECTOR
For EMI
BOM - Option Parts
POWER OK MAP
RESET MAP
A A
Power Sequence
Power Delivery
History
5
35~36
37
38
39
40
41
42
43
44
45
4
Other:
FDD *1
SATA(SATA2-300MB/s) *4
USB2.0 *10 (Rear*6 Front*4)
DVI*1
VGA PORT *1
PRINT Header *1
TPM *1
COM PORT *1
COM Header *1
3
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Cover Sheet
Cover Sheet
Cover Sheet
MS-7500
MS-7500
MS-7500
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148Monday, October 29, 2007
148Monday, October 29, 2007
148Monday, October 29, 2007
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AMD CONFIDENTIAL
RX780/RS780 + SB700 CUSTOMER DESKTOP REFERENCE DESIGN
D D
AMD
AM2/AM2g2
Clock
Generator
Seligo P625
HyperTransport
Link
AM2 SOCKET
OUT
IN
16x16
DDRII 400,533,667,800
128bit
DDRII 400,533,667,800
UNBUFFERED
DDRII DIMM1
UNBUFFERED
DDRII DIMM2
DDRII FIRST LOGICAL DIMM DDRII SECOND LOGICAL DIMM
RS740/RS780
HyperTransport LINK0 CPU I/F
DVI CON
C C
VGA CON
1CH TMDS
DX10 IGP( RS780)
LVDS/TVOUT/TMDS(RS780/740)
DISPLAY PORT X2 (RS780)
Side Port Memory(RS780/740)
1 X16 PCIE I/F
1 X4 PCIE I/F WITH SB
I2C I/F
16X
6 1X PCIE INTERFACE
BOOTSTRAPS
ROM(NB)
PCIE
16X
SLOT
UNBUFFERED
DDRII DIMM3
UNBUFFERED
DDRII DIMM4
4X
PCIE
USB-2USB-6 USB-3USB-4USB-5
USB-1
USB-0
USB 2.0
SB700
USB2.0 (12)+ 1.1(2)
PCIE X1
SLOT
HD AUDIO I/F
PCIE X1
SLOT
SATA II (6 PORTS)
AZALIA HD AUDIO
USB-7
B B
USB-8 USB-9
ATA 66/100/133
SPI I/F
LPC I/F(S5)
SATA II I/F
GIGA LAN
BCM5754/5764
HD AUDIO ADI 1884
SATA#0 SATA#1 SATA#2 SATA#3
ACPI 1.1
SPI ROM
SPI I/F
INT RTC
HW MONITOR
PCI BUS
PCI SLOT
#1
DESKTOP AM2/AM2g2
POWER
A A
DDR2
MEMORY
POWER
5
RS780
CORE POWER
+1.1V, +1.2V
POWER
4
PCI/PCI BDGE
SMSC SIO
5327
KBD
MOUSE
COM
3
FLOPPY
LPC I/F
2
TPM 1.2
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Block Diagram
Block Diagram
Block Diagram
MS-7500
MS-7500
MS-7500
1
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248Monday, October 29, 2007
248Monday, October 29, 2007
248Monday, October 29, 2007
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DDR DIMM Config.
DEVICE
DIMM 2
CH-A
D D
DIMM 4
10100000B
10100010B
CH-A
DIMM 1
CH-B
DIMM 3
CH-B
USB
Rear
C C
Front
10100001B
10100011B
Port DATA +/-
QUAD STACK
LAN_USB1
FRONT USB
MEDIA CARD
READER
CLOCKADDRESS
MEM_MA0_CLK_H0/L0
MEM_MA0_CLK_H1/L1
MEM_MA0_CLK_H2/L2
MEM_MA1_CLK_H0/L0
MEM_MA1_CLK_H1/L1
MEM_MA1_CLK_H2/L2
MEM_MB0_CLK_H0/L0
MEM_MB0_CLK_H1/L1
MEM_MB0_CLK_H2/L2
MEM_MB1_CLK_H0/L0
MEM_MB1_CLK_H1/L1
MEM_MB1_CLK_H2/L2
OC#
USB0USB0+
USB1USB1+
USB2USB2+
USB3USB3+
USB4USB4+
USB5USB5+
USB6USB6+
USB7USB7+
USB8USB8+
USB9USB9+
USB_OC#0
( OC#0~1 )
USB_OC#1
( OC#2 )
USB_OC#2
( OC#3 )
USB_OC#3
( OC#4 )
PCI Config.
DEVICE MCP1 INT Pin
PCI_INT#E
PCI Slot 1
PCI_INT#F
PCI_INT#G
PCI_INT#H
TPM
SIO
PCI RESET DEVICE
SB 700
Signals
PCIRST#
PE_RST#
PE_RST#
REQ#/GNT#
PCI_REQ0#
PCI_GNT0#
Target
PCISLOT1
TPM_RST#
LPC/SIO
IDSEL
AD20
CLOCK
PCICLK2_SLOT1
(PCICLK2)
LPCCLK0
LPCCLK1
B B
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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Date: Sheet
MICRO-STAR INt'L CO., LTD.
Device Map
Device Map
Device Map
MS-7500
MS-7500
MS-7500
348Monday, October 29, 2007
348Monday, October 29, 2007
348Monday, October 29, 2007
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0C
0C
0C
5
D D
C C
4
3
2
1
B B
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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Date: Sheet
MICRO-STAR INt'L CO., LTD.
GPIO Table
GPIO Table
GPIO Table
MS-7500
MS-7500
MS-7500
448Monday, October 29, 2007
448Monday, October 29, 2007
448Monday, October 29, 2007
of
of
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1
0C
0C
0C
5
D D
DIMM3 DIMM4
4
3
2
1
DIMM1 DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU
C C
B B
AM2 SOCKET
3 PAIR MEM CLK
3 PAIR MEM CLK
(RX780)
25MHZ OSC INPUT
AMD NB
RX780/RS780
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 1 LANES
PCIE GBE BCM 5754
25MHz
SATA
1 PAIR CPU CLK
200MHZ
HT REFCLK
100MHz DIFF(RX780/RS780)
EXTERNAL
CLK GEN.
NB-OSCIN
14.318MHZ
NB ALINK PCIE CLK
100MHZ
SB ALINK PCIE CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
RTC_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK2
33MHZ
LPC_CLK0
33MHZ
32.768 KHZ
LPC_CLK1
33MHZ
32.768 KHZ
25MHz
PCI SLOT 0
TPM
SUPER IO
SMSC 5327
HD AUDIO
SIO 14M
14.318MHZ
32.768KHz
14.31818MHz
A A
External clock mode
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Clock Distribution
Clock Distribution
Clock Distribution
MS-7500
MS-7500
MS-7500
548Monday, October 29, 2007
548Monday, October 29, 2007
548Monday, October 29, 2007
of
of
1
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0C
0C
0C
5
XU1A
XU1A
HYPERTRANSPORT
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
ZIF-SOCKET940
ZIF-SOCKET940
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
CLKIP113
CLKIN113
CLKIP013
CLKIN013
CTLIP113 CTLOP1 13
CTLIN113
D D
CTLIP013
CTLIN013
C C
CTLIP1
CTLIN1
CTLIP0
CTLIN0
CADIP15
CADIN15
CADIP14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
N12-9400040-L06
B B
15u
CADOP15
CADON15
CADOP14
CADON14CADIN14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8
CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3
CADOP2
CADON2
CADOP1
CADON1
CADOP0
CADON0
4
CLKOP1 13
CLKON1 13
CLKOP0 13
CLKON0 13
CTLON1 13
CTLOP0 13
CTLON0 13
As the SIC and SID are
not recommended to use for
the rev. F processors.
5/10/10
If SI is not used,the SID pin can
be left unconnector and SIC should
have a 390 ohm pull-up to VDDIO
(CPU schematic checklist item 5-22
5-23)
AMD Sensor bus
X_N-2N7002_SOT23
X_N-2N7002_SOT23
THERM_SIC
THERM_SID
G
Q60
Q60
Q61 X_N-2N7002_SOT23Q61 X_N-2N7002_SOT23
HP Recommand 2007/08/06
3
CADIP[0..15]13
CADIN[0..15]13
CADOP[0..15]13
CADON[0..15]13
Layout : Place R63
within 0.5 inch of CPU
R390 changed from 1K to
390 ohm 2007/10/18
VCC5
R339
R339
X_8.2K/4
X_8.2K/4
C70
C70
X_0.1uf/10V/X7R/4
X_0.1uf/10V/X7R/4
R338
R338
X_8.2K/4
X_8.2K/4
SMB_CLK_SENSE
DS
G
SMB_DATA_SENSE
DS
For S3 issue(LDT RST can not still low)
-LDTSTOP15,19
-LDT_RST15,19
LDT_PWRGD19
VCC_DDR
CADIP[0..15]
CADIN[0..15]
CADOP[0..15]
CADON[0..15]
C64
C64
392pf/50V/X7R/6
CPUCLKO_H18
CPUCLKO_L18
SMB_CLK_SENSE 27,32
SMB_DATA_SENSE 27,32
392pf/50V/X7R/6
R63
R63
169/6/1
169/6/1
C67
C67
392pf/50V/X7R/6
392pf/50V/X7R/6
VCC_DDR
R99
R99
X_1K/4
X_1K/4
VCC_DDR
R105
R105
39.2/6/1
39.2/6/1
R106
R106
39.2/6/1
39.2/6/1
RN3
-LDTSTOP LDT_STOP#_L
-LDT_RST LDT_RST#_L
LDT_PWRGD LDT_PWRGD_L
RN3
1
3
5
7
8P4R-0R0402
8P4R-0R0402
CPU_PRESENT_L32
VDDA_25
R101
R101
390/4
390/4
THERM_SIC
THERM_SID
5/10/10
R98
R98
X_300/4
X_300/4
MEMZN
MEMZP
VCC_DDR
2
4
6
8
47nH/300mA/8
47nH/300mA/8
2 1
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
CPU_VTT_SENSE35
CPU_PRESENT_L
L1
L1
5/5/20
R107 changed from 1K to
10M ohm 2007/10/18
VCC_DDR
COREFB_H37
COREFB_L37
C53
C53
CPUCLKIN_H
CPUCLKIN_L
VBAT
R107 10M/4R107 10M/4
10/5/10
R59 510/6R59 510/6
R62 510/6R62 510/6
C59
C59
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
CPU_TEST25_H
CPU_TEST25_L
R50 300/4R50 300/4
R51 300/4R51 300/4
TP5TP5
TP7TP7
TP8TP8
TP4TP4
TP12TP12
C57
C57
332pf/50V/X7R/4
332pf/50V/X7R/4
LDT_PWRGD_L
LDT_STOP#_L
LDT_RST#_L
CPU_PRESENT_L
R655 1K/6R655 1K/6
R561 0/4R561 0/4
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB_H
COREFB_L
CPU_VTT_SENSE
CPU_M_VREF
+1.8V_S0
VDDA25
AL10
AJ10
AH10
AH11
AJ11
RN7
RN7
300R_8P4R/6
300R_8P4R/6
1
3
5
7
C10
D10
AL3
AL6
AK6
AL4
AK4
AL9
E12
F12
A10
B10
F10
AJ7
AH9
AJ5
AH7
AJ6
XU1D
XU1D
MISC
MISC
VDDA1
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
CPU_PRESENT_L
SIC
SID
ALERT_L
SA0
TDI
TRST_L
TCK
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
E9
TEST18
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
TEST12
E5
TEST7
TEST6
TEST3
TEST2
KEY/VSS1
KEY/VSS2
PLATFORM_TYPE
CORE_TYPE
SVC/VID(3)
SVD/VID(2)
PVIEN/VID(1)
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
TEST29_H
TEST29_L
TEST28_H
TEST28_L
N12-9400040-L06
2
LDT_PWRGD_L
4
LDT_RST#_L
6
LDT_STOP#_L
8
2
H22
AE9
F2
G5
D2
VID(5)
D1
VID(4)
C1
E3
E2
E1
VID(0)
AG9
AG8
AK7
AL7
AK10
TDO
B6
DBRDY
AK11
AL11
G4
G3
F1
PSI_L
V8
HTREF1
V7
HTREF0
C11
D11
AK8
TEST24
AH8
TEST23
AJ9
TEST22
AL8
TEST21
AJ8
TEST20
J10
H9
AK9
TEST27
AK5
TEST26
G7
TEST10
D4
TEST8
CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST_L
CPU_TDO
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
CPU_CORE_TYPE
VID5
VID4
VID3/SVC
VID2/SVD
VID1/SEL
VID0/VFIXEN
CPU_THRIP#
PROCHOT#
CPU_TDO
CPU_DBRDY
CPU_VDDIOFB_H
CPU_VDDIOFB_L
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_PSI_L
HTREF1
HTREF0
FBCLKOUT
FBCLKOUT#
8/5/20
TP14TP14
R110 300/4R110 300/4
VCC_DDR
C487
C487
X_300/4
X_300/4
VCC_DDR
11
13
15
17
19
21
23
1
3
5
7
9
R64
R64
TP11TP11
TP6TP6
R56
R56
80.6/6/1
80.6/6/1
R75
R75
X_300/4
X_300/4
THERMDC_CPU 27
THERMDA_CPU 27
TP20TP20
TP16TP16
TP18TP18
TP13TP13
KEY
KEY
X_hdr_k8_hdt_B
X_hdr_k8_hdt_B
Solder side
VCC_DDR
R635
R635
R636
R636
1K/6
1K/6
1K/6
1K/6
5/10/10
CPU_VDDIOFB_H 35
CPU_VDDIOFB_L 35
CPU_VDDNB_FB_H 37
CPU_VDDNB_FB_L 37
Layout :
1. Place R56
within 0.5 inch
R100
R100
300/4
300/4
15u
X_XDP1
X_XDP1
R74
R74
X_300/4
X_300/4
CPU_CORE_TYPE 37
VID5 37
VID4 37
VID3/SVC 37
VID2/SVD 37
VID1/SEL 37
VID0/VFIXEN 37
R685
R685
X_300/4
X_300/4
Layout : Place
with in 1 inch
C157
C157
X_102pf/50V/X7R/4
X_102pf/50V/X7R/4
VCC_DDR
R58
R58
15/6/1
15/6/1
R57
R57
15/6/1
15/6/1
2
4
6
8
VCC3
10
12
14
16
18
20
22
24
26
1
VCC_DDR
R103 44.2/6/1R103 44.2/6/1
R104 44.2/6/1R104 44.2/6/1
C158
C158
X_102pf/50V/X7R/4
X_102pf/50V/X7R/4
VCC_DDR
R80
R80
X_220/4
X_220/4
X_NC7WZ07_SC70-6
X_NC7WZ07_SC70-6
R102
R102
X_300/4
X_300/4
CPU_THRIP# 21,32
PROCHOT_1.8# 19,32
5/10/10
VCCA_1V2
15 mils
CPU_M_VREF
C63
C63
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
52
V
V
16
G
G
U8A
U8A
C60
C60
102pf/50V/X7R/4
102pf/50V/X7R/4
LDT_RST#_L
R183
R183
4.7K/4
4.7K/4
B
Q17
Q17
LDT_PWRGD
A A
SYS_PWRGD15,34
R199 X_0/4R199 X_0/4
CE
N-2N3904_SOT23
N-2N3904_SOT23
HP recommend 2007/10/19
5
4
10K/410K/4
VCC3
PWROK_PWM 37
X_D1x2-BK
X_D1x2-BK
LDT_RST#_L
12
J80
J80
FOR AMD HT DEBUG
3
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
PU-HT & Straps
PU-HT & Straps
PU-HT & Straps
MS-7500
MS-7500
MS-7500
1
of
of
of
648Monday, October 29, 2007
648Monday, October 29, 2007
648Monday, October 29, 2007
0C
0C
0C
5
MEMORY INTERFACE A
D D
C C
B B
MEM_MA0_CLK_H210,12
MEM_MA0_CLK_L210,12
MEM_MA0_CLK_H110,12
MEM_MA0_CLK_L110,12
MEM_MA0_CLK_H010,12
MEM_MA0_CLK_L010,12
MEM_MA0_CS_L110,12
MEM_MA0_CS_L010,12
MEM_MA0_ODT010,12
MEM_MA1_CLK_H211,12
MEM_MA1_CLK_L211,12
MEM_MA1_CLK_H111,12
MEM_MA1_CLK_L111,12
MEM_MA1_CLK_H011,12
MEM_MA1_CLK_L011,12
MEM_MA1_CS_L111,12
MEM_MA1_CS_L011,12
MEM_MA1_ODT011,12
MEM_MA_CAS_L10,11,12
MEM_MA_WE_L10,11,12
MEM_MA_RAS_L10,11,12
MEM_MA_BANK210,11,12
MEM_MA_BANK110,11,12
MEM_MA_BANK010,11,12
MEM_MA_CKE111,12 MEM_MB_CKE111,12
MEM_MA_CKE010,12
MEM_MA_ADD[15..0]10,11,12
MEM_MA_DQS_H710,11
MEM_MA_DQS_L710,11
MEM_MA_DQS_H610,11
MEM_MA_DQS_L610,11
MEM_MA_DQS_H510,11
MEM_MA_DQS_L510,11
MEM_MA_DQS_H410,11
MEM_MA_DQS_L410,11
MEM_MA_DQS_H310,11
MEM_MA_DQS_L310,11
MEM_MA_DQS_H210,11
MEM_MA_DQS_L210,11
MEM_MA_DQS_H110,11
MEM_MA_DQS_L110,11
MEM_MA_DQS_H010,11
MEM_MA_DQS_L010,11
MEM_MA_DM710,11
MEM_MA_DM610,11
MEM_MA_DM510,11
MEM_MA_DM410,11
MEM_MA_DM310,11
MEM_MA_DM210,11
MEM_MA_DM110,11
MEM_MA_DM010,11
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CS_L1
MEM_MA1_CS_L0
MEM_MA1_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1 MEM_MB_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
AD27
AA25
AC27
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AJ25
AH29
G19
H19
U27
U26
G20
G21
V27
W27
N25
Y27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
U25
W24
D29
C29
C25
D25
E19
G15
B29
E24
E18
H15
L27
T25
T27
F19
F15
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
XU1B
XU1B
4
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
3
MEM_MA_DATA[63..0] 10,11
2
XU1C
XU1C
MEMORY INTERFACE B
MEM_MB0_CLK_H210,12
MEM_MB0_CLK_L210,12
MEM_MB0_CLK_H110,12
MEM_MB0_CLK_L110,12
MEM_MB0_CLK_H010,12
MEM_MB0_CLK_L010,12
MEM_MB0_CS_L110,12
MEM_MB0_CS_L010,12
MEM_MB0_ODT010,12
MEM_MB1_CLK_H211,12
MEM_MB1_CLK_L211,12
MEM_MB1_CLK_H111,12
MEM_MB1_CLK_L111,12
MEM_MB1_CLK_H011,12
MEM_MB1_CLK_L011,12
MEM_MB1_CS_L111,12
MEM_MB1_CS_L011,12
MEM_MB1_ODT011,12
MEM_MB_CAS_L10,11,12
MEM_MB_WE_L10,11,12
MEM_MB_RAS_L10,11,12
MEM_MB_BANK210,11,12
MEM_MB_BANK110,11,12
MEM_MB_BANK010,11,12
MEM_MB_CKE010,12
MEM_MB_ADD[15..0]10,11,12
MEM_MB_DQS_H710,11
MEM_MB_DQS_L710,11
MEM_MB_DQS_H610,11
MEM_MB_DQS_L610,11
MEM_MB_DQS_H510,11
MEM_MB_DQS_L510,11
MEM_MB_DQS_H410,11
MEM_MB_DQS_L410,11
MEM_MB_DQS_H310,11
MEM_MB_DQS_L310,11
MEM_MB_DQS_H210,11
MEM_MB_DQS_L210,11
MEM_MB_DQS_H110,11
MEM_MB_DQS_L110,11
MEM_MB_DQS_H010,11
MEM_MB_DQS_L010,11
MEM_MB_DM710,11
MEM_MB_DM610,11
MEM_MB_DM510,11
MEM_MB_DM410,11
MEM_MB_DM310,11
MEM_MB_DM210,11
MEM_MB_DM110,11
MEM_MB_DM010,11
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CS_L1
MEM_MB1_CS_L0
MEM_MB1_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
AE30
AC31
AD29
AL19
AL18
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
AA31
AA28
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
A18
A19
U31
U30
C19
D19
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
1
MEM_MB_DATA[63..0] 10,11
N12-9400040-L06 N12-9400040-L06
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
CPU-Memory
CPU-Memory
CPU-Memory
MS-7500
MS-7500
MS-7500
1
of
of
of
748Monday, October 29, 2007
748Monday, October 29, 2007
748Monday, October 29, 2007
0C
0C
0C
5
4
3
2
1
VDD_NB
XU1F
XU1F
VDD1
VDDNB1
VDDNB2
VDDNB3
VDDNB4
VDDNB5
VDDNB6
VDDNB7
VDDNB8
VDDNB9
VDDNB10
VDDNB11
VDDNB12
VDDNB13
VDDNB14
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD31
VDD32
VDD35
VDD36
VDD39
VDD40
VDD43
VDD44
VDD47
VDD48
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151
VDD1
A4
A6
B5
B7
E10
F11
G10
G12
AA8
AA10
AA12
AA14
AA16
AA18
AB7
AB9
AB11
AC4
AC5
AC8
AC10
AD2
AD3
AD7
AD9
AE10
AF7
AF9
AG4
AG5
AG7
AH2
AH3
H11
H23
J12
J14
J16
J18
J20
J22
J24
K11
K13
K15
K17
K19
K21
K23
L10
L12
Y17
Y19
C6
C8
D7
D9
E8
F9
B3
C2
C4
D3
D5
E4
E6
F5
F7
G6
G8
H7
J8
K7
K9
L4
L5
L8
D D
VCORE
C C
B B
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCORE
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
W10
VDD62
W12
VDD63
W14
VDD64
W16
VDD65
W18
VDD66
W20
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
N12-9400040-L06
XU1G
XU1G
VDD2
VDD2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCORE
AA20
VDD1
AA22
VDD2
AB13
VDD3
AB15
VDD4
AB17
VDD5
AB19
VDD6
AB21
VDD7
AB23
VDD8
AC12
VDD9
AC14
VDD10
AC16
VDD11
AC18
VDD12
AC20
VDD13
AC22
VDD14
AD11
VDD15
AD23
VDD16
AE12
VDD17
AF11
VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
1
GND
2
GND
3
GND
N12-9400040-L06
XU1H
XU1H
VDD3
VDD3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
VCC_DDR
VCCA_1V2
VTT_DDR
XU1I
XU1I
VDDIO
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
AJ4
AJ3
AJ2
AJ1
N12-9400040-L06
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
VLDT_RUN_B
VTT_DDR
X_0.01uf/25V/X7R/4
X_0.01uf/25V/X7R/4
C86
C86
4.7uf/10V/Y5V/8
4.7uf/10V/Y5V/8
C81
C81
X_0.01uf/25V/X7R/4
X_0.01uf/25V/X7R/4
C235
C235
180pf/50V/NPO/4
180pf/50V/NPO/4
X_0.01uf/25V/X7R/4
X_0.01uf/25V/X7R/4
C82
C82
C240
C240
C85
C85
180pf/50V/NPO/4
180pf/50V/NPO/4
N12-9400040-L06
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
CPU-Power & GND
CPU-Power & GND
CPU-Power & GND
MS-7500
MS-7500
MS-7500
1
of
of
of
848Monday, October 29, 2007
848Monday, October 29, 2007
848Monday, October 29, 2007
0C
0C
0C
5
VTT_DDR-Decoupling
VTT_DDR
100p/50V/NPO/4
100p/50V/NPO/4
C194
C194
C188
C259
C259
D D
180pf/50V/NPO/4
180pf/50V/NPO/4
VTT_DDR
X_180pf/50V/NPO/4
X_180pf/50V/NPO/4
C168
C168
180pf/50V/NPO/4
180pf/50V/NPO/4
C188
10pf/25V/NPO/4
10pf/25V/NPO/4
C39
C39
C189
C189
X_102pf/50V/X7R/6
X_102pf/50V/X7R/6
4
C55
C55
102pf/50V/X7R/6
102pf/50V/X7R/6
C23
C23
X_102pf/50V/X7R/6
X_102pf/50V/X7R/6
VCC_DDR
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C469
C469
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C450
C450
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
VCC_DDR
C155
C155
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C173
C173
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C444
C444
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C97
C97
3
C90
C90
C92
C92
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C91
C91
180pf/50V/NPO/4
180pf/50V/NPO/4
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
VCC_DDR
VCC_DDR-Decoupling
VCC_DDR
C691
C691
C690
C690
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C608 0.1uf/25V/Y5V/6C608 0.1uf/25V/Y5V/6
C609 100pf/50V/NPO/6C609 100pf/50V/NPO/6
VCC_DDR
C201
C201
180pf/50V/NPO/4
180pf/50V/NPO/4
2
1
VCCA_1V2-Decoupling
VCCA_1V2
X_0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C156
C156
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
VCCA_1V2
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C191
C191
10uf/6.3V/X5R/1206
10uf/6.3V/X5R/1206
C159
C159
C166
C166
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
C174
C174
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
C179
C179
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
C187
C187
C162
C162
C182
C182
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
180pf/50V/NPO/4
180pf/50V/NPO/4
C280
C280
C185
C185
180pf/50V/NPO/4
180pf/50V/NPO/4
C281
C281
VCCA_1V2
C C
VCORE-Decoupling
VDD_NB
VCORE
X_22uf/6.3V/X5R/1206
X_22uf/6.3V/X5R/1206
C463
C463
C458
C458
10uf/16V/X7R/1206
10uf/16V/X7R/1206
VCORE
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C436
C436
C437
B B
A A
C437
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
VCORE
C512
C512
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
VCORE
VCORE
X_10uf/6.3V/X5R/8
X_10uf/6.3V/X5R/8
C688
C688
C413
C413
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C419
C419
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
X_22uf/6.3V/X5R/1206
X_22uf/6.3V/X5R/1206
C454
C454
10uf/16V/X7R/1206
10uf/16V/X7R/1206
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C470
C470
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
C689
C689
100pf/50V/NPO/8
100pf/50V/NPO/8
C418
C418
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C420
C420
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
5
C448
C448
C443
C443
10uf/16V/X7R/1206
10uf/16V/X7R/1206
C438
C438
C93
C93
180pf/50V/NPO/4
180pf/50V/NPO/4
C687
C687
C684
C684
X_10uf/6.3V/X5R/8
X_10uf/6.3V/X5R/8
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C440
C440
X_22uf/6.3V/X5R/1206
X_22uf/6.3V/X5R/1206
10uf/16V/X7R/1206
10uf/16V/X7R/1206
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
C649
C649
VCORE
C56
C56
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C466
C466
C462
C462
10uf/16V/X7R/1206
10uf/16V/X7R/1206
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C686
C686
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
C61
C61
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
X_22uf/6.3V/X5R/1206
X_22uf/6.3V/X5R/1206
C457
C457
10uf/16V/X7R/1206
10uf/16V/X7R/1206
VCC_DDR
C136
C136
C272
C272
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C68
C68
4
C453
C453
VCORE
VDD_NB
VCORE
C447
C447
10uf/16V/X7R/1206
10uf/16V/X7R/1206
C268
C268
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
22uf/6.3V/X5R/1206
22uf/6.3V/X5R/1206
100p/50V/NPO/4
100p/50V/NPO/4
10uf/16V/X7R/1206
10uf/16V/X7R/1206
VTT_DDR
C696
C696
VCC_DDR
10uf/16V/X7R/1206
10uf/16V/X7R/1206
C682
C682
10uf/16V/X7R/1206
10uf/16V/X7R/1206
22uf/6.3V/X5R/8
22uf/6.3V/X5R/8
C692
C692
0.1uf/16V/X7R/8
0.1uf/16V/X7R/8
C461
C461
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
10pf/25V/NPO/4
10pf/25V/NPO/4
C207
C207
C683
C683
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
C693
C693
22uf/6.3V/X5R/8
22uf/6.3V/X5R/8
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C66
C66
C151
C151
100p/50V/NPO/4
100p/50V/NPO/4
10uf/6.3V/X5R/8
10uf/6.3V/X5R/8
C681
C681
C685
C685
C695
C695
C694
C694
10uf/6.3V/X5R/8
C58
C58
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C167
C167
3
10uf/6.3V/X5R/8
10pf/25V/NPO/4
10pf/25V/NPO/4
10uf/16V/X7R/1206
10uf/16V/X7R/1206
VCC_DDR
C456
C456
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C62
C62
C169
C169
180pf/50V/NPO/4
180pf/50V/NPO/4
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C69
C69
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C610
C610
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C192
C192
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C87
C87
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C421
C421
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C611
C611
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C697
C697
C128
C128
180pf/50V/NPO/4
180pf/50V/NPO/4
C423
C423
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C613
C613
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C698
C698
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C424
C424
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C612
C612
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C699
C699
2
C426
C426
C425
C425
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C485
C485
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C47
C47
C701
C701
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C429
C429
C486
C486
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C48
C48
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Place close to Q22
C760 10uf/10V/Y5V/1206C760 10uf/10V/Y5V/1206
C758 4.7uf/16V/X7R/8C758 4.7uf/16V/X7R/8
C761 0.1uf/25V/Y5V/6C761 0.1uf/25V/Y5V/6
0.01uf/25V/X7R/4C759 0.01uf/25V/X7R/4C759
C146
C146
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C181
C181
C177
C177
33pf/50V/NPO/6
33pf/50V/NPO/6
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
CPU-Decoupling
CPU-Decoupling
CPU-Decoupling
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C275
C275
MS-7500
MS-7500
MS-7500
1
C430
C430
C171
C171
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
948Monday, October 29, 2007
948Monday, October 29, 2007
948Monday, October 29, 2007
of
of
of
C526
C526
0C
0C
0C
5
D D
MEM_MA_DATA[63..0]7,11
C C
B B
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
XMM1
XMM1
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
170
197
55
102
19
NC
3
RC118RC0
DQ0
4
DQ1
9
NC/TEST
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS
8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
112
115
118
121
191
194
75
VDD6
VDD3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
139
181
142
175
VDD7
VSS
145
VDD8
VSS
VDDQ0
VSS
148
151
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
154
157
160
163
172
VDDQ469VDDQ7
VSS
166
N13-2400481-L06 N13-2400481-L06
187
VDDQ5
VSS
169
184
VDDQ6
VSS
198
178
VDDQ7
VSS
VSS
201
189
VDDQ8
VSS
204
67
VDDQ9
VSS
207
VSS
210
238
VDDSPD
VSS
213
216
4
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
3
XMM2
XMM2
55
161
162
167
168
CB5
CB6
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
DQS1#
MEM_MA_DQS_H2
28
DQS2
MEM_MA_DQS_L2
27
DQS2#
MEM_MA_DQS_H3
37
DQS3
MEM_MA_DQS_L3
36
DQS3#
MEM_MA_DQS_H4
84
DQS4
MEM_MA_DQS_L4 MEM_MB_DATA10
83
DQS4#
MEM_MA_DQS_H5
93
DQS5
MEM_MA_DQS_L5
92
DQS5#
MEM_MA_DQS_H6
105
DQS6
MEM_MA_DQS_L6
104
DQS6#
MEM_MA_DQS_H7
114
DQS7
MEM_MA_DQS_L7
113
DQS7#
46
DQS8
45
DQS8#
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
183
A1
MEM_MA_ADD2
63
A2
MEM_MA_ADD3
182
A3
MEM_MA_ADD4
61
A4
MEM_MA_ADD5
60
A5
MEM_MA_ADD6
180
A6
MEM_MA_ADD7
58
A7
MEM_MA_ADD8
179
A8
MEM_MA_ADD9
177
A9
MEM_MA_ADD10
70
A10_AP
MEM_MA_ADD11
57
A11
MEM_MA_ADD12
176
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
174
A14
MEM_MA_ADD15
173
A15
MEM_MA_BANK2
54
A16/BA2
MEM_MA_BANK1
190
BA1
MEM_MA_BANK0
71
BA0
MEM_MA_WE_L
73
WE#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RAS_L
192
RAS#
MEM_MA_DM0
125
DM0/DQS9
126
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
228
231
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
VSS
234
MEM_MA_DM1
134
135
MEM_MA_DM2
146
147
MEM_MA_DM3
155
156
MEM_MA_DM4
202
203
MEM_MA_DM5
211
212
MEM_MA_DM6
223
224
MEM_MA_DM7
232
233
164
165
MEM_MA0_ODT0
195
ODT0
77
ODT1
52
CKE0
171
CKE1
MEM_MA0_CS_L0
193
CS0#
MEM_MA0_CS_L1
76
CS1#
MEM_MA0_CLK_H0
185
MEM_MA0_CLK_L0
186
MEM_MA0_CLK_H1
137
MEM_MA0_CLK_L1
138
MEM_MA0_CLK_H2
220
MEM_MA0_CLK_L2
221
SCL0
120
SCL
SDA0
119
SDA
VDDR_VREF
1
VREF
239
SA0
240
SA1
101
SA2
VSS
VSS
DDRII-240_WHITE
DDRII-240_WHITE
237
ADDRESS: 1010 000 ADDRESS: 1010 001
MEM_MA_DQS_H0 7,11
MEM_MA_DQS_L0 7,11
MEM_MA_DQS_H1 7,11
MEM_MA_DQS_L1 7,11
MEM_MA_DQS_H2 7,11
MEM_MA_DQS_L2 7,11
MEM_MA_DQS_H3 7,11
MEM_MA_DQS_L3 7,11
MEM_MA_DQS_H4 7,11
MEM_MA_DQS_L4 7,11
MEM_MA_DQS_H5 7,11
MEM_MA_DQS_L5 7,11
MEM_MA_DQS_H6 7,11
MEM_MA_DQS_L6 7,11
MEM_MA_DQS_H7 7,11
MEM_MA_DQS_L7 7,11
MEM_MA_ADD[15..0] 7,11,12
MEM_MA_BANK2 7,11,12
MEM_MA_BANK1 7,11,12
MEM_MA_BANK0 7,11,12
MEM_MA_WE_L 7,11,12
MEM_MA_CAS_L 7,11,12
MEM_MA_RAS_L 7,11,12
MEM_MA_DM[7..0] MEM_MB_DM[7..0]
MEM_MA0_ODT0 7,12
MEM_MA_CKE0 7,12
MEM_MA0_CS_L0 7,12
MEM_MA0_CS_L1 7,12
MEM_MA0_CLK_H0 7,12
MEM_MA0_CLK_L0 7,12
MEM_MA0_CLK_H1 7,12
MEM_MA0_CLK_L1 7,12
MEM_MA0_CLK_H2 7,12
MEM_MA0_CLK_L2 7,12
SCL0 11,18,21,32
SDA0 11,18,21,32
C42
C42
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
MEM_MB_DATA[63..0]7,11
MEM_MA_DM[7..0] 7,11 MEM_MB_DM[7..0] 7,11
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
102
19
NC
3
RC118RC0
DQ0
4
DQ1
9
NC/TEST
DQ2
10
DQ3
DQ4
DQ5
DQ6
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
DQ12
DQ13
DQ14
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
DQ20
DQ21
DQ22
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
DQ28
DQ29
DQ30
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
DQ36
DQ37
DQ38
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
DQ44
DQ45
DQ46
DQ47
98
DQ48
99
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VSS
VSS
VSS
VSS
100
103
106
109
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
VSS
112
115
118
121
191
75
VDD3
VSS
VSS
VSS
VSS
124
127
130
133
136
2
VCC3VCC_DDRVCC3VCC_DDR
172
187
184
178
VDDQ5
VDDQ6
VDDQ7
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
163
166
169
198
201
189
204
67
VDDQ8
VSS
207
VDDQ9
VSS
210
238
VSS
213
VDDSPD
VSS
VSS
216
219
CB042CB143CB248CB349CB4
DM0/DQS9
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
VSS
VSS
222
225
228
161
162
167
CB5
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
CAS#
RAS#
NC/DQS9#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
VREF
VSS
VSS
231
234
237
168
CB6
CB7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
A14
A15
BA1
BA0
WE#
SCL
SDA
SA0
SA1
SA2
VSS
DDRII-240_WHITE
DDRII-240_WHITE
170
197
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
139
142
145
148
151
154
157
160
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
28
MEM_MB_DQS_L2
27
MEM_MB_DQS_H3
37
MEM_MB_DQS_L3
36
MEM_MB_DQS_H4
84
MEM_MB_DQS_L4
83
MEM_MB_DQS_H5
93
MEM_MB_DQS_L5
92
MEM_MB_DQS_H6
105
MEM_MB_DQS_L6
104
MEM_MB_DQS_H7
114
MEM_MB_DQS_L7
113
46
45
MEM_MB_ADD0
188
MEM_MB_ADD1
183
MEM_MB_ADD2
63
MEM_MB_ADD3
182
MEM_MB_ADD4
61
MEM_MB_ADD5
60
MEM_MB_ADD6
180
MEM_MB_ADD7
58
MEM_MB_ADD8
179
MEM_MB_ADD9
177
MEM_MB_ADD10
70
MEM_MB_ADD11
57
MEM_MB_ADD12
176
MEM_MB_ADD13
196
MEM_MB_ADD14
174
MEM_MB_ADD15
173
MEM_MB_BANK2
54
MEM_MB_BANK1
190
MEM_MB_BANK0
71
MEM_MB_WE_L
73
MEM_MB_CAS_L
74
MEM_MB_RAS_L
192
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
146
147
MEM_MB_DM3
155
156
MEM_MB_DM4
202
203
MEM_MB_DM5
211
212
MEM_MB_DM6
223
224
MEM_MB_DM7
232
233
164
165
MEM_MB0_ODT0
195
77
52
171
MEM_MB0_CS_L0
193
MEM_MB0_CS_L1
76
MEM_MB0_CLK_H0
185
MEM_MB0_CLK_L0
186
MEM_MB0_CLK_H1
137
MEM_MB0_CLK_L1
138
MEM_MB0_CLK_H2
220
MEM_MB0_CLK_L2
221
SCL0
120
SDA0
119
VDDR_VREF
1
VCC3
239
240
101
MEM_MB_DQS_H0 7,11
MEM_MB_DQS_L0 7,11
MEM_MB_DQS_H1 7,11
MEM_MB_DQS_L1 7,11
MEM_MB_DQS_H2 7,11
MEM_MB_DQS_L2 7,11
MEM_MB_DQS_H3 7,11
MEM_MB_DQS_L3 7,11
MEM_MB_DQS_H4 7,11
MEM_MB_DQS_L4 7,11
MEM_MB_DQS_H5 7,11
MEM_MB_DQS_L5 7,11
MEM_MB_DQS_H6 7,11
MEM_MB_DQS_L6 7,11
MEM_MB_DQS_H7 7,11
MEM_MB_DQS_L7 7,11
MEM_MB_BANK2 7,11,12
MEM_MB_BANK1 7,11,12
MEM_MB_BANK0 7,11,12
MEM_MB_WE_L 7,11,12
MEM_MB_CAS_L 7,11,12
MEM_MB_RAS_L 7,11,12
MEM_MB0_ODT0 7,12
MEM_MB_CKE0 7,12
MEM_MB0_CS_L0 7,12
MEM_MB0_CS_L1 7,12
MEM_MB0_CLK_H0 7,12
MEM_MB0_CLK_L0 7,12
MEM_MB0_CLK_H1 7,12
MEM_MB0_CLK_L1 7,12
MEM_MB0_CLK_H2 7,12
MEM_MB0_CLK_L2 7,12
SCL0 11,18,21,32
SDA0 11,18,21,32
C41
C41
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
PLACE CLOSE TO DIMM PINPLACE CLOSE TO DIMM PIN
1
MEM_MB_ADD[15..0] 7,11,12
WHITE COLOR WHITE COLOR
VCC_DDR
C549
C549
4.7uf/10V/Y5V/8
4.7uf/10V/Y5V/8
A A
5
VCC_DDR
R35
R35
15/6/1
15/6/1
R33
R33
15/6/1
15/6/1
C29
C29
X_0.1uf/10V/X7R/4
X_0.1uf/10V/X7R/4
VDDR_VREF
C33
C33
X_0.1uf/10V/X7R/4
X_0.1uf/10V/X7R/4
VDDR_VREF
C36
C36
102pf/50V/X7R/4
102pf/50V/X7R/4
4
C763
C763
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
SCL0 SDA0
3
3
2
D15
D15
BAV99_SOT23
BAV99_SOT23
1
3VDUAL3VDUAL
3
2
D13
D13
BAV99_SOT23
BAV99_SOT23
1
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
MS-7500
MS-7500
MS-7500
1
of
10 48Monday, October 29, 2007
of
10 48Monday, October 29, 2007
of
10 48Monday, October 29, 2007
0C
0C
0C
5
4
3
2
1
D D
XMM4
XMM3
XMM3
55
102
68
MEM_MA_DATA[63..0]7,10
C C
B B
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
19
NC
NC
3
RC118RC0
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VDD051VDD156VDD262VDD372VDD478VDD5
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
170
197
191
194
181
175
75
VDD6
VDD7
VDD8
VDD3
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
VSS
139
142
145
148
151
154
157
160
N13-2400121-L06 N13-2400121-L06
172
187
184
178
VDDQ5
VDDQ6
VDDQ7
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
163
166
169
198
201
189
VDDQ8
VSS
204
67
VDDQ9
VSS
207
VSS
210
238
VDDSPD
VSS
213
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
161
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
228
231
162
167
168
CB5
CB6
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
DQS1#
MEM_MA_DQS_H2
28
DQS2
MEM_MA_DQS_L2
27
DQS2#
MEM_MA_DQS_H3
37
DQS3
MEM_MA_DQS_L3
36
DQS3#
MEM_MA_DQS_H4
84
DQS4
MEM_MA_DQS_L4 MEM_MB_DATA10
83
DQS4#
MEM_MA_DQS_H5
93
DQS5
MEM_MA_DQS_L5
92
DQS5#
MEM_MA_DQS_H6
105
DQS6
MEM_MA_DQS_L6
104
DQS6#
MEM_MA_DQS_H7
114
DQS7
MEM_MA_DQS_L7
113
DQS7#
46
DQS8
45
DQS8#
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
183
A1
MEM_MA_ADD2
63
A2
MEM_MA_ADD3
182
A3
MEM_MA_ADD4
61
A4
MEM_MA_ADD5
60
A5
MEM_MA_ADD6
180
A6
MEM_MA_ADD7
58
A7
MEM_MA_ADD8
179
A8
MEM_MA_ADD9
177
A9
MEM_MA_ADD10
70
A10_AP
MEM_MA_ADD11
57
A11
MEM_MA_ADD12
176
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
174
A14
MEM_MA_ADD15
173
A15
MEM_MA_BANK2
54
A16/BA2
MEM_MA_BANK1
190
BA1
MEM_MA_BANK0
71
BA0
MEM_MA_WE_L
73
WE#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RAS_L
192
RAS#
MEM_MA_DM0
125
126
MEM_MA_DM1
134
135
MEM_MA_DM2
146
147
MEM_MA_DM3
155
156
MEM_MA_DM4
202
203
MEM_MA_DM5
211
212
MEM_MA_DM6
223
224
MEM_MA_DM7
232
233
164
165
MEM_MA1_ODT0
195
ODT0
77
ODT1
52
CKE0
171
CKE1
MEM_MA1_CS_L0
193
CS0#
MEM_MA1_CS_L1
76
CS1#
MEM_MA1_CLK_H0
185
CK0(DU)
MEM_MA1_CLK_L0
186
CK0#(DU)
MEM_MA1_CLK_H1
137
CK1(CK0)
MEM_MA1_CLK_L1
138
MEM_MA1_CLK_H2
220
CK2(DU)
MEM_MA1_CLK_L2
221
CK2#(DU)
SCL0
120
SCL
SDA0
119
SDA
VDDR_VREF
1
VREF
VCC3 VCC3
239
SA0
240
SA1
101
SA2
VSS
VSS
VSS
DDRII-240_BLACK
DDRII-240_BLACK
234
237
ADDRESS: 1010 010
MEM_MA_DQS_H0 7,10
MEM_MA_DQS_L0 7,10
MEM_MA_DQS_H1 7,10
MEM_MA_DQS_L1 7,10
MEM_MA_DQS_H2 7,10
MEM_MA_DQS_L2 7,10
MEM_MA_DQS_H3 7,10
MEM_MA_DQS_L3 7,10
MEM_MA_DQS_H4 7,10
MEM_MA_DQS_L4 7,10
MEM_MA_DQS_H5 7,10
MEM_MA_DQS_L5 7,10
MEM_MA_DQS_H6 7,10
MEM_MA_DQS_L6 7,10
MEM_MA_DQS_H7 7,10
MEM_MA_DQS_L7 7,10
MEM_MA_ADD[15..0] 7,10,12
MEM_MA_BANK2 7,10,12
MEM_MA_BANK1 7,10,12
MEM_MA_BANK0 7,10,12
MEM_MA_WE_L 7,10,12
MEM_MA_CAS_L 7,10,12
MEM_MA_RAS_L 7,10,12
MEM_MA_DM[7..0] MEM_MB_DM[7..0]
MEM_MA1_ODT0 7,12
MEM_MA_CKE1 7,12
MEM_MA1_CS_L0 7,12
MEM_MA1_CS_L1 7,12
MEM_MA1_CLK_H0 7,12
MEM_MA1_CLK_L0 7,12
MEM_MA1_CLK_H1 7,12
MEM_MA1_CLK_L1 7,12
MEM_MA1_CLK_H2 7,12
MEM_MA1_CLK_L2 7,12
SCL0 10,18,21,32
SDA0 10,18,21,32
C664
C664
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
MEM_MB_DATA[63..0]7,10
MEM_MA_DM[7..0] 7,10 MEM_MB_DM[7..0] 7,10
VDDR_VREF
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
XMM4
55
102
68
19
NC
NC
3
RC118RC0
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VDD051VDD156VDD262VDD372VDD478VDD5
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
170
191
194
181
175
75
VDD6
VDD7
VDD8
VDD3
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
VSS
136
139
142
145
148
151
154
157
197
172
187
VDDQ5
VDDQ469VDDQ7
VSS
VSS
VSS
160
163
166
169
184
VDDQ6
VDDQ7
VSS
VSS
198
VCC3VCC_DDRVCC3VCC_DDR
238
189
67
178
VDDQ8
VSS
VSS
201
204
VDDQ9
VSS
207
VSS
210
VDDSPD
VSS
213
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
161
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
VSS
VSS
VSS
228
231
162
167
168
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK2(DU)
SCL
SDA
VREF
SA0
SA1
SA2
VSS
VSS
DDRII-240_BLACK
DDRII-240_BLACK
234
237
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
28
MEM_MB_DQS_L2
27
MEM_MB_DQS_H3
37
MEM_MB_DQS_L3
36
MEM_MB_DQS_H4
84
MEM_MB_DQS_L4
83
MEM_MB_DQS_H5
93
MEM_MB_DQS_L5
92
MEM_MB_DQS_H6
105
MEM_MB_DQS_L6
104
MEM_MB_DQS_H7
114
MEM_MB_DQS_L7
113
46
45
MEM_MB_ADD0
188
MEM_MB_ADD1
183
MEM_MB_ADD2
63
MEM_MB_ADD3
182
MEM_MB_ADD4
61
MEM_MB_ADD5
60
MEM_MB_ADD6
180
MEM_MB_ADD7
58
MEM_MB_ADD8
179
MEM_MB_ADD9
177
MEM_MB_ADD10
70
MEM_MB_ADD11
57
MEM_MB_ADD12
176
MEM_MB_ADD13
196
MEM_MB_ADD14
174
MEM_MB_ADD15
173
MEM_MB_BANK2
54
MEM_MB_BANK1
190
MEM_MB_BANK0
71
MEM_MB_WE_L
73
MEM_MB_CAS_L
74
MEM_MB_RAS_L
192
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
146
147
MEM_MB_DM3
155
156
MEM_MB_DM4
202
203
MEM_MB_DM5
211
212
MEM_MB_DM6
223
224
MEM_MB_DM7
232
233
164
165
MEM_MB1_ODT0
195
77
52
171
MEM_MB1_CS_L0
193
MEM_MB1_CS_L1
76
MEM_MB1_CLK_H0
185
MEM_MB1_CLK_L0
186
MEM_MB1_CLK_H1
137
MEM_MB1_CLK_L1
138
MEM_MB1_CLK_H2
220
MEM_MB1_CLK_L2
221
SCL0
120
SDA0
119
VDDR_VREF
1
239
240
101
MEM_MB_DQS_H0 7,10
MEM_MB_DQS_L0 7,10
MEM_MB_DQS_H1 7,10
MEM_MB_DQS_L1 7,10
MEM_MB_DQS_H2 7,10
MEM_MB_DQS_L2 7,10
MEM_MB_DQS_H3 7,10
MEM_MB_DQS_L3 7,10
MEM_MB_DQS_H4 7,10
MEM_MB_DQS_L4 7,10
MEM_MB_DQS_H5 7,10
MEM_MB_DQS_L5 7,10
MEM_MB_DQS_H6 7,10
MEM_MB_DQS_L6 7,10
MEM_MB_DQS_H7 7,10
MEM_MB_DQS_L7 7,10
MEM_MB_BANK2 7,10,12
MEM_MB_BANK1 7,10,12
MEM_MB_BANK0 7,10,12
MEM_MB_WE_L 7,10,12
MEM_MB_CAS_L 7,10,12
MEM_MB_RAS_L 7,10,12
MEM_MB1_ODT0 7,12
MEM_MB_CKE1 7,12
MEM_MB1_CS_L0 7,12
MEM_MB1_CS_L1 7,12
MEM_MB1_CLK_H0 7,12
MEM_MB1_CLK_L0 7,12
MEM_MB1_CLK_H1 7,12
MEM_MB1_CLK_L1 7,12
MEM_MB1_CLK_H2 7,12
MEM_MB1_CLK_L2 7,12
SCL0 10,18,21,32
SDA0 10,18,21,32
C665
C665
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
PLACE CLOSE TO DIMM PINPLACE CLOSE TO DIMM PIN
MEM_MB_ADD[15..0] 7,10,12
ADDRESS: 1010 011
BLACK COLOR
A A
5
4
3
BLACK COLOR
2
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
MS-7500
MS-7500
MS-7500
1
of
11 48Monday, October 29, 2007
of
11 48Monday, October 29, 2007
of
11 48Monday, October 29, 2007
0C
0C
0C
5
4
3
2
1
Place Between Processor and DIMMs
VCC_DDR
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
D D
RTT:Place Behind DIMMs
VTT_DDR
RN16
RN16
47R_8P4R/4
MEM_MA_BANK27,10,11
MEM_MB_BANK27,10,11
MEM_MB_ADD127,10,11
MEM_MB_ADD97,10,11
MEM_MA_CKE07,10
MEM_MB_ADD147,10,11
MEM_MA_ADD157,10,11
MEM_MA_ADD147,10,11
MEM_MB_ADD67,10,11
MEM_MA_ADD67,10,11
MEM_MA_ADD57,10,11
C C
MEM_MA_ADD47,10,11
MEM_MA_ADD27,10,11
MEM_MB_ADD37,10,11
MEM_MB_ADD17,10,11
MEM_MB_ADD27,10,11
MEM_MA_BANK17,10,11
MEM_MB_BANK07,10,11
MEM_MB_RAS_L7,10,11
MEM_MA_ADD107,10,11
MEM_MA_WE_L7,10,11
MEM_MA_CAS_L7,10,11
MEM_MB0_ODT07,10
MEM_MA0_ODT07,10
MEM_MA0_CS_L17,10
MEM_MB0_CS_L17,10
MEM_MB1_CS_L17,11
B B
MEM_MA1_CS_L17,11
MEM_MA_BANK2
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_CKE0
MEM_MB_ADD14
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MB_ADD6
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD2
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MA_BANK1
MEM_MB_BANK0
MEM_MB_RAS_L
MEM_MA_ADD10
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MB0_ODT0
MEM_MA0_ODT0
MEM_MA0_CS_L1
MEM_MB0_CS_L1
MEM_MB1_CS_L1
MEM_MA1_CS_L1
47R_8P4R/4
1
3
5
7
RN17
RN17
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN20
RN20
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN22
RN22
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN24
RN24
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN26
RN26
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN57
RN57
47R_8P4R/4
47R_8P4R/4
1
3
5
7
VTT_DDR
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C495
C495
180pf/50V/NPO/4
180pf/50V/NPO/4
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C94
C94
VCC_DDR
C127 0.1uf/10V/X7R/4C127 0.1uf/10V/X7R/4
C178 0.1uf/10V/X7R/4C178 0.1uf/10V/X7R/4
C126 0.1uf/10V/X7R/4C126 0.1uf/10V/X7R/4
C172 0.1uf/10V/X7R/4C172 0.1uf/10V/X7R/4
C121 0.1uf/10V/X7R/4C121 0.1uf/10V/X7R/4
C129 0.1uf/10V/X7R/4C129 0.1uf/10V/X7R/4
C183 0.1uf/10V/X7R/4C183 0.1uf/10V/X7R/4
C180 0.1uf/10V/X7R/4C180 0.1uf/10V/X7R/4
C115 0.1uf/10V/X7R/4C115 0.1uf/10V/X7R/4
C234 0.1uf/10V/X7R/4C234 0.1uf/10V/X7R/4
C110 0.1uf/10V/X7R/4C110 0.1uf/10V/X7R/4
C106 0.1uf/10V/X7R/4C106 0.1uf/10V/X7R/4
C108 0.1uf/10V/X7R/4C108 0.1uf/10V/X7R/4
C123 47pf/50V/NPO/4C123 47pf/50V/NPO/4
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C530
C530
C96
C96
180pf/50V/NPO/4
180pf/50V/NPO/4
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C531
C531
C140
C140
180pf/50V/NPO/4
180pf/50V/NPO/4
MEM_MB_ADD117,10,11
MEM_MA_ADD127,10,11
MEM_MA_ADD97,10,11
MEM_MB_ADD77,10,11
MEM_MB_ADD87,10,11
MEM_MA_ADD117,10,11
MEM_MA_ADD77,10,11
MEM_MA_ADD87,10,11
MEM_MB_ADD57,10,11
MEM_MB_ADD47,10,11
MEM_MA_ADD37,10,11
MEM_MA_ADD17,10,11
MEM_MB_ADD07,10,11
MEM_MB_BANK17,10,11
MEM_MB_ADD107,10,11
MEM_MA_ADD07,10,11
MEM_MB1_CS_L07,11
MEM_MB0_CS_L07,10
MEM_MA_BANK07,10,11
MEM_MA_RAS_L7,10,11
MEM_MB_CKE17,11
MEM_MB_CKE07,10
MEM_MA_CKE17,11
MEM_MB_ADD157,10,11
MEM_MA0_CS_L07,10
MEM_MA1_CS_L07,11
MEM_MB_WE_L7,10,11
MEM_MB_CAS_L7,10,11
MEM_MA1_ODT07,11
MEM_MA_ADD137,10,11
MEM_MB1_ODT07,11
MEM_MB_ADD137,10,11
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C537
C537
C154
C154
180pf/50V/NPO/4
180pf/50V/NPO/4
MEM_MB_ADD11
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MA_ADD11
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MA_ADD0
MEM_MB1_CS_L0
MEM_MB0_CS_L0
MEM_MA_BANK0
MEM_MA_RAS_L
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MA_CKE1
MEM_MB_ADD15
MEM_MA0_CS_L0
MEM_MA1_CS_L0
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MA1_ODT0
MEM_MA_ADD13
MEM_MB1_ODT0
MEM_MB_ADD13
C566
C566
C170
C170
180pf/50V/NPO/4
180pf/50V/NPO/4
RN14
RN14
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN18
RN18
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN21
RN21
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN23
RN23
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN25
RN25
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN15
RN15
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN28
RN28
47R_8P4R/4
47R_8P4R/4
1
3
5
7
RN56
RN56
47R_8P4R/4
47R_8P4R/4
1
3
5
7
VTT_DDR
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
VCC_DDR
C193 0.1uf/10V/X7R/4C193 0.1uf/10V/X7R/4
C228 47pf/50V/NPO/4C228 47pf/50V/NPO/4
C184 0.1uf/10V/X7R/4C184 0.1uf/10V/X7R/4
C233 0.1uf/10V/X7R/4C233 0.1uf/10V/X7R/4
C176 0.1uf/10V/X7R/4C176 0.1uf/10V/X7R/4
C226 0.1uf/10V/X7R/4C226 0.1uf/10V/X7R/4
C153 0.1uf/10V/X7R/4C153 0.1uf/10V/X7R/4
C231 47pf/50V/NPO/4C231 47pf/50V/NPO/4
C164 0.1uf/10V/X7R/4C164 0.1uf/10V/X7R/4
C232 0.1uf/10V/X7R/4C232 0.1uf/10V/X7R/4
C152 0.1uf/10V/X7R/4C152 0.1uf/10V/X7R/4
C277 0.1uf/10V/X7R/4C277 0.1uf/10V/X7R/4
C131 0.1uf/10V/X7R/4C131 0.1uf/10V/X7R/4
C278 0.1uf/10V/X7R/4C278 0.1uf/10V/X7R/4
C276 0.1uf/10V/X7R/4C276 0.1uf/10V/X7R/4
C279 0.1uf/10V/X7R/4C279 0.1uf/10V/X7R/4
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3 MEM_MB_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA1_CLK_H27,11
MEM_MA1_CLK_L27,11
MEM_MA1_CLK_H17,11
MEM_MA1_CLK_L17,11
MEM_MA1_CLK_H07,11
MEM_MA1_CLK_L07,11
MEM_MB1_CLK_H27,11
MEM_MB1_CLK_L27,11
MEM_MB1_CLK_H17,11
MEM_MB1_CLK_L17,11
MEM_MB1_CLK_H07,11
MEM_MB1_CLK_L07,11
22pf/50V/NPO/4C446 22pf/50V/NPO/4C446
22pf/50V/NPO/4C441 22pf/50V/NPO/4C441
22pf/50V/NPO/4C479 22pf/50V/NPO/4C479
22pf/50V/NPO/4C445 22pf/50V/NPO/4C445
22pf/50V/NPO/4C449 22pf/50V/NPO/4C449
22pf/50V/NPO/4C476 22pf/50V/NPO/4C476
22pf/50V/NPO/4C455 22pf/50V/NPO/4C455
22pf/50V/NPO/4C459 22pf/50V/NPO/4C459
22pf/50V/NPO/4C452 22pf/50V/NPO/4C452
22pf/50V/NPO/4C465 22pf/50V/NPO/4C465
22pf/50V/NPO/4C460 22pf/50V/NPO/4C460
22pf/50V/NPO/4C464 22pf/50V/NPO/4C464
22pf/50V/NPO/4C467 22pf/50V/NPO/4C467
22pf/50V/NPO/4C468 22pf/50V/NPO/4C468
22pf/50V/NPO/4C471 22pf/50V/NPO/4C471
22pf/50V/NPO/4C474 22pf/50V/NPO/4C474
22pf/50V/NPO/4C475 22pf/50V/NPO/4C475
22pf/50V/NPO/4C478 22pf/50V/NPO/4C478
22pf/50V/NPO/4C477 22pf/50V/NPO/4C477
22pf/50V/NPO/4C451 22pf/50V/NPO/4C451
22pf/50V/NPO/4C472 22pf/50V/NPO/4C472
22pf/50V/NPO/4C473 22pf/50V/NPO/4C473
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
C238
C238
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C529
C529
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C534
C534
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C273
C273
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C161
C161
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C533
C533
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MA0_CLK_H27,10
MEM_MA0_CLK_L27,10
MEM_MA0_CLK_H17,10
MEM_MA0_CLK_L17,10
MEM_MA0_CLK_H07,10
MEM_MA0_CLK_L07,10
MEM_MB0_CLK_H27,10
MEM_MB0_CLK_L27,10
MEM_MB0_CLK_H17,10
MEM_MB0_CLK_L17,10
MEM_MB0_CLK_H07,10
MEM_MB0_CLK_L07,10
22pf/50V/NPO/4C101 22pf/50V/NPO/4C101
22pf/50V/NPO/4C95 22pf/50V/NPO/4C95
22pf/50V/NPO/4C160 22pf/50V/NPO/4C160
22pf/50V/NPO/4C98 22pf/50V/NPO/4C98
22pf/50V/NPO/4C100 22pf/50V/NPO/4C100
22pf/50V/NPO/4C142 22pf/50V/NPO/4C142
22pf/50V/NPO/4C109 22pf/50V/NPO/4C109
22pf/50V/NPO/4C103 22pf/50V/NPO/4C103
22pf/50V/NPO/4C107 22pf/50V/NPO/4C107
22pf/50V/NPO/4C116 22pf/50V/NPO/4C116
22pf/50V/NPO/4C105 22pf/50V/NPO/4C105
22pf/50V/NPO/4C120 22pf/50V/NPO/4C120
22pf/50V/NPO/4C111 22pf/50V/NPO/4C111
22pf/50V/NPO/4C118 22pf/50V/NPO/4C118
22pf/50V/NPO/4C124 22pf/50V/NPO/4C124
22pf/50V/NPO/4C132 22pf/50V/NPO/4C132
22pf/50V/NPO/4C133 22pf/50V/NPO/4C133
22pf/50V/NPO/4C150 22pf/50V/NPO/4C150
22pf/50V/NPO/4C147 22pf/50V/NPO/4C147
22pf/50V/NPO/4C102 22pf/50V/NPO/4C102
22pf/50V/NPO/4C125 22pf/50V/NPO/4C125
22pf/50V/NPO/4C130 22pf/50V/NPO/4C130
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
VCC_DDR
C165
C165
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C54
C54
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C113
C113
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C163
C163
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C65
C65
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
C117
C117
1.5pf/50V/NPO/4
1.5pf/50V/NPO/4
VTT_DDR
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
A A
0.01uf/25V/X7R/4
5
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C186
C186
C568
C568
180pf/50V/NPO/4
180pf/50V/NPO/4
0.01uf/25V/X7R/4
C190
C190
C573
C573
180pf/50V/NPO/4
180pf/50V/NPO/4
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C196
C196
C622
C622
180pf/50V/NPO/4
180pf/50V/NPO/4
C624
C624
180pf/50V/NPO/4
180pf/50V/NPO/4
4
0.01uf/25V/X7R/4
0.01uf/25V/X7R/4
C199
C199
C642
C642
180pf/50V/NPO/4
180pf/50V/NPO/4
C200
C200
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet
DDR II Termination
DDR II Termination
DDR II Termination
MS-7500
MS-7500
MS-7500
0C
0C
0C
of
12 48Monday, October 29, 2007
12 48Monday, October 29, 2007
12 48Monday, October 29, 2007
1
5
D D
4
3
2
1
CADOP[0..15]6
C C
CADON[0..15]6
B B
CADOP[0..15]
CADON[0..15]
CADOP0
CADON0
CADOP1
CADON1
CADOP2
CADON2
CADOP3
CADON3
CADOP4
CADON4
CADOP5
CADON5
CADOP6
CADON6
CADOP7
CADON7
CADOP8
CADON8
CADOP9
CADON9
CADOP10
CADON10
CADOP11
CADON11
CADOP12
CADON12
CADOP13
CADON13
CADOP14
CADON14
CADOP15
CADON15
CLKOP06
CLKON06
CLKOP16
CLKON16
CTLOP06
CTLON06
CTLOP16
CTLON16
R34301/4/1 R34301/4/1
CLKOP0
CLKON0
CLKOP1
CLKON1
CTLOP0
CTLON0
CTLOP1
CTLON1
HT_RXCALP
HT_RXCALN
5 / 10 5 / 10
08/10/07 AMD: Please note that R34 and R36 are 301 1% resistor when using RS780.
20 / 5 / 5 / 5 / 20 20 / 5 / 5 / 5 / 20
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
M22
M23
R21
R20
C23
A24
U3A
U3A
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
PART 1 OF 6
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU
I/F
HYPER TRANSPORT CPU
I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
HT_TXCALP
HT_TXCALN
CLKIP0
CLKIN0
CLKIP1
CLKIN1
CTLIP0
CTLIN0
CTLIP1
CTLIN1
CLKIP0 6
CLKIN0 6
CLKIP1 6
CLKIN1 6
CTLIP0 6
CTLIN0 6
CTLIP1 6
CTLIN1 6
R36 301/4/1R36 301/4/1
R34 and R36 are 1.21K 1% resistor when using RX780.
CADIP0
CADIN0
CADIP1
CADIN1
CADIP2
CADIN2
CADIP3
CADIN3
CADIP4
CADIN4
CADIP5
CADIN5
CADIP6
CADIN6
CADIP7
CADIN7
CADIP8
CADIN8
CADIP9
CADIN9
CADIP10
CADIN10
CADIP11
CADIN11
CADIP12
CADIN12
CADIP13
CADIN13
CADIP14
CADIN14
CADIP15
CADIN15
CADIP[0..15]
CADIN[0..15]
CADIP[0..15] 6
CADIN[0..15] 6
RX780/RS740/RS780 difference table (HT LINK)
SIGNALS
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
RS740 RX780
49.9R (GND)
49.9R (VDDHT)
1.21K
1.21K100R
RS780
301R
301R
VCORE
C920
C920
C925
0.01uf/16V/X7R/4
0.01uf/16V/X7R/4
Adding some 0.01uF stitching capacitors
A A
for crossing a split when these signals
change different reference layer.
For 07/09/07
5
C925
0.01uf/16V/X7R/4
0.01uf/16V/X7R/4
AMD-215NDA7BKA11FG-A11-RH
AMD-215NDA7BKA11FG-A11-RH
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
RS780/RX780-HT LINK I/F
RS780/RX780-HT LINK I/F
RS780/RX780-HT LINK I/F
MS-7500
MS-7500
MS-7500
13 48Monday, October 29, 2007
13 48Monday, October 29, 2007
13 48Monday, October 29, 2007
1
0C
0C
0C
of
of
of
5
4
3
2
1
20 / 5.5 / 4.5 / 5.5 / 20 20 / 5.5 / 4.5 / 5.5 / 20
PE0_RX025
PE0_RX0#25
PE0_RX125
PE0_RX1#25
D D
C C
B B
PE0_RX225
PE0_RX2#25
PE0_RX325
PE0_RX3#25
PE0_RX425
PE0_RX4#25
PE0_RX525
PE0_RX5#25
PE0_RX625
PE0_RX6#25
PE0_RX725
PE0_RX7#25
PE0_RX825
PE0_RX8#25
PE0_RX925
PE0_RX9#25
PE0_RX1025
PE0_RX10#25
PE0_RX1125
PE0_RX11#25
PE0_RX1225
PE0_RX12#25
PE0_RX1325
PE0_RX13#25
PE0_RX1425
PE0_RX14#25
PE0_RX1525
PE0_RX15#25
PE1_RX25
PE1_RX#25
PE2_RX25
PE2_RX#25
PE3_RX24
PE3_RX#24
A_RX0P19
A_RX0N19
A_RX1P19
A_RX1N19
A_RX2P19
A_RX2N19
A_RX3P19
A_RX3N19
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
AMD-215NDA7BKA11FG-A11-RH
AMD-215NDA7BKA11FG-A11-RH
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_BCALRP
PCE_BCALRN
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
PE0_TX0 25
PE0_TX0# 25
PE0_TX1 25
PE0_TX1# 25
PE0_TX2 25
PE0_TX2# 25
PE0_TX3 25
PE0_TX3# 25
PE0_TX4 25
PE0_TX4# 25
PE0_TX5 25
PE0_TX5# 25
PE0_TX6 25
PE0_TX6# 25
PE0_TX7 25
PE0_TX7# 25
PE0_TX8 25
PE0_TX8# 25
PE0_TX9 25
PE0_TX9# 25
PE0_TX10 25
PE0_TX10# 25
PE0_TX11 25
PE0_TX11# 25
PE0_TX12 25
PE0_TX12# 25
PE0_TX13 25
PE0_TX13# 25
PE0_TX14 25
PE0_TX14# 25
PE0_TX15 25
PE0_TX15# 25
X7R
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
A_TX2P_C
A_TX2N_C
A_TX3P_C
A_TX3N_C
R39 1.27K/4/1R39 1.27K/4/1
R40 2K/4/1R40 2K/4/1
C359 0.1uf/10V/X7R/4C359 0.1uf/10V/X7R/4
C389 0.1uf/10V/X7R/4C389 0.1uf/10V/X7R/4
C197 0.1uf/10V/X7R/4C197 0.1uf/10V/X7R/4
C206 0.1uf/10V/X7R/4C206 0.1uf/10V/X7R/4
C212 0.1uf/10V/X7R/4C212 0.1uf/10V/X7R/4
C251 0.1uf/10V/X7R/4C251 0.1uf/10V/X7R/4
C349 0.1uf/10V/X7R/4C349 0.1uf/10V/X7R/4
C352 0.1uf/10V/X7R/4C352 0.1uf/10V/X7R/4
PE1_TX 25
PE1_TX# 25
PE2_TX 25
PE2_TX# 25
PE3_TX 24
PE3_TX# 24
A_TX0P 19
A_TX0N 19
A_TX1P 19
A_TX1N 19
A_TX2P 19
A_TX2N 19
A_TX3P 19
A_TX3N 19
VCC1_1
1.1V(RX780.RS780)
RS780 Display Port Support (muxed on GFX)
DP0
DP1
A A
5
4
3
2
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RX780/RS780-PCIE I/F
RX780/RS780-PCIE I/F
RX780/RS780-PCIE I/F
MS-7500
MS-7500
MS-7500
1
of
14 48Monday, October 29, 2007
of
14 48Monday, October 29, 2007
of
14 48Monday, October 29, 2007
0C
0C
0C
5
3VDUAL
X_NC7WZ07_SC70-6
X_NC7WZ07_SC70-6
SYS_PWRGD6,34
WD_PWRGD21
D D
Deleted R302 ,unpopulated
U62 and R108,added R304 and
R357 for RS780 A12 spec
2007/10/12
RX740/RS740/RS780 difference table
NB_PWRGD IN
ALLOW_LDTSTOP
OUT(default)/IN
LDT_STOP#
IN(default)/IN
*, CLMC mode: NB send LDT_STOP#, ALLOW_LDTSTOP will become input
C C
KG_NBHT_CLKP18
KG_NBHT_CLKN18
KG_NBGFX_CLKP18
KG_NBGFX_CLKN18
KG_NBGPP_CLKP18
KG_NBGPP_CLKN18
KG_NBREF_CLKP18
KG_NBREF_CLKN18
RS740 RX780
3.3V IN
OC OC OC/3.3V IN
3.3V IN
R188 X_0/4R188 X_0/4
R254 X_0/4R254 X_0/4
Refer to page 18 for clock
difference among RS780 and RX780
RS780
B B
ALLOW_LDTSTOP19
Unpopulated R176,R179,Q15,R170,R171
and Q10;populated R275 and R291 for
meet RS780 A12 spec. 2007/10/12
C37
C37
0.1uf/10V/X7R/4
0.1uf/10V/X7R/4
near Q10
HP recommend 2007/10/19
-LDTSTOP6,19
1 6
R304 0/4R304 0/4
3 4
X_NC7WZ07_SC70-6
X_NC7WZ07_SC70-6
R357 0/4R357 0/4
1.8V IN
1.8V IN 3.3V IN/OC
1.1V
VCC1_1
+1.8V_S0
RX780
R166 0/4R166 0/4
RX780
R202 0/4R202 0/4
RX780
RX780
+1.8V_S0 +VDDG_NB
R176
R176
X_4.7K/4
X_4.7K/4
B
RS780
Q15
Q15
CE
X_N-2N3904_SOT23
X_N-2N3904_SOT23
R291 0/4R291 0/4
RX780
+1.8V_S0 +VDDG_NB
R170
R170
X_4.7K/4
X_4.7K/4
RS780
B
RS780
Q10
Q10
CE
X_N-2N3904_SOT23
X_N-2N3904_SOT23
R275 0/4R275 0/4
U62A
U62A
52
V
V
G
G
U62B
U62B
52
V
V
G
G
RS780
1.8V IN
*
*
RS780
FB13 220-2000mAFB13 220-2000mA
FB15 220-2000mAFB15 220-2000mA
RS780
FB14 220-2000mAFB14 220-2000mA
FB16 220-2000mAFB16 220-2000mA
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
R179
R179
X_4.7K/4
X_4.7K/4
RS780
ALLOW_LDTSTOP_NB
RS780
2007/08/01
3VDUAL
X_4.7K/4
X_4.7K/4
R171
R171
X_4.7K/4
X_4.7K/4
+1.8V_S0
R93
R93
4.7K/4
R108
R108
For meet power
sequence
2007/08/06
SB_PWRGD 21
R27
G27
B27
4.7K/4
FOR EMI 07/06/15
C542 X_5pF/50V/NPO/4C542 X_5pF/50V/NPO/4
C597 X_5pF/50V/NPO/4C597 X_5pF/50V/NPO/4
C745 X_5pF/50V/NPO/4C745 X_5pF/50V/NPO/4
NB_PWRGD_IN
NB_PWRGD_IN must have a pull-up
resister to +1.8V_S0 due to
NC7W207 output pin is op-drain
X_4.7K/4
X_4.7K/4
PLL X5R
C488
C488
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C496
C496
R192
R192
LDT_STOP#_NB
RS780 RS780
C307
C307
0.1uf/16V/Y5V/4
0.1uf/16V/Y5V/4
DVI_DDC_DATA28
DVI_DDC_CLK28
R181
R181
X_4.7K/4
X_4.7K/4
RX780
A A
-LDT_RST6,19
A_RST#19,32
+1.8V_S0
RS780
X_4.7K/4
X_4.7K/4
B
Q9 N-2N3904_SOT23Q9 N-2N3904_SOT23
RS780
RX780
R191 X_0/4R191 X_0/4
R282 0/4R282 0/4
for HP recommend 2007/10/22
5
+VDDG_NB
R81
R81
CE
R84
R84
X_4.7K/4
X_4.7K/4
RS780
SYSRESET#
4
VCC3
+1.8V_S0
R49 0/4R49 0/4
+1.8V_S0
HSYNC#27
VSYNC#27
DDC_DATA27
DDC_CLK27
VCC1_1
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
C498
C498
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
NB_OSC_14M18
VCC1_1
+VDDG_NB
R172 and R175 changed to 15K
ohm for AMD SCL Checklist
2007/10/19
R175
R175
39K/4
39K/4
DDC_DATA_TP
ANALOG POWER X5R
FB8 220-2000mAFB8 220-2000mA
RS780
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
RS780
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
FB17 220-2000mAFB17 220-2000mA
RS780
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
HSYNC#
VSYNC#
RX780
R60 X_2K/4/1R60 X_2K/4/1
RX780
R66 X_2K/4/1R66 X_2K/4/1
C435
C435
C337
C337
0.1uf/16V/Y5V/4
0.1uf/16V/Y5V/4
NB_OSC_14M
R88 150/4R88 150/4
DVI_DDC_DATA
DVI_DDC_CLK
R172
R172
39K/4
39K/4
DVI_DDC_DATA
DVI_DDC_CLK
DDC_CLK_TP
Note: for RS780, change R198 to 150R as AUX_CAL,
place close to pin C8
4
AVDD
15 MILS WIDTH
RS780
C506
C506
AVDDDI
RS780
RS780
C544
C544
R205 150/4/1R205 150/4/1
R206 150/4/1R206 150/4/1
R53 150/4/1R53 150/4/1
R54 0/4R54 0/4
R55 0/4R55 0/4
C543
C543
0.1uf/16V/Y5V/4
0.1uf/16V/Y5V/4
15 MILS WIDTH
15 MILS WIDTH
VSYNC#
RX780_DFT_GPIO2
RX780_DFT_GPIO4
RX780_DFT_GPIO5
PA_RX7X0A1:R189,R190,R196 have been changed
from 3K to 1K. 2007/08/06
15 MILS WIDTH
C514
C514
AVDDQ
15 MILS WIDTH
RS780
C540
C540
0.1uf/16V/Y5V/4
0.1uf/16V/Y5V/4
10 MILS WIDTH
RS780
10 MILS WIDTH
RS780
10 MILS WIDTH
RS780
RS780
RS780
15 MILS WIDTH
15 MILS WIDTH
R61 0/4R61 0/4
HSYNC#
R178 150/4R178 150/4
TP47TP47
TP48TP48
STRP_DATA36
TP84TP84
For RS780 2007/09/06
reference AMD demo borard
SHINER rev 2.0 C)
RS740_DFT_GPIO1
For RS780 2007/08/14
R184 3K/4R184 3K/4
R169 X_3K/4R169 X_3K/4
R189 X_1K/4R189 X_1K/4
R190 X_1K/4R190 X_1K/4
R196 X_1K/4R196 X_1K/4
R127 3K/4R127 3K/4
R185 X_10K/4R185 X_10K/4
RX780_DFT_GPIO5
RX780_DFT_GPIO2
RX780_DFT_GPIO4
DAC_RSET
R200715/4/1 R200715/4/1
RS780
PLLVDD
PLLVDD18
VDDA18HTPLL
VDDA18PCIEPLL
SYSRESET#
NB_PWRGD_IN
LDT_STOP#_NB
ALLOW_LDTSTOP_NB
NBHT_REFCLKP
NBHT_REFCLKN
NBGFX_SRCCLK
NBGFX_SRCCLK#
NBGPP_CLKP
NBGPP_CLKN
SBLINKCLK
SBLINKCLK#
DVI_DDC_DATA
DVI_DDC_CLK
DDC_DATA_TP
DDC_CLK_TP
STRP_DATA
RSVD
RS740_DFT_GPIO1
R198 150/4R198 150/4
3
RS780 RX780
R149 0/4R149 0/4
U3C
U3C
F12
NC1
E12
NC2
F14
NC3
G15
NC4
H15
NC5
H14
NC6
E17
DFT_GPIO5
F17
DFT_GPIO2
F15
DFT_GPIO4
G18
RED(DFT_GPIO0)
G17
NC7
E18
GREEN(DFT_GPIO1)
F18
NC8
E19
BLUE(DFT_GPIO3)
F19
NC9
A11
DAC_HSYNV(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
E8
DAC_SCL(PCE_TCALRN)
F8
DAC_SDA(PCE_RCALRN)
G14
PWM_GPIO1
A12
PLLVDD(NC10)
D14
PLLVDD18(NC11)
B12
PLLVSS(NC12)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL
E7
VDDA18PCIEPLL
D8
SYSRESET#
A10
POWERGOOD
C10
LDTSTOP#
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
OSCIN
F11
PWM_GPIO3
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
SB_REFCLKP
V3
SB_REFCLKN
A9
I2C_DATA
B9
I2C_CLK
B8
DDC_DATA0/AUX0N(NC13)
A8
DDC_CLK0/AUX0P(NC14)
B7
DDC_CLK1/AUX1P(NC15)
A7
DDC_DATA1/AUX(NC16)
B10
STRP_DATA
G11
VSS
C8
AUX_CAL(NC17)
AMD-215NDA7BKA11FG-A11-RH
AMD-215NDA7BKA11FG-A11-RH
R163 X_0/4R163 X_0/4
PART 3 OF 6
PART 3 OF 6
CRT/TVOUT
CRT/TVOUT
LVTM
LVTM
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
+1.8V_S0+VDDG_NBVCC3
DVI_TXD00P
NC18
NC19
NC20
NC21
NC22
DBG_GPIO0
NC23
DBG_GPIO2
NC24
NC25
PCIE_RESET_GPIO3
PCIE_RESET_GPIO2
NC26
NC27
PCIE_RESET_GPIO5
NC28
DBG_GPIO1
DBG_GPIO3
PCIE_RESET_GPIO4
PCIE_RESET_GPIO1
VDDLTP18(NC29)
VSSLTP18(NC30)
VDDLT18_1(NC31)
VDDTL18_2(NC32)
NC33
NC34
PCE_TCALRP
PCE_RCALRP
PWM_GPIO2
HPD0
SUS_STAT#(PWM_GPIO5)
HPD1
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
DVI_TXD01P
DVI_TXD02P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
RS780
R41 110/4R41 110/4
RS780
R44 110/4R44 110/4
RS780 RS780
R46 110/4R46 110/4
15 / 5 / 7 / 5 / 15
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
DBG_GPIO1
B16
DBG_GPIO3
A16
D16
D17
VDDLTP18
A13
B13
0.1uf/16V/Y5V/4
0.1uf/16V/Y5V/4
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
R210 4.7K/4R210 4.7K/4
E9
F7
G12
RX780
RX780
D9
R112 0/4R112 0/4
HPD1
D10
R187 10K/4R187 10K/4
D12
RS780
AE8
AD8
TEST_EN
D13
R87
R87
1.8K/4
1.8K/4
RS740/RX780/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE
VCC3
Enables the Test Debug Bus using GPIO and/or memory IO
1 : Disable (RS740/RS780); Enable (RX780)
0 : Enable (RS740/RS780); Disable(RX780)
RS740: pin DFT_GPIO5
RX780: pin DFT_GPIO5
RS780: pin VSYNC
RX780: STRAP_PCIE_GPP_CFG[2:0] (Pins: RX780_DFT_GPIO[4:2])
111: 1-1-1-1-1-1 Mode L default
110: 1-1-1-1-1-1 Mode L
101: 2-0-2-0-2-0 Mode C2
100: 2-0-2-0-1-1 Mode K
011: 2-0-1-1-1-1 Mode E
010: 1-1-1-1-1-1 Mode L
001: 4-0-0-0-1-1 Mode C
000: 4-0-0-0-2-0 Mode B
RS740/RX780/RS780: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RX780: pin DFT_GPIO1
RS780: pin SUS_STAT#
RS740/RX780/RS780: SIDE-PORT MEMORY ENABLE
Enables Side port memory
VCC3
1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
RS780: pin HSYNC
RX780: Not Appicable
3
RS780: STRAP_PCIE_GPP_CFG[2:0]
(configure thru register setting)
1-1-1-1-1-1 Mode L default
1-1-1-1-1-1 Mode L
2-0-2-0-2-0 Mode C2
2-0-2-0-1-1 Mode K
2-0-1-1-1-1 Mode E
1-1-1-1-1-1 Mode L
4-0-0-0-1-1 Mode C
4-0-0-0-2-0 Mode B
2
DVI_TXD00N
DVI_TXD00P 28
DVI_TXD00N 28
DVI_TXD01P 28
DVI_TXD01N 28
DVI_TXD02P 28
DVI_TXD02N 28
DVI_TXC0P 28
DVI_TXC0N 28
15 MILS WIDTH
C428
C428
RS780
VDDLT18
VDDLT33
DVI_TXD01N
DVI_TXD02N
C505
C505
2.2uf/6.3V/X5R/6
2.2uf/6.3V/X5R/6
15 MILS WIDTH
TP38TP38
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
DVI_TXC0P
RS780
L9 28L900m_100_0805L9 28L900m_100_0805
RS780
L7
L7
C539
C539
C570
C570
1uf/6.3V/Y5V/4
1uf/6.3V/Y5V/4
RS780
RS780
R47 110/4R47 110/4
+1.8V_S0
28L900m_100_0805
28L900m_100_0805
ANALOG POWER X5R
RS780
PWM_GPIO2
R72 X_1.27K/4/1R72 X_1.27K/4/1
R71 X_1.27K/4/1R71 X_1.27K/4/1
THERMDA_NB 27
THERMDC_NB 27
RX780/RS740/RS780 DEBUG PIN MAPPING
DEBUG_OUT0
DEBUG_OUT1
DEBUG_OUT2
DEBUG_OUT3
DEBUG_OUT4
DEBUG_OUT5
DEBUG_OUT6
DEBUG_OUT7
VCC3
TP37TP37
TMDS_HPD0 28
TMDS_HPD1 25
Refer to page 50 (item 12-31) of
RS780 schematic checklist.
RX780
RED(DFT_GPIO0)
GREEN(DFT_GPIO1)
Y(DFT_GPIO2)
BLUE(DFT_GPIO3)
LVDS_DIGON
LVDS_ENA_BL
LVDS_BLON
TMDS_HPD
TXOUT_L2N(DBG_GPIO0)
TXCLK_LP(DBG_GPIO1)
TXOUT_L3N(DBG_GPIO2)
TXCLK_LN(DBG_GPIO3)
RX780/RS780: STRAP_DEBUG_BUS_PCIE_ENABLE
Enables Test debug bus
using PCIE bus
1. Disable (can be enabled
thru nbcfg register)
0 : Enable
RX780: pin DFT_GPIO0
RS780: configurable thru register
setting only
RS740: Not supported
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
MICRO-STAR INt'L CO., LTD.
RX780/RS780-SYSTEM I/F
RX780/RS780-SYSTEM I/F
RX780/RS780-SYSTEM I/F
1
DVI_TXC0N
Q4
Q4
RS780
SD
N-2N7002_SOT23
N-2N7002_SOT23
G
R90 4.7K/4R90 4.7K/4
RS780
RS740 RS780
LVDS_DIGON
LVDS_ENA_BL
LVDS_BLON
TMDS_HPD
X
X
X
X
MS-7500
MS-7500
MS-7500
1
AUX1N
AUX1P
HPD
AUX_CAL
15 48Monday, October 29, 2007
15 48Monday, October 29, 2007
15 48Monday, October 29, 2007
+1.8V_S0
of
+12V
0C
0C
0C
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