MSI MS-7418 7418_21_0630
1
COVER SHEET
BLOCK DIAGRAM
CLOCK MAP
POWER MAP
1
MS-7418 (MS-6496)
2
3
4
CPU:
Version 2.1
Intel Dimondville
GPIO MAP
Intel Diamondville-CPU
VRM Single Phase
Intel Lakeport -GMCH
DDR II SO-DIMM
Mini PCIE Slot
5
6-7
8
9-12
13-14
15
System Chipset:
Intel 945GC (North Bridge)
Intel ICH7(South Bridge)
On Board Chipset:
LAN 8111C
VGA CONNECTOR
16
17
BIOS -- SPI
HD AUDIO CODEC(ALC888)
Clock Generator - ICS954120
A A
ICH7R
TPM LPC Debug port
18
19-21
22
LAN -- Realtek RTL8111C
Clock Generator - ICS954119
Main Memory:
USB CONNECTORS
HD AUDIO CODEC(ALC 888)
+19V DC-IN
5DUAL-PCIRST#
F_ PANEL
SATA & CF_Card & FAN CONTROL
ACPI Controller
Auto BOM manual
PWOK MAP
23
24
25
26
27
28
29
30
31
32History
DDR II SO-DIMM x 1 (Max 2GB)
CF Card Connector for flash Memory
Expansion Slots:
Internal Mini PCIE x1
Intersil PWM:
Controller:
1
6314
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7418
MS-7418
MS-7418
of
of
of
132Monday, June 30, 2008
132Monday, June 30, 2008
132Monday, June 30, 2008
2.1
2.1
2.1
1
2
3
4
5
VRM
A A
1-Phase PWM
Intel Diamondville
>1.6GHz, SC
Block Diagram
FSB
533
Analog
RGB
Video Out
B B
CF Slot x1
SATA
SATA 0~1
USB
USB Port 0~7
include
Lakeport
945GC
ICH7
DMI
PCI Express x1
DDR II
533 SO-DIMM x1
Mini PCIE1
Realtek RTL8111C
GbE LAN
4in1 Cardreader
Azalia Codec
C C
ALC888
SPI
BIOS
D D
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7418 2.1
MS-7418 2.1
MS-7418 2.1
232Monday, June 30, 2008
232Monday, June 30, 2008
232Monday, June 30, 2008
5
5
4
3
2
1
HCLK
CLOCK MAP
D D
MCHCLK
PE_100M
Diamondville
Lakeport
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
266MHz
266MHz
266MHz
266MHz
DDRII
SO-DIMM
MCH
DOTCLK
ICS954119
ICHCLK
Clock
Generator
C C
SATACLK
USB48MHz
ICH14.318MHz
ICH7
24MHz
ALC888 Azalia
32.768MHz
48MHz
4in1 CardReader
PE_100M
100MHz
Mini PCIE
B B
PE_100M
100MHz
LAN Realtek
8111C
LPC Debug port
33MHz
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
CLOCK MAP
CLOCK MAP
CLOCK MAP
MS-7418
MS-7418
MS-7418
1
2.1
2.1
332Monday, June 30, 2008
332Monday, June 30, 2008
332Monday, June 30, 2008
2.1
of
of
of
5
4
3
2
1
POWER MAP
DC12V IN
D D
+12V +5V +3.3V +5VSB
MSI
C C
ACPI
Logic gate
VCC5_SB
VCC5
V_FSB_VTT
B B
4.9A
PCIE1
VRM
VCC_DDR
6.75+1.2 = 7.95A7.95*1.8/5/0.8 = 3.58A
UPI
V_1P5_CORE
UPI
V_1P05_CORE
LINEAR
LINEAR
22.84A
0.86A
4.9A
17.08A
0.86A
Diamondville
Lakeport
4.4A
MCH
13.8A + 1.5A
= 15.3A
2.35A
SO-DIMM
1.2A
DDR2 X 1
1.78A
0.86A
ICH7
0.375A
0.9A
14mA
4A
0.375A
VCC3_SB VTT_DDR
W83310DS
5VDUAL
A A
5
4
1.2A
3A
3
USB
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
POWER MAP
POWER MAP
POWER MAP
MS-7418
MS-7418
MS-7418
1
2.1
2.1
432Monday, June 30, 2008
432Monday, June 30, 2008
432Monday, June 30, 2008
2.1
of
of
of
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
8
7
6
5
4
3
2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name or status
GPIO[0] SIO_SMI# AB18 I/O Vcc3p3 N Y 5 Input pull high VCC3
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-down
FPGI[1] 5 Main 3.3 pull-down
FPGI[2] 4 Main 3.3 pull-down
FPGI[3] 3 Main 3.3 pull-down
FPGI[4] 30 Main 3.3 pull-downGPIO[6] ATADET0 AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] GPI7 AC18 I/O Vcc3p3 N Y 3.3 Input pull high VCC3
GPIO[8] SIO_PME# E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME# pull high VCC3_SB
GPIO[9] WLAN_PWRON E20 I/O VccSus3p3 N Y 3.3 Output pull high VCC3_SB
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[14] ADT7467_ALERT R4 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC
SIGNAL DEVICE
MiniPCIeRST#
TPMRST#
LANRST#
PCIRST_ICH7#
CF_RST#
H_CPURST#
FWHRST#
MCHRST#
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
C C
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
SMBCLK, SMBDATA DDR2, PCIEX1, CLKGEN, ICH7, ADT7464
DDRII DIMM Config.
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change NC
GPIO[25] S1_3_LED D20 I/O VccSus3p3 Y N 3.3 1 pull high VCC3 SB
DIMM 1
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 NC
GPIO[29] OC#2 C3 I/O VccSus3p3 N N 3.3 Input OC#5
GPIO[30] OC#2 A2 I/O VccSus3p3 N N 3.3 Input OC#6
JUMPER SETTING
JBAT1
GPIO[31] OC#2 B3 I/O VccSus3p3 N N 3.3 Input OC#7
GPIO[32] CLEAR_CMOS# AG18 I/O Vcc3p3 N N 3.3 1 CLEAR_CMOS#, ONLY pull high VCC3
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 NC
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input pull high VCC3
B B
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A GNT4#
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
GPI[15..0] can configured to cause a SMI# or SCI.
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
MINI PCIE SLOT
TPM
LAN 8111C
BUFFER IC
CF_CARD
CPU
LPT Debug port
MCH
CLOCKDEVICE ADDRESS
A0H
(1-2)NORMAL
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
(2-3)CLEAR
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
GPIO MAP
GPIO MAP
GPIO MAP
MS-7418
MS-7418
MS-7418
2.1
2.1
2.1
of
of
of
532Monday, June 30, 2008
532Monday, June 30, 2008
532Monday, June 30, 2008
1
8
7
6
5
4
3
2
1
CPU SIGNAL BLOCK
D D
U10A
H_A#[3..31]9
H_ADSTB#09
T1T1
H_REQ#[0..4]9
C C
H_A#[3..31]9
V_FSB_VTT
7 8
5 6
8P4R-1KR0402
8P4R-1KR0402
B B
A A
3 4
1 2
H_ADSTB#19
T4T4
H_A20M#19
H_FERR#19
H_IGNNE#19
H_STPCLK#19
H_INTR19
H_NMI19
ICH_H_SMI#19
0B changed 3
unstuff Resistors refer
to CRB V0.8
H_A20M#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
ICH_H_SMI#
R14 unstuffed refer to CRB V0.8
8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
RN2
RN2
T15T15
T16T16
T18T18
T20T20
T22T22
T23T23
T24T24
R243 X_1KST_0402R243 X_1KST_0402
R227 X_1KST_0402R227 X_1KST_0402
R229 X_56R/4R229 X_56R/4
R716 X_51R1%0402R716 X_51R1%0402
R717 X_51R1%0402R717 X_51R1%0402
R718 X_1KST_0402R718 X_1KST_0402
P21
H20
N20
R20
J19
N19
G20
M19
H21
L20
M20
K19
J20
L21
K20
D17
N21
J21
G19
P20
R19
C19
F19
E21
A16
D19
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
U18
T16
J4
R16
T15
R15
U17
D6
G6
H6
K4
K5
M15
L16
V_FSB_VTT
U10A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
7
XDP/ITP SIGNALSTHERM
XDP/ITP SIGNALSTHERM
THERMTRIP#
H CLK
H CLK
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
BR1#
PROCHOT#
THERMDA
THERMDC
BCLK[0]
BCLK[1]
RSVD3
RSVD2
RSVD1
ADDR GROUP
0
ADDR GROUP
0
ADDR GROUP 1
ADDR GROUP 1
Diamondville
Diamondville
V19
Y19
U21
T21
T19
Y18
T20
H_IERR#
F16
V16
W20
D15
H_RS#0
W18
H_RS#1
Y17
H_RS#2
U20
W19
AA17
HIT#
V20
H_BPM#0
K17
H_BPM#1
J18
H_BPM#2
H15
H_BPM#3
J15
H_BPM#4
K18
PREQ#
J16
H_TCK
M17
TCK
TDO
TMS
TDI
N16
M16
L17
K16
V15
G17
E4
E5
H17
V11
V12
C21
C1
A3
H_TDI
H_TMS
H_TRST#
H_PROCHOT#
BSEL
1 FSB FREQUENCY
0 0 133 MHZ (533)
For Diamondville processor
, the BSEL is fixed to operate
at 133-MHz BCLK frequency.
T17T17
T19T19
T21T21
02
1
H_ADS# 9
H_BNR# 9
H_BPRI# 9
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BR#0 9
H_LOCK# 9
H_CPURST# 9
H_TRDY# 9
H_HIT# 9
H_HITM# 9
R715 X_150R1%0402-1R715 X_150R1%0402-1
R723
R723
22R1%0402
22R1%0402
CPU_TMPA 28
VTIN_GND 28
TRMTRIP# 19
CK_H_CPU 18
CK_H_CPU# 18
TABLE
6
1
3
5
7
R713
R713
RN35
RN35
R235
R235
62R
62R
51R1%0402
51R1%0402
0B changed 2
2
4
6
8
0B changed 1
unstuff R712 refer
to CRB V0.8
V_FSB_VTT
R712
R712
X_330R0402-1
X_330R0402-1
R27
R27
1KST_0402
1KST_0402
V_FSB_VTT
8P4R-51R0402
8P4R-51R0402
H_INIT# 19
H_IERR#
H_TDI
H_TMS
PREQ#
V_FSB_VTT
V_FSB_VTT
V_FSB_VTT
R15 51R1%0402R15 51R1%0402
R16 1KST_0402R16 1KST_0402
R17 51R1%0402R17 51R1%0402
V_FSB_VTT
H_RS#[0..2] 9
0B Change 13
V_FSB_VTT
R1 1KST_0402R1 1KST_0402
RN1
RN1
1
2
3
4
5
6
8P4R-51R0402
8P4R-51R0402
7
8
H_TCK
H_TRST#
R240
R240
X_1KST_0402
X_1KST_0402
R13 56R/4R13 56R/4
R2 51R1%0402R2 51R1%0402
R3 51R1%0402R3 51R1%0402
0B changed 4
H_FERR#
PLACE AT ICH END OF ROUTE
0B changed 5
H_CPURST#
H_PWRGD
H_BR#0
PLACE AT CPU END OF ROUTE
RN3
RN3
1
3
5
7
8P4R-470R
8P4R-470R
H_FSBSEL2
2
H_FSBSEL1
4
H_FSBSEL0
6
8
5
H_DBI#[0..3] 9
C1
C0.1U25YC1C0.1U25Y
H_CPURST# 9
H_PWRGD 19
H_BR#0 9
H_FSBSEL2 11,18
H_FSBSEL1 11,18
H_FSBSEL0 11,18
C2
C0.1U25YC2C0.1U25Y
U10B
H_D#[0..63]9
H_DSTBN#09
H_DSTBP#09
T2T2
H_D#[0..63]9
H_DSTBN#19
H_DSTBP#19
T5T5
R5 X_1KR0402R5 X_1KR0402
R7 X_1KR0402R7 X_1KR0402
T9T9
H_FSBSEL011,18
H_FSBSEL111,18
H_FSBSEL211,18
1KST_0402
1KST_0402
2KR1%0402
2KR1%0402
4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DBI#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DBI#1
GTLREF
BINIT#
T7T7
EDM
T8T8
EXTBGREF
FORCEPR#
T10T10
HFPLL
T11T11
MCERR#
T12T12
RSP#
T13T13
V_FSB_VTT V_FSB_VTTV_FSB_VTT
0.5" max
length
R18
R18
EXTBGREF CPU_CMREFGTLREF
R21
R21
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
C4
C4
C1u6.3X50402
C1u6.3X50402
U10B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGR
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
3
DATA GRP1
DATA GRP1
MISC
MISC
Diamondville
Diamondville
D[32]#
D[33]#
D[34]#
DATA GRP0
DATA GRP0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
CORE_D
CMREF
R19
R19
1KST_0402
1KST_0402
R22
R22
2KR1%0402
2KR1%0402
H_D#32
R3
H_D#33
R2
H_D#34
P1
H_D#35
N1
H_D#36
M2
H_D#37
P2
H_D#38
J3
H_D#39
N3
H_D#40
G3
H_D#41
H2
H_D#42
N2
H_D#43
L2
H_D#44
M3
H_D#45
J2
H_D#46
H1
H_D#47
J1
K2
K3
H_DBI#2
L1
M4
H_D#48
C2
H_D#49
G2
H_D#50
F1
H_D#51
D3
H_D#52
B4
H_D#53
E1
H_D#54
A5
H_D#55
C3
H_D#56
A6
H_D#57
F2
H_D#58
C6
H_D#59
B6
H_D#60
B3
H_D#61
C4
H_D#62
C7
H_D#63
D2
E2
F3
H_DBI#3
C5
D4
H_COMP0
T1
H_COMP1
T2
H_COMP2
F20
H_COMP3
F21
R25 X_1KR0402R25 X_1KR0402
R10 1KR0402R10 1KR0402
R18
R11 1KR0402R11 1KR0402
R17
R12 1KR0402R12 1KR0402
U4
V17
R14 X_1KR0402R14 X_1KR0402
N18
A13
CPU_CMREF
B7
0.5" max
length
C5
C5
X_0.1u10X4
X_0.1u10X4
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
H_D#[0..63] 9
H_DSTBN#2 9
H_DSTBP#2 9
T3T3
H_D#[0..63] 9
0B changed 6
Change R4,R8 to 24.9R
R6,R9 to 49.9R.
H_DSTBN#3 9
H_DSTBP#3 9
T6T6
R4 24.9R1%0402R4 24.9R1%0402
R6 49.9R1%0402R6 49.9R1%0402
R8 24.9R1%0402R8 24.9R1%0402
R9 49.9R1%0402R9 49.9R1%0402
VCC3_SB
V_FSB_VTT
V_FSB_VTT
V_FSB_VTT
H_PWRGD 19
V_FSB_VTT
T14T14
0R0402
0R0402
H_SB_CPUSLP_N 19
R254
R254
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Signals
Intel LGA775 - Signals
Intel LGA775 - Signals
0.5" max length
25 MIL AWAY FROM HIGH
SPEED SIGNAL
HCOMP0,2==>18MIL
HCOMP1,3==>5MIL
0.5" max
length
C3
0.1u10X4C30.1u10X4
MS-7418
MS-7418
MS-7418
R20
R20
1KST_0402
1KST_0402
R23
R23
2KR1%0402
2KR1%0402
632Monday, June 30, 2008
632Monday, June 30, 2008
632Monday, June 30, 2008
1
2.1
2.1
2.1
of
of
of
8
U10C
V10
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
U10C
VCCF
A9
VCCQ1
B9
VCCQ2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
J10
VCCP25
J11
VCCP26
J12
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
Diamondville
Diamondville
POWER
POWER
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VCCSENSE
VSSSENSE
V_FSB_VTT
VCCP
D D
C C
B B
7
V_FSB_VTT
C9
VTT1
D9
VTT2
E9
VTT3
F8
VTT4
F9
VTT5
G8
VTT6
G14
VTT7
H8
VTT8
H14
VTT9
J8
VTT10
J14
VTT11
K8
VTT12
K14
VTT13
L8
VTT14
L14
VTT15
M8
VTT16
M14
VTT17
N8
VTT18
N14
VTT19
P8
VTT20
P14
VTT21
R8
VTT22
R14
VTT23
T8
VTT24
T14
VTT25
U8
VTT26
U9
VTT27
U10
VTT28
U11
VTT29
U12
VTT30
U13
VTT31
U14
VTT32
F14
F13
E14
E13
D7
VCCA
F15
VID[0]
D16
VID[1]
E18
VID[2]
G15
VID[3]
G16
VID[4]
E17
VID[5]
G18
VID[6]
C13
D13
LAYOUT NOTE:
Route VCCSENSE and VSSSENSE
traces at 27.4Ohms with 50
mil spacing.
Place PU and PD within 1
inch of CPU.
0B changed 7
unstuff R304,stuff R303
V_FSB_VTT
R3030RR303
0R
H_VCCA
R172 0R0402R172 0R0402
R190 0R0402R190 0R0402
R191 0R0402R191 0R0402
R192 0R0402R192 0R0402
R214 0R0402R214 0R0402
R220 0R0402R220 0R0402
R268 0R0402R268 0R0402
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCC_VRM_SENSE 8
VSS_VRM_SENSE 8
VCCP
6
C483
C483
X_C0.1U25Y
X_C0.1U25Y
C484
C484
X_C0.1U25Y
X_C0.1U25Y
C485
C485
X_C0.1U25Y
X_C0.1U25Y
C486
C486
X_C0.1U25Y
X_C0.1U25Y
R304
R304
X_0R
X_0R
VID3
R473 2.2KR0402R473 2.2KR0402
VID1
R472 2.2KR0402R472 2.2KR0402
VID2
R471 2.2KR0402R471 2.2KR0402
VID4
R470 2.2KR0402R470 2.2KR0402
VID0
R469 2.2KR0402R469 2.2KR0402
VID5
R468 2.2KR0402R468 2.2KR0402
VID6
R467 2.2KR0402R467 2.2KR0402
VID0
R269 X_0R0402R269 X_0R0402
VID1
R274 X_0R0402R274 X_0R0402
VID2
R275 X_0R0402R275 X_0R0402
VID3
R276 X_0R0402R276 X_0R0402
VID4
R281 X_0R0402R281 X_0R0402
VID5
R282 X_0R0402R282 X_0R0402
VID6
R286 X_0R0402R286 X_0R0402
Change VID circuit for jump VID.
VID[6..0] 8
V_FSB_VTT
5
U10D
U10D
A2
VSS
A4
VSS
A8
VSS
A15
VSS
A18
VSS
A19
VSS
A20
VSS
B1
VSS
B2
VSS
B5
VSS
B8
VSS
B13
VSS
B20
VSS
B21
VSS
C8
VSS
C17
VSS
D1
VSS
D5
VSS
D8
VSS
D14
VSS
D18
VSS
D21
VSS
E3
VSS
E6
VSS
E7
VSS
E8
VSS
E15
VSS
E16
VSS
E19
VSS
F4
VSS
F5
VSS
F6
VSS
F7
VSS
F17
VSS
F18
VSS
G1
VSS
G4
VSS
G7
VSS
G9
VSS
G13
VSS
G21
VSS
H3
VSS
H4
VSS
H7
VSS
H9
VSS
H13
VSS
H16
VSS
H18
VSS
H19
VSS
J5
VSS
J7
VSS
J9
VSS
J13
VSS
J17
VSS
K1
VSS
K6
VSS
K7
VSS
K9
VSS
K13
VSS
K15
VSS
K21
VSS
L3
VSS
L4
VSS
L5
VSS
L6
VSS
L7
VSS
L9
VSS
L13
VSS
L15
VSS
L18
VSS
L19
VSS
M1
VSS
M5
VSS
M7
VSS
M9
VSS
M13
VSS
Diamondville
Diamondville
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N9
N7
N5
N4
M21
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
3
2
0B changed 8-->change pull up circuit follow CRB V0.7.
X_0R
X_0R
H_VCCA
C6
C6
C10U10Y1206
C10U10Y1206
V_1P5_CORE
R24
R24
VCC_DDR
C7
C7
C0.01U50X
C0.01U50X
R719
R719
2R1%
2R1%
R720
R720
53.6R1%
53.6R1%
R721
R721
53.6R1%
53.6R1%
NEAR THE PROCESS SOCKET
2.5A: before VCC stable
1.5A: after VCC stable
R722
R722
53.6R1%
53.6R1%
C8 C10U10Y0805C8 C10U10Y0805
C9 C10U10Y0805C9 C10U10Y0805
C10 C10U10Y0805C10 C10U10Y0805
C11 C0.1U25YC11 C0.1U25Y
C12 C0.1U25YC12 C0.1U25Y
CAPS FOR FSB GENERIC
1
V_FSB_VTT
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Power
Intel LGA775 - Power
Intel LGA775 - Power
MS-7418
MS-7418
MS-7418
2
2.1
2.1
732Monday, June 30, 2008
732Monday, June 30, 2008
732Monday, June 30, 2008
1
2.1
of
of
of
8
VRM_GD
D D
+12V
ENVTT
C C
+12V
R1004.7KR R1004.7KR
Q2
Q2
N-PMBS3904_SOT23-RH
N-PMBS3904_SOT23-RH
VCC_VRM_SENSE7
VSS_VRM_SENSE7
VCC5
B B
7
VCC5_SB
D1
D1
1N4148W-F_SOD123-RH
1N4148W-F_SOD123-RH
R28
R28
4.7KR
4.7KR
100KR
100KR
R41
R41
5.6KR
5.6KR
R43 1KRR43 1KR
SOT23EBC
SOT23EBC
Q29
Q29
N-MMBT2222ALT1_SOT23
N-MMBT2222ALT1_SOT23
ECB
R44 10KRR44 10KR
AC
R30
R30
C1U10X
C1U10X
VID_GD 29
R48 0R0402R48 0R0402
R51 0R0402R51 0R0402
VCC5
C14
C14
R55
R55
100K
100K
R56
R56
X_0R0402
X_0R0402
R345
R345
R309
R309
210R1%
210R1%
210R1%
210R1%
R344
R344
X_0R
X_0R
210R1%
210R1%
R346
R346
UBUF2E
UBUF2E
147
74LVC07AD
74LVC07AD
11 10
0B Change 10
C18
C18
C10u6.3X5-RH
C10u6.3X5-RH
VCCP
R46
R46
100_0402
100_0402
R52
R52
100_0402
100_0402
VCC3_SB
VID[6..0]7
C21
C21
X_0.1u_0402
X_0.1u_0402
C31
C31
X_C0.01u16X0402
X_C0.01u16X0402
C39
C39
C0.01u16X0402
C0.01u16X0402
100K 1%_0402
100K 1%_0402
6
Fix RTC time lost issue.
disconnect UBUF2 pin14 of partA~E
and add voltage divided circuit at part E.
VCC3VCC3
R29
R29
4.7KR
C13
C13
C0.1U25X
C0.1U25X
P0_SS
R57
R57
4.7KR
0R0402
0R0402
C26
C26
X_C0.01u16X0402
X_C0.01u16X0402
C32
C32
X_0.1u_0402
X_0.1u_0402
VID6
VID5
VID4
VID3
VID2
VID1
VID0
R101
R101
R58
R58
243KR1%0402-RH-1
243KR1%0402-RH-1
0R
R310RR31
U3
U3
1
PGOOD
17
EN
32
VID7
25
VID6
26
VID5
27
VID4
28
VID3
29
VID2
30
VID1
31
VID0
12
VSEN
11
RGND
5
OFS
4
REF
3
FS
2
SS
6X6 QFN
BOTTOM PAD
CONNECT TO GND
Through 8 VIAs
5
ALLPWRGD 20,29VRM_GD18
VCC5
R32
R32
2.2R
2.2R
C161uC16
1u
18
PVCC
VCC
BOOT
UGATE
PHASE
LGATE
ISEN+
ISEN-
ISENNO
OCSET
NC
VDIFF
DVC
FB
COMP
APA
GND
ISL6314CRZ
ISL6314CRZ
33
+12V
C17
C17
C1U16X0805-1
C1U16X0805-1
19
R39 2.2_1%R39 2.2_1%
22
23
24
21
ISEN_CPU0
16
15
PHASE_CPU0
14
13
487R1%0402-1
487R1%0402-1
20
10
8
22KR1%0402-RH-1
22KR1%0402-RH-1
9
7
6
R33
R33
2.2R
2.2R
R45
R45
R47 X_220_1%_0402R47 X_220_1%_0402
R49 169R1%0402R49 169R1%0402
R50
R50
C37 0.1u_0402C37 0.1u_0402
R54 3K_1%R54 3K_1%
4
C19 0.1u_0402C19 0.1u_0402
R40 14.7KR1%0402R40 14.7KR1%0402
R42
R42
24KR1%0402
24KR1%0402
C24 C0.022u16X0402C24 C0.022u16X0402
C27 1000p_0402C27 1000p_0402
C36 C470p16X-1C36 C470p16X-1
R53 768R1%0402R53 768R1%0402
C22 X_0.1u_0402C22 X_0.1u_0402
C25 X_2200pC25 X_2200p
C38 C0.01u16X0402C38 C0.01u16X0402
3
R35 0R0805R35 0R0805
R36 10KR0402R36 10KR0402
R37 0R0805R37 0R0805
C23
C23
0.1u_0402
0.1u_0402
VCCP
VCCP
VCCP
VCCP
VCCP
C585
C585
C10u6.3X5-RH
C10u6.3X5-RH
C596
C596
C10u6.3X5-RH
C10u6.3X5-RH
+12V
2
3
4
C139
C139
C1u6.3X50402
C1u6.3X50402
C149
C149
C1u6.3X50402
C1u6.3X50402
C211
C211
C1u6.3X50402
C1u6.3X50402
C586
C586
C10u6.3X5-RH
C10u6.3X5-RH
C591
C591
X_C10u6.3X5-RH
X_C10u6.3X5-RH
2
C15
C15
10u-16V-1206
10u-16V-1206
Q1
Q1
81
7
6
5
NN-SP8K10S_SOP8-RH
NN-SP8K10S_SOP8-RH
C142
C142
C1u6.3X50402
C1u6.3X50402
C150
C150
C1u6.3X50402
C1u6.3X50402
C160
C160
C1u6.3X50402
C1u6.3X50402
VCCP
+
+
EC46
EC46
1800u_6.3V
1800u_6.3V
C587
C587
X_C10u6.3X5-RH
X_C10u6.3X5-RH
C592
C592
C10u6.3X5-RH
C10u6.3X5-RH
C143
C143
C1u6.3X50402
C1u6.3X50402
C152
C152
C1u6.3X50402
C1u6.3X50402
C457
C457
C1u6.3X50402
C1u6.3X50402
R38
R38
2.2R0805
2.2R0805
C20
C20
1000p_0402
1000p_0402
PHASE_CPU0
ISEN_CPU0
C144
C144
C1u6.3X50402
C1u6.3X50402
C154
C154
C1u6.3X50402
C1u6.3X50402
C456
C456
C1u6.3X50402
C1u6.3X50402
C590
C590
C10u6.3X5-RH
C10u6.3X5-RH
C595
C595
C10u6.3X5-RH
C10u6.3X5-RH
CHOKE1 1.2uHCHOKE1 1.2uH
SP1
SP1
X_PAD_0402
X_PAD_0402
C145
C145
C1u6.3X50402
C1u6.3X50402
C156
C156
C1u6.3X50402
C1u6.3X50402
C459
C459
C1u6.3X50402
C1u6.3X50402
C588
C588
X_C10u6.3X5-RH
X_C10u6.3X5-RH
C594
C594
X_C10u6.3X5-RH
X_C10u6.3X5-RH
1
C147
C147
C1u6.3X50402
C1u6.3X50402
C158
C158
C1u6.3X50402
C1u6.3X50402
C458
C458
C1u6.3X50402
C1u6.3X50402
C589
C589
X_C10u6.3X5-RH
X_C10u6.3X5-RH
C593
C593
X_C10u6.3X5-RH
X_C10u6.3X5-RH
VCCP
SP2
SP2
X_PAD_0402
X_PAD_0402
5A
C40
C40
10u-16V-1206
10u-16V-1206
C41
C41
X_10u-16V-1206
A A
8
X_10u-16V-1206
C42
C42
X_10u-16V-1206
X_10u-16V-1206
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
VRM- Single Phase
VRM- Single Phase
VRM- Single Phase
MS-7418
MS-7418
MS-7418
2
2.1
2.1
832Monday, June 30, 2008
832Monday, June 30, 2008
832Monday, June 30, 2008
1
2.1
of
of
of
8
H_A#[3..31]6
D D
H_ADSTB#06
H_ADSTB#16
H_REQ#[0..4]6
H_RS#[0..2]6
H_BR#06
H_BPRI#6
H_BNR#6
H_LOCK#6
H_ADS#6
H_HIT#6
H_HITM#6
H_DEFER#6
H_TRDY#6
H_DBSY#6
H_DRDY#6
CK_H_MCH18
CK_H_MCH#18
PWR_GD20,26,29
H_CPURST#6
ICH_SYNC#
HXRCOMP
MCH_GTLREF_CPU
HXSCOMP
HXSWING
C C
B B
MCHRST#26
ICH_SYNC#20
R59 16.9R1%R59 16.9R1%
Rule:
HXRCOMP_N_10/7/7
HXSCOMP_N_5/8/8
HSWING_N_15/10/10
A A
R63
V_FSB_VTT
R63
_60.4R1%-1
_60.4R1%-1
8
C46
C46
X_C2.2P50N
X_C2.2P50N
7
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
U15A
U15A
H_A#3 H_D#0
J39
HA3#
H_A#4
K38
HA4#
VCC
VCC
VCC
VCC
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
AA37
AA41
W42
G37
W41
W40
M31
M29
AJ12
M18
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
M36
V35
F38
D42
U39
U40
E41
D41
K36
E42
U41
P40
U42
V41
Y40
T40
Y43
T43
AJ9
C30
A28
C27
B27
D27
D28
J42
J37
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
T30T30
T32T32
T33T33
VCC
RSVRD
AA35
AA42
V_FSB_VTT
AF7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
L15
A43
U27
R27
M15
AA34
AA38
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R61
HXSCOMP
R61
301R1%
301R1%
R66
R66
84.5R1%
84.5R1%
R64 62RR64 62R
C47
C47
C0.1U25Y
C0.1U25Y
AF8
VCC
VCC
RSVRD
RSVRD
M11
AF9
VCC
RSVRD
AG25
AF10
AF11
VCC
RSVRD
AG26
AG27
AF12
VCC
VCC
RSVRD
RSVRD
AJ24
6
AF13
VCC
RSVRD
AJ27
AF14
VCC
RSVRD
AK40
AF30
AG2
VCC
VCC
RSVRD
RSVRD
AL39
AW17
HXSWING
AG3
AG4
VCC
RSVRD
AY14
AW18
V_1P5_CORE
AG5
AG6
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
BC16
AD30
AG7
AG8
VCC
RSVRD
Y30
AC34
AG9
VCC
VCC
RSVRD
RSVRD
Y33
AG10
AG11
VCC
RSVRD
AF31
AD31
AG12
VCC
VCC
RSVRD
RSVRD
U30
AG13
AG14
VCC
RSVRD
V31
AA30
AH1
VCC
VCC
RSVRD
RSVRD
AC30
AH2
AH4
VCC
RSVRD
AJ23
AK21
AJ5
VCC
VCC
RSVRD
RSVRD
AJ26
AJ13
AJ14
VCC
RSVRD
AL29
AL20
AK2
VCC
VCC
RSVRD
RSVRD
AJ21
5
AK3
AK4
VCC
RSVRD
AL26
AK27
AK14
AK15
AK20
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
V30
AJ29
AG29
V_FSB_VTT
R15
R17
R18
VCC
VCC
VCC
VCC
RSVRD
NC
BC43NCBC42
R60
R60
124R1%
124R1%
R62 10RR62 10R
R65
R65
210R1%
210R1%
4
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
E35
B43NCB42NCB41
BC2NCBC1
BB43
BB2NCBB1NCBA2
C42
AW2
AV27NCAV26
AW26
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
C43
C43
C44
C44
C0.1U25Y
C0.1U25Y
X_C220P50N
X_C220P50N
A42
V21
V22
V23
V25
V27
W17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y17
Y18
Y19
Y21
Y23
Y25
MCH_GTLREF_CPU
C45
C45
C0.1U25Y
C0.1U25Y
W18
Y27
VCC
VCC
W19
VCC
VCC
AA15
W20
VCC
VCC
AA17
W22
VCC
VCC
AA18
W24
VCC
VCC
AA19
W26
VCC
VCC
AA20
W27
3
Y15
M17
HD0#
HD1#
VCC
VCC
VCC
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
(INTEL-QG82945G-A2)
(INTEL-QG82945G-A2)
V_1P5_CORE
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
CAPS SHOULD BE PLACED NEAR MCH PIN
7
6
5
4
3
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
2
H_D#[0..63] 6
H_DBI#[0..3] 6
H_DSTBP#0 6
H_DSTBN#0 6
H_DSTBP#1 6
H_DSTBN#1 6
H_DSTBP#2 6
H_DSTBN#2 6
H_DSTBP#3 6
H_DSTBN#3 6
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU
Intel Lakeport - CPU
Intel Lakeport - CPU
MS-7418
MS-7418
MS-7418
2
1
2.1
2.1
932Monday, June 30, 2008
932Monday, June 30, 2008
932Monday, June 30, 2008
1
2.1
of
of
of
8
7
6
5
4
3
2
1
DATA_A37
DATA_A38
AT32
AR34
SADQ37
SBDQ35
AP27
AM31
DATA_A40
DATA_A39
AU37
AR41
SADQ38
SADQ39
SBDQ36
SBDQ37
AP31
AR27
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
SCKE_A[0..1]13,14
DATA_A43
DATA_A44
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_A48
DATA_A47
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AL34
AM34
DATA_A51
SADQ50
SBDQ48
DATA_A[0..63]13
DATA_A16
DATA_A21
DATA_A6
DATA_A4
AN1
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
DATA_A5
AP4
SADQ5
SBDQ3
AP9
DATA_A7
AU5
SADQ6
SBDQ4
AJ11
AU2
SADQ7
SBDQ5
AL9
DATA_A8
AW3
SADQ8
SBDQ6
AM10
DATA_A9
AY3
AP6
DATA_A10
DATA_A11
BA7
SADQ9
SADQ10
SBDQ7
SBDQ8
AU7
DATA_A12
BB7
AV1
SADQ11
SBDQ9
AV6
AV12
DATA_A14
DATA_A13
AW4
BC6
SADQ12
SADQ13
SBDQ10
SBDQ11
AR5
AM11
DATA_A15
AY7
AW12
SADQ14
SADQ15
SBDQ12
SBDQ13
AR7
AR12
DATA_A17
AY10
SADQ16
SBDQ14
AR10
DATA_A0
DATA_A1
DATA_A3
D D
SCS_A#[0..1]13,14
RAS_A#13,14
CAS_A#13,14
WE_A#13,14
MAA_A[0..13]13,14
C C
B B
ODT_A[0..1]13,14
SBS_A[0..2]13,14
DQS_A013
DQS_A#013
DQS_A113
DQS_A#113
DQS_A213
DQS_A#213
DQS_A313
DQS_A#313
DQS_A413
DQS_A#413
DQS_A513
DQS_A#513
DQS_A613
DQS_A#613
DQS_A713
DQS_A#713
P_DDR0_A13
N_DDR0_A13
P_DDR1_A13
N_DDR1_A13
SCS_A#0
SCS_A#1
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
ODT_A0
ODT_A1
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_B
Rule:
U15B
U15B
BB37
SACS0#
BA39
SACS1#
BA35
SACS2#
AY38
SACS3#
BA34
SARAS#
BA37
SACAS#
BB35
SAWE#
BA32
SAMA0
AW32
SAMA1
BB30
SAMA2
BA30
SAMA3
AY30
SAMA4
BA27
SAMA5
BC28
SAMA6
AY27
SAMA7
AY28
SAMA8
BB27
SAMA9
AY33
SAMA10
AW27
SAMA11
BB26
SAMA12
BC38
SAMA13
AW37
SAODT0
AY39
SAODT1
AY37
SAODT2
BB40
SAODT3
BC33
SABA0
AY34
SABA1
BA26
SABA2
AU4
SADQS0
AR2
SADQS0#
BA3
SADQS1
BB4
SADQS1#
AY11
SADQS2
BA10
SADQS2#
AU18
SADQS3
AR18
SADQS3#
AU35
SADQS4
AV35
SADQS4#
AP42
SADQS5
AP40
SADQS5#
AG42
SADQS6
AG41
SADQS6#
AC42
SADQS7
AC41
SADQS7#
BB32
SACLK0
AY32
SACLK0#
AY5
SACLK1
BB5
SACLK1#
AK42
SACLK2
AK41
SACLK2#
BA31
SACLK3
BB31
SACLK3#
AY6
SACLK4
BA5
SACLK4#
AH40
SACLK5
AH43
SACLK5#
AL5
MCH_SRCOMP0
AJ6
MCH_SRCOMP1
AJ8
SMOCDCOMP0
AM3
SMOCDCOMP1
(INTEL-QG82945G-A2)
(INTEL-QG82945G-A2)
AP3
SADQ0
DATA_A2
AP2
SADQ1
AU3
SADQ2
SBDQ0
AL6
AV4
AL8
SMPCOMP_N_12mils
DATA_A18
DATA_A19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
DATA_A20
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
DATA_A22
DATA_A23
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
DATA_A24
DATA_A25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
DATA_A26
DATA_A27
AV20
AM21
SADQ25
SADQ26
SBDQ23
SBDQ24
AM24
AM23
DATA_A29
DATA_A28
AP17
AR17
SADQ27
SADQ28
SBDQ25
SBDQ26
AV24
AM26
DATA_A31
DATA_A30
AP20
AT20
SADQ29
SADQ30
SBDQ27
SBDQ28
AP21
AR21
DATA_A32
DATA_A33
AP32
AV34
SADQ31
SADQ32
SBDQ29
SBDQ30
AT24
AP24
DATA_A34
DATA_A35
AV38
AU39
SADQ33
SADQ34
SBDQ31
SBDQ32
AU27
AN29
DATA_A36
AV32
SADQ35
SADQ36
SBDQ33
SBDQ34
AR31
DATA_A52
AE40
AM41
SADQ51
SADQ52
SBDQ49
SBDQ50
AJ34
AF32
DATA_A53
DATA_A54
AM42
AF41
SADQ53
SBDQ51
AL31
AF34
DATA_A56
DATA_A55
AF42
AD40
SADQ54
SADQ55
SBDQ52
SBDQ53
AJ32
AG35
DQM_A[0..7]13
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SBDQ54
SBDQ55
AD32
AC32
DATA_A60
DATA_A59
AA40
AE42
SADQ58
SADQ59
SBDQ56
SBDQ57
Y32
AD34
DATA_A61
DATA_A62
AE41
AB41
SADQ60
SADQ61
SBDQ58
SBDQ59
AF35
AA32
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SBDQ62
SBDQ63
AC35
BC24
BA25
SACKE1
SACKE2
SBCKE0
BA14
AY16
SACKE3
SBCKE1
SBCKE2
BA13
BB13
DQM_A1
DQM_A0
AY2
AR3
SADM0
SBCKE3
AD39
DQM_A2
BB10
SADM2
SADM1
SBDM6
SBDM7
AJ39
DQM_A3
AP18
AR38
DQM_A4
DQM_A5
AT34
SADM4
SADM3
SBDM4
SBDM5
AR29
DQM_A6
AG40
AP39
SADM5
SBDM3
AP13
AP23
DQM_A7
AC40
SADM7
SADM6
SBDM1
SBDM2
AW7
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
AL11
BA40
AW41
BA41
AW40
BA23
AY24
BB23
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
AY42
AV40
AV43
AU40
AW23
AY23
AY17
AM8
AM6
AV7
AR9
AV13
AT13
AU23
AR23
AT29
AV29
AP36
AM35
AG34
AG32
AD36
AD38
AM29
AM27
AV9
AW9
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AM2
AM4
MCH_VREF_A
PLACE 0.1UF CAP CLOSE TO MCH
C49
C49
C0.1U25Y
C0.1U25Y
0B Change 20
R411 0R0402R411 0R0402
SMPCOMP_P_12mils
VCC_DDR
R67 1KR1%R67 1KR1%
A A
VCC_DDR
R69 80.6R1%R69 80.6R1%
C50
C50
C0.1U25Y
C0.1U25Y
8
7
R70 80.6R1%R70 80.6R1%
SMPCOMP_PSMPCOMP_N
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
6
5
4
3
Date: Sheet
2
MCH_VREF_A
R68
R68
1KR1%
1KR1%
PLACE 0.1UF CAP CLOSE TO MCH
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - Memory
Intel Lakeport - Memory
Intel Lakeport - Memory
MS-7418
MS-7418
MS-7418
C48
C48
C0.1U25Y
C0.1U25Y
10 32Monday, June 30, 2008
10 32Monday, June 30, 2008
10 32Monday, June 30, 2008
1
2.1
2.1
2.1
of
of
of
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