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MSI
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MS-7411
Schematic 0A
39 pgs1.43 Mb0

MSI MS-7411 Schematic 0A

1
Cover Sheet BLOCK DIAGRAM
1 2
MS-7411
Ver:0A
3GPIO Configuration Clock Distribution Power Deliver Chart VRM Intersil 6323 3 Phase AMD Socket AM2 & AM2+ DDR II DIMM 1and DIMM2 1 & 2 & 3 & 4 DDR Terminatior AMD - RS780 AMD - SB700 DVI / VGA Connector
Clock Gen ICS9LPR471 SATA/LPT/KB/ FAN Control
A A
LAN-Marvell 88E8039/8056/8071/8075/8070
LPC I/O ITE IT8718F MS-6 ACPI Controller IEEE-1394 VT6308P Azalia CODEC ALC662/888 USB CONNECTORS PCI EXPRESS X16 & X 1 SLOT NB Power core & PCI resistor TMP/Asset ID/HWM W83201G ATX & Front Panel
4
5
6
7 ~ 9
10 ~ 11
12
13 ~ 16
17 ~ 21
22
23
24
25
26
27
28
29
30
31
32
33
34
CPU:
AMD AM2+ AMD AMD Athlon 64 X2 AMD Athlon 64 FX AMD Athlon 64 AMD Sempron CPUs
System Chipset:
AMD - RS780 (North Bridge)
- RX780 (North Bridge)
AMD - SB700 (South Bridge)
On Board Chipset:
BIOS - SPI Azalia CODEC - Realtek ALC662(Default)/888 LPC Super I/O -- ITE IT8718F(GX) LAN - Marvell 8039/8056/8071/8075/8070(Default) IEEE1394 - VIA VT6308P TMP - WPCT200(Default)/ST19WP18 Asset ID - PCA24S08 HWM W83201G
Main Memory:
DDR II * 4 (Max 4GB)
Expansion Slots:
PCI Express X16 Slot * 1 PCI Express X1 Slot * 1 PCI 2.3 Slot * 2
Auto BOM Manual
PCI EXPRESS X1 SLOT& IDE DAE-3
TV-OUT/RCA
History
35
36
37
38
39
Intersil PWM:
Controller - Intersil 6323 3 Phase
1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
of
of
of
139Thursday, October 11, 2007
139Thursday, October 11, 2007
139Thursday, October 11, 2007
5
4
3
2
1
Project RS-780 BLOCK DIAGRAM
DDRII 400,533,667,800
D D
AMD AM2/AM2g2
AM2 SOCKET
7,8,9
IN
13,14,15,16
A-LINK
16x16 2.6GHZ(HT3)HyperTransport LINK
D-SUB
YPBCOMP
2X PCIE
PCIE x1 SLOT1
OUT
HDMI CON
TMDS
38
ATI NB - RS780
HyperTransport LINK0 CPU I/F 1 16X PCIE VIDEO I/F
PCIE GFX x16
C C
4X1 PCIE INTERFACE
Gbit ETHERNET
8039/8056 /8071/8075
PCIE x16
31
PCIE x1 SLOT1
3125
1 4X PCIE I/F WITH SB 2 1X PCIE I/F
128bit
DDRII 400,533,667,800
128bit
VGA CON
TV-OUT/RCA
36
4X PCIE
USB-4USB-5
30
30 30 30 30 30
HDR
USB-1USB-2USB-3
USB-0 REARREARHDRREARREAR
USB 2.0
ATI SB - SB700
USB2.0 (12)
AZALIA
XPC Headers
AZALIA CODEC
SATA2 (4 PORTS)
USB-11 HDR
B B
USB-10 HDR
HDR HDR HDR HDR
USB-7USB-8USB-9
USB-6
AC97 2.3
303030303030
HD AUDIO 1.0 ACPI 1.1
SERIAL ATA 2.0
SATA#0 SATA#1
SPI I/F
UNBUFFERED DDRII DIMM1
UNBUFFERED DDRII DIMM2
DDRII FIRST LOGICAL DIMM DDRII SECOND LOGICAL DIMM
10
10
38
38
PCI-EX1 SLOT
DAE-3
36
37
38
29
SATA#2 SATA#3
24
24 24 24
UNBUFFERED DDRII DIMM3
UNBUFFERED DDRII DIMM4
11
11
PCI/PCI BRIDGE
1394 VT6308
28
PCI BUS
SPI Bus
SPI ROM 8M
19
ACPI CONTROLLER
MS6
CPU CORE POWER NB CORE POWER Intersil ISL6323 Intersil ISL6612A
6
27
17,18,19,20,21
LPC BUS
CPU VLDT Power
RS780 CORE POWER
PCIE & SB POWER
A A
DDR2 DRAM POWER
27
ITE SIO
IT8718F (GX)
26
TPM
33
Debug port
23
27
ATX CON & DUAL POWER
5
27
4
FLOPPY
Title
Title
22
3
2
Title
BLOCK Diagram
BLOCK Diagram
BLOCK Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
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239Thursday, October 11, 2007
239Thursday, October 11, 2007
239Thursday, October 11, 2007
5
D D
C C
4
3
2
1
B B
PCI Config.
DEVICE MCP1 INT Pin REQ#/GNT#
PCI Slot 1
PCI Slot 2
IEEE-1394 PCI_INTC#
A A
5
4
PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTA#
PREQ#0 PGNT#0
PREQ#1 PGNT#1
PREQ#2 PGNT#2
3
IDSEL
AD16
AD17
AD18 PCICLK2
CLOCK
PCICLK0
PCICLK1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
GPIO Configuration
GPIO Configuration
GPIO Configuration
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
339Thursday, October 11, 2007
339Thursday, October 11, 2007
339Thursday, October 11, 2007
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5
4
3
2
1
DIMM3 DIMM4
D D
DIMM1 DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU AM2 SOCKET
C C
B B
1 PAIR CPU CLK
200MHZ
HT REFCLK
100MHz DIFF(RX780/RS780)
EXTERNAL CLK GEN.
NB-OSCIN
14.318MHZ
NB ALINK PCIE CLK
100MHZ
SB ALINK PCIE CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
AMD NB RX780/RS780
(RX780)
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
25MHz LAN
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/ NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
PCI CLK5
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
SB_BITCLK
48MHZ
PCI SLOT 0 33MHz
PCI SLOT 1 33MHz
IEEE1394 33MHz
SUPER IO IT8718F 33MHz
TPM 33MHz
LEO CHIP 33MHz
HD AUDIO ALC 662/883
25MHz
SIO CLK
48MHZ
25MHz SATA
32.768KHz
14.31818MHz
A A
5
External clock mode
Internal clock mode
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Clock Distribution Chart
Clock Distribution Chart
Clock Distribution Chart
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
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439Thursday, October 11, 2007
439Thursday, October 11, 2007
439Thursday, October 11, 2007
5
Power Deliver Chart
4
3
2
1
2.5V Shunt Regulator
VRM SW REGUALTOR
D D
ATX P/S WITH 1A STBY CURRENT
5V
5VSB
+/-5%
+/-5%
3.3V +/-5%
12V +/-5%
-12V +/-5%
CPU PW 12V +/-5%
5VDIMM Linear REGULATOR
1.8V VDD SW REGULATOR
1.8V VCC Linear REGULATOR
VDDA25 (S0, S1)
VCCP (S0, S1) / VCC_NB (S0, S1)
0.9V VTT_DDR REGULATOR
1.1V VCC Linear REGULATOR
1.2V VCC Linear REGULATOR
VCC_DDR (S0, S1, S3) VTT_DDR (S0, S1, S3)
DDRII DIMMX4
VDD MEM
12A
VTT_DDR
2A
NB_VCC1P1 (S0, S1)
VCC_1V2 (S0, S1)
+1.8V_S0 (S0, S1)
C C
AMD AM2r2 CPU
VDDA 2.5V 0.2A VDDCORE
0.8-1.55V
DDR2 MEM I/F VDD MEM 1.8V VTT MEM 0.9V
VLDT 1.2V
NB RS780
VDDHT/RX 1.1V VDDHTTX 1.2V VDDPCIE 1.1V NB CORE VDDC
1.1V VDDA18PCIE 1.8V
PLLs 1.8V VDD18/VDD18_MEM
1.8V VDD_MEM 1.8V/1.5V
AVDD 3.3V
110A
10A 2A
0.5A
1.2A
0.5A 2A 7A
0.9A
0.1A
0.01A
0.5A
0.135A
SB700
VCC3_SB Linear REGULATOR
VCC3_SB (S0, S1, S3, S5)
1.2V_SB Linear REGULATOR
+1.2VSB (S0, S1) VCC3_SB (S0, S1, S3, S5)
VCC3 (S0, S1)
+5VA Linear
B B
5VDUAL Linear REGULATOR
REGULATOR
+5VA (S0, S1)
VCC3_SB (S0, S1, S3, S5)
X4 PCI-E
ATA I/O
ATA PLL
PCI-E PVDD
SB CORE
CLOCK
1.2V S5 PW
3.3V S5 PW
USB CORE I/O
3.3V I/O
AUDIO CODEC
3.3V CORE
5V ANALOG
+3.3VDUAL (S3)
+3.3V (S0, S1)
+5V (S0, S1)
0.8A
0.5A
0.01A 80mA
0.6A
0.22A
0.01A
0.2A
0.45A
0.1A
0.1A
SUPER I/O
0.01A
0.01A
0.1A
5.0A
7.6A
0.5A
0.1A
X1 PCIE per
3.3V 12V
3.3Vaux
PCI Slot (per slot)
A A
5
5V
3.3V 12V
3.3VDual
-12V
0.375A
3.0A
0.5A
0.1A
4
X16 PCIE per
3.0A
3.3V
5.5A
12V
0.1A
3.3VDual
USB X6 FR
VDD 5VDual
3.0A
USB X6 RL 2XPS/2
VDD 5VDual
3.0A
3
5VDual
0.5A
ENTHENET
3.3V (S3)
3.3V (S0, S1)
0.1A
0.5A
IEEE-1394 x1
3.3V (S0, S1)
12V (S0, S1) 1.1A
0.1A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Power Deliver Chart
Power Deliver Chart
Power Deliver Chart
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
539Thursday, October 11, 2007
539Thursday, October 11, 2007
539Thursday, October 11, 2007
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of
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5
Intersil 6323 3 Phase
4
3
2
1
G
Q16
Q16
G
G
Q21
Q21
G
G
R175
R175 10KR0402
10KR0402
Q28
Q28
G
C56
C56 C1U16X5
C1U16X5
R101
R101
2.2R1%0805
2.2R1%0805
C60
C60
C1000P50X0402
C1000P50X0402
VIN
C101
C101 C1U16X5
C1U16X5
DS
Q14
Q14 N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q17
N-P0903BD_TO252
Q17
N-P0903BD_TO252
DS
DS
G
VIN
C140
C140 C1U16X5
C1U16X5
DS
Q20
Q20 N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q22
N-P0903BD_TO252
Q22
N-P0903BD_TO252
DS
DS
G
VIN
C211
C211 C1U16X5
C1U16X5
DS
Q23
Q23 N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q27
N-P0903BD_TO252
Q27
N-P0903BD_TO252
DS
DS
G
C59
C59 C10u16Y1206
C10u16Y1206
C96
C96 C10u16Y1206
C10u16Y1206
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
R138
R138
2.2R1%0805
2.2R1%0805
C133
C133 C1000P50X0402
C1000P50X0402
C149
C149 C10u16Y1206
C10u16Y1206
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH CHOKE4
CHOKE4
R153
R153
2.2R1%0805
2.2R1%0805
C207
C207 C1000P50X0402
C1000P50X0402
C223
C223 C10u16Y1206
C10u16Y1206
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH CHOKE6
CHOKE6
R180
R180
2.2R1%0805
2.2R1%0805
C264
C264 C1000P50X0402
C1000P50X0402
CH-1.2u18A3.5m-RH
CH-1.2u18A3.5m-RH CHOKE1
CHOKE1
1 2
CP39CP39
PHASE_NB_A ISEN_NB_A
CHOKE2
CHOKE2
PHASE11 ISEN1
PHASE22 ISEN2
PHASE33 ISEN3
1 2
CP41CP41
1 2
CP43CP43
1 2
CP45CP45
12
12
CP38CP38
12
12
12
12
CP40CP40
12
CP42CP42
12
CP44CP44
CPU_VDDNB
VCCP
VCCP
VCCP
VCCP
EC9
EC9
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC12
EC12
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC15
EC15
X_CD1800U6.3EL20-2
X_CD1800U6.3EL20-2 EC16
EC16
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC18
EC18
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC19
EC19
X_CD1800U6.3EL20-2
X_CD1800U6.3EL20-2 EC24
EC24
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC26
EC26
X_CD1800U6.3EL20-2
X_CD1800U6.3EL20-2
CPU_VDDNB
EC5
EC5
CD1800U6.3EL20-2
CD1800U6.3EL20-2 EC4
EC4
X_CD1800U6.3EL20-2
X_CD1800U6.3EL20-2 EC7
EC7
CD1800U6.3EL20-2
CD1800U6.3EL20-2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
+
+
1 2
R39
R39
2.2R0805
2.2R0805
7X7 QFN
U1
U1
24
EN
37
VDDPWRGD
34
PWROK
9
VID5
8
VID4
7
VID3/SVC
6
VID2/SVD
5
VID1/SEL
4
VID0/VFIXEN
48
COMP_NB
1
FB_NB
2
VSEN_NB
3
RGND_NB
18
COMP
17
FB
15
RCOMP
13
VSEN
12
RGND
19
APA
16
RESET
14
OFS
11
FS
BOTTOM PAD CONNECT TO GND Through 8 VIAs
VCC5
C32
C32 C4.7U10Y0805
C4.7U10Y0805
10
PVCC1_2
VCC
BOOT1
UGATE1 PHASE1 LGATE1
ISEN1+
ISEN1-
BOOT2
UGATE2 PHASE2 LGATE2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
PVCC_NB
BOOT_NB
UGATE_NB PHASE_NB LGATE_NB
ISEN_NB
GND
49
ISL6323CRZ_QFN48-RH
ISL6323CRZ_QFN48-RH
+12VIN
R51
R51
2.2R0805
2.2R0805
C35
C35 C1U16X5
C1U16X5
29
R52 2.2R1%0805R52 2.2R1%0805
31
U_G1
32
PHASE1
33
L_G1
30
20
ISEN1-
21
PHASE11
R46 2.2R1%0805R46 2.2R1%0805
27
U_G2
26
PHASE2
25
L_G2
28
ISEN2+
22
ISEN2-
23
PHASE22
PWM_3
35
ISEN3+
44
ISEN3-
43
PHASE33
36
Disable PWM4 Use 3phase
46 45
R70 2.2R1%0805R70 2.2R1%0805
42
C52 C1U25X0805C52 C1U25X0805
R68
R68
40
2.2R1%0805
2.2R1%0805
UGATE_NB
39
PHASE_NB
38
LGATE_NB
41
47
PHASE_NB_A ISEN_NB_A
R333
R333 X_0R0402
X_0R0402
R82 1KR0402R82 1KR0402
R33 200R1%0402R33 200R1%0402 R32
R32
4.32KR1%0402
4.32KR1%0402
R31 200R1%0402R31 200R1%0402 R30
R30
4.32KR1%0402
4.32KR1%0402
R65 200R1%0402R65 200R1%0402 R64
R64
4.32KR1%0402
4.32KR1%0402
VCC5
R62
R62
3.4KR1%0402
3.4KR1%0402
B
C41 C0.1U25XC41 C0.1U25X
C27 C0.1U25XC27 C0.1U25X
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C51 C0.1U25XC51 C0.1U25X
R75 X_6.2KR1%0402R75 X_6.2KR1%0402
C53
C53 C0.1U16Y0402
C0.1U16Y0402
VCC3_SB
R100
R100 10KR0402
10KR0402
N-2N7002_SOT23
N-2N7002_SOT23
CE
Q5
Q5 N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
C5
C5 C0.1U16Y0402
C0.1U16Y0402
C3
C3
C54
C54
+12VIN
27R0402
27R0402
ISEN1ISEN1+
ISEN2
ISEN3
VCC_DDR
R78
R78
Q4
Q4
G
C6
C0.1U16Y0402C6C0.1U16Y0402
C4
C0.1U16Y0402C4C0.1U16Y0402
C55
C0.1U16Y0402
C55
C0.1U16Y0402
R66
R66 300R0402
300R0402
VID1_SEL
LOW FOR SVID
DS
+12VIN
R191
R191
2.2R0805
2.2R0805
C271
C271
C1U25X0805
C1U25X0805
PWM_3
U11
U11
6
VCC
UGATE
7
BOOT
PVCC
PHASE
4
GND
3
PWM
LGATE
ISL6612ACBZT_SOIC8-RH
ISL6612ACBZT_SOIC8-RH
UGATE_NB
PHASE_NB
LGATE_NB
U_G1
PHASE1
L_G1
U_G2
PHASE2
L_G2
1 2
R186
R186
2.2R1%0805
2.2R1%0805
8
5
N-P0903BD_TO252
N-P0903BD_TO252
R120 1R0805R120 1R0805
R118
R118
10KR0402
10KR0402
N-P0903BD_TO252
N-P0903BD_TO252
R77 1R0805R77 1R0805
R137 1R0805R137 1R0805
R151 1R0805R151 1R0805
U_G3
PHASE3
L_G3
R136
R136
10KR0402
10KR0402
N-P0903BD_TO252
N-P0903BD_TO252
R152
R152
10KR0402
10KR0402
N-P0903BD_TO252
N-P0903BD_TO252
R176 1R0805R176 1R0805 C260
C260 C0.1U25X
C0.1U25X
N-P0903BD_TO252
N-P0903BD_TO252
VIN
Q6
Q6
DS
G
Q7
Q7
DS
G
+12VIN
D D
PWM_EN27
VCC5
R63
R63 10KR0402
R57
R57
X_470R1%0402
X_470R1%0402
360R1%0402
360R1%0402
X_470R1%0402
X_470R1%0402 R18
R18
X_C1000P50X0402
X_C1000P50X0402
C26
C26 X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
5
GND GND
GND GND
10KR0402
X_C680P50X0402
X_C680P50X0402
R59
R59
C8
C8
560R1%0402-RH
560R1%0402-RH
R4
R4
C24
C24
X_C0.1U16Y0402
X_C0.1U16Y0402
VCC5
VCC5
1
2
EC10
CD1000U16EL20-2+EC10
CD1000U16EL20-2
+
12
VRM_GD27
NB_PWRGD_NB15,34
VID57
VID47 VID3_SVC7 VID2_SVD7 VID1_SEL7 VID07
CPU_VDDNB
R58
R58
100R0402
100R0402
V_NB7
C C
B B
A A
V_GND7
COREFB+7
COREFB-7
+12VIN
X_C0.01U25X0402
X_C0.01U25X0402
+12VIN
X_C0.1U16Y0402
X_C0.1U16Y0402
R50
R50
100R0402
100R0402
C283
C283
100R0402R5100R0402
100R0402
100R0402
C39
C39
VCCP
R5
R42
R42
JPW1
JPW1
12V
12V
3
12V
12V
4
PWR-2X2M_natural-RH
PWR-2X2M_natural-RH
CHOKE7 CH-1.2U18A-LFCHOKE7 CH-1.2U18A-LF
1 2
C284
X_C0.01U25X0402
C284
X_C0.01U25X0402
X_10KR0402
X_10KR0402
PWM_EN
10KR0402
10KR0402
R49 0R0402R49 0R0402
C42
C42
C40
C40 X_C0.1U16Y0402
X_C0.1U16Y0402
C38
C38 X_C0.1U16Y0402
X_C0.1U16Y0402
1.2KR1%0402
1.2KR1%0402 R34
R34
R17
R17
1.3KR1%0402
1.3KR1%0402
C30
C30
R37 56KR1%0402R37 56KR1%0402
R19 59KR1%0402R19 59KR1%0402
R28
R28
X_10KR0402
X_10KR0402
EC17
EC28
CD1000U16EL20-2+EC28
CD1000U16EL20-2
+
+
12
12
R38
R38
R36
R36
R69
R69
1.2KR1%0402
1.2KR1%0402 C44 C10P50N0402C44 C10P50N0402
ISEN_NB_A
R53 0R0402R53 0R0402 R54 X_0R0402R54 X_0R0402
C0.01U16X0402
C0.01U16X0402
1 2
C7 C33P50N0402C7 C33P50N0402
C19 C0.01U16X0402C19 C0.01U16X0402
COREFB+ COREFB-
R16
R16
4.99KR1%0402
4.99KR1%0402
VRM_SET
VCC5
120KR1%0402
120KR1%0402
CD1000U16EL20-2+EC17
CD1000U16EL20-2
EC6
X_CD1000U16EL20-2+EC6
X_CD1000U16EL20-2
+
12
C20
C0.1U16Y0402
C20
C0.1U16Y0402
C0.01U16X0402
C0.01U16X0402
1 2
C48
C48
C23
C23
12
C0.1U16Y0402
C0.1U16Y0402
C22
C22
OFS
R47
R47
X_100KR0402
X_100KR0402
R45
R45
VIN
C270
C0.1U16Y0402
C270
C0.1U16Y0402
CPU_CORE_TYPE7
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intersil 6323 3 Phase
Intersil 6323 3 Phase
Intersil 6323 3 Phase
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
639Thursday, October 11, 2007
639Thursday, October 11, 2007
639Thursday, October 11, 2007
of
of
of
5
4
3
2
1
RS740: STUFF R286,R287(49.9OHM) ; RS780 :UNSTUFF R286,R287(49.9OHM) when Layout must be put in CPU side
CPU1A
CPU1A
L0_CLKIN_H(1) L0_CLKIN_L(1) L0_CLKIN_H(0) L0_CLKIN_L(0)
L0_CTLIN_H(1) L0_CTLIN_L(1) L0_CTLIN_H(0) L0_CTLIN_L(0)
L0_CADIN_H(15) L0_CADIN_L(15) L0_CADIN_H(14) L0_CADIN_L(14) L0_CADIN_H(13) L0_CADIN_L(13) L0_CADIN_H(12) L0_CADIN_L(12) L0_CADIN_H(11) L0_CADIN_L(11) L0_CADIN_H(10) L0_CADIN_L(10) L0_CADIN_H(9) L0_CADIN_L(9) L0_CADIN_H(8) L0_CADIN_L(8)
L0_CADIN_H(7) L0_CADIN_L(7) L0_CADIN_H(6) L0_CADIN_L(6) L0_CADIN_H(5) L0_CADIN_L(5) L0_CADIN_H(4) L0_CADIN_L(4) L0_CADIN_H(3) L0_CADIN_L(3) L0_CADIN_H(2) L0_CADIN_L(2) L0_CADIN_H(1) L0_CADIN_L(1) L0_CADIN_H(0) L0_CADIN_L(0)
HT_CADIN_H[15..0] HT_CADIN_L[15..0] HT_CADOUT_H[15..0] HT_CADOUT_L[15..0]
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1) L0_CLKOUT_L(1) L0_CLKOUT_H(0) L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15) L0_CADOUT_L(15) L0_CADOUT_H(14) L0_CADOUT_L(14) L0_CADOUT_H(13) L0_CADOUT_L(13) L0_CADOUT_H(12) L0_CADOUT_L(12) L0_CADOUT_H(11) L0_CADOUT_L(11) L0_CADOUT_H(10) L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
CPU_CLK23
CPU_CLK#23
AD5 AD4 AD1 AC1
Y6 W6 W2 W3
Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4
Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1
HT_CLKOUT_H1 13 HT_CLKOUT_L1 13 HT_CLKOUT_H0 13 HT_CLKOUT_L0 13
HT_CTLOUT_H1 13 HT_CTLOUT_L1 13 HT_CTLOUT_H0 13 HT_CTLOUT_L0 13
HT_CADOUT_H15 HT_CADOUT_L15 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H8 HT_CADOUT_L8
HT_CADOUT_H7 HT_CADOUT_L7 HT_CADOUT_H6 HT_CADOUT_L6 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H3 HT_CADOUT_L3 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H0 HT_CADOUT_L0
D D
VCC_1V2
HT_CLKIN_H113 HT_CLKIN_L113 HT_CLKIN_H013
R286
R286
HT_CLKIN_L013
49.9R1%0402
HT_CTLIN_H113 HT_CTLIN_L113
C C
49.9R1%0402
R287
R287
49.9R1%0402
49.9R1%0402
HT_CTLIN_H013 HT_CTLIN_L013
HT_CADIN_H15 HT_CADIN_L15 HT_CADIN_H14 HT_CADIN_L14 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H8 HT_CADIN_L8
HT_CADIN_H7 HT_CADIN_L7 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H3 HT_CADIN_L3 HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H0 HT_CADIN_L0
HT_CADIN_H[15..0]13
HT_CADIN_L[15..0]13 HT_CADOUT_H[15..0]13 HT_CADOUT_L[15..0]13
N6 P6 N3 N2
V4 V5 U1 V1
U6 V6 T4 T5 R6 T6 P4
P5 M4 M5
L6 M6 K4 K5
J6 K6
U3 U2 R1
T1 R3 R2 N1 P1
L1 M1
L3
L2
J1 K1
J3
J2
C84
C84 C3900P50X
C3900P50X
C91
C91 C3900P50X
C3900P50X
R121
R121 169R1%0402
169R1%0402
VCC_DDR
R162
R162
39.2R1%0402
39.2R1%0402
R160
R160
39.2R1%0402
39.2R1%0402
CPU_M_VREF
TP22TP22 TP21TP21
C0.1U16Y0402
C0.1U16Y0402
R371
R371
300R0402
300R0402
LDT_PWRGD17 LDT_STOP#15,17
LDT_RST#17
TP1TP1
C77
C77
C4.7U10Y0805
C4.7U10Y0805
COREFB+6 COREFB-6
R352
R352 300R0402
300R0402
C69
C69
C1U10Y
C1U10Y
CPU_VTT_SENSE
CPU_STRAP_HI_E11 CPU_STRAP_LO_F11
CPU_TEST25_H CPU_TEST25_L
C89
C89
C3300P50X0402
C3300P50X0402
CPUCLKIN CPUCLKIN#
LDT_PWRGD LDT_STOP# LDT_RST#
CPU_PRESENT_L CPU_SIC
CPU_SID
R146 0R0402R146 0R0402
CPU_TDI CPU_TRST_L CPU_TCK CPU_TMS
CPU_DBREQ_L COREFB+
COREFB-
TP19TP19 TP20TP20 TP23TP23 TP18TP18 TP25TP25
C74
C74
VDDA25
AL10 AJ10
AH10
AH11
AJ11
C10 D10
A8 B8
C9 D8 C7
AL3 AL6
AK6
AL4
AK4
AL9
A5
G2 G1
E12 F12
A10 B10 F10
E9
AJ7
F6 D6
E7 F8 C5
AH9
E5
AJ5
AH7
AJ6
L5
L5 47n300mA_0805-RH-2
47n300mA_0805-RH-2
CPU1D
CPU1D
VDDA1 VDDA2
CLKIN_H
PLATFORM_TYPE
CLKIN_L PWROK
LDTSTOP_L RESET_L
CPU_PRESENT_L SIC
SID ALERT_L SA0
TDI TRST_L TCK TMS
DBREQ_L VDD_FB_H
VDD_FB_L
VTT_SENSE M_VREF
M_ZN M_ZP
TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9
TEST17 TEST16 TEST15 TEST14 TEST12
TEST7 TEST6
TEST3 TEST2
21
MISC
MISC
KEY/VSS1 KEY/VSS2
CORE_TYPE
SVC/VID(3) SVD/VID(2)
PVIEN/VID(1)
THERMDC THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L VDDNB_FB_H VDDNB_FB_L
HTREF1 HTREF0
TEST29_H TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H TEST28_L
TEST27 TEST26 TEST10
VDDA25VDDA_25
VID(5) VID(4)
VID(0)
TDO
PSI_L
TEST8
CPU_CORE_TYPE VID3_SVC
VID2_SVD
H22 AE9
CPU_PF_TYPE
F2
CPU_CORE_TYPE
G5
VID5
D2
VID4
D1
VID3_SVC
C1
VID2_SVD
E3
VID1_SEL
E2
VID0
E1 AG9
AG8
CPU_THRIP_L#
AK7
PROCHOT_L
AL7
CPU_TDO
AK10
CPU_DBRDY
B6 AK11
AL11 G4 G3
CPU_PSI_L
F1
HTREF1
V8
HTREF2
V7
R123 80.6R1%0402R123 80.6R1%0402
C11 D11
Keep trace < 1" from CPU.
TP28TP28
AK8
TP24TP24
AH8
TP27TP27
AJ9
R531 300R0402R531 300R0402
AL8 AJ8
TP26TP26
J10 H9 AK9
R165 300R0402R165 300R0402
AK5 G7 D4
R102 0R0402R102 0R0402
R163 100R0402R163 100R0402
TP3TP3
R168 44.2R1%R168 44.2R1% R171 44.2R1%R171 44.2R1%
R80 300R0402R80 300R0402 R72 1KR0402R72 1KR0402
R71 1KR0402R71 1KR0402
TP2TP2
CPU_CORE_TYPE 6 VID5 6
VID4 6 VID3_SVC 6 VID2_SVD 6 VID1_SEL 6 VID0 6
THERMDC_CPU 26 THERMDA_CPU 26
V_NB 6 V_GND 6
VCC_1V2
VCC_DDR
VCC_DDR
CPU_PROCHOT# 17
VCC_DDR
R373
R373 X_0R0402
X_0R0402
TP4TP4
B B
AMD REQUEST
VCC_DDR
CPU_M_VREF
R110
R110 15R1%
15R1%
C92
C92
C86
C86
R109
R109 15R1%
15R1%
C0.1U16Y0402
C0.1U16Y0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
CPU AM2 HT I/F,CTRL&DEBUG
CPU AM2 HT I/F,CTRL&DEBUG
CPU AM2 HT I/F,CTRL&DEBUG
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
C1000P50X0402
C1000P50X0402
739Thursday, October 11, 2007
739Thursday, October 11, 2007
739Thursday, October 11, 2007
of
of
of
CPU_FETGATE
G
CPU_FETGATE
LDT_STOP# LDT_RST# LDT_PWRGD PROCHOT_L
Q29 N-2N7002_SOT23Q29 N-2N7002_SOT23
D S
G
R174 39.2KR1%0402R174 39.2KR1%0402 R184 20KR1%0402R184 20KR1%0402 C255 C0.1U16Y0402C255 C0.1U16Y0402
G
D S
Q26 N-2N7002_SOT23Q26 N-2N7002_SOT23
G
D S
Q25 N-2N7002_SOT23Q25 N-2N7002_SOT23
R182 X_0R0402R182 X_0R0402
Q30
Q30
D S
R178 X_0R0402R178 X_0R0402
VCC_DDR
3
VCC_DDRVCC3
R21
B
Q1
Q1 X_N-MMBT3904_NL_SOT23
X_N-MMBT3904_NL_SOT23
J1
J1
R21 X_4.7KR0402
X_4.7KR0402
CE
2 4 6 8 10 12 14 16 18 20 22 24 26
LDT_RST_L
4
For SIC/SID
CPU_SID
CPU_SIC CPU_PRESENT_L CPU_TEST25_H
CPU_TEST25_L
R22
R22
X_1KR0402
X_1KR0402
X_100R0402
VCC_DDR
X_100R0402
LDT_RST_L LDT_RST#
R8
R8
1 3 5 7
9 11 13 15 17 19 21 23
KEY
KEY
X_H2X13[25]_black
X_H2X13[25]_black
SW1 X_SW-TACT4PSSW1 X_SW-TACT4PS
123
4
CPU_DBREQ_L CPU_DBRDY CPU_TCK
A A
CPU_TMS CPU_TDI CPU_TRST_L CPU_TDO
5
VCC_DDR
TALERT#19
SCLK10,11,18,23,27,37
R177 1KR0402R177 1KR0402
N-2N7002_SOT23
N-2N7002_SOT23 R183 X_0R0402R183 X_0R0402
SDATA10,11,18,23,27,37
CPU_PRESENT#19
R654 1KR0402R654 1KR0402
R167 1KR0402R167 1KR0402 R170 1KR0402R170 1KR0402 R111 510R0402R111 510R0402
R119 510R0402R119 510R0402
CPU_SIC
CPU_SID
CPU_PRESENT_LCPU_PRESENT#
R106 300R0402R106 300R0402 R105 300R0402R105 300R0402 R107 300R0402R107 300R0402 R103 300R0402R103 300R0402
VCC_DDR
VCC3
HTREF1 HTREF2 LDT_RST#
R169
R169
300R0402
300R0402
CPU_THRIP_L#
C227 X_C1000P50X0402C227 X_C1000P50X0402 C228 X_C1000P50X0402C228 X_C1000P50X0402 C67 X_C1000P50X0402C67 X_C1000P50X0402
2
Q24
Q24
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
VCC_DDR
B
R166
R166
4.7KR0402
4.7KR0402
CE
CPU_THRIP# 27
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
5
MEM_MA_DQS_L[7..0]10,11 MEM_MA_DQS_H[7..0]10,11
MEM_MA_DM[7..0]10,11
D D
CPU1B
CPU1B
MEMORY INTERFACE A
MEM_MA0_CLK_H210,12 MEM_MA0_CLK_L210,12 MEM_MA0_CLK_H110,12 MEM_MA0_CLK_L110,12 MEM_MA0_CLK_H010,12 MEM_MA0_CLK_L010,12
MEM_MA0_CS_L110,12 MEM_MA0_CS_L010,12
MEM_MA0_ODT010,12 MEM_MA1_CLK_H211,12
MEM_MA1_CLK_L211,12 MEM_MA1_CLK_H111,12 MEM_MA1_CLK_L111,12 MEM_MA1_CLK_H011,12 MEM_MA1_CLK_L011,12
MEM_MA1_CS_L111,12 MEM_MA1_CS_L011,12
MEM_MA1_ODT011,12
C C
B B
MEM_MA_CAS_L10,11,12 MEM_MA_WE_L10,11,12 MEM_MA_RAS_L10,11,12
MEM_MA_BANK210,11,12 MEM_MA_BANK110,11,12 MEM_MA_BANK010,11,12
MEM_MA_CKE111,12 MEM_MA_CKE010,12
MEM_MA_ADD[15..0]10,11,12
MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H0 MEM_MA0_CLK_L0
MEM_MA0_CS_L1 MEM_MA0_CS_L0
MEM_MA0_ODT0 MEM_MA1_CLK_H2
MEM_MA1_CLK_L2 MEM_MA1_CLK_H1 MEM_MA1_CLK_L1 MEM_MA1_CLK_H0 MEM_MA1_CLK_L0
MEM_MA1_CS_L1 MEM_MA1_CS_L0
MEM_MA1_ODT0
MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_CKE1 MEM_MA_CKE0
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0
MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0
AG21 AG20
AC25 AA24
AC28 AE20
AE19
W27
AD27 AA25
AC27
AB25 AB27 AA26
AA27
M25 M27
AC26
W24
AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28
AF15 AF19
AJ25
AH29
G19 H19 U27 U26
G20 G21 V27
N25 Y27
L27
N24 N26
P25 Y25 N27 R24 P27 R25 R26 R27
T25
U25
T27
D29 C29 C25 D25 E19
F19 F15
G15
B29 E24 E18 H15
MEMORY INTERFACE A
MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0)
MA0_CS_L(1) MA0_CS_L(0)
MA0_ODT(0) MA1_CLK_H(2)
MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0)
MA1_CS_L(1) MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L MA_WE_L MA_RAS_L
MA_BANK(2) MA_BANK(1) MA_BANK(0)
MA_CKE(1) MA_CKE(0)
MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)
MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)
MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)
4
MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)
MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)
MA_DQS_H(8) MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)
AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14
J28 J27
J25 K25
J26 G28 G27 L24 K27 H29 H27
MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0
MEM_MA_DATA[63..0] 10,11
3
MEM_MB0_CLK_H210,12 MEM_MB0_CLK_L210,12 MEM_MB0_CLK_H110,12 MEM_MB0_CLK_L110,12 MEM_MB0_CLK_H010,12 MEM_MB0_CLK_L010,12
MEM_MB0_CS_L110,12 MEM_MB0_CS_L010,12
MEM_MB0_ODT010,12 MEM_MB1_CLK_H211,12
MEM_MB1_CLK_L211,12 MEM_MB1_CLK_H111,12 MEM_MB1_CLK_L111,12 MEM_MB1_CLK_H011,12 MEM_MB1_CLK_L011,12
MEM_MB1_CS_L111,12 MEM_MB1_CS_L011,12
MEM_MB1_ODT011,12
MEM_MB_CAS_L10,11,12 MEM_MB_WE_L10,11,12 MEM_MB_RAS_L10,11,12
MEM_MB_BANK210,11,12 MEM_MB_BANK110,11,12 MEM_MB_BANK010,11,12
MEM_MB_CKE111,12 MEM_MB_CKE010,12
MEM_MB_ADD[15..0]10,11,12
MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H0 MEM_MB0_CLK_L0
MEM_MB0_CS_L1 MEM_MB0_CS_L0
MEM_MB0_ODT0 MEM_MB1_CLK_H2
MEM_MB1_CLK_L2 MEM_MB1_CLK_H1 MEM_MB1_CLK_L1 MEM_MB1_CLK_H0 MEM_MB1_CLK_L0
MEM_MB1_CS_L1 MEM_MB1_CS_L0
MEM_MB1_ODT0
MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_CKE1 MEM_MB_CKE0
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0
MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0
MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0
AJ19 AK19
AE30
AC31 AD29
AL19 AL18
W29 W28
AE29 AB31
AD31
AC29 AC30
AB29
AA31 AA28
AE31
AA29
AA30 AK13
AJ13 AK17 AJ17 AK23 AL23 AL28 AL29
AJ14
AH17
AJ23 AK29
A18 A19 U31 U30
C19 D19
N31
M31 M29
N28 N29
N30 P29
P31 R29 R28 R31 R30 T31 T29 U29 U28
D31 C31 C24 C23 D17 C17 C14 C13
C30 A23 B17 B13
MEM_MB_DQS_L[7..0]10,11 MEM_MB_DQS_H[7..0]10,11
MEM_MB_DM[7..0]10,11
CPU1C
CPU1C
MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0)
MB0_CS_L(1) MB0_CS_L(0)
MB0_ODT(0) MB1_CLK_H(2)
MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0)
MB1_CS_L(1) MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L MB_WE_L MB_RAS_L
MB_BANK(2) MB_BANK(1) MB_BANK(0)
MB_CKE(1) MB_CKE(0)
MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)
MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)
MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)
2
MEMORY INTERFACE B
MEMORY INTERFACE B
MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)
MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)
MB_DQS_H(8) MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)
AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29 K29
K31 G30 G29 L29 L28 H31 G31
MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0
1
MEM_MB_DATA[63..0] 10,11
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CPU AM2 DDR MEMORY I/F
CPU AM2 DDR MEMORY I/F
CPU AM2 DDR MEMORY I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
of
of
of
839Thursday, October 11, 2007
839Thursday, October 11, 2007
839Thursday, October 11, 2007
5
4
3
2
1
CPU AM2 PWR & GND
CPU_VDDNB
CPU1F
CPU1F
VDD1
VDD1
A4
VDDNB1
A6
VDDNB2
B5
VDDNB3
B7
VDDNB4
C6
VDDNB5
C8
VDDNB6
D7
VDDNB7
D9
VDDNB8
AA10 AA12 AA14 AA16 AA18
AB11
AC10
AE10
E8
VDDNB9
E10
VDDNB10
F9
VDDNB11
F11
VDDNB12
G10
VDDNB13
G12
VDDNB14
AA8
VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
AB7
VDD9
AB9
VDD10 VDD11
AC4
VDD12
AC5
VDD13
AC8
VDD14 VDD15
AD2
VDD16
AD3
VDD17
AD7
VDD18
AD9
VDD19 VDD20
AF7
VDD21
AF9
VDD22
AG4
VDD23
AG5
VDD24
AG7
VDD25
AH2
VDD26
AH3
VDD27
B3
VDD28
C2
VDD31
C4
VDD32
D3
VDD35
D5
VDD36
E4
VDD39
E6
VDD40
F5
VDD43
F7
VDD44
G6
VDD47
G8
VDD48
H7
VDD51
H11
VDD52
H23
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
K11
VDD64
K13
VDD65
K15
VDD66
K17
VDD67
K19
VDD68
K21
VDD69
K23
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
Y17
VDD150
Y19
VDD151
D D
C C
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44
VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74
VSS240 VSS241
A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5
AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16
VCCPVCCP
CPU1G
CPU1G
VDD2
VDD2
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
W10
VDD62
W12
VDD63
W14
VDD64
W16
VDD65
W18
VDD66
W20
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48
VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75
AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18
H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18
VCCP
Change to Passive Pin
AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11
CPU1H
CPU1H
VDD3
VDD3
N17
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
5
GND
6
GND
7
GND
8
GND
1
GND
2
GND
3
GND
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65
N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22
VCC_1V2
VTT_DDR
VCC_DDR
AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30
AF30
CPU1I
CPU1I
VDDIO
VDDIO
AJ4 AJ3 AJ2 AJ1
D12 C12 B12 A12
M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29
VLDT_A1 VLDT_A2 VLDT_A3 VLDT_A4
VTT1 VTT2 VTT3 VTT4
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29
VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28
VTT5 VTT6 VTT7 VTT8 VTT9
H6 H5 H2 H1
AK12 AJ12 AH12 AG12 AL12
K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15
VLDT_RUN_B
VTT_DDR
C116
C120
C120 C4.7U10Y0805
C4.7U10Y0805
C116 X_C0.01U25Y
X_C0.01U25Y
VCCP
C788
C788
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
near (1900,-4700)*3, near C116*2
EMI_0B
C790
C790
C789
C789
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C792
C792
C791
C791
X_C0.1U16Y0402
X_C0.1U16Y0402
B B
A A
VCCP
C685
C685
C22u6.3X1206
C22u6.3X1206
X_C22u6.3X1206
X_C22u6.3X1206
VCCP
C114
C114
C0.01u16X-1
C0.01u16X-1
CPU_VDDNB
C72
C72
C22u6.3X1206
C22u6.3X1206
X_C22u6.3X1206
X_C22u6.3X1206
VCC_1V2
C236
C236
X_C4.7U10Y0805
X_C4.7U10Y0805
Bottom side
C688
C688
C700
C700
C704
C713
C713
C22u6.3X1206
C22u6.3X1206
C698
C698
X_C22u6.3X1206
X_C22u6.3X1206
C706
C706
C22u6.3X1206
C22u6.3X1206
C689
C689
X_C22u6.3X1206
X_C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C704
C22u6.3X1206
C22u6.3X1206
X_C22u6.3X1206
X_C22u6.3X1206
Bottom side
C709
C709
C682
C682
X_C0.22U16X
X_C0.22U16X
C4.7U10Y0805
C4.7U10Y0805
C10u6.3X50805
C10u6.3X50805
C0.22U16X
C0.22U16X
Bottom side TOP side, place close to CPU socket
C683
C683
C679
C679
C10u6.3X50805
C10u6.3X50805
C0.01u16X-1
C0.01u16X-1
C244
C244
C229
C229
X_C0.22u10Y0402
X_C0.22u10Y0402
5
C686
C686
X_C10u6.3X50805
X_C10u6.3X50805
C107
C107
X_C10u6.3X50805
X_C10u6.3X50805
C242
C242
C0.22u10Y0402
C0.22u10Y0402
C680
C680
X_C10u6.3X50805
X_C10u6.3X50805
C81
C81
X_C0.22U16X
X_C0.22U16X
X_C180P50N0402
X_C180P50N0402
C703
C703
X_C10u6.3X50805
X_C10u6.3X50805
C108
C108
X_C0.22U16X
X_C0.22U16X
C249
C249
C180P50N0402
C180P50N0402
C691
C691
X_C10u6.3X50805
X_C10u6.3X50805
C79
C79
C4.7U10Y0805
C4.7U10Y0805
C237
C237
C711
C711
C10u6.3X50805
C10u6.3X50805
C80
C80
C0.01U16X0402
C0.01U16X0402
C693
C693
C22u6.3X1206
C22u6.3X1206
C715
C715
C10u6.3X50805
C10u6.3X50805
12
C111
C111
X_C0.01U16X0402
X_C0.01U16X0402
C701
C701
X_C22u6.3X1206
X_C22u6.3X1206
C710
C710
12
C110
C110
4
C694
C694
C695
C695
C0.01u16X-1
C0.01u16X-1
C699
C699
C4.7U10Y0805
C4.7U10Y0805
C707
C707
C4.7U10Y0805
C4.7U10Y0805
C696
C696
X_C4.7U10Y0805
X_C4.7U10Y0805
VCC_DDR
C697
C697
C702
X_C22u6.3X1206
X_C22u6.3X1206
C210
C210
C4.7U10Y0805
C4.7U10Y0805
Bottom side
C224
C224
C0.01u16X-1
C0.01u16X-1
C90
C90
X_C0.22u10Y0402
X_C0.22u10Y0402
3
C702
X_C22u6.3X1206
X_C22u6.3X1206
C131
C131
C4.7U10Y0805
C4.7U10Y0805
C716
C716
C66
C66
C0.22u10Y0402
C0.22u10Y0402
C681
C681
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
VCC_DDR
Place along the VCC_DDR/VSS plane splite
C234
C234
C180P50N0402
C180P50N0402
X_C4.7U10Y0805
X_C4.7U10Y0805
VTT_DDR
C50
C50
X_C22u6.3X1206
X_C22u6.3X1206
C0.22U16X
C0.22U16X
VTT_DDR
C68
C68
C0.22u10Y0402
C0.22u10Y0402
C0.22u10Y0402
C0.22u10Y0402
Bottom side
C684
C684
C712
C712
X_C0.22U16X
X_C0.22U16X
C0.01u16X-1
C0.01u16X-1
C132
C132
C220
C220
X_C4.7U10Y0805
X_C4.7U10Y0805
C180P50N0402
C180P50N0402
VTT_DDR
Place behind the DIMM Slot
C287
C287
X_C4.7U10Y0805
X_C4.7U10Y0805
C4.7U10Y0805
C4.7U10Y0805
Place between the DIMM Slot
12
C233
C233
C76
C76
X_C4.7U10Y0805
X_C4.7U10Y0805
C0.01U16X0402
C0.01U16X0402
C705
C705
C0.01u16X-1
C0.01u16X-1
C774
C774
C267
C267
X_C4.7U10Y0805
X_C4.7U10Y0805
C252
C252
C4.7U10Y0805
C4.7U10Y0805
C687
C687
C180p50N
C180p50N
C65
C65
C4.7U10Y0805
C4.7U10Y0805
C61
C61
X_C4.7U10Y0805
X_C4.7U10Y0805
C690
C690
X_C10u6.3X50805
X_C10u6.3X50805
C130
C130
C57
C57
C4.7U10Y0805
C4.7U10Y0805
C714
C714
X_C0.22U16X
X_C0.22U16X
C258
C258
C10u6.3X50805
C10u6.3X50805
C768
C768
C331
C331
C245
C245
C0.1U16Y0402
C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
2
C240
C240
CPU_VDDNBVCCP
C88 C2.2u10Y-RHC88 C2.2u10Y-RH
Bottom side
VCC_DDR
C708 C2.2u10Y-RHC708 C2.2u10Y-RH C692 C2.2u10Y-RHC692 C2.2u10Y-RH
Title
Title
Title
CPU AM2 PWR & GND
CPU AM2 PWR & GND
CPU AM2 PWR & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
VCCP
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
939Thursday, October 11, 2007
939Thursday, October 11, 2007
939Thursday, October 11, 2007
of
of
of
5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
VSS VSS#5 VSS#8 VSS#11 VSS#14 VSS#17 VSS#20 VSS#23 VSS#26 VSS#29 VSS#32 VSS#35 VSS#38 VSS#41 VSS#44 VSS#47 VSS#50 VSS#65 VSS#66 VSS#79 VSS#82 VSS#85 VSS#88 VSS#91 VSS#94 VSS#97
VCC_DDR
102
19
55
68
75
191
194
181
175
VDD3#75
VSS#121
VSS#124
VSS#127
VSS#130
121
124
127
130
133
170
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#133
VSS#136
VSS#139
VSS#142
VSS#145
VSS#148
VSS#151
136
139
142
145
148
151
154
DIMM 1
ADDR=1010000B
NC
RC118RC0
VDD051VDD156VDD262VDD372VDD478VDD5
NC#19
NC/TEST
VSS#100
VSS#103
VSS#106
VSS#109
VSS#112
VSS#115
VSS#118
100
103
106
109
112
115
118
MEM_MA_DQS_H[7..0]8,11 MEM_MA_DQS_L[7..0]8,11
MEM_MA_DATA[63..0]8,11
D D
C C
B B
A A
5
MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63
DIMM1
DIMM1
3 4 9
10 122 123 128 129
12
13
21
22 131 132 140 141
24
25
30
31 143 144 149 150
33
34
39
40 152 153 158 159
80
81
86
87 199 200 205 206
89
90
95
96 208 209 214 215
98
99 107 108 217 218 226 227 110 111 116 117 229 230 235 236
2 5
8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97
4
VCC3
238
161
162
167
VDDSPD
VSS#213
213
CB042CB143CB248CB349CB4
VSS#216
VSS#219
216
219
222
VSS#222
VSS#225
225
A16/BA2
DM0/DQS9 NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
VSS#228
VSS#231
228
231
234
168
CB5
CB6
CB7
7
DQS0
6
DQS0#
16
DQS1
15
DQS1#
28
DQS2
27
DQS2#
37
DQS3
36
DQS3#
84
DQS4
83
DQS4#
93
DQS5
92
DQS5#
105
DQS6
104
DQS6#
114
DQS7
113
DQS7#
46
DQS8
45
DQS8#
X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
A10_AP
57
A11
176
A12
196
A13
174
A14
173
A15
54 190
BA1
71
BA0
73
WE#
74
CAS#
192
RAS#
125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165
195
ODT0
77
ODT1
52
CKE0
171
CKE1
193
CS0#
76
CS1#
185 186 137 138 220 221
120
SCL
119
SDA
X1
X1
1
VREF
X2
X2
239
SA0
240
SA1
101
SA2
VSS#234
VSS#237
DDRII-240_BLUE-15U-IN-RH
DDRII-240_BLUE-15U-IN-RH
237
MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7
MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_WE_L MEM_MA_CAS_L MEM_MA_RAS_L
MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7
MEM_MA0_ODT0
MEM_MA_CKE0
MEM_MA0_CS_L0 MEM_MA0_CS_L1
MEM_MA0_CLK_H0 MEM_MA0_CLK_L0 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2
SCLK SDATA
VDDR_VREF
MEM_MA_ADD[15..0] 8,11,12
MEM_MA_BANK2 8,11,12 MEM_MA_BANK1 8,11,12 MEM_MA_BANK0 8,11,12
MEM_MA_WE_L 8,11,12 MEM_MA_CAS_L 8,11,12 MEM_MA_RAS_L 8,11,12
MEM_MA_DM[7..0] 8,11
MEM_MA0_ODT0 8,12
MEM_MA_CKE0 8,12
MEM_MA0_CS_L0 8,12 MEM_MA0_CS_L1 8,12
MEM_MA0_CLK_H0 8,12 MEM_MA0_CLK_L0 8,12 MEM_MA0_CLK_H1 8,12 MEM_MA0_CLK_L1 8,12 MEM_MA0_CLK_H2 8,12 MEM_MA0_CLK_L2 8,12
SCLK 7,11,18,23,27,37 SDATA 7,11,18,23,27,37
VDDR_VREF
178
69
197
172
187
184
189
67
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ4#69
VDDQ7#178
VSS#154
VSS#157
VSS#160
VSS#163
VSS#166
VSS#169
VSS#198
VSS#201
VSS#204
VSS#207
157
VSS#210
160
163
166
169
198
201
204
207
210
4
VCC_DDR
R44
R44 15R1%
15R1%
R55
R55 15R1%
15R1%
3
3
MEM_MB_DATA[63..0]8,11
C34
C34 C0.1U16Y0402
C0.1U16Y0402
VDDR_VREF
C36
C0.1U16Y0402
C36
C0.1U16Y0402
2
DIMM2
DIMM2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
VSS VSS#5 VSS#8 VSS#11 VSS#14 VSS#17 VSS#20 VSS#23 VSS#26 VSS#29 VSS#32 VSS#35 VSS#38 VSS#41 VSS#44 VSS#47 VSS#50 VSS#65 VSS#66 VSS#79 VSS#82 VSS#85 VSS#88 VSS#91 VSS#94 VSS#97
VCC_DDR
102
19
55
68
75
191
194
181
175
VDD3#75
VSS#121
VSS#124
VSS#127
VSS#130
VSS#133
121
124
127
130
133
170
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#136
VSS#139
VSS#142
VSS#145
VSS#148
VSS#151
VSS#154
136
139
142
145
148
151
154
DIMM 2
ADDR=1010001B
2
NC
RC118RC0
VDD051VDD156VDD262VDD372VDD478VDD5
NC#19
NC/TEST
VSS#100
VSS#103
VSS#106
VSS#109
VSS#112
VSS#115
VSS#118
100
103
106
109
112
115
118
MEM_MB_DQS_H[7..0]8,11 MEM_MB_DQS_L[7..0]8,11
C785
C785
VDDR_VREF
C1000P50X0402
C1000P50X0402
C772
C772
C1000P50X0402
C1000P50X0402
MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63
3 4 9
10 122 123 128 129
12
13
21
22 131 132 140 141
24
25
30
31 143 144 149 150
33
34
39
40 152 153 158 159
80
81
86
87 199 200 205 206
89
90
95
96 208 209 214 215
98
99 107 108 217 218 226 227 110 111 116 117 229 230 235 236
2 5
8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97
VCC3
238
161
162
167
VDDSPD
VSS#213
213
216
CB042CB143CB248CB349CB4
VSS#216
VSS#219
VSS#222
219
222
225
168
CB5
CB6
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A11 A12 A13 A14 A15
A16/BA2
BA1 BA0
WE# CAS# RAS#
DM0/DQS9
NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#
ODT0 ODT1
CKE0 CKE1
CS0# CS1#
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
SCL
SDA
VREF
SA0 SA1 SA2
VSS#225
VSS#228
VSS#231
VSS#234
VSS#237
DDRII-240_BLUE-15U-IN-RH
DDRII-240_BLUE-15U-IN-RH
228
231
234
237
CB7
7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70 57 176 196 174 173
54 190 71
73 74 192
125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165
195 77
52 171
193 76
185 186 137 138 220 221
120 119 X1
X1
1 X2
X2
239 240 101
MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_WE_L MEM_MB_CAS_L MEM_MB_RAS_L
MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7
MEM_MB0_ODT0
MEM_MB_CKE0
MEM_MB0_CS_L0 MEM_MB0_CS_L1
MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2
SCLK SDATA
VDDR_VREF
VCC3
PLACE CLOSE TO DIMM PIN
ADDRESS: 001 0xA4
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
178
69
197
172
187
184
189
67
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ4#69
VDDQ7#178
VSS#157
VSS#160
VSS#163
VSS#166
VSS#169
VSS#198
VSS#201
VSS#204
VSS#207
157
VSS#210
160
163
166
169
198
201
204
207
210
1
MEM_MB_ADD[15..0] 8,11,12
MEM_MB_BANK2 8,11,12 MEM_MB_BANK1 8,11,12 MEM_MB_BANK0 8,11,12
MEM_MB_WE_L 8,11,12 MEM_MB_CAS_L 8,11,12 MEM_MB_RAS_L 8,11,12
MEM_MB_DM[7..0] 8,11
MEM_MB0_ODT0 8,12
MEM_MB_CKE0 8,12
MEM_MB0_CS_L0 8,12 MEM_MB0_CS_L1 8,12
MEM_MB0_CLK_H0 8,12 MEM_MB0_CLK_L0 8,12 MEM_MB0_CLK_H1 8,12 MEM_MB0_CLK_L1 8,12 MEM_MB0_CLK_H2 8,12 MEM_MB0_CLK_L2 8,12
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
10 39Thursday, October 11, 2007
10 39Thursday, October 11, 2007
10 39Thursday, October 11, 2007
5
4
3
2
1
VCC_DDR
MEM_MA_DQS_H[7..0]8,10 MEM_MA_DQS_L[7..0]8,10
D D
C C
B B
A A
MEM_MA_DATA[63..0]8,10
MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63
5
102
19
55
68
75
191
194
181
175
VDD6
VDD7
VDD3#75
VSS#121
VSS#124
VSS#127
VSS#130
VSS#133
VSS#136
VSS#139
VSS#142
121
124
127
130
133
136
139
142
DIMM3
ADDR=1010010B
170
VDD8
VSS#145
145
148
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#148
VSS#151
VSS#154
151
154
DIMM3
DIMM3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
VSS VSS#5 VSS#8 VSS#11 VSS#14 VSS#17 VSS#20 VSS#23 VSS#26 VSS#29 VSS#32 VSS#35 VSS#38 VSS#41 VSS#44 VSS#47 VSS#50 VSS#65 VSS#66 VSS#79 VSS#82 VSS#85 VSS#88 VSS#91 VSS#94 VSS#97
NC
RC118RC0
VDD051VDD156VDD262VDD372VDD478VDD5
NC#19
NC/TEST
VSS#100
VSS#103
VSS#106
VSS#109
VSS#112
VSS#115
VSS#118
100
103
106
109
112
115
118
3 4 9
10 122 123 128 129
12
13
21
22 131 132 140 141
24
25
30
31 143 144 149 150
33
34
39
40 152 153 158 159
80
81
86
87 199 200 205 206
89
90
95
96 208 209 214 215
98
99 107 108 217 218 226 227 110 111 116 117 229 230 235 236
2 5
8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97
VCC3
238
161
162
167
VDDSPD
VSS#213
213
CB042CB143CB248CB349CB4
VSS#216
VSS#219
216
219
222
VSS#222
225
DM0/DQS9
DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#
CK1#(CK0#)
VSS#225
VSS#228
228
CB5 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#
A10_AP
A16/BA2
NC/DQS9#
CK0(DU) CK0#(DU) CK1(CK0)
CK2(DU) CK2#(DU)
VSS#231
VSS#234
231
234
168
CB6
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
MEM_MA_DQS_H2
28
DQS2
MEM_MA_DQS_L2
27
MEM_MA_DQS_H3
37
DQS3
MEM_MA_DQS_L3
36
MEM_MA_DQS_H4
84
DQS4
MEM_MA_DQS_L4
83
MEM_MA_DQS_H5
93
DQS5
MEM_MA_DQS_L5
92
MEM_MA_DQS_H6
105
DQS6
MEM_MA_DQS_L6
104
MEM_MA_DQS_H7
114
DQS7
MEM_MA_DQS_L7
113 46
DQS8
45 X3
X3
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
183
A1
MEM_MA_ADD2
63
A2
MEM_MA_ADD3
182
A3
MEM_MA_ADD4
61
A4
MEM_MA_ADD5
60
A5
MEM_MA_ADD6
180
A6
MEM_MA_ADD7
58
A7
MEM_MA_ADD8
179
A8
MEM_MA_ADD9
177
A9
MEM_MA_ADD10
70
MEM_MA_ADD11
57
A11
MEM_MA_ADD12
176
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
174
A14
MEM_MA_ADD15
173
A15
MEM_MA_BANK2
54
MEM_MA_BANK1
190
BA1
MEM_MA_BANK0
71
BA0
MEM_MA_WE_L
73
WE#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RAS_L
192
RAS#
MEM_MA_DM0
125 126
MEM_MA_DM1
134 135
MEM_MA_DM2
146 147
MEM_MA_DM3
155 156
MEM_MA_DM4
202 203
MEM_MA_DM5
211 212
MEM_MA_DM6
223 224
MEM_MA_DM7
232 233 164 165
MEM_MA1_ODT0
195
ODT0
77
ODT1
MEM_MA_CKE1
52
CKE0
171
CKE1
MEM_MA1_CS_L0
193
CS0#
MEM_MA1_CS_L1
76
CS1#
MEM_MA1_CLK_H0
185
MEM_MA1_CLK_L0
186
MEM_MA1_CLK_H1
137
MEM_MA1_CLK_L1
138
MEM_MA1_CLK_H2
220
MEM_MA1_CLK_L2
221
SCLK
120
SCL
SDATA
119
SDA
X1
X1
VDDR_VREF
1
VREF
X2
X2
239
SA0
240
VCC3
SA1
101
SA2
VSS#237
DDRII-240_GREEN-15U-IN-RH
DDRII-240_GREEN-15U-IN-RH
237
MEM_MA_ADD[15..0] 8,10,12
MEM_MA_BANK2 8,10,12 MEM_MA_BANK1 8,10,12 MEM_MA_BANK0 8,10,12
MEM_MA_WE_L 8,10,12 MEM_MA_CAS_L 8,10,12 MEM_MA_RAS_L 8,10,12
MEM_MA_DM[7..0] 8,10
MEM_MA1_ODT0 8,12
MEM_MA_CKE1 8,12
MEM_MA1_CS_L0 8,12 MEM_MA1_CS_L1 8,12
MEM_MA1_CLK_H0 8,12 MEM_MA1_CLK_L0 8,12 MEM_MA1_CLK_H1 8,12 MEM_MA1_CLK_L1 8,12 MEM_MA1_CLK_H2 8,12 MEM_MA1_CLK_L2 8,12
SCLK 7,10,18,23,27,37 SDATA 7,10,18,23,27,37
VDDR_VREF
C29
C29 C0.1U16Y0402
C0.1U16Y0402
178
69
197
172
187
184
189
67
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ4#69
VDDQ7#178
VSS#157
VSS#160
VSS#163
VSS#166
VSS#169
VSS#198
VSS#201
VSS#204
VSS#207
157
VSS#210
160
163
166
169
198
201
204
207
210
4
MEM_MB_DQS_H[7..0]8,10 MEM_MB_DQS_L[7..0]8,10 MEM_MB_DATA[63..0]8,10
3
MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63
3 4 9
10 122 123 128 129
12
13
21
22 131 132 140 141
24
25
30
31 143 144 149 150
33
34
39
40 152 153 158 159
80
81
86
87 199 200 205 206
89
90
95
96 208 209 214 215
98
99 107 108 217 218 226 227 110 111 116 117 229 230 235 236
2 5
8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97
DIMM4
DIMM4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
VSS VSS#5 VSS#8 VSS#11 VSS#14 VSS#17 VSS#20 VSS#23 VSS#26 VSS#29 VSS#32 VSS#35 VSS#38 VSS#41 VSS#44 VSS#47 VSS#50 VSS#65 VSS#66 VSS#79 VSS#82 VSS#85 VSS#88 VSS#91 VSS#94 VSS#97
VCC_DDR
102
19
55
68
75
191
194
181
175
VDD6
VDD3#75
VSS#121
VSS#124
VSS#127
VSS#130
VSS#133
VSS#136
VSS#139
121
124
127
130
133
136
139
DIMM 4
ADDR=1010011B
142
VDD7
VSS#142
170
VDD8
VSS#145
145
148
2
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#148
VSS#151
VSS#154
151
154
NC
RC118RC0
VDD051VDD156VDD262VDD372VDD478VDD5
NC#19
NC/TEST
VSS#100
VSS#103
VSS#106
VSS#109
VSS#112
VSS#115
VSS#118
100
103
106
109
112
115
118
VCC3
238
161
162
167
VDDSPD
VSS#213
213
216
CB042CB143CB248CB349CB4
VSS#216
VSS#219
VSS#222
219
222
225
168
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
X3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10_AP
A11 A12 A13 A14 A15
A16/BA2
BA1 BA0
WE# CAS# RAS#
DM0/DQS9
NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#
ODT0 ODT1
CKE0 CKE1
CS0# CS1#
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
SCL SDA
X1
VREF
X2
SA0 SA1 SA2
VSS#225
VSS#228
VSS#231
VSS#234
VSS#237
DDRII-240_GREEN-15U-IN-RH
DDRII-240_GREEN-15U-IN-RH
228
231
234
237
7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 X3 188 183 63 182 61 60 180 58 179 177 70 57 176 196 174 173
54 190 71
73 74 192
125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165
195 77
52 171
193 76
185 186 137 138 220 221
120 119 X1 1
VCC3
X2 239
240 101
MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_WE_L MEM_MB_CAS_L MEM_MB_RAS_L
MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7
MEM_MB1_ODT0
MEM_MB_CKE1
MEM_MB1_CS_L0 MEM_MB1_CS_L1
MEM_MB1_CLK_H0 MEM_MB1_CLK_L0 MEM_MB1_CLK_H1 MEM_MB1_CLK_L1 MEM_MB1_CLK_H2 MEM_MB1_CLK_L2
SCLK SDATA
VDDR_VREF
MEM_MB_ADD[15..0] 8,10,12
MEM_MB_BANK2 8,10,12 MEM_MB_BANK1 8,10,12 MEM_MB_BANK0 8,10,12
MEM_MB_WE_L 8,10,12 MEM_MB_CAS_L 8,10,12 MEM_MB_RAS_L 8,10,12
MEM_MB_DM[7..0] 8,10
MEM_MB1_ODT0 8,12
MEM_MB_CKE1 8,12
MEM_MB1_CS_L0 8,12 MEM_MB1_CS_L1 8,12
MEM_MB1_CLK_H0 8,12 MEM_MB1_CLK_L0 8,12 MEM_MB1_CLK_H1 8,12 MEM_MB1_CLK_L1 8,12 MEM_MB1_CLK_H2 8,12 MEM_MB1_CLK_L2 8,12
C37
C37 C0.1U16Y0402
C0.1U16Y0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
11 39Thursday, October 11, 2007
11 39Thursday, October 11, 2007
11 39Thursday, October 11, 2007
178
69
197
172
187
184
189
67
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ4#69
VDDQ7#178
VSS#157
VSS#160
VSS#163
VSS#166
VSS#169
VSS#198
VSS#201
VSS#204
VSS#207
157
VSS#210
160
163
166
169
198
201
204
207
210
5
4
3
2
1
VTT_DDR
MEM_MB_ADD158,10,11 MEM_MB_ADD148,10,11 MEM_MB_BANK28,10,11 MEM_MA_ADD98,10,11 MEM_MA_ADD118,10,11 MEM_MB_ADD128,10,11
D D
C C
MEM_MB_ADD98,10,11 MEM_MA_ADD78,10,11 MEM_MA_ADD68,10,11 MEM_MB_ADD68,10,11 MEM_MB_ADD58,10,11 MEM_MA_ADD58,10,11 MEM_MB_ADD18,10,11 MEM_MB_ADD28,10,11 MEM_MA_ADD18,10,11 MEM_MA_ADD28,10,11
MEM_MB_ADD108,10,11 MEM_MB_BANK08,10,11 MEM_MB_RAS_L8,10,11 MEM_MB0_CS_L08,10
MEM_MA_BANK08,10,11 MEM_MB_BANK18,10,11 MEM_MA_RAS_L8,10,11 MEM_MA0_CS_L08,10
MEM_MA0_CS_L18,10 MEM_MB1_CS_L18,11 MEM_MA_ADD138,10,11 MEM_MA1_CS_L18,11
MEM_MA1_CS_L08,11 MEM_MA1_ODT08,11
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_BANK2 MEM_MA_ADD9 MEM_MA_ADD11 MEM_MB_ADD12 MEM_MB_ADD9 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MA_ADD5 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MA_ADD1 MEM_MA_ADD2
MEM_MB_ADD10 MEM_MB_BANK0 MEM_MB_RAS_L MEM_MB0_CS_L0
MEM_MA_BANK0 MEM_MB_BANK1 MEM_MA_RAS_L MEM_MA0_CS_L0
MEM_MA0_CS_L1 MEM_MB1_CS_L1 MEM_MA_ADD13 MEM_MA1_CS_L1
MEM_MA1_CS_L0 MEM_MA1_ODT0
RN17 8P4R-47R0402RN17 8P4R-47R0402
1
2
3
4
5
6
7
RN18 8P4R-47R0402RN18 8P4R-47R0402
RN22 8P4R-47R0402RN22 8P4R-47R0402
RN24 8P4R-47R0402RN24 8P4R-47R0402
RN27 8P4R-47R0402RN27 8P4R-47R0402
RN26 8P4R-47R0402RN26 8P4R-47R0402
RN30 8P4R-47R0402RN30 8P4R-47R0402
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
R159 47R0402R159 47R0402 R173 47R0402R173 47R0402
MEM_MA0_CLK_H28,10
MEM_MA0_CLK_L28,10
MEM_MA0_CLK_H18,10
MEM_MA0_CLK_L18,10
MEM_MA0_CLK_H08,10
MEM_MA0_CLK_L08,10
MEM_MB0_CLK_H28,10
MEM_MB0_CLK_L28,10
MEM_MB0_CLK_H18,10
MEM_MB0_CLK_L18,10
MEM_MB0_CLK_H08,10
MEM_MB0_CLK_L08,10
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
C248
C248 C1.5P50N0402
C1.5P50N0402
C83
C83 C1.5P50N0402
C1.5P50N0402
C162
C162 C1.5P50N0402
C1.5P50N0402
C241
C241 C1.5P50N0402
C1.5P50N0402
C71
C71 C1.5P50N0402
C1.5P50N0402
C168
C168 C1.5P50N0402
C1.5P50N0402
VTT_DDR
C286
C286
C0.1U16Y0402
C0.1U16Y0402
VTT_DDR
C70
C70
C0.1U16Y0402
C0.1U16Y0402
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
C137 C22P50N0402C137 C22P50N0402 C142 C22P50N0402C142 C22P50N0402 C225 C22P50N0402C225 C22P50N0402 C150 C22P50N0402C150 C22P50N0402 C157 C22P50N0402C157 C22P50N0402 C198 C22P50N0402C198 C22P50N0402 C153 C22P50N0402C153 C22P50N0402 C164 C22P50N0402C164 C22P50N0402 C160 C22P50N0402C160 C22P50N0402 C169 C22P50N0402C169 C22P50N0402 C170 C22P50N0402C170 C22P50N0402 C172 C22P50N0402C172 C22P50N0402 C177 C22P50N0402C177 C22P50N0402 C181 C22P50N0402C181 C22P50N0402 C188 C22P50N0402C188 C22P50N0402 C184 C22P50N0402C184 C22P50N0402 C193 C22P50N0402C193 C22P50N0402
C221 C22P50N0402C221 C22P50N0402 C217 C22P50N0402C217 C22P50N0402 C212 C22P50N0402C212 C22P50N0402
C146 C22P50N0402C146 C22P50N0402 C201 C22P50N0402C201 C22P50N0402 C208 C22P50N0402C208 C22P50N0402
Decoupling Between Processor and DIMMs
Layout: Spread out on VTT pour
C280
C280
C263
C263
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C295
C295
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C323
C323
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
VCC_DDR
C97
C97
C0.1U16Y0402
C0.1U16Y0402
C186
C186
C0.1U16Y0402
C0.1U16Y0402
C118
C118
C0.1U16Y0402
C0.1U16Y0402
C163
C163
C0.1U16Y0402
C0.1U16Y0402
C318
C318
X_C0.1U16Y0402
X_C0.1U16Y0402
C112
C112
C0.1U16Y0402
C0.1U16Y0402
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0
MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
C250
C250
C0.1U16Y0402
C0.1U16Y0402
C281
C281
C0.1U16Y0402
C0.1U16Y0402
C235
C235
C357
C357
C138 C22P50N0402C138 C22P50N0402 C143 C22P50N0402C143 C22P50N0402 C226 C22P50N0402C226 C22P50N0402 C151 C22P50N0402C151 C22P50N0402 C158 C22P50N0402C158 C22P50N0402 C202 C22P50N0402C202 C22P50N0402 C154 C22P50N0402C154 C22P50N0402 C165 C22P50N0402C165 C22P50N0402 C161 C22P50N0402C161 C22P50N0402
C173 C22P50N0402C173 C22P50N0402 C178 C22P50N0402C178 C22P50N0402 C182 C22P50N0402C182 C22P50N0402 C189 C22P50N0402C189 C22P50N0402 C185 C22P50N0402C185 C22P50N0402 C194 C22P50N0402C194 C22P50N0402
C222 C22P50N0402C222 C22P50N0402 C218 C22P50N0402C218 C22P50N0402 C213 C22P50N0402C213 C22P50N0402
C147 C22P50N0402C147 C22P50N0402 C199 C22P50N0402C199 C22P50N0402 C209 C22P50N0402C209 C22P50N0402
VCC_DDR
VTT_DDR
MEM_MB_CKE18,11 MEM_MB_CKE08,10 MEM_MA_BANK28,10,11 MEM_MA_ADD128,10,11 MEM_MA_ADD88,10,11 MEM_MB_ADD118,10,11 MEM_MB_ADD78,10,11 MEM_MB_ADD88,10,11
B B
A A
MEM_MB_ADD48,10,11 MEM_MB_ADD38,10,11 MEM_MA_ADD48,10,11 MEM_MA_ADD38,10,11 MEM_MA_ADD08,10,11 MEM_MA_ADD108,10,11 MEM_MB_ADD08,10,11 MEM_MA_BANK18,10,11
MEM_MB_WE_L8,10,11 MEM_MB_CAS_L8,10,11
MEM_MA_WE_L8,10,11 MEM_MA_CAS_L8,10,11
MEM_MA_CKE18,11 MEM_MA_CKE08,10 MEM_MA_ADD158,10,11 MEM_MA_ADD148,10,11
MEM_MA0_ODT08,10
MEM_MB0_ODT08,10 MEM_MB_ADD138,10,11 MEM_MB0_CS_L18,10
MEM_MB1_CS_L08,11 MEM_MB1_ODT08,11
5
MEM_MB_CKE1 MEM_MB_CKE0 MEM_MA_BANK2 MEM_MA_ADD12 MEM_MA_ADD8 MEM_MB_ADD11 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD0 MEM_MA_ADD10 MEM_MB_ADD0 MEM_MA_BANK1
MEM_MB_WE_L MEM_MB_CAS_L MEM_MA_WE_L MEM_MA_CAS_L
MEM_MA_CKE1 MEM_MA_CKE0 MEM_MA_ADD15 MEM_MA_ADD14
MEM_MA0_ODT0 MEM_MB0_ODT0 MEM_MB_ADD13 MEM_MB0_CS_L1
MEM_MB1_CS_L0 MEM_MB1_ODT0
RN14 8P4R-47R0402RN14 8P4R-47R0402
1
2
3
4
5
6
7
RN21 8P4R-47R0402RN21 8P4R-47R0402
RN23 8P4R-47R0402RN23 8P4R-47R0402
RN25 8P4R-47R0402RN25 8P4R-47R0402
RN28 8P4R-47R0402RN28 8P4R-47R0402
RN11 8P4R-47R0402RN11 8P4R-47R0402
RN29 8P4R-47R0402RN29 8P4R-47R0402
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
R164 47R0402R164 47R0402 R172 47R0402R172 47R0402
MEM_MA1_CLK_H28,11
MEM_MA1_CLK_L28,11
MEM_MA1_CLK_H18,11
MEM_MA1_CLK_L18,11
MEM_MA1_CLK_H08,11
MEM_MA1_CLK_L08,11
MEM_MB1_CLK_H28,11
MEM_MB1_CLK_L28,11
MEM_MB1_CLK_H18,11
MEM_MB1_CLK_L18,11
MEM_MB1_CLK_H08,11
MEM_MB1_CLK_L08,11
4
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
C246
C246 C1.5P50N0402
C1.5P50N0402
C85
C85 C1.5P50N0402
C1.5P50N0402
C175
C175 C1.5P50N0402
C1.5P50N0402
C243
C243 C1.5P50N0402
C1.5P50N0402
C75
C75 C1.5P50N0402
C1.5P50N0402
C180
C180 C1.5P50N0402
C1.5P50N0402
3
VTT_DDR
C125
C125
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
For EMI
C276
C313
C313
C139
C139
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
VTT_DDR
C300
C300 C0.1U16Y0402
C0.1U16Y0402
VTT_DDR VCC_DDR
C230 C0.1U16Y0402C230 C0.1U16Y0402 C238 C0.1U16Y0402C238 C0.1U16Y0402 C200 C0.1U16Y0402C200 C0.1U16Y0402 C192 C0.1U16Y0402C192 C0.1U16Y0402 C256 C0.1U16Y0402C256 C0.1U16Y0402 C176 C0.1U16Y0402C176 C0.1U16Y0402 C155 C0.1U16Y0402C155 C0.1U16Y0402 C134 C0.1U16Y0402C134 C0.1U16Y0402
C276
C337
C337
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C288
C288 C0.1U16Y0402
C0.1U16Y0402
C262
C262 C0.1U16Y0402
C0.1U16Y0402
2
C293
C293
C278
C278
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C259
C259
VTT_DDR VCC_DDR
C121 C0.1U16Y0402C121 C0.1U16Y0402 C247 C0.1U16Y0402C247 C0.1U16Y0402 C216 C0.1U16Y0402C216 C0.1U16Y0402 C254 C0.1U16Y0402C254 C0.1U16Y0402 C187 C0.1U16Y0402C187 C0.1U16Y0402 C166 C0.1U16Y0402C166 C0.1U16Y0402 C144 C0.1U16Y0402C144 C0.1U16Y0402 C127 C0.1U16Y0402C127 C0.1U16Y0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
DDR TERMINATOR
DDR TERMINATOR
DDR TERMINATOR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7411 0A
MS-7411 0A
MS-7411 0A
1
of
of
of
12 39Thursday, October 11, 2007
12 39Thursday, October 11, 2007
12 39Thursday, October 11, 2007
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