MSI MS-7396L2 Schematic 0A
1
COVER SHEET
BLOCK DIAGRAM
GPIO & JUMPER SETTING
Intel LGA775-CPU
Intel G31
DDR II DIMM 1and DIMM2 1 & 2
ICH7
Clock Generator - ICS9LP505-2
PCI EXPRESS X16 & X1
PCI SLOT X1
INTEL 82562GZ/82573L
VGA CONNECTOR
Azalia CODEC(ALC662)
SIO-ITE8718F
A A
USB CONNECTORS
IDE&SATA& COM1& COM2& LPT
IEEE 1394 VT6308P
SPI & FAN & V_1P25_CORE
ATX & Front Panel
MS7 ACPI Controller
VRM11 Intersil 6312 3Phase
V_FSB_CTT SELECT CIRCUIT
EMI Cap
1
2
3
4-6
7-10
11-12
13-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS-7396L2-0A
CPU:
Intel Prescott
Intel Conroe
Intel Kensfield
Intel Wolfdale
System Chipset:
Intel G31 - GMCH (North Bridge)
Intel ICH7(South Bridge)
On Board Chipset:
BIOS -- SPI FLASH 4Mb
Azalia CODEC(ALC 662)
LPC Super I/O -- ITE8718F
INTEL 82562GZ/82573L
Clock Generator - ICS9LP505-2
Main Memory:
Dual Channel DDR II * 2
Expansion Slots:
PCI Express X16 SLOT * 1
PCI Express X1 SLOT * 2
PCI SLOT * 1
Intersil PWM:
Intersil 6312 3 Phase
Auto BOM manual
PWOK MAP
History
Power Delivery
Clock Map
32
33
34
35
36
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
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Title
COVER SHEET
COVER SHEET
COVER SHEET
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Custom
Date: Sheet
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Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
136Friday, July 06, 2007
136Friday, July 06, 2007
136Friday, July 06, 2007
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Block Diagram
D D
VRD 11
Intersil 6312
3Phase PWM
PCI_E X16
Connector
Analog
C C
Video Out
PCI_E X1
Connector*2
PCI Slot * 1
SATA-II 0~3
B B
USB Port 0~7
PCI EXPRESS X16
RGB
PCI EXPRESS X1
PCI
SATA2
USB2.0
Intel LGA775 Processor
FSB 800/1066
FSB
G31
GMCH
DMI
ICH7
LPC Bus
DDRII
HD Audio Link
DDR2 667/800
2X DDR II
DIMM
Modules
HD Audio Codec
ALC 662
Board Stack-up
(1080 Prepreg Considerations)
Solder Mask
PREPREG 2.7mils
CORE 50mils
Solder Mask
PREPREG 2.7mils
Single End 50ohm Top/Bottom : 4mils
USB2.0 - 90ohm : 15/7.5/4.5/7.5/15
SATA - 95ohm : 15/8/4/8/15
LAN - 100ohm : 15/10/4/10/15
PCIE - 95ohm : 15/8/4/8/15
1.9mils Cu plus plating
1.9mils Cu plus plating
1 oz. (1.2mils)
Cu Power
Plane
1 oz. (1.2mils)
Cu GND
Plane
INTEL PHY
82562GZ
82573L
A A
LCI
SPI
SPI
Flash BIOS
5
4
LPC SIO
ITE8718F
Keyboard
Mouse
Floopy
Serial
3
Parallel
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
1
236Friday, July 06, 2007
236Friday, July 06, 2007
236Friday, July 06, 2007
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ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name
GPIO[0] BM_BUSY# AB18 I/O Vcc3p3 N Y 5 Input GPI0
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
7
6
5
4
3
2
1
PCI Config.
DEVICE
MCP1 INT Pin
REQ#/GNT#
IDSEL
PIRQ#A
PCI SLOT 1
PIRQ#B
PIRQ#C
PIRQ#D
PREQ#0
PGNT#0
AD16
CLOCK
PCI_CLK0
GPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] unmuxed AC18 I/O Vcc3p3 N Y 3.3 Input GPI7
GPIO[8] unmuxed E21 I/O VccSus3p3 N Y 3.3 Input GPI8
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input GPI9
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input GPI10
PCI 1394
PREQ#2PIRQ#C 1394_PCLKAD20
PGNT#2
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT#
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input CLR_COMS#
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input SIO_PME#
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input GPI14
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input GPI15
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 N/A GPIO16_ICH
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 Input PGNT#5
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input GPI19
C C
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 Input FAN_CTRL
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input GPI21
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input GPI23
GPIO[24] R3 I/O VccSus3p3 N N 3.3 Input LAN_DIS#
DDRII DIMM Config.
CLOCKDEVICE ADDRESS
DIMM 1
A0H
A4H
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
MCLK_B0/MCLK_B#0
MCLK_B1/MCLK_B#1DIMM 2
MCLK_B2/MCLK_B#2
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 Input DMI_MODE
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 N/A NC
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 N/A NC
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 N/A NC
JUMPER SETTING
JBAT1
(1-2)NORMAL
(2-3)CLEAR
GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 Input NC
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 N/A NC
B B
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input GPIO36_ICH
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input GPIO37_ICH
GPIO[38] AD20 I/O Vcc3p3 N N 3.3 Input SPI_WP#1
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input SPI_WP#2
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A PGNT#4
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
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Custom
Custom
Date: Sheet
Date: Sheet
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7
6
5
4
3
Date: Sheet
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MICRO-START INT'L CO.,LTD.
GPIO MAP
GPIO MAP
GPIO MAP
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
336Friday, July 06, 2007
336Friday, July 06, 2007
336Friday, July 06, 2007
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CPU SIGNAL BLOCK
C36
C36
X_C10U6.3X51206
D D
H_INIT#13
H_BPRI#7
H_PROCHOT#
H_A20M#13
R97 51R0402R97 51R0402
CPU_GTLREF1
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
CPU_GTLREF0
H_IERR#
H_DBI#[0..3]7
H_FERR#13
H_STPCLK#13
H_DBSY#7
H_DRDY#7
H_TRDY#7
THERMDA_CPU22
H_TRMTRIP#5,13
H_PROCHOT#5
R68 0R0402R68 0R0402
H_D#[0..63]7
H_ADS#7
H_LOCK#7
H_BNR#7
H_HIT#7
H_HITM#7
H_DEFER#7
VTIN_GND22
H_IGNNE#13
ICH_H_SMI#13,26
H_SLP#13
H_FSBSEL016
H_FSBSEL116
H_FSBSEL216
H_PWRGD5,13
H_CPURST#5,7
C C
VTT_OUT_LEFT
H_BPM#1
B B
A A
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
H_A#[3..35]7
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
U5A
U5A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
H_D#53
VID3
VID4
VID0
VID2
VID5
VID1
VID7
AN6
AJ3
VSS_MB_REGULATION
VCC_MB_REGULATION
D10#
D9#
D8#
A11
A10
H_D#8
H_D#7
H_D#9
VID6
AM5
AL4
AK4
AM7
AK3
VID6#
VID5#
VID_SELECT
ITP_CLK1
ITP_CLK0
RSVD#AM7
GTLREF_SEL
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
H_D#5
H_D#2
H_D#3
H_D#6
H_D#4
H_D#1
AL6
AM3
AL5
AM2
VID4#
VID3#
VID2#
VID1#
VID0#
GTLREF0
GTLREF1
GTLREF2
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD#G6
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
B4
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
H_D#0
H_A#3
H_A#6
H_A#8
H_A#10
H_A#5
H_A#7
H_A#28
H_A#24
H_A#26
H_A#29
H_A#30
H_A#27
H_A#25
H_A#31
H_A#35
H_A#34
H_A#33
H_A#32
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
AB5
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
F21
F20
F18
A14
C14
H_D#52
E22
C15
D17
D20
D22
G22
G21
H_D#45
H_D#49
H_D#46
H_D#50
H_D#51
H_D#47
H_D#44
H_D#48
F17
E21
E19
E18
H_D#38
H_D#39
H_D#40
H_D#43
H_D#41
H_D#42
H_D#37
H_A#17
H_A#15
H_A#14
H_A#18
H_A#19
H_A#23
H_A#20
H_A#22
H_A#21
AA5
AD6
AA4
A24#
A23#
A22#
A21#
A20#Y4A19#Y6A18#W6A17#
D37#
D36#
D35#
D34#
D33#
D32#
E16
E15
G17
G18
G16
G15
H_D#32
H_D#36
H_D#33
H_D#31
H_D#34
H_D#35
H_A#16
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D31#
D30#
D29#
D28#
F15
F14
G14
G13
H_D#30
H_D#27
H_D#29
H_D#28
H_A#11
H_A#12
H_A#13
D27#
D26#
D25#
F12
E13
D13
H_D#25
H_D#24
H_D#26
H_A#9
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D24#
D23#
D22#
F11
E10
D10
H_D#23
H_D#21
H_D#22
H_A#4
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
H_D#17
H_D#19
H_D#20
H_D#18
AN4
AN5
L5
AC2
AN3
DBR#
VSS_SENSE
VCC_SENSE
D14#
D13#
D12#D8D11#
B12
B10
D11
C12
C11
H_D#12
H_D#15
H_D#13
H_D#10
H_D#11
H_D#14
H_D#16
VID[0..7] 29
AN7
H1
H2
TP_GTLREF_SEL
H29
MCH_GTLREF_CPU
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI8
H5
H_TESTHI9
G4
H_TESTHI10
G3
F24
G24
G26
G27
G25
F25
W3
F26
AK6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
U3
U2
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
X_C10U6.3X51206
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
H_FORCEPH
RSVD_GB
R47
R47
VTT_OUT_RIGHT
680R0402
680R0402
R79 X_0R0402R79 X_0R0402
TP14TP14
TP13TP13
R88 51R1%0402R88 51R1%0402
R103 51R1%0402R103 51R1%0402
R90 51R1%0402R90 51R1%0402
R116 51R1%0402R116 51R1%0402
R86 51R1%0402R86 51R1%0402
R153 51R1%0402R153 51R1%0402
TP15TP15
TP18TP18
TP19TP19
TP16TP16
H_NMI 13
H_INTR 13
VCC_VRM_SENSE
VSS_VRM_SENSE
VID_SEL 29
CPU_GTLREF0 5
CPU_GTLREF1 5
TP17TP17
MCH_GTLREF_CPU 7
H_BPM#0 6
PECI 22
H_TESTHI12 6
H_TESTHI1
RN10 8P4R-51R0402RN10 8P4R-51R0402
R141 51R0402R141 51R0402
R143 51R0402R143 51R0402
R62 X_62R0402R62 X_62R0402
R118 X_62R0402R118 X_62R0402
CK_H_CPU# 16
CK_H_CPU 16
H_RS#[0..2] 7
H_BR#0
H_ADSTB#1 7
H_ADSTB#0 7
H_DSTBP#3 7
H_DSTBP#2 7
H_DSTBP#1 7
H_DSTBP#0 7
H_DSTBN#3 7
H_DSTBN#2 7
H_DSTBN#1 7
H_DSTBN#0 7
H_REQ#[0..4] 7
R92 51R0402R92 51R0402
R87 51R0402R87 51R0402
1
2
3
4
5
6
7
8
V_FSB_VTT
VTT_OUT_RIGHT
VCC_VRM_SENSE 29
VSS_VRM_SENSE 29
VTT_OUT_LEFT
VTT_OUT_RIGHT5,6
H_BR#0 5,7
VTT_OUT_LEFT 5
C69
C69
X_C0.1u16Y0402
X_C0.1u16Y0402
C72
C72
X_C0.1u16Y0402
X_C0.1u16Y0402
VTT_OUT_RIGHT 5,6
C84
C84
C0.1u16Y0402
C0.1u16Y0402
VTT_OUT_RIGHT
C63 C0.1u16Y0402C63 C0.1u16Y0402
C67 C0.1u16Y0402C67 C0.1u16Y0402
V_FSB_VTT
1
3
5
7
H_TESTHI9
H_TESTHI8
BSEL
02
1
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN4 8P4R-680RRN4 8P4R-680R
VID5
1
VID2
3
VID4
5
VID0
7
VID7
1
VID3
3
VID6
5
VID1
7
RN2 8P4R-680RRN2 8P4R-680R
R93 62R0402R93 62R0402
RN7 8P4R-51R0402RN7 8P4R-51R0402
1
3
5
7
1
3
5
7
RN8 8P4R-51R0402RN8 8P4R-51R0402
1
3
5
7
RN9 8P4R-51R0402RN9 8P4R-51R0402
PLACE BPM TERMINATION NEAR CPU
RN31
RN31
8P4R-470R0402
8P4R-470R0402
2
4
6
8
R80 0R0402R80 0R0402
R71 0R0402R71 0R0402
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
TABLE
FSB FREQUENCY
267 MHZ (1067)000
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
H_FSBSEL1 16
H_FSBSEL0 16
H_FSBSEL2 16
Kentsfield
H_BPM#2
H_BPM#3
VTT_OUT_RIGHT
H_FERR#
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_BPM#2
H_TDI
H_TCK
H_TDO
H_IERR#
H_TMS
H_BPM#4
H_TRST#
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Intel LGA775 - Signals
Intel LGA775 - Signals
Intel LGA775 - Signals
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
436Friday, July 06, 2007
436Friday, July 06, 2007
436Friday, July 06, 2007
of
of
of
1
8
7
6
5
4
3
2
1
AE9
AD8
AC8
AB8
AA8
U5BU5B
VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
VCCP
VCCP
AF21
VCC#AF21
VCC#Y8
Y8
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AG9
AF22
AG11
AF9
AF8
VCC#AF9
VCC#AF8
VCC#AF22
VCC#AG11
VCC#Y27
VCC#Y28
VCC#Y29
VCC#Y30
Y27
Y28
Y29
Y30
AG22
AG21
AG19
AG18
AG15
AG14
AG12
VCC#AG22
VCC#AG21
VCC#AG19
VCC#AG18
VCC#AG15
VCC#AG14
VCC#AG12
VCC#W29
VCC#W30
VCC#W8W8VCC#Y23
VCC#Y24
VCC#Y25
VCC#Y26
Y23
Y24
Y25
Y26
W29
W30
AG8
AH15
AH14
AH12
AH11
AG30
AG29
AG28
AG27
AG26
AG25
VCC#AG9
VCC#AG8
VCC#AH14
VCC#AH12
VCC#AH11
VCC#AG30
VCC#AG29
VCC#AG28
VCC#AG27
VCC#AG26
VCC#AG25
VCC#U28
VCC#U29
VCC#U30
VCC#U8U8VCC#V8V8VCC#W23
VCC#W24
VCC#W25
VCC#W26
VCC#W27
VCC#W28
U27
U28
U29
U30
W23
W24
W25
W26
W27
W28
AH27
AH26
AH25
AH22
AH21
AH19
AH18
VCC#AH18
VCC#AH15
VCC#U26
VCC#U27
U26
AH28
AH29
AH30
VCC#AH8
VCC#AH9
VCC#AJ11
VCC#AH27
VCC#AH26
VCC#AH25
VCC#AH22
VCC#AH21
VCC#AH19
VCC#T29
VCC#T30
VCC#T8T8VCC#U23
VCC#U24
VCC#U25
T29
T30
U23
U24
U25
VCC#AJ12
VCC#AH28
VCC#AH29
VCC#AH30
VCC#T24
VCC#T25
VCC#T26
VCC#T27
VCC#T28
T23
T24
T25
T26
T27
T28
AJ26
AJ8
AJ9
VCC#AJ8
VCC#AJ14
VCC#AJ15
VCC#AJ18
VCC#N30
VCC#N8N8VCC#P8P8VCC#R8R8VCC#T23
N30
VCC#AJ9
VCC#AJ19
VCC#AJ21
VCC#AJ22
VCC#AJ25
VCC#AJ26
VCC#AK11
VCC#AK12
VCC#AK14
VCC#M29
VCC#M30
VCC#M8M8VCC#N23
VCC#N24
VCC#N25
VCC#N26
VCC#N27
VCC#N28
VCC#N29
N23
N24
N25
N26
N27
N28
N29
M29
M30
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
VCC#AK8
VCC#AK9
VCC#AL11
VCC#AL12
VCC#AL14
VCC#AL15
VCC#AK15
VCC#AK18
VCC#AK19
VCC#AK21
VCC#AK22
VCC#AK25
VCC#AK26
VCC#M24
VCC#M25
VCC#M26
VCC#M27
VCC#M28
M23
M24
M25
M26
M27
M28
VCC#AL18
VCC#K25
VCC#K26
VCC#K27
VCC#K28
VCC#K29
VCC#K30
VCC#K8K8VCC#L8L8VCC#M23
K24
K25
K26
K27
K28
K29
K30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AN11
AN12
AN14
AN15
AN18
AN19
AN21
VCC#AN11
VCC#AN9
AN8
VCC#AN12
VCC#AN8
VCC#AN14
VCC#AN30
AN30
AN22
VCC#AN15
VCC#AN18
VCC#AN19
VCC#AN21
VCC#AN22
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
VCC#AN26
VCC#AN29
1122334
AN25
AN26
AN29
VCCA
VSSA
VCCPLL
H_VCCA
A23
H_VSSA
B23
H_VCCPLL
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
H_VCCA
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
H_VCCPLL 8
V_FSB_VTT
VTT_OUT_RIGHT 4,6
VTT_OUT_LEFT 4
VTT_SEL 30
V_FSB_VTT
C178 C0.1U16X0402C178 C0.1U16X0402
C161 C0.1U16X0402C161 C0.1U16X0402
C170
C170
C4.7U10Y0805
C4.7U10Y0805
CAPS FOR FSB GENERIC
4
AL21
AL22
AL25
AL26
AL29
AL30
VCC#AL8
VCC#AL19
VCC#AL21
VCC#K24
K23
VCC#AL9
VCC#AL22
VCC#AL25
VCC#AL26
VCC#AL29
VCC#AL30
VCC#AM11
VCC#AM12
VCC#AM14
VCC#AM15
VCC#AM18
VCC#AM19
VCC#J20
VCC#J21
VCC#J22
VCC#J23
VCC#J24
VCC#J25
VCC#J26
VCC#J27
VCC#J28
VCC#J29
VCC#J30
VCC#J8J8VCC#J9J9VCC#K23
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
AM8
AM9
VCC#AM8
VCC#AM21
VCC#J19
J19
VCC#AM9
VCC#AM22
VCC#AM25
VCC#AM26
VCC#AM29
VCC#AM30
VCC#J10
VCC#J11
VCC#J12
VCC#J13
VCC#J14
VCC#J15
VCC#J18
J10
J11
J12
J13
J14
J15
J18
AN9
VCCP_CPUVCCP_CPU
VCCP
AF19
D D
C C
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
R105
8
R105
100R1%0402
100R1%0402
100R1%0402
100R1%0402
R100
R100
R112
R112
200R1%0402
200R1%0402
R106
R106
200R1%0402
200R1%0402
PLACE AT CPU END OF ROUTE
C86
C86
C1u16Y
C1u16Y
C78
C78
C1u16Y
C1u16Y
R66 130R1%0402R66 130R1%0402
R67 62R0402R67 62R0402
R94 62R0402R94 62R0402
R120 62R0402R120 62R0402
R91 X_100R0402R91 X_100R0402
R111 10R0402R111 10R0402
R109 10R0402R109 10R0402
H_PROCHOT#
H_CPURST#
H_TRMTRIP#
H_BR#0
H_PWRGD
7
C94
C94
C220P50N0402
C220P50N0402
C89
C89
C220P50N0402
C220P50N0402
H_CPURST# 4,7
H_BR#0 4,7
H_PWRGD 4,13
CPU_GTLREF0 4
CPU_GTLREF1 4
H_PROCHOT# 4
H_TRMTRIP# 4,13
6
VTT_OUT_RIGHT
VTT_OUT_RIGHT
B B
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
L11 X_10U125m_0805-1L11 X_10U125m_0805-1
C159
VCC5_SB
R77
R77
1KR0402
1KR0402
R70 4.7KR0402R70 4.7KR0402
C159
C4.7U10Y0805
C4.7U10Y0805
680R0402
680R0402
4
R78
R78
CP5
CP5
X_CP003
X_CP003
5
VID_GD#28,29
C167
C167
C1u16Y
C1u16Y
VTT_OUT_LEFT
C155
C155
X_C4.7U10Y0805
X_C4.7U10Y0805
VTT_PWG
Q7
2N3904SQ72N3904S
H_VCCA
H_VSSA
V_1P5_CORE
L12 X_10U125m_0805-1L12 X_10U125m_0805-1
CP6
CP6
X_CP003
X_CP003
C64
C64
C1u16Y
C1u16Y
3
C191
C191
C4.7U10Y0805
C4.7U10Y0805
Title
Title
Title
Intel LGA775 - Power
Intel LGA775 - Power
Intel LGA775 - Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
H_VCCPLL
C185
C187
C187
C1u16Y
C1u16Y
C185
X_C4.7U10Y0805
X_C4.7U10Y0805
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
536Friday, July 06, 2007
536Friday, July 06, 2007
536Friday, July 06, 2007
of
of
of
1
8
VTT_OUT_RIGHT4,5
D D
A12
A15
A18
A2
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE20
AE24
AE25
AE26
AE27
AE28
A21
A24
A6
A9
AA3
AA6
AA7
AB1
AB7
AE2
R142 X_1KR0402R142 X_1KR0402
C C
B B
R81
R81
51R1%0402
51R1%0402
U5C
U5C
VSS#A12
VSS#A15
VSS#A18
VSS#A2
VSS#A21
VSS#A24
VSS#A6
VSS#A9
VSS#AA23
VSS#AA24
VSS#AA25
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
AE29
R69
R69
51R1%0402
51R1%0402
H_COMP6
H_COMP7
AE3
COMP6Y3COMP7
VSS#AE29
VSS#AE30
AE5
AE30
VSS#AE5
AE4
AE7
7
RSVD#AE4
VSS#AE7
6
R83
R83
R82
R76
R76
51R0402
51R0402
R150
R150
TP21TP21
TP22TP22
TP20TP20
E23
D1
D14
RSVD#D1
RSVD#E23
RSVD#D14
VSS#AF10
VSS#AF13
VSS#AF16
VSS#AF17
AF10
AF13
AF16
AF17
AF20
RSVD#E5E5RSVD#E6E6RSVD#E7
VSS#AF20
AF23
24.9R1%0402
24.9R1%0402
H_COMP8
B13
F23
E7
F6
IMPSEL#
RSVD#F23
RSVD#B13
VSS#AF23
VSS#AF24
VSS#AF25
VSS#AF26
VSS#AF27
VSS#AF28
VSS#AF29
AF24
AF25
AF26
AF27
AF28
AF29
51R0402
51R0402
N4
J3
RSVD#J3
RSVD#N4
VSS#AF3
VSS#AF30
AF3
AF30
R82
51R0402
51R0402
MSID1
MSID0
V30
V29
V28
V27
V26
V25
V24
W1
P5
AC4
MSID[1]V1MSID[0]
RSVD#P5
RSVD#AC4
VSS#AF6
VSS#AF7
VSS#AG10
VSS#AG13
VSS#AG16
AF6
AF7
AG10
AG13
AG16
W4
Y2
V6
V3
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#V7V7VSS#V6
VSS#V3
VSS#W7W7VSS#W4
VSS#V30
VSS#AG17
VSS#AG20
VSS#AG23
VSS#AG24
VSS#AG7
VSS#AH1
VSS#AH10
VSS#AH13
VSS#AH16
VSS#AH17
VSS#AH20
AH1
AG7
AH10
AH13
AH16
AH17
AG17
AG20
AG23
AG24
AH20
V23
VSS#V29
VSS#V28
VSS#V27
VSS#V26
VSS#V25
VSS#V24
VSS#V23
VSS#AH23
VSS#AH24
VSS#AH3
VSS#AH6
VSS#AH7
VSS#AJ10
VSS#AJ13
AH3
AH6
AH7
AJ10
AJ13
AH23
AJ16
AH24
R84 0R0402R84 0R0402
T3
U1
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#AJ16
VSS#AJ17
VSS#AJ20
VSS#AJ23
AJ17
AJ20
AJ23
AJ24
5
H_TESTHI12 4
P30
P29
P28
P27
R5
R30
R29
VSS#R7R7VSS#R5
VSS#R30
VSS#AJ24
VSS#AJ27
VSS#AJ28
VSS#AJ29
AJ27
AJ28
AJ29
AJ30
R2
R28
R27
R26
R25
R24
R23
VSS#R29
VSS#AJ30
VSS#R2
VSS#R28
VSS#R27
VSS#R26
VSS#R25
VSS#R24
VSS#R23
VSS#AJ4
VSS#AJ7
VSS#AK10
VSS#AK13
VSS#AK16
VSS#AK17
VSS#AK2
AJ4
AJ7
AK2
AK10
AK13
AK16
AK17
P26
P4
VSS#P7P7VSS#P4
VSS#P30
VSS#P29
VSS#P28
VSS#P27
VSS#P26
VSS#AK20
VSS#AK23
VSS#AK24
VSS#AK27
VSS#AK28
VSS#AK29
VSS#AK30
AK20
AK23
AK24
AK27
AK28
AK29
AK30
P25
AK5
VSS#P25
VSS#AK5
P24
AK7
VSS#P24
VSS#AK7
4
L30
L29
L28
L27
L26
L25
L24
M1
P23
N3
L6
L3
VSS#L7L7VSS#L6
VSS#N7N7VSS#N6N6VSS#N3
VSS#P23
VSS#AL10
VSS#AL13
VSS#AL16
AL10
AL13
AL16
VSS#L3
VSS#M7M7VSS#M1
VSS#L30
VSS#AL17
VSS#AL20
VSS#AL23
VSS#AL24
VSS#AL27
VSS#AL28
VSS#AL3
AL3
AL17
AL20
AL23
AL24
AL27
AL28
L23
K2
K5
VSS#K2
VSS#L29
VSS#AL7
AL7
VSS#K7K7VSS#K5
VSS#L28
VSS#L27
VSS#L26
VSS#L25
VSS#L24
VSS#L23
VSS#AM1
VSS#AM10
VSS#AM13
VSS#AM16
VSS#AM17
VSS#AM20
VSS#AM23
VSS#AM24
VSS#AM27
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
3
H9
J7
VSS#J4J4VSS#J7
VSS#AM28
VSS#AM4
VSS#AN1
VSS#AN10
VSS#AN13
AN1
AM4
AN10
AN13
AM28
H24
H25
H26
H27
H28
VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9
VSS#H24
VSS#H25
VSS#H26
VSS#H27
VSS#H28
VSS#AN16
VSS#AN17
VSS#AN2
VSS#AN20
VSS#AN23
VSS#AN24
VSS#AN27
AN2
AN16
AN17
AN20
AN23
AN24
AN27
H23
VSS#H23
VSS#AN28
AN28
H21
H22
VSS#H21
VSS#H22
VSS#B1B1VSS#B11
H17
H18
H19
H20
VSS#H14
VSS#H13
VSS#H17
VSS#H18
VSS#H19
VSS#H20
VSS#H12
VSS#H11
VSS#H10
VSS#G1
VSS#F7
VSS#F4
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E8
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E2
VSS#E17
VSS#E14
VSS#E11
VSS#D9
VSS#D6
VSS#D5
VSS#D3
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C7
VSS#C4
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B8
VSS#B5
VSS#B24
VSS#B20
VSS#B17
VSS#B14
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B11
B14
2
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R114
R114
0R0402
0R0402
R148
R148
0R0402
0R0402
H_BPM#0 4
1
Optics Orientation Holes
OPTICS4
OPTICS5
8
OPTICS5
FM001
FM001
OPTICS3
OPTICS3
FM001
FM001
OPTICS2
OPTICS2
FM001
FM001
OPTICS1
OPTICS1
FM001
FM001
A A
OPTICS4
FM001
FM001
OPTICS8
OPTICS8
FM001
FM001
OPTICS6
OPTICS6
FM001
FM001
OPTICS7
OPTICS7
FM001
FM001
7
7
8
9
2
MH1MH1
9
2
MH5MH5
6
6
5
3
4
7
8
6
5
3
4
8
9
2
MH2MH2
3
8
9
2
MH6MH6
3
5
Mounting Holes
7
4
7
4
8
6
9
5
2
MH3MH3
3
8
6
9
5
2
MH7MH7
3
TP12TP12
7
7
4
7
4
8
9
6
2
5
MH4MH4
9
6
2
5
MH8MH8
6
5
3
4
7
8
6
5
3
4
4
3
Title
Title
Title
Intel LGA775 - GND
Intel LGA775 - GND
Intel LGA775 - GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
636Friday, July 06, 2007
636Friday, July 06, 2007
636Friday, July 06, 2007
of
of
of
1
8
H_A#[3..35]4
D D
C C
B B
H_ADSTB#04
H_ADSTB#14
H_REQ#[0..4]4
H_ADS#4
H_TRDY#4
H_DRDY#4
H_DEFER#4
H_HITM#4
H_HIT#4
H_LOCK#4
H_BR#04,5
H_BNR#4
H_BPRI#4
H_DBSY#4
H_RS#[0..2]4
CK_H_MCH16
CK_H_MCH#16
PWR_GD8,14,28
H_CPURST#4,5
PLTRST#8,13,28
ICH_SYNC#14
R186 16.5R1%0402-RHR186 16.5R1%0402-RH
H_CPURST#
H_A#[3..35]
H_REQ#[0..4]
NB_RSTNB_RST
C160 X_C33P50N0402C160 X_C33P50N0402
V_FSB_VTT_GMCHV_FSB_VTT_GMCH
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSCOMPB
HXSWING
MCH_GTLREF
V_1P25_CORE
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
W10/S7
W4/S14
W4/S14
W10/S5
N32
N34
M38
N37
M36
R34
N35
N38
U37
N39
R37
R39
R38
U36
U33
R35
AA37
M34
U34
G43
W40
W41
U42
AA42
W42
G39
U40
U41
AA41
U39
R32
U32
AM17
C31
AM18
D23
C25
D25
D24
J42
L39
J40
L37
L36
K42
P42
V36
V33
V35
Y34
V42
V38
Y36
Y38
Y39
F40
L35
L38
J37
Y40
T43
Y43
V41
J13
B25
B24
7
V_FSB_VTT
U8A
U8A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#
HADSTB0#
HADSTB1#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADS#
HTRDY#
HDRDY#
HDEFER#
HITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS0#
HRS1#
HRS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSCOMP#
HSWING
HDVREF
HAVREF
P29
VTT_1
P27
P26
VTT_2
VCC_1
AJ12
AJ11
P24
VTT_3
VTT_4
VCC_2
VCC_3
AJ10
P23
VTT_5
VCC_4
AJ9
N29
VTT_6
VCC_5
AJ8
N26
VTT_7
VCC_6
AJ7
N24
VTT_8
VCC_7
AJ6
N23
VTT_9
VCC_8
AJ5
M29
VTT_10
VCC_9
AJ4
M24
M23
VTT_11
VTT_12
VCC_10
VCC_11
AJ3
AJ2
L24
L23
VTT_13
VCC_12
AH4
AH2
K24
K23
VTT_14
VTT_15
VCC_13
VCC_14
AH1
AG13
6
J24
J23
VTT_16
VTT_17
VCC_15
VCC_16
AG12
AG11
H24
H23
VTT_18
VTT_19
VCC_17
VCC_18
AG9
AG10
G26
G24
VTT_20
VTT_21
VCC_19
VCC_20
AG8
AG7
G23
F26
VTT_22
VTT_23
VCC_21
VCC_22
AG6
AG5
F24
F23
VTT_24
VTT_25
VCC_23
VCC_24
AG4
AG3
E29
E27
VTT_26
VTT_27
VCC_25
VCC_26
AG2
AF13
E26
E23
VTT_28
VTT_29
VCC_27
VCC_28
AF12
AF11
D29
D28
VTT_30
VTT_31
VCC_29
VCC_30
AD24
AD22
D27
C30
VTT_32
VTT_33
VCC_31
VCC_32
AD20
AC25
C29
C27
VTT_34
VTT_35
VCC_80
VCC_34
AC23
AC21
5
B30
B29
VTT_36
VTT_37
VCC_35
VCC_36
AC19
AC13
B28
B27
VTT_38
VTT_39
VCC_37
VCC_38
AC6
AB24
A30
A28
VTT_40
VTT_41
VCC_39
VCC_40
AB22
AB20
R27
R26
VTT_42
VTT_43
VCC_41
VCC_42
AA25
AA23
R24
R23
VTT_44
VTT_45
VCC_43
VCC_44
AA21
AA19
AG19
VTT_46
VCC_45
VCC_46
AA3
AA13
AG18
AG17
VCC_84
VCC_85
VCC_47
VCC_48
Y24
Y22
AG15
AG14
VCC_86
VCC_87
VCC_49
VCC_50
Y20
Y13
AF26
AF25
VCC_88
VCC_89
VCC_51
VCC_52Y6VCC_53
V13
AF24
AF22
VCC_90
VCC_91
VCC_54
V12
V10
4
AF20
AF18
VCC_93
VCC_94
VCC_95
VCC_55
VCC_56V9VCC_57
U13
AF17
AF15
AF14
AE27
VCC_96
VCC_97
VCC_98
VCC_58
VCC_59U9VCC_60U6VCC_61U3VCC_62
U10
AE26
AE25
AE23
AE21
AE19
AE17
AD27
AD26
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_63
VCC_64N9VCC_65N8VCC_66N6VCC_67N3VCC_68L6VCC_69J6VCC_70J3VCC_71J2VCC_72G2VCC_73
N12
N11
AD18
AD17
VCC_107
VCC_108
VCC_109
AD15
AD14
VCC_110
VCC_111
F11
AC27
AC26
AC17
AC15
VCC_112
VCC_113
VCC_114
VCC_74F9VCC_75D4VCC_76
C13
3
V_1P25_CORE
AC14
AB27
AB26
AB18
AB17
AA27
AA26
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDSTBP0#
HDSTBN0#
HDSTBP1#
HDSTBN1#
HDSTBP2#
HDSTBN2#
HDSTBP3#
HDSTBN3#
VCC_77C9VCC_78
VCC_79
VCC_81
VCC_82
VCC_83
(INTEL-BROADWATER-946GZ-C2-R)
(INTEL-BROADWATER-946GZ-C2-R)
P20
Y11
AG25
AG21
AG20
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
R40
P41
R41
N40
R42
M39
N41
N42
L41
J39
L42
J41
K41
G40
F41
F42
C42
D41
F38
G37
E42
E39
E37
C39
B39
G33
A37
F33
E35
K32
H32
B34
J31
F32
M31
E31
K31
G31
K29
F31
J29
F29
L27
K27
H26
L26
J26
M26
C33
C35
E41
B41
D42
C40
D35
B40
C38
D37
B33
D33
C34
B35
A32
D32
M40
J33
G29
E33
L40
M43
G35
H33
G27
H27
B38
D38
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0
H_DSTBN#0
H_DSTBP#1
H_DSTBN#1
H_DSTBP#2
H_DSTBN#2
H_DSTBP#3
H_DSTBN#3
2
H_D#[0..63]
H_DBI#[0..3]
H_D#[0..63] 4
H_DBI#[0..3] 4
H_DSTBP#0 4
H_DSTBN#0 4
H_DSTBP#1 4
H_DSTBN#1 4
H_DSTBP#2 4
H_DSTBN#2 4
H_DSTBP#3 4
H_DSTBN#3 4
1
V_FSB_VTT
A A
R177 49.9R1%0402R177 49.9R1%0402
R178
R178
49.9R1%0402
49.9R1%0402
8
HXSCOMP
C234
C234
X_C2.7P25N0402
X_C2.7P25N0402
HXSCOMPB
C232
C232
X_C2.7P25N0402
X_C2.7P25N0402
7
HXSWING SHOULD BE 1/4*VTT
V_FSB_VTT
R176
R176
301R1%0402
301R1%0402
R182
R182
100R1%0402
100R1%0402
R183
R183
49.9R1%0402
49.9R1%0402
C235
C235
C0.01U16X0402
C0.01U16X0402
HXSWING
6
V_FSB_VTT
R175
100R1%0402
100R1%0402
R180
R180
200R1%0402
200R1%0402
*GTLREF VOLTAGE SHOULD BE
0.67*VTT=0.756V
MCH_GTLREF_CPU
R184 51R0402R184 51R0402
C238
C239
C239
C1u16Y
C1u16Y
5
C238
C0.1u16Y0402
C0.1u16Y0402
MCH_GTLREF_CPU 4
MCH_GTLREF
4
V_FSB_VTT
C225 X_C0.1u16Y0402C225 X_C0.1u16Y0402
C223 C0.1u16Y0402C223 C0.1u16Y0402R175
C227 C4.7U10Y0805C227 C4.7U10Y0805
C209 C0.1u16Y0402C209 C0.1u16Y0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
GMCH G31 - CPU
GMCH G31 - CPU
GMCH G31 - CPU
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
of
of
of
736Friday, July 06, 2007
736Friday, July 06, 2007
736Friday, July 06, 2007
1
8
D D
V_1P25_CORE
C296 C0.1u16Y0402C296 C0.1u16Y0402
R215 5.1KR0402R215 5.1KR0402
R225 5.1KR0402R225 5.1KR0402
R226 5.1KR0402R226 5.1KR0402
R212 5.1KR0402R212 5.1KR0402
C C
H_VCCPLL5
B B
V_1P25_CORE
DMI_ITP_MRP_0
DMI_ITP_MRP_1
DMI_ITP_MRP_2
DMI_ITP_MRP_3
V_1P25_CORE
EXP16_PRSNT#17
V_1P25_CORE
VCCA_DAC_GMCHVCCA_DAC_GMCH
CP12
CP12
X_CP003
X_CP003
1uF for pin B21
0.1uF for pin C21
L15
L15
X_10U100M_0805
X_10U100M_0805
21
CP9
CP9
X_CP003
X_CP003
CK_PE_100M_MCH16
CK_PE_100M_MCH#16
R451 0R0603R451 0R0603
L18
L18
X_10U100M_0805
X_10U100M_0805
21
C262
C262
C1u16Y
C1u16Y
VCCA_HPLL
C248
C248
X_C1u16Y
X_C1u16Y
DMI_ITP_MRP_013
DMI_ITN_MRN_013
DMI_ITP_MRP_113
DMI_ITN_MRN_113
DMI_ITP_MRP_213
DMI_ITN_MRN_213
DMI_ITP_MRP_313
DMI_ITN_MRN_313
SDVO_CTRL_DATA17
SDVO_CTRL_CLK17
R201 1KR0402R201 1KR0402
C246
C246
C0.1u16Y0402
C0.1u16Y0402
EXP_A_RXP_017
EXP_A_RXN_017
EXP_A_RXP_117
EXP_A_RXN_117
EXP_A_RXP_217
EXP_A_RXN_217
EXP_A_RXP_317
EXP_A_RXN_317
EXP_A_RXP_417
EXP_A_RXN_417
EXP_A_RXP_517
EXP_A_RXN_517
EXP_A_RXP_617
EXP_A_RXN_617
EXP_A_RXP_717
EXP_A_RXN_717
EXP_A_RXP_817
EXP_A_RXN_817
EXP_A_RXP_917
EXP_A_RXN_917
EXP_A_RXP_1017
EXP_A_RXN_1017
EXP_A_RXP_1117
EXP_A_RXN_1117
EXP_A_RXP_1217
EXP_A_RXN_1217
EXP_A_RXP_1317
EXP_A_RXN_1317
EXP_A_RXP_1417
EXP_A_RXN_1417
EXP_A_RXP_1517
EXP_A_RXN_1517
H_BSL016
H_BSL116
H_BSL216
EXP16_PRSNT#
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_3P3_DAC_FILTERED
VCCA_EXP
VCCDQ_CRT
C261
C261
C0.1u16Y0402
C0.1u16Y0402
7
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
H_BSL0
H_BSL1
H_BSL2
C284
C284
C0.1u16Y0402
C0.1u16Y0402
VCC3
V_1P25_CORE
U8C
U8C
F15
EXP_RXP0
G15
EXP_RXN0
K15
EXP_RXP1
J15
EXP_RXN1
F12
EXP_RXP2
E12
EXP_RXN2
J12
EXP_RXP3
H12
EXP_RXN3
J11
EXP_RXP4
H11
EXP_RXN4
F7
EXP_RXP5
E7
EXP_RXN5
E5
EXP_RXP6
F6
EXP_RXN6
C2
EXP_RXP7
D2
EXP_RXN7
G6
EXP_RXP8
G5
EXP_RXN8
L9
EXP_RXP9
L8
EXP_RXN9
M8
EXP_RXP10
M9
EXP_RXN10
M4
EXP_RXP11
L4
EXP_RXN11
M5
EXP_RXP12
M6
EXP_RXN12
R9
EXP_RXP13
R10
EXP_RXN13
T4
EXP_RXP14
R4
EXP_RXN14
R6
EXP_RXP15
R7
EXP_RXN15
W2
DMI_RXP0
V1
DMI_RXN0
Y8
DMI_RXP1
Y9
DMI_RXN1
AA7
DMI_RXP2
AA6
DMI_RXN2
AB3
DMI_RXP3
AA4
DMI_RXN3
B12
GCLKP
B13
GCLKN
G17
SDV0_CTRLDATA
E17
SDVO_CTRLCLK
G20
BSEL0
J20
BSEL1
J18
BSEL2
G18
MTYPE
E18
EXP_SLR
J17
EXP_EN
Y32
VCC_CL_PLL
C23
VCCA_HPLL
A24
VCCA_MPLL
A22
VCCA_DPLLA
C22
VCCA_DPLLB
B15
VCCA_EXPPLL
C17
VCCA_DAC_17
B16
VCCA_DAC_18
A16
VCCA_EXP_19
C21
VCCD_CRT_20
B21
VCCDQ_CRT_21
D16
VSS_1
B17
VCC33
V_1P25_CORE
V_1P25_CORE
AL26
VCC_EXP_1
AD11
AD10
VCC_DDR_GMCHVCC_DDR_GMCH
L16
L16
X_10U100M_0805
X_10U100M_0805
21
CP10
CP10
X_CP003
X_CP003
AL24
AL23
VCC_CL_1
VCC_CL_2
VCC_CL_3
VCC_EXP_2
VCC_EXP_3
VCC_EXP_4
AD9
AD8
VCCA_DPLLA
C253
C253
X_C1u16Y
X_C1u16Y
6
AL21
AL20
AL18
AL17
AL15
AK30
AK29
AK27
AJ31
AG31
AF31
AD32
AC32
AA32
AJ30
AJ29
AJ27
AG30
AG29
AG27
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_CL_7
VCC_CL_8
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_CL_12
VCC_CL_13
VCC_CL_14
VCC_CL_15
VCC_CL_16
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_CL_20
VCC_CL_21
VCC_CL_22
VCC_CL_23
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
VCC_EXP_8
VCC_EXP_9
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
VCC_EXP_14
VCC_EXP_15
VCC_EXP_16
VCCSM_1
VCCSM_2
VCCSM_3
VCCSM_4
VCCSM_5
VCCSM_6
VCCSM_7
AE4
AE3
AD2
AD1
AC4
AC3
AC2
C251
C251
C0.1u16Y0402
C0.1u16Y0402
AE2
BC39
BC34
BC30
BC26
BC22
BC18
BC14
AD7
AD6
AD5
AD4
5
AG26
AF30
AF29
AF27
AD30
AD29
AC30
AC29
AL12
AL11
AL10
AL9
AL8
AL7
AL6
AL5
AL4
AL3
AL2
AK26
AK24
AK23
AK21
AK20
AK18
VCC_CL_24
VCC_CL_25
VCC_CL_26
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCC_CL_33
VCC_CL_34
VCC_CL_35
VCC_CL_36
VCC_CL_37
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_CL_46
VCC_CL_47
VCCSM_8
VCCSM_9
VCCSM_10
VCCSM_11
VCCSM_12
VCCSM_13
VCCSM_14
VCCSM_15
VCCSM_16
VCCSM_17
VCCSM_18
VCCSM_19
VCCSM_20
VCCSM_21
VCCSM_22
VCC_SMCLK_5
VCC_SMCLK_4
VCC_SMCLK_3
VCC_SMCLK_2
VCC_SMCLK_1
BB39
BB37
BB32
BB28
BB26
BB24
BB20
BB18
BB16
BB12
AY32
AV26
AV18
AW24
AW20
L13
L13
X_10U100M_0805
X_10U100M_0805
CP7
CP7
X_CP003
X_CP003
21
VCC_DDR
H18
BA43
BB42
AY42
BA42
BB41
V_CKDDRVCC_DDR
V_CKDDR
C200
C200
X_C1u16Y
X_C1u16Y
VCC_CL_48
RESERVED_1
4
AK17
AK15
AK3
AK2
AK1
AJ13
AD31
AC31
AA31
Y31
AJ26
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AJ15
AJ14
AA30
AA29
Y30
Y29
V30
VCC_CL_49
VCC_CL_50
VCC_CL_51
VCC_CL_52
VCC_CL_53
VCC_CL_54
VCC_CL_55
VCC_CL_56
VCC_CL_57
VCC_CL_58
VCC_CL_59
VCC_CL_60
VCC_CL_61
VCC_CL_62
VCC_CL_63
VCC_CL_64
VCC_CL_65
VCC_CL_66
VCC_CL_67
VCC_CL_68
VCC_CL_69
VCC_CL_70
VCC_CL_71
VCC_CL_72
RESERVED_2
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10
RESERVED_3
BB2
BB19
AN21
AW42
AN32
AM31
AF32
AG32
AM21
C198
C198
C0.1u16Y0402
C0.1u16Y0402
RESERVED_11
RESERVED_12
RESERVED_13
RESERVED_14
RESERVED_15
RESERVED_16
RESERVED_17
Y12
U30
U31
AA9
AJ32
AL31
AA10
AA11
RESERVED_25
RESERVED_18
RESERVED_19
RESERVED_20
RESERVED_21
RESERVED_22
RESERVED_23
RESERVED_24
R29
R30
U12
U11
R12
R13
AP21
V_1P25_CORE
3
V29
U29
U27
AL13
AK14
AL29
AL27
EXP_A_TXP_0
D11
EXP_TXP0
EXP_TXN0
EXP_TXP1
VCC_CL_74
VCC_CL_75
VCC_CL_76
VCC_CL_77
VCC_CL_78
VCC_CL_79
EXP_COMPO
TEST2
TEST1
RESERVED_28
RESERVED_27
A43
V31
BC1
AA39
BC43
EXP_TXN1
EXP_TXP2
EXP_TXN2
EXP_TXP3
EXP_TXN3
EXP_TXP4
EXP_TXN4
EXP_TXP5
EXP_TXN5
EXP_TXP6
EXP_TXN6
EXP_TXP7
EXP_TXN7
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
EXP_COMPI
HSYNC
VSYNC
GREEN
GREEN#
BLUE#
DDC_DATA
DDC_CLK
DREFCLKP
DREFCLKN
REFSET
CL_PWROK
CL_RST#
CL_VERF
CL_CLK
CL_DATA
ALLZTEST
XORTEST
TESTIN#
TEST0
(INTEL-BROADWATER-946GZ-C2-R)
(INTEL-BROADWATER-946GZ-C2-R)
L20
L20
X_10U100M_0805
X_10U100M_0805
CP14
CP14
X_CP003
X_CP003
VCC_CL_73
RESERVED_26
F13
RED
BLUE
RED#
21
D12
B11
A10
C10
D9
B9
B7
D7
D6
B5
B6
B3
B4
F2
E2
F4
G4
J4
K3
L2
K1
N2
M2
P3
N4
R2
P1
U2
T2
V3
U4
V7
V6
W4
Y4
AC8
AC9
Y2
AA2
AC11
AC12
C15
D15
B18
C19
B20
C18
D19
D20
L13
M13
C14
D13
A20
AM15
AA12
AM5
AD13
AD12
K20
F20
A14
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_NB_TXN0
DMI_NB_TXP1
DMI_NB_TXN1
DMI_NB_TXP2
DMI_NB_TXN2
DMI_NB_TXP3
DMI_NB_TXN3
GRCOMP
VGA_R
VGA_G
VGA_B
DDC_DATAVCC_CL_PLL
DDC_CLK
CK_96M_DREF
CK_96M_DREF#
DACREFSET
PLTRST#
CL_VREF_MCH
CPU_TESTIN#
CPU_TEST0
CPU_TEST1
CPU_TEST2
VCCA_GPLL
C278
C278
X_C1u16Y
X_C1u16Y
C279
C279
C0.1u16Y0402
C0.1u16Y0402
2
EXP_A_TXP_0 17
EXP_A_TXN_0 17
EXP_A_TXP_1 17
EXP_A_TXN_1 17
EXP_A_TXP_2 17
EXP_A_TXN_2 17
EXP_A_TXP_3 17
EXP_A_TXN_3 17
EXP_A_TXP_4 17
EXP_A_TXN_4 17
EXP_A_TXP_5 17
EXP_A_TXN_5 17
EXP_A_TXP_6 17
EXP_A_TXN_6 17
EXP_A_TXP_7 17
EXP_A_TXN_7 17
EXP_A_TXP_8 17
EXP_A_TXN_8 17
EXP_A_TXP_9 17
EXP_A_TXN_9 17
EXP_A_TXP_10 17
EXP_A_TXN_10 17
EXP_A_TXP_11 17
EXP_A_TXN_11 17
EXP_A_TXP_12 17
EXP_A_TXN_12 17
EXP_A_TXP_13 17
EXP_A_TXN_13 17
EXP_A_TXP_14 17
EXP_A_TXN_14 17
EXP_A_TXP_15 17
EXP_A_TXN_15 17
C302 C0.1U10X0402C302 C0.1U10X0402
C301 C0.1U10X0402C301 C0.1U10X0402
C290 C0.1U10X0402C290 C0.1U10X0402
C291 C0.1U10X0402C291 C0.1U10X0402
C298 C0.1U10X0402C298 C0.1U10X0402
C299 C0.1U10X0402C299 C0.1U10X0402
C288 C0.1U10X0402C288 C0.1U10X0402
C289 C0.1U10X0402C289 C0.1U10X0402
R208 24.9R1%0402R208 24.9R1%0402
DDC_DATA 20
DDC_CLK 20
CK_96M_DREF 16
CK_96M_DREF# 16
R187 1.3KR1%0402R187 1.3KR1%0402
PWR_GD 7,14,28
PLTRST# 7,13,28
HSYNC 20
VSYNC 20
TP23TP23
TP6TP6
TP8TP8
TP7TP7
V_1P25_CORE
W10/S6
R191 0R0603R191 0R0603
R190 0R0603R190 0R0603
R188 0R0603R188 0R0603
DMI_MTP_IRP_0DMI_NB_TXP0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
VGA_RED
VGA_GREEN
VGA_BLUE
VGA_RED
VGA_GREEN
VGA_BLUEVGA_BLUE
C263
C263
C10P50N0402
C10P50N0402
DMI_MTP_IRP_0 13
DMI_MTN_IRN_0 13
DMI_MTP_IRP_1 13
DMI_MTN_IRN_1 13
DMI_MTP_IRP_2 13
DMI_MTN_IRN_2 13
DMI_MTP_IRP_3 13
DMI_MTN_IRN_3 13
C267
C267
C10P50N0402
C10P50N0402
CL_VREF_MCH = 0.349V
V_1P25_CORE
R218
R218
1KR1%0402
1KR1%0402
R219
R219
392R1%0402
392R1%0402
1
VGA_RED 20
VGA_GREEN 20
VGA_BLUE 20
C268
C268
C10P50N0402
C10P50N0402
CL_VREF_MCH
C293
C293
C0.1u16Y0402
C0.1u16Y0402
L17
L14
L14
X_10U100M_0805
A A
V_1P25_CORE
X_10U100M_0805
CP8
CP8
X_CP003
X_CP003
8
VCCA_MPLL
21
C242
C242
C245
C245
C0.1u16Y0402
C0.1u16Y0402
X_C1u16Y
X_C1u16Y
V_1P25_CORE
7
L17
X_10U100M_0805
X_10U100M_0805
21
CP11
CP11
X_CP003
X_CP003
VCCA_DPLLB
C259
C259
X_C1u16Y
X_C1u16Y
6
C258
C258
C0.1u16Y0402
C0.1u16Y0402
VCCA_HPLL ---- >50mA ; Min Vout -- 1.121V
VCCA_MPLL ---- >130mA ; Min Vout -- 1.128V
VCCA_DPLLA --- >80mA ; Min Vout -- 1.132V
VCCA_DPLLB --- >80mA ; Min Vout -- 1.131V
VCCA_DAC ----- 70mA ; Min Vout -- 3.14V
VCCD_CRT ----- 20mA ; Min Vout -- 1.425V
VCCDQ_CRT ---- 0.5mA ; Min Vout -- 1.425V
VCCA_EXPPLL -- 50mA ; Min Vout -- 1.129V
VCC_SMCLK ---- 250mA
5
CP13
CP13
X_CP003
X_CP003
L19
L19
VCC3
X_0.1U50M
X_0.1U50M
4
VCCA_EXP V_3P3_DAC_FILTERED
C275
C275
X_C1u16Y
X_C1u16Y
R199 1R1%0402R199 1R1%0402
C272
C272
C0.1u16Y0402
C0.1u16Y0402
3
C276
C276
C0.01U16X0402
C0.01U16X0402
21
For non-Graphic sku
Cxx change to 0-ohm
Rxx unstuff
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
GMCH G31 - PCI Express
GMCH G31 - PCI Express
GMCH G31 - PCI Express
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
836Friday, July 06, 2007
836Friday, July 06, 2007
836Friday, July 06, 2007
1
of
of
of
8
RAS_A#11,12
CAS_A#11,12
WE_A#11,12
DATA_B[0..63]
SCS_A#[0..1]
MAA_A[0..14]
ODT_A[0..1]
SBS_A[0..2]
DQS_A011
DQS_A#011
DQS_A111
DQS_A#111
DQS_A211
DQS_A#211
DQS_A311
DQS_A#311
DQS_A411
DQS_A#411
DQS_A511
DQS_A#511
DQS_A611
DQS_A#611
DQS_A711
DQS_A#711
P_DDR0_A11
N_DDR0_A11
P_DDR1_A11
N_DDR1_A11
P_DDR2_A11
N_DDR2_A11
R211 20R1%0402R211 20R1%0402
R210 20R1%0402R210 20R1%0402
R163 20R1%0402R163 20R1%0402
R162 20R1%0402R162 20R1%0402
DATA_A[0..63]11
SCS_A#0
SCS_A#1
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
ODT_A0
ODT_A1
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
5W/10S
DATA_A[0..63]
DATA_B[0..63]11
D D
C C
B B
A A
SCS_A#[0..1]11,12
MAA_A[0..14]11,12
ODT_A[0..1]11,12
SBS_A[0..2]11,12
VCC_DDR VCC_DDR
C197
C197
C0.1u16Y0402
C0.1u16Y0402
AW35
BA35
BA34
BB38
BB33
AY35
BB34
BA31
BB25
BA26
BA25
AY25
BA23
AY24
AY23
BB23
BA22
AY33
BB22
AW21
AY38
BA21
AY37
BA38
BB35
BA39
BA33
AW32
BB21
AU4
AR3
AT20
AU18
AR41
AR40
AL41
AL40
AG42
AG41
AC42
AC41
AU31
AR31
AP27
AN27
AV33
AW33
AP29
AP31
AM26
AM27
AT33
AU33
AN2
AN3
BB40
BA40
BB3
BA4
BB9
BA9
7
U8B
U8B
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SRAS_A#
SCAS_A#
SWE_A#
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_A14
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SBS_A0
SBS_A1
SBS_A2
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
6
DATA_B8
DATA_B4
DATA_B1
DATA_B3
DATA_B6
DATA_B0
DATA_B2
AN7
AN8
AW5
AW7
AN5
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
AV3
AV2
AP3
AR5
AR4
DATA_A4
DATA_A1
DATA_A2
DATA_A0
DATA_A3
DATA_B11
DATA_B5
DATA_B9
DATA_B10
DATA_B7
AN6
AN9
AU7
AT11
AU11
AP13
AR13
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
AP2
AV4
AY2
AY3
BB5
AY6
AU1
DATA_A8
DATA_A10
DATA_A5
DATA_A7
DATA_A6
DATA_A9
DATA_A11
DATA_B18
DATA_B19
DATA_B24
DATA_B16
DATA_B15
DATA_B17
DATA_B13
DATA_B14
DATA_B12
AR11
AU9
AV12
AU12
AU15
AV13
AU17
AT17
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
BA5
BB4
AY7
BC7
AW2
AW3
AY11
AW11
DATA_A17
DATA_A15
DATA_A18
DATA_A19
DATA_A14
DATA_A12
DATA_A13
DATA_A16
DATA_B26
DATA_B22
DATA_B20
DATA_B23
DATA_B21
AU13
AM13
AV15
AW17
AV24
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
BB6
BA6
AT18
BA10
BB10
DATA_A20
DATA_A24
DATA_A22
DATA_A21
DATA_A23
DATA_B31
DATA_B28
DATA_B27
DATA_B25
DATA_B30
DATA_B29
AT23
AT26
AP26
AU23
AW23
AR24
AN26
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
AT21
AP17
AP20
AV20
AR18
AU21
AN17
DATA_A25
DATA_A26
DATA_A31
DATA_A29
DATA_A27
DATA_A28
DATA_A30
5
DQM_B[0..7]11
SCKE_B[0..1]11,12
DATA_B34
DATA_B38
DATA_B33
DATA_B35
DATA_B36
DATA_B37
DATA_B32
AW37
AV38
AN36
AN37
AU35
AR35
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
AV42
AP42
AV40
AV41
AU40
AN39
DATA_A33
DATA_A36
DATA_A34
DATA_A37
DATA_A32
DATA_A35
DATA_B44
DATA_B45
DATA_B40
DATA_B43
DATA_B42
DATA_B41
DATA_B39
AN35
AR37
SDQ_B37
SDQ_B38
SDQ_A37
SDQ_A38
AP41
AR42
DATA_A39
DATA_A38
DATA_B46
AM35
AM38
AJ34
AL38
AR39
AM34
AL37
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
AL42
AK42
AK41
AN41
AN40
AN42
AM39
DATA_A41
DATA_A45
DATA_A46
DATA_A44
DATA_A43
DATA_A42
DATA_A40
DQM_B[0..7]
SCKE_B[0..1]
DATA_B48
DATA_B51
DATA_B49
DATA_B47
DATA_B53
DATA_B52
DATA_B50
AL32
AG38
AJ38
AF35
AF33
AJ37
AJ35
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
AJ40
AJ42
AJ41
AL39
AF39
AE40
AH43
DATA_A53
DATA_A51
DATA_A48
DATA_A47
DATA_A52
DATA_A49
DATA_A50
SCKE_A[0..1]11,12
DQM_A[0..7]11
DATA_B54
AG33
AF41
DATA_A54
DATA_B55
AF34
SDQ_B54
SDQ_B55
SDQ_A54
SDQ_A55
AF42
DATA_A55
DATA_B58
DATA_B57
DATA_B56
AD36
AC33
SDQ_B56
SDQ_B57
SDQ_A56
SDQ_A57
AD40
AD43
DATA_A58
DATA_A57
DATA_A56
SCKE_A[0..1]
DQM_A[0..7]
4
SCKE_B0
SCKE_B1
DATA_B63
DATA_B60
DATA_B59
DATA_B61
DATA_B62
AA34
AA36
AD34
AF38
AC34
AA33
AY12
AW12
BB11
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SCKE_B0
SCKE_B1
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SCKE_A0
SCKE_A1
AB41
AA40
AE42
AE41
AB42
AY20
AY21
AC39
BC20
SCKE_A0
SCKE_A1
DATA_A61
DATA_A63
DATA_A59
DATA_A60
DATA_A62
DQM_B4
DQM_B2
DQM_B5
DQM_B0
DQM_B3
DQM_B1
DQM_B6
AR7
AW9
AW13
AP23
AU37
BA11
SCKE_B2
SCKE_B3
SCKE_A2
SCKE_A3
BA19
AM37
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
BA2
AY9
AR2
AN18
AU43
AM43
DQM_A1
DQM_A4
DQM_A2
DQM_A6
DQM_A0
DQM_A3
DQM_A5
3
DQM_B7
AG39
AD38
SDM_B6
SDM_B7
SMRCOMPVOL
SMRCOMPVOH
SDM_A6
SDM_A7
(INTEL-BROADWATER-946GZ-C2-R)
(INTEL-BROADWATER-946GZ-C2-R)
AC40
AG40
DQM_A7
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SMA_B14
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SBS_B0
SBS_B1
SBS_B2
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SVREF
BB27
BB30
AY27
AY31
AW26
AW29
BA27
BB17
AY17
BA17
BC16
AW15
BA15
BB15
BA14
AY15
BB14
AW18
BB13
BA13
AY29
AY13
BA29
BA30
BB29
BB31
AY19
BA18
BC12
AV6
AU5
AR12
AP12
AP15
AR15
AT24
AU26
AW39
AU39
AL35
AL34
AG35
AG36
AC36
AC37
AV31
AW31
AU27
AT27
AV32
AT32
AU29
AR29
AV29
AW27
AN33
AP32
AM6
AM8
AM10
VCC_DDR
SCS_B#0
SCS_B#1
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
MAA_B14
ODT_B0
ODT_B1
SBS_B0
SBS_B1
SBS_B2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
MCH_VREF_A
DDR_RCOMPVOL
DDR_RCOMPVOH
R220 1KR1%0402R220 1KR1%0402
R237 1KR1%0402R237 1KR1%0402
SCS_B#[0..1]
MAA_B[0..14]
ODT_B[0..1]
SBS_B[0..2]
VTT_GMCHVTT_GMCH
2
DQS_B0 11
DQS_B#0 11
DQS_B1 11
DQS_B#1 11
DQS_B2 11
DQS_B#2 11
DQS_B3 11
DQS_B#3 11
DQS_B4 11
DQS_B#4 11
DQS_B5 11
DQS_B#5 11
DQS_B6 11
DQS_B#6 11
DQS_B7 11
DQS_B#7 11
P_DDR0_B 11
N_DDR0_B 11
P_DDR1_B 11
N_DDR1_B 11
P_DDR2_B 11
N_DDR2_B 11
R221
R221
3.01KR1%0402
3.01KR1%0402
SCS_B#[0..1] 11,12
RAS_B# 11,12
CAS_B# 11,12
WE_B# 11,12
MAA_B[0..14] 11,12
ODT_B[0..1] 11,12
SBS_B[0..2] 11,12
R229 1KR1%0402R229 1KR1%0402
R228
R228
1KR1%0402
1KR1%0402
DDR_RCOMPVOL = 0.2 * VCC_DDR
DDR_RCOMPVOL
C294
C294
C0.01U16X0402
C0.01U16X0402
DDR_RCOMPVOH
C303
C303
C0.01U16X0402
C0.01U16X0402
1
MCH_VREF_A
C306
C306
C0.1u16Y0402
C0.1u16Y0402
DDR_RCOMPVOH = 0.8 * VCC_DDR
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
GMCH G31 - Memory
GMCH G31 - Memory
GMCH G31 - Memory
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
936Friday, July 06, 2007
936Friday, July 06, 2007
936Friday, July 06, 2007
of
of
of
1
8
BC37
BC32
BC28
BC24
BC10
BC5
BB7
AY41
AY4
AW43
AW41
AW1
AV37
AV35
AV27
AV23
AV21
AV17
AV11
AV9
AV7
AU42
AU38
AU32
AU24
AU20
AU6
AU2
AT31
AT29
AT15
AT13
AT12
AR38
AR33
AR32
AR27
AR26
AR23
AR21
AR20
AR17
AR9
AR6
AP43
AP24
AP18
AP1
AN38
AN31
AN29
AN24
AN23
AN20
AN15
AN13
AN12
AN11
AN4
AM42
AM40
AM36
AM33
AM29
AM24
AM23
AM20
AM11
AM9
AM7
AM4
AM2
AM1
AL36
AL33
AK43
V_1P25_CORE
U8D
U8D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
AA17
AA15
AA14
Y27
Y26
Y18
Y17
Y15
Y14
W27
W26
W25
W23
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
V1P25_GMCHV1P25_GMCH
D D
C C
B B
W21
VCC_136
W19
VCC_137
W18
VCC_138
W17
VCC_139
7
V27
V26
V25
V24
V23
V22
V21
V20
V19
V18
V17
V15
V14
U26
U25
U24
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
6
U23
U22
U21
U20
U19
U18
U17
U15
U14
R20
R18
R17
R15
R14
P15
P14
AG24
AG23
AG22
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
5
N20
BC42
BC2
BB43
BB1
B43
M20
L15
L18
M18
F17
L17
N17
N18
N15
RESERVED_29
RESERVED_30
RESERVED_31
K17
RESERVED_33
RESERVED_34
RESERVED_35
RESERVED_36
RESERVED_37
RESERVED_32
RESERVED_38
B42
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8B2NC_9
4
L12
M11
A42
VCC
VSS
A41
VSS_293A3VSS_292A5VSS_291
C43
VSS_290C1VSS_289
R21
VSS_288E1VSS_287
W20
VSS_286
W22
VSS_285
W24
VSS_284
AA18
VSS_283
AC18
AE18
VSS_282
VSS_281
AE20
VSS_280
3
M42
VSS_270
N10
M35
M37
VSS_267
VSS_266N5VSS_265N7VSS_264
VSS_269
VSS_268
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_195
VSS_194
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_188
AE22
AE24
AF19
AF21
AF23
AY40
BA1
BC3
BC41
M33
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
N13
N21
N27
N31
N33
N36
P2
P17
P18
P21
P30
P43
R3
R5
R8
R11
R31
R33
R36
T1
T42
U5
U7
U8
U35
U38
V2
V5
V8
V11
V32
V34
V37
V39
V43
W3
Y1
Y5
Y7
Y10
Y19
Y21
Y23
Y25
Y33
Y35
Y37
Y42
AA5
AA8
AA20
AA22
AA24
AA35
AA38
AB1
AB2
AB19
AB21
AB23
AB25
AB43
AC5
AC7
AC10
AC20
AC22
AC24
AC35
AC38
AD19
AD21
AD23
AD25
AD33
AD35
2
1
Edge Decoupling Caps
Place close to GMCH
VCC_DDR
C233 C1u16YC233 C1u16Y
C240 C1u16YC240 C1u16Y
C264 C1u16YC264 C1u16Y
C270 C1u16YC270 C1u16Y
C224 C1u16YC224 C1u16Y
C247 C1u16YC247 C1u16Y
V_1P25_CORE
BOTTOM SIDE
C593 X_C4.7U10Y0805C593 X_C4.7U10Y0805
C587 X_C4.7U10Y0805C587 X_C4.7U10Y0805
C586 X_C4.7U10Y0805C586 X_C4.7U10Y0805
C588 X_C1u16YC588 X_C1u16Y
C590 X_C1u16YC590 X_C1u16Y
C589 C1u16YC589 C1u16Y
C591 C1u16YC591 C1u16Y
C300 C0.1u16Y0402C300 C0.1u16Y0402
C305 C0.1u16Y0402C305 C0.1u16Y0402
C317 C1u16YC317 C1u16Y
C592 C1u16YC592 C1u16Y
V_1P25_CORE
C310 C4.7U10Y0805C310 C4.7U10Y0805
C313 C4.7U10Y0805C313 C4.7U10Y0805
C311 C1u16YC311 C1u16Y
C312 C1u16YC312 C1u16Y
C318 C1u16YC318 C1u16Y
C316 C1u16YC316 C1u16Y
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96M7VSS_97M1VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105L7VSS_106L5VSS_107L3VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114K2VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120J9VSS_121J7VSS_122J5VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137G9VSS_138G7VSS_139G1VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145F3VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154E9VSS_155E3VSS_156
VSS_157
VSS_158
VSS_159
VSS_160D3VSS_161
VSS_162
VSS_163C6VSS_164C5VSS_165C4VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180A7VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
(INTEL-BROADWATER-946GZ-C2-R)
J38
J35
J32
J27
L33
L32
L31
L29
L21
L20
L11
K43
K26
K21
K18
K13
AF9
AF8
AF7
AF6
M27
M21
M17
M15
AJ39
AJ36
AJ33
AF43
AF37
AF36
A A
AH42
8
AF10
AG37
AG34
M10
7
K12
J21
H31
H29
H21
H20
H17
H15
H13
G42
G38
G32
G21
G13
6
F37
F35
F27
F21
F18
E43
E32
E24
E21
E20
E15
E13
E11
D40
D31
D21
G12
G11
5
D17
4
B37
B32
B31
B26
B23
B22
B19
B14
B10
A39
A34
A26
A18
C26
C11
A12
AF5
AF3
3
(INTEL-BROADWATER-946GZ-C2-R)
AF2
AF1
AD42
AD39
AD37
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
GMCH G31 - GND
GMCH G31 - GND
GMCH G31 - GND
Custom
Custom
Custom
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
10 36Friday, July 06, 2007
10 36Friday, July 06, 2007
10 36Friday, July 06, 2007
of
of
of
1
8
DIMM1
DIMM1
DATA_A[0..63]9
D D
C C
B B
A A
DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6 DQS_A#2
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63
8
VCC_DDR
3
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS#5
8
VSS#8
11
VSS#11
14
VSS#14
17
VSS#17
20
VSS#20
23
VSS#23
26
VSS#26
29
VSS#29
32
VSS#32
35
VSS#35
38
VSS#38
41
VSS#41
44
VSS#44
47
VSS#47
50
VSS#50
65
VSS#65
66
VSS#66
79
VSS#79
82
VSS#82
85
VSS#85
88
VSS#88
91
VSS#91
94
VSS#94
97
VSS#97
1KR1%0402
1KR1%0402
R222
R222
7
VCC_DDR
170
181
142
175
VDD7
VSS#142
145
VDD8
VSS#145
148
VDDQ0
VSS#148
151
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#151
VSS#154
154
157
VSS#157
197
69
VSS#160
160
163
102
55
19
NC
RC118RC0
NC#19
NC/TEST
VSS#100
VSS#103
VSS#106
VSS#109
VSS#112
VSS#115
100
103
106
109
112
115
7
191
VDD051VDD156VDD262VDD372VDD478VDD5
VDD3#75
VSS#118
VSS#121
VSS#124
VSS#127
VSS#130
VSS#133
118
121
124
127
130
133
136
DIMM_VREF_A
R227
R227
1KR1%0402
1KR1%0402
VSS#136
194
VDD6
VSS#139
139
75
68
VDDQ4#69
VSS#163
6
VCC3
172
187
184
189
67
178
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ7#178
VSS#166
VSS#169
VSS#198
VSS#201
VSS#204
VSS#207
VSS#210
166
169
198
201
204
207
210
238
VDDSPD
VSS#213
VSS#216
213
216
CB042CB143CB248CB349CB4
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS#219
VSS#222
VSS#225
VSS#228
219
222
225
228
161
162
167
CB5
CB6
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
VREF
VSS#231
VSS#234
VSS#237
231
234
237
168
CB7
DQS_A0
7
DQS_A#0
6
DQS_A1
16
DQS_A#1
15
DQS_A2
28
27
DQS_A3
37
DQS_A#3
36
DQS_A4
84
DQS_A#4
83
DQS_A5
93
DQS_A#5
92
DQS_A6
105
DQS_A#6
104
DQS_A7
114
DQS_A#7
113
46
45
X3
X3
MAA_A0
188
A0
MAA_A1
183
A1
MAA_A2
63
A2
MAA_A3
182
A3
MAA_A4
61
A4
MAA_A5
60
A5
MAA_A6
180
A6
MAA_A7
58
A7
MAA_A8
179
A8
MAA_A9
177
A9
MAA_A10
70
MAA_A11
57
A11
MAA_A12
176
A12
MAA_A13
196
A13
MAA_A14 MAA_B14
174
A14
173
A15
SBS_A2
54
SBS_A1
190
BA1
SBS_A0
71
BA0
WE_A#
73
CAS_A#
74
RAS_A#
192
DQM_A0
125
126
DQM_A1
134
135
DQM_A2
146
147
DQM_A3
155
156
DQM_A4
202
203
DQM_A5
211
212
DQM_A6
223
224
DQM_A7
232
233
164
165
ODT_A0
195
ODT_A1
77
SCKE_A0
52
SCKE_A1
171
SCS_A#0
193
SCS_A#1
76
P_DDR0_A
185
N_DDR0_A
186
P_DDR1_A
137
N_DDR1_A
138
P_DDR2_A
220
N_DDR2_A
221
SMBCLK
120
SCL
SMBDATA
119
SDA
X1
X1
DIMM_VREF_A
1
X2
X2
239
SA0
240
SA1
101
SA2
DDRII-240_blue-RH
DDRII-240_blue-RH
DDR2 DIMM1
6
5
C56
C56
C0.1u16Y0402
C0.1u16Y0402
DQS_A0 9
DQS_A#0 9
DQS_A1 9
DQS_A#1 9
DQS_A2 9
DQS_A#2 9
DQS_A3 9
DQS_A#3 9
DQS_A4 9
DQS_A#4 9
DQS_A5 9
DQS_A#5 9
DQS_A6 9
DQS_A#6 9
DQS_A7 9
DQS_A#7 9
MAA_A[0..14] 9,12
SBS_A2 9,12
SBS_A1 9,12
SBS_A0 9,12
WE_A# 9,12
CAS_A# 9,12
RAS_A# 9,12
DQM_A[0..7] 9
ODT_A0 9,12
ODT_A1 9,12
SCKE_A0 9,12
SCKE_A1 9,12
SCS_A#0 9,12
SCS_A#1 9,12
P_DDR0_A 9
N_DDR0_A 9
P_DDR1_A 9
N_DDR1_A 9
P_DDR2_A 9
N_DDR2_A 9
SMBCLK 14,16,17,18,19,25,28
SMBDATA 14,16,17,18,19,25,28
C297
C297
C0.1u16Y0402
C0.1u16Y0402
PLACE CLOSE TO DIMM PIN
ADDRESS: 000
0xA0
5
DATA_B[0..63]9
DIMM_VREF_DDRDIMM_VREF_DDR
4
DATA_B0
DATA_B1
DATA_B2
DATA_B3
DATA_B4
DATA_B5
DATA_B6
DATA_B7
DATA_B8
DATA_B9
DATA_B10
DATA_B11
DATA_B12
DATA_B13
DATA_B14
DATA_B15
DATA_B16
DATA_B17
DATA_B18
DATA_B19
DATA_B20
DATA_B21
DATA_B22
DATA_B23
DATA_B24
DATA_B25
DATA_B26
DATA_B27
DATA_B28
DATA_B29
DATA_B30
DATA_B31
DATA_B32
DATA_B33
DATA_B34
DATA_B35
DATA_B36
DATA_B37
DATA_B38
DATA_B39
DATA_B40
DATA_B41
DATA_B42
DATA_B43
DATA_B44
DATA_B45
DATA_B46
DATA_B47
DATA_B48
DATA_B49
DATA_B50
DATA_B51
DATA_B52
DATA_B53
DATA_B54
DATA_B55
DATA_B56
DATA_B57
DATA_B58
DATA_B59
DATA_B60
DATA_B61
DATA_B62
DATA_B63
4
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
DIMM_B1
DIMM_B1
3
DQ0
4
DQ1
9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS#5
8
VSS#8
VSS#11
VSS#14
VSS#17
VSS#20
VSS#23
VSS#26
VSS#29
VSS#32
VSS#35
VSS#38
VSS#41
VSS#44
VSS#47
VSS#50
VSS#65
VSS#66
VSS#79
VSS#82
VSS#85
VSS#88
VSS#91
VSS#94
VSS#97
55
100
VSS#100
103
RC118RC0
VSS#103
102
19
NC#19
VSS#106
106
109
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
NC/TEST
VSS#109
VSS#112
VSS#115
VSS#118
112
115
118
121
VSS#121
3
VCC_DDRVCC_DDR
170
197
172
187
184
75
191
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDD3#75
VSS#124
VSS#127
VSS#130
124
127
130
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#133
VSS#136
VSS#139
VSS#142
VSS#145
VSS#148
VSS#151
VSS#154
VSS#157
133
136
139
142
145
148
151
154
157
189
178
69
VDDQ5
VDDQ6
VDDQ7
VDDQ4#69
VDDQ7#178
VSS#160
VSS#163
VSS#166
VSS#169
VSS#198
VSS#201
160
163
166
169
198
201
204
VDDQ8
VSS#204
2
VCC3VCC_DDR
67
VDDQ9
VSS#207
VSS#210
207
210
238
VDDSPD
VSS#213
VSS#216
213
216
CB042CB143CB248CB349CB4
VSS#219
VSS#222
VSS#225
219
222
225
228
161
162
167
168
CB5
CB6
CB7
7
DQS0
6
DQS0#
16
DQS1
15
DQS1#
28
DQS2
27
DQS2#
37
DQS3
36
DQS3#
84
DQS4
83
DQS4#
93
DQS5
92
DQS5#
105
DQS6
104
DQS6#
114
DQS7
113
DQS7#
46
DQS8
45
DQS8#
X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
A10_AP
57
A11
176
A12
196
A13
174
A14
173
A15
54
A16/BA2
190
BA1
71
BA0
73
WE#
74
CAS#
192
RAS#
125
DM0/DQS9
126
NC/DQS9#
134
DM1/DQS10
135
NC/DQS10#
146
DM2/DQS11
147
NC/DQS11#
155
DM3/DQS12
156
NC/DQS12#
202
DM4/DQS13
203
NC/DQS13#
211
DM5/DQS14
212
NC/DQS14#
223
DM6/DQS15
224
NC/DQS15#
232
DM7/DQS16
233
NC/DQS16#
164
DM8/DQS17
165
NC/DQS17#
195
ODT0
77
ODT1
52
CKE0
171
CKE1
193
CS0#
76
CS1#
185
CK0(DU)
186
CK0#(DU)
137
CK1(CK0)
138
CK1#(CK0#)
220
CK2(DU)
221
CK2#(DU)
120
SCL
119
SDA
X1
X1
1
VREF
X2
X2
239
SA0
240
SA1
101
SA2
VSS#228
VSS#231
VSS#234
VSS#237
DDRII-240_GREEN-15U-IN-RH
DDRII-240_GREEN-15U-IN-RH
231
234
237
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
MAA_B0
MAA_B1MAA_B1
MAA_B2MAA_B2MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
SBS_B2
SBS_B1
SBS_B0
WE_B#
CAS_B#
RAS_B#
DQM_B0
DQM_B1
DQM_B2
DQM_B3
DQM_B4
DQM_B5
DQM_B6
DQM_B7
ODT_B0
ODT_B1
SCKE_B0
SCKE_B1
SCS_B#0
SCS_B#1
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
SMBCLK
SMBDATA
DIMM_VREF_A
VCC3
ADDRESS: 010
1
DQS_B0 9
DQS_B#0 9
DQS_B1 9
DQS_B#1 9
DQS_B2 9
DQS_B#2 9
DQS_B3 9
DQS_B#3 9
DQS_B4 9
DQS_B#4 9
DQS_B5 9
DQS_B#5 9
DQS_B6 9
DQS_B#6 9
DQS_B7 9
DQS_B#7 9
MAA_B[0..14] 9,12
SBS_B2 9,12
SBS_B1 9,12
SBS_B0 9,12
WE_B# 9,12
CAS_B# 9,12
RAS_B# 9,12
DQM_B[0..7] 9
ODT_B0 9,12
ODT_B1 9,12
SCKE_B0 9,12
SCKE_B1 9,12
SCS_B#0 9,12
SCS_B#1 9,12
P_DDR0_B 9
N_DDR0_B 9
P_DDR1_B 9
N_DDR1_B 9
P_DDR2_B 9
N_DDR2_B 9
PLACE CLOSE TO DIMM PIN
0xA4
DDR2 DIMM2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
DDR II DIMM 1&2
DDR II DIMM 1&2
DDR II DIMM 1&2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7396L2 0A
MS-7396L2 0A
MS-7396L2 0A
11 36Friday, July 06, 2007
11 36Friday, July 06, 2007
11 36Friday, July 06, 2007
of
of
of
1
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