MSI MS-7222 Schematics 20
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B
C
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MSI
MS-7222 Ver:20
4 4
CPU:
Intel Prescott LGA775 -Mainstream CPU
System Chipset:
North Bridge : VIA P4M800 Pro
South Bridge : VIA VT8237R Plus
On Board Chipset:
LPC Super I/O -- W83627EHG
LAN(PHY) --- Realtek 8201CL
AC'97 Codec --Realtek ALC655
BIOS --LPC FLASH ROM
3 3
CLOCK Chip :
CLOCK Generator --
Realtek RTM866-522
Main Memory:
DDRII * 2 (Max 2GB)
Expansion Slots:
PCI 2.3 SLOT * 3
PWM:
VRM10.1 Intersil 6566 3Phase
2 2
CHIPSET P4M800_Pro + VT8237R_PLUS
TITLE
COVER SHEET
BLOCK DIAGRAM
PWR And CLOCK Map
GPIO/MEMORY/PCI/HW STRPPING
PROCESSOR ( Intel LGA775)
NORTH BRIDGE P4M800_Pro
DDR II DIMM 1 & 2
DIMM1&2 Terminations
AGP SLOT
VGA Connector
Clock Generator RTM866-522
SOUTH BRIDGE (VT8237R Plus)
PCI Slot 1 & 2 & 3
Realtek 8201CL
Super I/O & FAN 83627EHG
AC97 Realtek ALC655
IDE Connectors , KB/MS
USB Connectors
COM / Parallel Port
MS7 ACPI Controller
VRM 10.1 - Intersil 6566_3 Phases
ATX & F_Panel & BIOS
PCB Components & EMI & Manual Part
SHEET
5,6,7
8,9,10,11
17,18,19
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MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
MICRO-START INT'L CO.,LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7222 20
MS-7222 20
MS-7222 20
E
130Wednesday, April 05, 2006
130Wednesday, April 05, 2006
130Wednesday, April 05, 2006
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VRM 10.1
Intersil 6566
3Phase
Block Diagram
Intel Prescott Processor-LGA775
FSB
mainstream
TDP=84W
Iccmax=78A
Icctdc=68A
1
AGP 1.5V
Connector
IDE Primary
IDE Secondary
A A
USB Port 0
USB Port 1
USB Port 2
2X/4X/8X
UltraDMA 33/66/100
USB
P4M800_Pro
VCORE= +2.5VNB
VDIMM= +2.5VDIMM
VDDQ= +1.5VAGP
VLINK= +2.5V
VT8237_PLUS
VCC25= +2.5V
VCC33= +3.3V
V-Link/8bits/S533M
LPC Bus
64bit DDR
PHY
2 DDRII
DIMM
Modules
PCI CNTRL
PCI ADDR/DATA
LAN
Realtek 8201CL
PCI Slot 1
PCI Slot 2
PCI Slot 3
USB Port 3
USB Port 4
LPC SIO
USB Port 5
Winbond
83627EHG
USB Port 6
USB Port 7
AC'97 Codec
AC'97 Link
SATA prot1 and
port2
LPC FLASH
ROM
KEYBOARD
MOUSE
FDD
1
Parallel
Serial
X2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7222 20
MS-7222 20
MS-7222 20
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231Wednesday, April 05, 2006
231Wednesday, April 05, 2006
231Wednesday, April 05, 2006
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P4M800 PLATFORM CLOCK GENERATOR MAP
3.3V 5V 5VSB 12V
P4M800_CE PLATFORM POWER DELIVERY MAP
PROCESSOR VCCP 1.2V~1.425V
D D
VRM
PROCESSOR 1.2V
Intel LGA775 Processor
CPU HOST
CLK
GUICK
DCLKO
DCLKI
NB
P4M800_Pro
GCLK_NB 66MHz
CLOCK GENERATOR
MEM CLK
0~5/CLK#0~5
C C
14.318MHZ
33MHz
48MHZ
2 DDRII DIMM
SB14MHz
APIC
USB
Modules
VT8237R_PLUS
VCLK
1.2V VREG
2.5V VREG
1.5V VREG
3VSB VREG
DDR 2.5V
VREG
2.5V VREG
VTT 1.25V
VREG
SPCLK
2.5VSB
FWH_CLK
PCI CLK 1~2
LPC
PCI Slot 1~3
VREG
Realtek 8201CL
B B
AGP SLOT 1.5V
NORTH BRIDGE VCCP
NORTH BRIDGE VCC_AGP
NORTH BRIDGE +2.5V
NORTH BRIDGE SYSEM MEMORY
VCC_DDR
3A
DDRII DIMM1 / DIMM2 2.5V
DDR VTT 1.25V
550mA
SOUTH BRIDGE +2.5V
SOUTH BRIDGE VCC3
Vlink=70mA
150mA
SOUTH BRIDGE RESUME 2.5V_SB
SOUTH BRIDGE RESUME VCC3_SB
SOUTH BRIDGE RTC 3.3V
LAN VCC3_SB
LPC 3.3V
10mA
120mA
SIOPCLK
SIO48MHZ
LPC SIO
Winbond
W83627EHG
LPC SUPER I/O 3.3V
LPC SUPER I/O VCC5
AC97XIN
AGP CLK
ALC655
AGP SLOT
AC97 VDD5
VREG
RTM866-522 3.3V
AC97 VDD5
+12V : 0.1U 25V X 5
A A
+12V_MOS: 4.7U 35V X 1
1U 16V X 2
1000U 16V X 4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
PWR And CLOCK Map
PWR And CLOCK Map
PWR And CLOCK Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
8
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Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7211 410
MS-7211 410
MS-7211 410
2
331Wednesday, April 05, 2006
331Wednesday, April 05, 2006
331Wednesday, April 05, 2006
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VT8237R_PLUS GPIO Function Define
PIN NAME Function define
GPO0 (VDDS)
GPO1(VDDS)
GPO2/SUSA#
(VDDS)
GPO3/SUSST#(VDDS)
GPO4/SUSCLK(VDDS)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/GNT5
GPO8/GPI8/VGATE
GPO9/UDPWREN
GPO10/GPI10/PICD0
GPO11/GPI11/PICD1
GPO12/GPI12/INTE#
GPO13/GPI13/INTF#
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
GPO20/GPI20
/ACSDIN2/PCS0#
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
A A
GPO22/GPI22/GHI#
GPO23/GPI23/DPSLP
/GPIOAGPO24/GPI24
GPO25/GPI25
GPO26/GPI26/SMBDT2
(VDDS)
GPO27/GPI27/SMBCK2
(VDDS)
GPO28/GPI28/VIDSEL
GPO29/GPI29/VRDSLP
GPO30/GPI30
GPO31/GPI31
/GPIOB
/GPIOC
/GPIOD
Default
Function
GPO0
GPO1
SUSA#
SUSST#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPO8
UDPWREN
GPO10
GPO11
GPO12
GPO13
GPO14
GPO15
GPI20/ACSDIN2
GPI21/ACSDIN3
GPI22
GPI23
GPIOA
GPIOB
SMBDT2
SMBCK2
GPO28
/VIDSEL
GPO29
/VRDSLP
GPIOC
GPIOD
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
ohm Pull up to VCC3
8.2K
2.7K ohm Pull up to VCC3
NC
1K ohm Pull up to VCC3
1K ohm Pull up to VCC3
8.2K ohm Pull up to VCC3
8.2K ohm Pull up to VCC3
8.2K ohm Pull up to VCC3
8.2K ohm Pull up to VCC3
4.7K ohm Pull down
4.7K ohm Pull down
4.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
2.2K ohm Pull up to VCC3
SEL Vlink Manual mode
2.2K ohm Pull down
SEL IOQ Depth=8 Level
ohm Pull up to VCC3_SB
2.7K
ohm Pull up to VCC3_SB
2.7K
SATA_LED
4.7K ohm Pull down
2.2K ohm Pull up to VCC3
SEL Host Clock=Auto mode
2.2K ohm Pull down
SEL GTL pull up=Enable
PIN NAME Function define
GPI0
(VBAT)
GPI1
(VSUS3)
GPI2/EXTSMI#
(VSUS3)
GPI3/RING#
(VSUS3)
GPI4/LID#
(VSUS3)
GPI5/BATLOW# (VDDS)
GPI6/AGPBZ
GPI7/REQ5
GPI9/UDPWREN
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPI19/APICCLK APICCLK
DDR DIMM Config.
DEVICE
DIMM 1
DIMM 2
1010000B
1010001B
PCI Config.
DEVICE
PCI Slot 1 PCIREQ#0 AD18 12
PCI Slot 2 PCIREQ#1 AD19 PCI_CLK2
PCI Slot 3 PCIREQ#2 AD20
Default
Function
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
AGPBZ
GPI7
UDPWR
INTRUDER#
CPUMISS
THERM#
APICCLK
CLOCKADDRESS
DCLKA0/MDCLKA#0
DCLKA1/MDCLKA#1
DCLKA2/MDCLKA#2
DCLKA3/MDCLKA#3
DCLKA4/MDCLKA#4
DCLKA5/MDCLKA#5
PIRQ#A
PIRQ#D
PIRQ#C
PIRQ#B
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#B
ohm Pull up to VBAT
1M
ATADET0=>Detect IDE1 ATA100/66
4.7K ohm Pull up to VCC3_SB
RING#
4.7K ohm Pull up to VCC3_SB
ATADET1=>Detect IDE2 ATA100/66
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to VCC3
8.2K ohm Pull up to VCC3
10K ohm Pull down
1M ohm Pull up to VBAT
4.7K ohm Pull up to VCC3_SB
4.7K ohm Pull up to
VCC3_SB
PCI RESET DEVICE
PCIRST#1
PCIRST#2
PCIRST#3 LPC
HD_RST#
IDSEL
PCIGNT#0
PCIGNT#1
PCIGNT#2
USB
Rear
Front
Signals Target
PCI_CLK1
PCI_CLK3
PCI slot 1-3
NB , Super I/O
Primary, Scondary IDE
CLOCKREQ#/GNT# CLK GEN PIN OUTMCP1 INT Pin
14
15
Port DATA +/-
USB1
LAN_USB1
JUSB2
JUSB1
USB1ÂUSB1+
USB0ÂUSB0+
USB2ÂUSB2+
USB3ÂUSB3+
USB4ÂUSB4+
USB6ÂUSB6+
USB5ÂUSB5+
USB7ÂUSB7+
OC#
OC#1
( OC#0~3 )
OC#4
( OC#4~7 )
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
GPIO/MEMORY/PCI/HW STRPPING
GPIO/MEMORY/PCI/HW STRPPING
GPIO/MEMORY/PCI/HW STRPPING
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
1
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7211 410
MS-7211 410
MS-7211 410
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431Wednesday, April 05, 2006
431Wednesday, April 05, 2006
431Wednesday, April 05, 2006
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CPU SIGNAL BLOCK
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
G11
AD3
AD1
AC1
AG1
AH2
G10
G29
G30
G23
HA#[3..33][8]
A8
D19
C20
F2
AB2
AB3
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
AF1
AE1
AL1
AK1
M2
AE8
AL2
N2
P2
K3
L2
N5
AE6
C9
D16
A20
Y1
V2
AA2
H30
N1
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
U5A
U5A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
HD#53
D53#
C14
HD#52
D52#
C15
HD#51
D51#
A14
HD#50
D50#
D17
HD#49
AJ6
D49#
D20
HD#48
AJ5
A35#
D48#
G22
HD#47
HA#33
AH5
A34#
D47#
D22
HD#46
HA#32
AH4
A33#
D46#
E22
HD#45
HA#31
AG5
A32#
D45#
G21
HD#44
HA#30
AG4
A31#
D44#
F21
HD#43
HA#29
AG6
A30#
D43#
E21
HD#42
A29#
D42#
HD#41 HA#28
AF4
F20
HA#27
AF5
A28#
D41#
E19
HD#40
HA#26
AB4
A27#
D40#
E18
HD#39
HA#25
AC5
A26#
D39#
F18
HD#38
HA#24
AB5
A25#
D38#
F17
HD#37
HA#23
AA5
A24#
D37#
G17
HD#36
HA#22
AD6
A23#
D36#
G18
HD#35
HA#21
AA4
A22#
D35#
E16
HD#34
HA#19
HA#20
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E15
G16
HD#32
HD#33
HA#18
D32#
G15
HD#31
HA#17
AB6
D31#
F15
HD#30
HA#16
D30#
G14
HD#29
HA#10
HA#14
HA#12
HA#11
HA#13
HA#15
U6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
D24#
F14
F12
F11
E13
D13
G13
HD#23
HD#28
HD#25
HD#26
HD#27
HD#24
HA#6
HA#8
HA#7
HA#9
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
HD#20
HD#21
HD#19
HD#22
HA#4
HA#5
HD#17
HD#18
HA#3
L5
HD#16
HD#15
D11
AC2
DBR#
D14#
C12
HD#13
HD#14
B12
AN3
D13#
HD#12
AN4
VSS_SENSE
VCC_SENSE
D12#D8D11#
C11
HD#11
D D
HDBI#[0..3][8]
TP12TP12
FERR#[6,19]
STPCLK#[19]
HINIT#[19]
HDBSY#[8]
HDRDY#[8]
HTRDY#[8]
HADS#[8]
HLOCK#[8]
C C
B B
A A
HBNR#[8]
HIT#[8]
HITM#[8]
HBPRI#[8]
HDEFER#[8]
CPU_TMPA[22]
VTIN_GND[22]
THERMTRIP#[6,29]
CPUMISS[18]
PROCHOT#[6]
IGNNE#[19]
SMI#[19]
SLP#[19]
HD#[0..63][8]
HDBI#0
HDBI#1
HDBI#2
HDBI#3
-EDRDY
1
IERR#
IERR#[6]
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_BSL0[6,16]
H_BSL1[6,16]
H_BSL2[6]
CPU_GD[6,27]
CPURST#[6,8]
AN6
AN5
VSS_MB_REGULATION
VCC_MB_REGULATION
D10#
D9#
D8#
B10
A11
A10
HD#10
HD#8
HD#9
HD#7
C4
C4
X_C10U10X1206
X_C10U10X1206
Close to CPU
TP1TP1
1
VID5
VID4
AJ3
AK3
AM5
AL4
AK4
AM7
VID6#
VID5#
VID_SELECT
ITP_CLK1
ITP_CLK0
RSVD#AM7
GTLREF_SEL
TESTHI12
TESTHI11
TESTHI10
FORCEPH
RSVD#G6
LINT1/NMI
LINT0/INTR
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
HD#3
HD#2
HD#4
HD#1
HD#6
HD#5
VID4#
GTLREF0
GTLREF1
GTLREF2
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
VCC_VRM_SENSE [28]
VSS_VRM_SENSE [28]
VID[0..5] [28]
VID0
VID3
VID2
VID1
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
H2
H29
E24
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
P1
H5
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
G6
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
ZIF-SOCK775_black-RH
ZIF-SOCK775_black-RH
B4
HD#0
R33 62R0402R33 62R0402
CPU_GTLREF0
CPU_GTLREF0
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
HRS#2
HRS#1
HRS#0
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
1
1
1
1
GTLREF_SEL
TP10TP10
1
HREQ#[0..4] [8]
R47 62R0402R47 62R0402
1
2
3
4
5
6
7
8
RN18 8P4R-62R0402RN18 8P4R-62R0402
R72 62R0402R72 62R0402
R49 62R0402R49 62R0402
R73 62R0402R73 62R0402
CPUCLK# [16]
CPUCLK [16]A20M#[19]
HRS#[0..2] [8]
-HAP1
-HAP1 [8]
-HAP0
-HAP0 [8]
R53 60.4R1%0402R53 60.4R1%0402
R61 60.4R1%0402R61 60.4R1%0402
R56 60.4R1%0402R56 60.4R1%0402
R65 60.4R1%0402R65 60.4R1%0402
R54 60.4R1%0402R54 60.4R1%0402
R74 60.4R1%0402R74 60.4R1%0402
TP9TP9
PLACE RESISTORS OUTSIDE SOCKET
TP4TP4
CAVITY IF NO ROOM FOR VARIABLE
TP3TP3
RESISTOR DON'T PLACE
TP7TP7
HADSTB#1 [8]
HADSTB#0 [8]
HDSTBP#3 [8]
HDSTBP#2 [8]
HDSTBP#1 [8]
HDSTBP#0 [8]
HDSTBN#3 [8]
HDSTBN#2 [8]
HDSTBN#1 [8]
HDSTBN#0 [8]
NMI_SB [19]
INTR [19]
H_BPM#5
H_BPM#1
H_BPM#0
H_TDO
H_BPM#4
H_TRST#
H_BPM#3
H_TMS
H_TDI
H_BPM#2
H_TCK
CPU_GTLREF0 [6]
TP11TP11
1
CPU_GTLREF0 [6]
GTLVREF_NB [8]
VTT_OUT_LEFT
V_FSB_VTT
HBR#0 [6,8]
VTT_OUT_LEFT
C30
C30
X_C0.1U25Y
X_C0.1U25Y
HINIT#
SMI#
IGNNE#
STPCLK#
NMI_SB
SLP#
INTR
A20M#
2
4
6
8
2
4
6
8
2
4
6
8
VTT_OUT_LEFT
1
3
5
7
1
3
5
7
VTT_OUT_RIGHT
1
3
5
7
1
3
5
7
1
3
5
7
2
RN12
RN12
4
8P4R-62R0402
8P4R-62R0402
6
8
2
RN10
RN10
4
8P4R-62R0402
8P4R-62R0402
6
8
RN4
RN4
8P4R-51R0402
8P4R-51R0402
RN5
RN5
8P4R-51R0402
8P4R-51R0402
RN8
RN8
8P4R-51R0402
8P4R-51R0402
100
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
INTEL LGA775 - SIGNALS
INTEL LGA775 - SIGNALS
INTEL LGA775 - SIGNALS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7222 20
MS-7222 20
MS-7222 20
of
of
of
531Wednesday, April 05, 2006
531Wednesday, April 05, 2006
531Wednesday, April 05, 2006
1
8
7
6
5
4
3
2
1
VCCP
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
M28
VCC#AK15
VCC#M28
M27
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
VCC#AK8
VCC#AK9
VCC#AL11
VCC#AL12
VCC#AL14
VCC#AL15
VCC#AL18
VCC#AL19
VCC#AL21
VCC#K27
VCC#K28
K27
K28
VCC#K25
VCC#K26
K25
K26
VCC#K24
K23
K24
C75
C75
C1U16Y
C1U16Y
C80
C80
C1U16Y
C1U16Y
VCC#AL22
VCC#AK18
VCC#AK19
VCC#AK21
VCC#AK22
VCC#AK25
VCC#AK26
VCC#K29
VCC#K30
VCC#K8
VCC#L8L8VCC#M23
VCC#M24
VCC#M25
VCC#M26
VCC#M27
K8
K29
K30
M23
M24
M25
M26
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
AL25
AL26
AL29
VCC#AL25
VCC#AL26
VCC#J30
VCC#J8J8VCC#J9J9VCC#K23
J29
J30
AL30
AL8
AL9
VCC#AL8
VCC#AL29
VCC#AL30
VCC#J27
VCC#J28
VCC#J29
J26
J27
J28
AM11
AM12
VCC#AL9
VCC#AM11
VCC#AM12
VCC#J24
VCC#J25
VCC#J26
J24
J25
AM14
AM15
VCC#AM14
VCC#AM15
VCC#J22
VCC#J23
J22
J23
AM18
AM19
VCC#AM18
VCC#AM19
VCC#J20
VCC#J21
J20
J21
AM21
AM22
VCC#AM21
VCC#AM22
VCC#J18
VCC#J19
J18
J19
AM25
VCC#AM25
VCC#J15
J15
AM26
AM29
AM30
AM8
VCC#AM8
VCC#AM26
VCC#AM29
VCC#AM30
VCC#J11
VCC#J12
VCC#J13
VCC#J14
J11
J12
J13
J14
H_VCCIOPLL
H_VSSA
H_VCCA
AM9
AN11
VCC#AM9
VCC#AN11
VCC#AN9
VCC#J10
J10
AN9
AN12
VCC#AN12
VCC#AN8
AN8
AN14
AN15
AN18
AN19
AN21
AN22
VCCPLL
VCC#AN14
VCC#AN15
VCC#AN18
VCC#AN19
VCC#AN21
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
VCC#AN26
VCC#AN29
VCC#AN30
AN25
AN26
AN29
AN30
VCCA
VSSA
VCC#AN22
1122334
4
H_VCCA
A23
H_VSSA
B23
D23
H_VCCIOPLL
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
ZIF-SOCK775_black-RH
ZIF-SOCK775_black-RH
AH8
AF22
AF21
AF9
AF8
U5B
AF19
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AE9
AD8
AC8
AB8
AA8
VCCP
U5B
VCC#AF19
VCC#AF18
VCC#AF22
VCC#AF21
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
VCC#Y30
VCC#Y8
Y8
Y30
R62 49.9R1%0402R62 49.9R1%0402
VCC#AF8
VCC#Y29
Y28
Y29
D D
VCCP
C C
VTT_OUT_RIGHT
B B
AG12
AG11
VCC#AF9
VCC#AG12
VCC#AG11
VCC#Y26
VCC#Y27
VCC#Y28
Y26
Y27
AG19
AG18
AG15
AG14
VCC#AG19
VCC#AG18
VCC#AG15
VCC#AG14
VCC#W8
VCC#Y23
VCC#Y24
VCC#Y25
W8
Y23
Y24
Y25
R63
R63
100R1%0402
100R1%0402
AG21
VCC#AG21
VCC#W30
W30
AG29
AG28
AG27
AG26
AG25
AG22
VCC#AG29
VCC#AG28
VCC#AG27
VCC#AG26
VCC#AG25
VCC#AG22
VCC#W24
VCC#W25
VCC#W26
VCC#W27
VCC#W28
VCC#W29
W24
W25
W26
W27
W28
W29
R64 10R0402R64 10R0402
C54
C54
C1U6.3Y50402/80-20%
C1U6.3Y50402/80-20%
AG30
AG9
AG8
VCC#AG9
VCC#AG8
VCC#AG30
VCC#U8
VCC#V8
VCC#W23
V8
U8
W23
AH14
AH12
AH11
VCC#AH12
VCC#AH11
VCC#U29
VCC#U30
U28
U29
U30
AH19
AH18
AH15
VCC#AH18
VCC#AH15
VCC#AH14
VCC#U26
VCC#U27
VCC#U28
U25
U26
U27
CPU_GTLREF0VTT_OUT_RIGHT
AH25
AH22
AH21
VCC#AH25
VCC#AH22
VCC#AH21
VCC#AH19
VCC#T8T8VCC#U23
VCC#U24
VCC#U25
U23
U24
C53
C53
C220P50N0402
C220P50N0402
AH27
AH26
AH28
VCC#AH27
VCC#AH26
VCC#AH28
VCC#T28
VCC#T29
VCC#T30
T28
T29
T30
AH29
AH30
VCC#AH29
VCC#AH30
VCC#T26
VCC#T27
T25
T26
T27
AH9
VCC#AH8
VCC#AH9
VCC#T24
VCC#T25
T24
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
VCC#AJ11
VCC#AJ12
VCC#AJ14
VCC#AJ15
VCC#AJ18
VCC#AJ19
VCC#AJ21
VCC#AJ22
VCC#N27
VCC#N28
VCC#N29
VCC#N30
VCC#N8
VCC#P8
VCC#R8
VCC#T23
P8
N8
R8
T23
CPU_GTLREF0 [5]
N27
N28
N29
N30
AJ25
AJ26
AJ8
VCC#AJ25
VCC#AJ26
VCC#N25
VCC#N26
N24
N25
N26
AJ9
VCC#AJ8
VCC#AJ9
VCC#AK11
VCC#M8M8VCC#N23
VCC#N24
N23
M30
VCC#AK12
VCC#AK14
VCC#M29
VCC#M30
M29
V_FSB_VTT
V_FSB_VTT
C72 C10U10Y0805C72 C10U10Y0805
CAPS FOR FSB GENERIC
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_OUT_LEFT
PLACE AT CPU END OF ROUTE
VTT_OUT_RIGHT
VTT_OUT_LEFT
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
R43 62R0402R43 62R0402
R42 120R0402R42 120R0402
R57 100R0402R57 100R0402
R66 62R0402R66 62R0402
R51 62R0402R51 62R0402
R58 62R0402R58 62R0402
CPURST#
PROCHOT#
CPU_GD
HBR#0
IERR#
THERMTRIP#
CPURST# [5,8]
PROCHOT# [5]
CPU_GD [5,27]
HBR#0 [5,8]
IERR# [5]
THERMTRIP# [5,29]
PLACE AT SB END OF ROUTE
V_FSB_VTT
8
7
R55 62R0402R55 62R0402
FERR#
6
FERR# [5,19]
5
V_FSB_VTT
VCC5_SB
R67
R67
1KR0402
1KR0402
4
R3 10KR0402R3 10KR0402
RN31
RN31
1
3
5
7
8P4R-470R0402
8P4R-470R0402
VID_GD#[27,28]
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
B
2
4
6
8
R37
R37
680R0402
680R0402
CE
Q1
Q1
N-PMBS3904_SOT23-RH
N-PMBS3904_SOT23-RH
H_BSL1 [5,16]
H_BSL2 [5]
H_BSL0 [5,16]
1.25V VTT_PWRGOOD
VTT_PWG
3
VTT_PWG [16]
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
INTEL LGA775 - POWER
INTEL LGA775 - POWER
INTEL LGA775 - POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7222 20
MS-7222 20
MS-7222 20
of
of
of
631Wednesday, April 05, 2006
631Wednesday, April 05, 2006
631Wednesday, April 05, 2006
1
1
VTT_OUT_RIGHT
VTT_OUT_RIGHT
R46
R46
62R0402
62R0402
A A
TP2TP2
H_COMP7
1
AE3
D1
D14
AE4
U5C
U5C
A12
VSS#A12
A15
VSS#A15
A18
VSS#A18
A2
VSS#A2
A21
VSS#A21
A24
VSS#A24
A6
VSS#A6
A9
VSS#A9
AA23
VSS#AA23
AA24
VSS#AA24
AA25
VSS#AA25
AA26
B B
C C
AA27
AA28
AA29
AA30
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
AA3
AA6
AA7
AB1
AB7
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
AE29
E23
COMP6Y3COMP7
VSS#AE29
VSS#AE30
VSS#AE5
AE5
AE30
AE7
RSVD#AE4
VSS#AE7
RSVD#E5E5RSVD#E6E6RSVD#E7
RSVD#D1
RSVD#E23
RSVD#D14
VSS#AF10
VSS#AF13
VSS#AF16
VSS#AF17
VSS#AF20
AF10
AF13
AF16
AF17
AF20
TP8TP8
AF23
62R0402
62R0402
TP6TP6
1
TP5TP5
1
1
F6
F23
E7
B13
IMPSEL#
RSVD#F23
RSVD#B13
VSS#AF23
VSS#AF24
VSS#AF25
VSS#AF26
VSS#AF27
VSS#AF28
AF24
AF25
AF26
AF27
AF28
2
3
4
5
MSID1 MSID0
VSS#R7R7VSS#R5
VSS#AJ27
0
0
R30
R29
R28
R27
R26
R5
AJ28
R25
VSS#R30
VSS#R29
VSS#R28
VSS#R27
VSS#R26
VSS#AJ28
VSS#AJ29
VSS#AJ30
VSS#AJ4
VSS#AJ7
VSS#AK10
AJ4
AJ7
AJ29
AJ30
AK10
AK13
05 Per FMB
V3
V29
VSS#V3
VSS#V30
VSS#V29
VSS#AH17
VSS#AH20
VSS#AH23
AH20
AH23
05 Value FMB
V28
V27
V26
V25
V24
VSS#V28
VSS#V27
VSS#V26
VSS#V25
VSS#V24
VSS#AH24
VSS#AH3
VSS#AH6
VSS#AH7
VSS#AJ10
AH3
AH6
AH7
AJ10
AH24
V23
T3
U1
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#V23
VSS#AJ13
VSS#AJ16
VSS#AJ17
VSS#AJ20
VSS#AJ23
VSS#AJ24
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
R50
R50
R48
R48
62R0402
62R0402
MSID1
MSID0
H_COMP6
J3
N4
AC4
W1
P5
MSID[1]V1MSID[0]
RSVD#J3
RSVD#P5
RSVD#N4
VSS#AF29
VSS#AF3
VSS#AF30
VSS#AF6
VSS#AF7
AF3
AF6
AF7
AF29
AF30
VSS#Y7Y7VSS#Y5Y5VSS#Y2
RSVD#AC4
VSS#AG10
VSS#AG13
VSS#AG16
VSS#AG17
VSS#AG20
VSS#AG23
AG10
AG13
AG16
AG17
AG20
AG23
AG24
R52
R52
62R0402
62R0402
Y2
V6
V30
W4
VSS#V7V7VSS#V6
VSS#W7W7VSS#W4
VSS#AG24
VSS#AG7
VSS#AH1
VSS#AH10
VSS#AH13
VSS#AH16
AH1
AG7
AH10
AH13
AH16
AH17
0
1
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
R24
R23
P4
P30
P29
P28
P27
P26
P25
P24
R2
VSS#P7P7VSS#P4
VSS#R2
VSS#R25
VSS#AK13
VSS#P30
VSS#R24
VSS#R23
VSS#AK16
VSS#AK17
VSS#AK2
VSS#AK20
VSS#AK23
VSS#AK24
AK2
AK16
AK17
AK20
AK23
AK24
AK27
P23
VSS#P29
VSS#P28
VSS#P27
VSS#P26
VSS#P25
VSS#P24
VSS#P23
VSS#AK27
VSS#AK28
VSS#AK29
VSS#AK30
VSS#AK5
VSS#AK7
VSS#AL10
AK5
AK7
AL10
AL13
AK28
AK29
AK30
VSS#N7N7VSS#N6N6VSS#N3
VSS#AL13
AL16
L6
L3
L30
L29
L28
L27
M1
N3
VSS#L7L7VSS#L6
VSS#M7M7VSS#M1
VSS#AL16
VSS#AL17
VSS#AL20
VSS#AL23
VSS#AL24
AL17
AL20
AL23
AL24
L26
VSS#L3
VSS#L30
VSS#L29
VSS#L28
VSS#L27
VSS#AL27
VSS#AL28
VSS#AL3
VSS#AL7
VSS#AM1
VSS#AM10
AL3
AL7
AM1
AL27
AL28
AM10
AM13
VSS#L26
VSS#AM13
K2
K5
L25
L24
L23
J7
H9
VSS#J4J4VSS#J7
VSS#K2
VSS#K7K7VSS#K5
VSS#L25
VSS#L24
VSS#L23
VSS#AM16
VSS#AM17
VSS#AM20
VSS#AM23
VSS#AM24
VSS#AM27
VSS#AM28
VSS#AM4
AM16
AM17
AM4
AM20
AM23
AM24
AM27
AM28
H28
VSS#H14
VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9
VSS#H25
VSS#H26
VSS#H27
VSS#H28
VSS#AN1
VSS#AN10
VSS#AN13
VSS#AN16
VSS#AN17
VSS#AN2
VSS#AN20
VSS#AN23
VSS#AN24
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
VSS#H13
VSS#H12
VSS#H19
VSS#H20
VSS#H21
VSS#H22
VSS#H23
VSS#H24
VSS#H11
VSS#H10
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E17
VSS#E14
VSS#E11
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B24
VSS#B20
VSS#B17
VSS#AN27
VSS#AN28
VSS#B1B1VSS#B11
VSS#B14
B11
B14
AN27
AN28
H14
H13
H12
VSS#H17
VSS#H18
H11
H10
G1
VSS#G1
F7
VSS#F7
F4
VSS#F4
F22
F19
F16
F13
F10
E8
VSS#E8
E29
E28
E27
E26
E25
E20
E2
VSS#E2
E17
E14
E11
D9
VSS#D9
D6
VSS#D6
D5
VSS#D5
D3
VSS#D3
D24
D21
D18
D15
D12
C7
VSS#C7
C4
VSS#C4
C24
C22
C19
C16
C13
C10
B8
VSS#B8
B5
VSS#B5
B24
B20
B17
ZIF-SOCK775_black-RH
ZIF-SOCK775_black-RH
D D
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
INTEL LGA775 - GND
INTEL LGA775 - GND
INTEL LGA775 - GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7222 20
MS-7222 20
MS-7222 20
731Wednesday, April 05, 2006
731Wednesday, April 05, 2006
731Wednesday, April 05, 2006
5
4
3
2
1
VIA confirmed
V_FSB_VTT
D D
U6A
HA#[3..33][5]
C C
HADSTB#0[5]
HADSTB#1[5]
HADS#[5]
HBNR#[5]
HBPRI#[5]
HBR#0[5,6]
HDBSY#[5]
HDEFER#[5]
HDRDY#[5]
HIT#[5]
HITM#[5]
HLOCK#[5]
HTRDY#[5]
B B
A A
HREQ#[0..4][5]
HRS#[0..2][5]
HDBI#[0..3][5]
CPURST#[5,6]
NBHCLK[16]
NBHCLK#[16]
C101 C0.01U50XC101 C0.01U50X
GTLVREF_NB
GTLVREF_NB1
-HAP0[5]
-HAP1[5]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
HDBI#0
HDBI#1
HDBI#2
HDBI#3
-HAP0
-HAP1
HRCOMP
HCOMPVREF
TP13TP13
4
U6A
Y29
HA3#
V27
HA4#
AA29
HA5#
Y27
HA6#
Y26
HA7#
AC27
HA8#
AA28
HA9#
AB27
HA1#
AA27
HA11#
AC29
HA12#
AB29
HA13#
AB28
HA14#
AC26
HA15#
AD29
HA16#
T28
HA17#
R28
HA18#
N29
HA19#
N28
HA20#
P29
HA21#
P27
HA22#
R27
HA23#
N26
HA24#
T26
HA25#
P26
HA26#
R25
HA27#
N27
HA28#
N25
HA29#
R29
HA30#
T27
HA31#
U26
HA32#
T25
HA33#
W28
HADSTB0#
R26
HADSTB1#
M29
ADS#
M28
ABR#
T29
BPRI#
K26
BREQ0#
M25
DBSY#
U27
DEFER
M26
DRDY#
L27
HIT#
U29
HITM#
L29
HLOCK#
M24
HTRDY#
W27
HREQ0#
V28
HREQ1#
V26
HREQ2#
W29
HREQ3#
V29
HREQ4#
L26
RS0
M27
RS1
K25
RS2
C29
HDBI0#
H27
HDBI1#
B21
HDBI2#
A21
HDBI3#
D14
CPURST#
Y23
HCLK+
W23
HCLK-
R24
HAVREF0
V24
HAVREF1
F22
HDVREF0
G24
HDVREF1
F19
HDVREF2
F16
HDVREF3
L24
GTLVREF
N24
HAP0#
W26
HAP1#
G25
HRCOMP
G26
HCOMPVREF
1
K24
DPWR#
GND
GND
A16
A19
B22
U19
M19
T19
L19
L18
L17
L16
P19
R19
N19
VTT
VTT#T19
VTT#P19
VTT#R19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E29
E26
E25
E22
B25
B28
D15
D16
D19
H26
L15
HD0#
HD1#
HD2#
GND
R18
HDSTB0P#
HDSTB0N#
HDSTB1P#
HDSTB1N#
HDSTB2P#
HDSTB2N#
HDSTB3P#
HDSTB3N#
GND
GND
V18
U18
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
GND
GND
VIA-P4M800Pro-CD
VIA-P4M800Pro-CD
T18
AC28
VTT#L19
VTT#L18
VTT#L17
VTT#L16
H29
VTT#L15
VTT#M19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L25
L28
P25
P28
Y25
Y28
P18
U28
U25
N18
M18
3
VTT#N19
GND
D27
D26
A29
C26
C28
D28
A27
B29
A26
B26
D25
E24
A25
A28
D24
C25
K28
K29
J28
K27
J26
J29
J25
J27
F28
G29
G27
D29
E27
F27
E28
F29
E23
B24
C24
A24
A23
B23
A22
C23
F21
C22
E21
C21
D20
D21
F20
E20
B19
C19
B20
B18
C20
A20
C18
B17
B16
A17
C14
C15
A18
B15
B14
A15
B27
C27
H28
G28
D23
D22
C17
C16
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HDSTBP#0 [5]
HDSTBN#0 [5]
HDSTBP#1 [5]
HDSTBN#1 [5]
HDSTBP#2 [5]
HDSTBN#2 [5]
HDSTBP#3 [5]
HDSTBN#3 [5]
HD#[0..63] [5]
V_FSB_VTT
near NB
C0.01U50X
C0.01U50X
C106
C106
2
V_FSB_VTT
Component Side
CP18
CP18
X_CP
X_CP
C281
C281
C0.01U50X/B
C0.01U50X/B
V_FSB_VTT
CB62
CB62
C10U10Y0805
C10U10Y0805
CB63
CB63
C10U10Y0805
C10U10Y0805
CB38
CB38
X_C0.1U25Y
X_C0.1U25Y
CB59
CB59
C1U16Y
C1U16Y
CB64
CB64
C1U16Y
C1U16Y
R181 49.9R1%0402R181 49.9R1%0402
R108 49.9R1%0402R108 49.9R1%0402
R101 100R1%0402R101 100R1%0402
R90 20.5R1%0402R90 20.5R1%0402
GTLVREF_NB
C282
C282
C0.01U50X/B
C0.01U50X/B
Solder Side
CB130
CB130
C1U16Y/B
C1U16Y/B
CB131
CB131
C1U16Y/B
C1U16Y/B
CB133
CB133
C1U16Y/B
C1U16Y/B
GTLVREF_NB1
R185
R185
100R1%0402
100R1%0402
GTLVREF_NB
R109
R109
100R1%0402
100R1%0402
HCOMPVREF
R105
R105
49.9R1%0402
49.9R1%0402
HRCOMP
near NB
C0.01U50X
C0.01U50X
Title
Title
Title
P4M800 Pro-CPU
P4M800 Pro-CPU
P4M800 Pro-CPU
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MS-7222 20
MS-7222 20
MS-7222 20
GTLVREF_NB [5]
GTLVREF_NB1
C99
C99
C285
C285
X_C0.01U50X/B
X_C0.01U50X/B
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
C287
C287
C0.01U50X/B
C0.01U50X/B
831Thursday, April 06, 2006
831Thursday, April 06, 2006
831Thursday, April 06, 2006
of
of
1
of
BY PASS CAP
4
VCC_DDR
3
2
VCC_DDR
1
V11
W12
W13
W14
U6B
AD28
AE27
AF27
AG28
AD27
AE29
AG27
AG29
AH29
AJ29
AG25
AJ25
AJ28
AH27
AH26
AJ26
AJ24
AG24
AJ22
AG21
AH24
AG23
AG22
AJ21
AH21
AJ20
AG18
AH18
AG20
AH19
AJ18
AG17
AJ12
AG12
AJ10
AH12
AJ11
AG10
AH9
AG8
AH6
AG9
AG5
AH4
AH1
AG4
AF4
AG3
AG1
AF2
AD3
AD1
AG2
AF3
AE1
AD2
AF21
AF23
AE22
AF24
AF28
AJ27
AJ23
AJ19
AG11
AH7
AF1
U6B
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
AJ9
MD35
MD36
MD37
MD38
MD39
MD40
AJ7
MD41
AJ6
MD42
MD43
MD44
AJ8
MD45
MD46
AJ5
MD47
MD48
AJ4
MD49
AJ2
MD50
MD51
MD52
MD53
MD54
AJ1
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
CKE0
CKE1
CKE2
CKE3
DQM0#
DQM1#
DQM2#
DQM3#
DQM4#
DQM5#
AJ3
DQM6#
DQM7#
-DQM0
-DQM1
-DQM2
-DQM3
-DQM4
-DQM5
-DQM6
-DQM7
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
CKEA0
CKEA1
CKEA2
CKEA3
D D
C C
B B
MD[0:63][12]
CKEA0[12,13]
CKEA1[12,13]
CKEA2[12,13]
CKEA3[12,13]
-DQM0[12]
-DQM1[12]
-DQM2[12]
-DQM3[12]
-DQM4[12]
-DQM5[12]
-DQM6[12]
-DQM7[12]
W11
VCC18MEM
VCC18MEM#V11
VCC18MEM#W13
VCC18MEM#W11
V19
W15
W16
W17
W18
W19
VCC18MEM#W14
VCC18MEM#W15
VCC18MEM#W16
VCC18MEM#W17
VCC18MEM#W18
VCC18MEM#W19
VCC18MEM#V19
MA10
MA11
MA12
MA13
DMCOMP
MEMDET
ODT0
ODT1
ODT2
ODT3
SRAS#
SCAS#
SWE#
CS0#
CS1#
CS2#
CS3#
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
MCLKIA
MCLKO-
MCLKO+
MEMVREF1
MEMVREF2
MEMVREF3
MEMVREF4
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
BA0
BA1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF13
AD15
AJ15
AJ16
AJ17
AF16
AG15
AE18
AF17
AE19
AJ14
AF20
AE21
AD7
AF12
AJ13
AE5
AE24
AE9
AE10
AF6
AD6
AE12
AF9
AF11
AD9
AF8
AG7
AF7
AF29
AG26
AH22
AG19
AH10
AG6
AH3
AE3
AD26
AE26
AF26
AD23
AD17
AD11
AD8
M16
N16
P16
R16
T16
U16
V16
M15
N15
P15
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MEMDET
-CS0
-CS1
-CS2
-CS3
-DQS0
-DQS1
-DQS2
-DQS3
-DQS4
-DQS5
-DQS6
-DQS7
DCLKI
MCLKO-
MCLKO+
BA0 [12,13]
BA1 [12,13]
R139 301R1%0402R139 301R1%0402
ODT0 [12,13]
ODT1 [12,13]
ODT2 [12,13]
ODT3 [12,13]
-SRASA [12,13]
-SCASA [12,13]
-SWEA [12,13]
-CS0 [12,13]
-CS1 [12,13]
-CS2 [12,13]
-CS3 [12,13]
-DQS0 [12]
-DQS1 [12]
-DQS2 [12]
-DQS3 [12]
-DQS4 [12]
-DQS5 [12]
-DQS6 [12]
-DQS7 [12]
R146 0R0402R146 0R0402
DCLKO as short as passable
DCLKI = DCLKx + 2 "
MVREF_NB
MAA[0:13] [12,13]
DCLKI [16]
DCLKO+ [16]
100R1%0402
100R1%0402
100R1%0402
100R1%0402
VCC_DDR
R131
R131
R132
R132
CB48
CB48
C10U10Y0805
C10U10Y0805
CB67
CB67
X_C1U16Y
X_C1U16Y
C172
C172
X_C10U10Y0805
X_C10U10Y0805
Component Side
MVREF_NB = 0.5* VCCDDR
MVREF_NB
C286
VCC_DDR
C286
C1000P50X/B
C1000P50X/B
Solder Side
C290
C290
C1000P50X/B
C1000P50X/B
VCC_DDR
R86 1KR1%0402R86 1KR1%0402
MCLKO-
R89 10KR0402R89 10KR0402
Near to NB chip
C280 X_C5P50N/BC280 X_C5P50N/B
DCLKI
Near to NB chip
C292
C292
C0.01U50X/B
C0.01U50X/B
CB132
CB132
C10U10Y0805/B
C10U10Y0805/B
CB135
CB135
C10U10Y0805/B
C10U10Y0805/B
CB139
CB139
C0.1U25Y/B
C0.1U25Y/B
CB129
CB129
C1U16Y/B
C1U16Y/B
CB141
CB141
X_C1U16Y/B
X_C1U16Y/B
CB137
CB137
X_C1U16Y/B
X_C1U16Y/B
CB134
CB134
C1U16Y/B
C1U16Y/B
CB127
CB127
X_C10U10Y0805/B
X_C10U10Y0805/B
CB145
CB145
X_C1U16Y/B
X_C1U16Y/B
MEMDET
HEATSINK1
HEATSINK1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE2
GND
AE8
AE11
AE14
AE16
AE17
AE20
AE23
AE25
AE28
AH2
AH5
AH8
AH11
AH14
AH17
A A
4
GND
AH20
GND
AH23
GND
AH25
GND
AH28
AF5
GND
GND
GND
GND
GND
GND
N17
P17
R17
GND
GND
GND
GND
GND
VIA-P4M800Pro-CD
U17
V17
VIA-P4M800Pro-CD
T15
V15
U15
R15
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
P4M800 Pro-DDRII
P4M800 Pro-DDRII
P4M800 Pro-DDRII
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7222 20
MS-7222 20
MS-7222 20
T17
HS-MS7059
HS-MS7059
931Wednesday, April 05, 2006
931Wednesday, April 05, 2006
931Wednesday, April 05, 2006
of
of
1
of
GND
M17
3
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