MSI MS-7210 Schematics 200

1

COVER SHEET BLOCK DIAGRAM GPIO & JUMPER SETTING Intel LGA775-CPU Intel Lakeport -GMCH ICH7/ICH7R DDR II DIMM 1and DIMM2 1 & 2 & 3 & 4 Clock Generator - ICS954129 PCI EXPRESS X16 & X 4 SLOT VGA CONNECTOR

1 2

3 4-6 7-10

11-13 14-16

17 18 19

MS-7210

CPU:

Intel Prescott ( L2=2MB ) - 3.8G Intel Cendar Mill (65nm) - 3.73G & Above Intel Smithfield (90nm Dual core) - 3.2G

System Chipset:

Intel Lakeport - GMCH (North Bridge) Intel ICH7/ICH7R (South Bridge)

On Board Chipset:

Version 2.0

20PCI Slot 1 & 2

LAN-Tekoa(82573E)/EKronR(82562GZ)

VIA VT-6307/6308P Azalia CODEC(ALC880) SIO-W83627EHF & KB/MS

A A

USB CONNECTORS IDE & SATA& COM1& COM2& LPT FWH & FAN ATX & Front Panel MS7 ACPI Controller VRM10.1 Intersil 6316 4Phase EMI Cap Auto BOM manual PWOK MAP History

21 22 23 24 25 26 27 28 29 30 31 32 33 34

Main Memory:

Expansion Slots:

Intersil PWM:

BIOS -- FWH FLASH 4Mb Azalia CODEC(ALC 880) LPC Super I/O -- W83627EHF LAN-Tekoa(82573E)/EKronR(82562GZ) 1394 -- VIA VT-6307/6308P Clock Generator - ICS954129

DDR II * 4 (Max 4GB)

PCI Express X16 SLOT * 1 PCI Express X4 SLOT * 1

PCI 2.3 SLOT * 2

Controller:

Intersil 6316CR 4 Phase

Driver:Intersil 6614ACB

PDF created with pdfFactory trial version www.pdffactory.com

MSI

Title

Size Document Number Rev

Date: Sheet of

1

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

COVER SHEET

MS-7210_051124K1

1 34Thursday, November 24, 2005

2.0

1

VRM_GD

VTT_PWG

PLTRST#2

HD_RST#

VRM 10.1

Intersil 6316CR

4-Phase PWM

PCI EXPRESS X16

Connector

Analog Video Out

IDE Primary

P.30

P.18

P.19

P.26

UltraDMA 33/66/100

Intel LGA775 Processor

FSB

H_PWRGD

H_CPURST#

Lakeport GMCH

P.7~10

DMI

VRM_GD

PLRST#

P.3~5

DDRII

333/400/533 MHz

PWR_GD

Block Diagram

PWR_GD

4 DDR II DIMM Modules

PCIRST#

MS7

VID_GD

RSMRST#

HD_RST#

PLTRST#_MS7

LPC Bus

P.27

SLP_S4#

SLP_S3#

PSON#

LPC SIO W83627EHF

Keyboard

Mouse

PLTRST#1

P.24

PCI

PWR_OK

ATX1

P.24

Floopy Parallel Serial

P.24 P.26 P.26

PCI Slot 1

P.20 P.20

PCI Slot 2

SERIAL ATA1

SERIAL ATA2

A A

SERIAL ATA3

SERIAL ATA4

USB2.0

P.26

ICH7

P.11~13

USB

USB Port0~ 7

P.25

RSMRST#

PWRBTN#

ALC880

PCIRST#_LAN

PCIRST#_1394

Azalia Codec

LAN INTEL

82573E/82562GZ

1394 VIA VT-

6307/6308P

P.23

P.21

P.22

PCI

FWH

FP_RST#PWRBTIN

LAN-Tekoa(82573E)/EKronR(82562GZ)

JFP1

PDF created with pdfFactory trial version www.pdffactory.com

P.28

PLTRST#1

1

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

BLOCK DIAGRAM

MS-7210_051124K1

2 34Thursday, November 24, 2005

2.0

8

7

6

5

4

3

2

1

ICH7

GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name

GPIO[0] BM_BUSY# AB18 I/O Vcc3p3 N Y 5 Input strapped hi GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5 GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G

D D

GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H GPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0 GPIO[7] unmuxed AC18 I/O Vcc3p3 N Y 3.3 Input strapped hi GPIO[8] unmuxed E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME# GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input WOL# GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input BIOS_WP# GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT# GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input strapped hi GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input strapped hi GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input strapped hi GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input strapped hi GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input strapped hi

C C

GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 FANTYP_DET GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input strapped hi GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4 GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input NC GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change NC GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 NC GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 NC GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2 GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2 GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#3 GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 1 NC GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 NC GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC

B B

GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input strapped hi GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input strapped hi GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input strapped hi GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input strapped hi GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A PGNT#4 GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD

Following are the GPIOs that need to be terminated properly if not used: GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused. GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.

FWH

GPIO Pin# Power Tol Signal Name

FPGI[0] 6 Main 3.3 pull-up FPGI[1] 5 Main 3.3 pull-up FPGI[2] 4 Main 3.3 pull-up FPGI[3] 3 Main 3.3 pull-up FPGI[4] 30 Main 3.3 pull-down

PCI Config.

Note: FWH GPs should only be used for static options, do not put dynamic nets on these

DEVICE

PCI SLOT 1

PCI SLOT 2

PCI LAN

MCP1 INT Pin

PIRQ#A PIRQ#B PIRQ#C PIRQ#D

PIRQ#B PIRQ#C PIRQ#D PIRQ#A

PIRQ#E

PCI 1394 PIRQ#F

REQ#/GNT#

PREQ#0 PGNT#0

PREQ#1 PGNT#1

PREQ#3 PGNT#3

PREQ#4 PGNT#4

IDSEL

AD16

AD19

AD20

CLOCK

PCI_CLK0

PCI_CLK1AD17

LAN_PCLK

1394_PCLK

DDRII DIMM Config.

DEVICE ADDRESS

DIMM 1

DIMM 2

A0H

A2H

A4H

DIMM 2

A6H

CLOCK

MCLK_A0/MCLK_A#0 MCLK_A1/MCLK_A#1 MCLK_A2/MCLK_A#2 MCLK_A3/MCLK_A#3 MCLK_A4/MCLK_A#4 MCLK_A5/MCLK_A#5 MCLK_B0/MCLK_B#0 MCLK_B1/MCLK_B#1DIMM 3 MCLK_B2/MCLK_B#2 MCLK_B3/MCLK_B#3 MCLK_B4/MCLK_B#4 MCLK_B5/MCLK_B#5

JUMPER SETTING

JBAT1

JCI1

(1-2)NORMAL

Chassis Intrision

Open

Normal Chassis Open(1-2)

(2-3)CLEAR

A A

MSI

MICRO-STAR INt'L CO., LTD.

Title

Size Document Number Rev

Date: Sheet of

8

7

6

5

4

3

Date: Sheet of

2

MICRO-STAR INt'L CO., LTD.

GPIO MAP

GPIO MAP MS-7210_051124K1 2.0

MS-7210_051124K1 2.0

3 34Thursday, November 24, 2005

1

PDF created with pdfFactory trial version www.pdffactory.com

8

7

6

5

4

3

2

1

CPU SIGNAL BLOCK

VCC_VRM_SENSE VSS_VRM_SENSE

D D

H_INIT#11

H_LOCK#7 H_HIT#7

H_BPRI#7

H_A20M#11

R12 X_62R0402R12 X_62R0402

H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3

H_IERR#

H_TDI H_TDO H_TMS H_TRST# H_TCK

H_TESTHI13

H_D#63 H_D#62 H_D#61 H_D#60 H_D#59 H_D#58 H_D#57 H_D#56 H_D#55 H_D#54

H_DBI#[0..3]7

H_FERR#11

H_STPCLK#11

H_DBSY#7

H_DRDY#7

H_TRDY#7

C C

H_SLP#11

B B

A A

H_ADS#7

H_BNR#7 H_HITM#7 H_DEFER#7

THERMDA_CPU24

VTIN_GND24

TRMTRIP#11

H_PROCHOT#30

H_IGNNE#11

ICH_H_SMI#11

R8

x_0/4R8x_0/4

H_FSBSEL09,17 H_FSBSEL19,17 H_FSBSEL29,17

H_PWRGD11

H_CPURST#7

H_D#[0..63]7

G11 D19 C20

AB2 AB3

AD3

AD1 AF1 AC1 AG1 AE1 AL1 AK1

AE8 AL2

AH2 AE6 G10

D16 A20

AA2 G29

H30 G30

G23 B22

A22 A19 B19 B21 C21 B18 A17 B16 C18

A8

F2

R3

M3

P3 H4

B2 C1 E3

D2 C3 C2 D4 E4 G8 G7

M2

N2 P2 K3 L2

N5 C9

Y1 V2

N1

H_A#[3..31]7

U3A

DBI0# DBI1# DBI2# DBI3#

EDRDY# IERR# MCERR# FERR#/PBE# STPCLK# BINIT# INIT# RSP#

DBSY# DRDY# TRDY#

ADS# LOCK# BNR# HIT# HITM# BPRI# DEFER#

TDI TDO TMS TRST# TCK THERMDA THERMDC THERMTRIP# GND/SKTOCC# PROCHOT# IGNNE# SMI# A20M# TESTI_13

RSVD#AH2 RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5

BOOTSELECT LL_ID0 LL_ID1

BSEL0 BSEL1 BSEL2

PWRGOOD RESET# D63#

D62# D61# D60# D59# D58# D57# D56# D55# D54#

B15

H_D#53

VID3

VID0

VID 2

VID1

AL6

AM3

AL5

AM2

VID3#

VID2#

VID1#

VID0#

GTLREF0 GTLREF1

GTLREF2

BPM5# BPM4# BPM3# BPM2# BPM1# BPM0#

PCREQ#

REQ4# REQ3# REQ2# REQ1# REQ0#

TESTHI12 TESTHI11 TESTHI10

TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1

TESTHI0 FORCEPH RSVD#G6

BCLK1# BCLK0#

RS2# RS1# RS0#

AP1# AP0#

BR0# COMP5 COMP4 COMP3 COMP2 COMP1 COMP0

DP3#

DP2#

DP1#

DP0#

ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0#

LINT1/NMI

LINT0/INTR

B4

ZIF-SOCK775-15u-in

H_D#0

VID[0..5] 24,30

VID_SELECT

AN7 H1 H2

TP_GTLREF_SEL

H29

MCH_GTLREF_CPU

E24

H_BPM#5

AG3

H_BPM#4

AF2

H_BPM#3

AG2

H_BPM#2

AD2

H_BPM#1

AJ1

H_BPM#0

AJ2 G5

H_REQ#4

J6

H_REQ#3

K6

H_REQ#2

M6

H_REQ#1

J5

H_REQ#0

K4

H_TESTHI12

W2

H_TESTHI11 MSID1MSID1

P1

H_TESTHI10

H5

H_TESTHI9

G4

H_TESTHI8

G3 F24 G24 G26 G27 G25

H_TESTHI2_7

F25

H_TESTHI1

W3

H_TESTHI0

F26

H_FORCEPH

AK6 G6

G28 F28

H_RS#2

A3

H_RS#1

F5

H_RS#0

B3

TP3TP3

U3

1

TP4TP4

1

U2 F3

H_COMP5 H_COMP4 H_COMP3 H_COMP2 H_COMP1 H_COMP0

1 1 1 1

R9 60.4/4/1R9 60.4/4/1 R11 60.4/4/1R11 60.4/4/1 R10 60.4/4/1R10 60.4/4/1 R14 60.4/4/1R14 60.4/4/1 R13 60.4R1%0402R13 60.4R1%0402 R15 60.4R1%0402R15 60.4R1%0402

TP5TP5 TP6TP6 TP7TP7 TP8TP8

T2 J2 R1 G2 T1 A13

J17 H16 H15 J16

AD5 R6 C17 G19 E12 B9 A16 G20 G12 C8 L1 K1

CPU_GTLREF0 5

TP2TP2

1

MCH_GTLREF_CPU 7

H_REQ#[0..4] 7

RN2 8P4R-62R0402RN2 8P4R-62R0402

H_BR#0

H_TESTHI1

1

2

3

4

5

6

7

8

R7 130/4/1R7 130/4/1

H_FORCEPH 30

CK_H_CPU# 17 CK_H_CPU 17

H_RS#[0..2] 7

H_BR#0

H_ADSTB#1 7 H_ADSTB#0 7 H_DSTBP#3 7 H_DSTBP#2 7 H_DSTBP#1 7 H_DSTBP#0 7 H_DSTBN#3 7 H_DSTBN#2 7 H_DSTBN#1 7 H_DSTBN#0 7

RN3 8P4R-62R0402RN3 8P4R-62R0402

RN72 8P4R-62R0402RN72 8P4R-62R0402

H_NMI 11 H_INTR 11

TP1TP1

1

VID4

AJ3

AK3

ITP_CLK1

ITP_CLK0

VSS_MB_REGULA TION

D9#

D8#

D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#

A10

H_D#8

H_D#7

H_D#5

H_D#6

AM7

RSVD#AM7

H_D#4

VID 5

AM5

AL4

VID6#

VID5#

H_D#2

H_D#3

AK4

VID4#

VID_SELECT

GTLREF_SEL

H_D#1

H_A#3

H_A#6

H_A#8

H_A#10

H_A#5

H_A#7

H_A#28

H_A#24

H_A#26

H_A#29

H_A#30

H_A #2 7

H_A#25

H_A#31

AJ6

AJ5

AH5

AH4

AG5

AG4

AG6

AF4

AF5

AB4

AC5

AB5

A35#

A34#

A33#

A32#

A31#

A30#

A29#

A28#

A27#

A26#

A25#

H_A#17

H_A#15

H_A#14

H_A#18

H_A#19

H_A#23

H_A#20

H_A#22

H_A#21

AA5

AD6

AA4

A24#

A23#

A22#

A21#

A20#Y4A19#Y6A18#W6A17#

H_A#16

AB6

A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#

H_A#11

H_A#12

H_A#13

H_A#9

U6

A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#

H_A#4

L5

AC2

AN3

AN4

AN5

AN6

DBR#

VCC_SENSE

VSS_SENSE

VCC_M B _REGULATION

D53#

D52#

D51#

D50#

D49#

D48#

D47#

D46#

D45#

D44#

D43#

D42#

D41#

D40#

D39#

D38#

D37#

D36#

D35#

D34#

D33#

D32#

D31#

D30#

D29#

D28#

D27#

D26#

D25#

D24#

D23#

D22#

D21#

D20#D7D19#E9D18#F9D17#F8D16#G9D15#

D14#

D13#

D12#D8D11#

D10#

F21

F20

F18

C14

C15

A14

D17

D20

D22

E22

G22

G21

H_D#45

H_D#49

H_D#46

H_D#50

H_D#51

H_D#47

H_D#52

H_D#44

H_D#48

F17

E21

E19

E18

H_D#38

H_D#39

H_D#40

H_D#43

H_D#41

H_D#42

H_D#37

F15

F14

F12

E16

E15

G17

G18

G16

G15

H_D#30

H_D#32

H_D#36

H_D#33

H_D#31

H_D#34

H_D#35

F11

E13

D13

D10

E10

D11

C12

B12

C11

B10

G14

G13

H_D#23

H_D#17

H_D#19

H_D#20

H_D#21

H_D#22

H_D#25

H_D#24

H_D#26

H_D#27

H_D#29

H_D#28

H_D#18

H_D#16

A11

H_D#9

H_D#12

H_D#15

H_D#13

H_D#10

H_D#11

H_D#14

1 3 5 7 1 3 5 7

2 4 6 8 2 4 6 8

V_FSB_VTT

VTT_OUT_LEFT

VCC_VRM_SENSE 30 VSS_VRM_SENSE 30

VTT_OUT_LEFT

VTT_OUT_LEFT 5

H_BR#0 7 VTT_OUT_LEFT 5

C5

x_0.1u/4/YC5x_0.1u/4/Y

VTT_OUT_RIGHT5,6

MSID1 6

VTT_OUT_LEFT

V_FSB_VTT

BSEL

1

02

FSB FREQUENCY

TABLE

267 MHZ (1067)000

0

01 200 MHZ (800) 1

00 133 MHZ (533)

Prescott / Cedar Mill LL_ID[1:0] = 00 GTLREF_SEL = 0 VTT_SEL = 1

RN1 8P4R-680RRN1 8P4R-680R

VID1

1

VID2 VID3 VID4 VID0 VID5

C2

C1

0.1u/4/YC10.1u/4/Y

x_0.1u/4/YC2x_0.1u/4/Y

VTT_OUT_RIGHT

C3 0.1u/4/YC3 0.1u/4/Y C4 x_0.1u/4/YC4 x_0.1u/4/Y

PLACE BPM TERMINATION NEAR CPU

PLACE AT CPU END OF ROUTE

R16 130/4/1R16 130/4/1

1

2

3

4

5

6

7

8

RN73 8P4R-62R0402RN73 8P4R-62R0402

FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS AND CEDAR MILL ARE SUPPORTED

RN7

1

2

3

4

5

6

7

8

8P4R-470R0402

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

RN75 8P4R-680RRN75 8P4R-680R

RN4 8P4R-62R0402RN4 8P4R-62R0402

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

RN5 8P4R-62R0402RN5 8P4R-62R0402

1

2

3

4

5

6

7

8

RN6 8P4R-62R0402RN6 8P4R-62R0402

H_PROCHOT#VTT_OUT_RIGHT

H_CPURST# H_TESTHI13 MSID0 VID_SELECT

H_FSBSEL1 H_FSBSEL0 H_FSBSEL2

H_CPURST# 7VTT_OUT_LEFT5 MSID0 6

H_FSBSEL1 9,17 H_FSBSEL0 9,17 H_FSBSEL2 9,17

VTT_OUT_RIGHT

H_BPM#3 H_BPM#5 H_BPM#1 H_BPM#0 H_TMS H_TDI H_BPM#2 H_BPM#4

H_TRST# H_IERR#

H_TCK

H_PROCHOT# 30

PDF created with pdfFactory trial version www.pdffactory.com

8

7

6

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel LGA775 - Signals

MS-7210_051124K1

2

2.0

4 34Thursday, November 24, 2005

1

2.0

8

VCCP

AG21

AG19

AG18

AG15

AG14

AG12

AG11

AF9

AF8

AF22

AF21

AF19 AF18 AF15 AF14 AF12 AF11

AE9 AE23 AE22 AE21 AE19 AE18 AE15 AE14 AE12 AE11

AD8 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23

AC8 AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23

AB8

AA8

U3BU3B

VCCP

VCC#AF19 VCC#AF18 VCC#AF15 VCC#AF14 VCC#AF12 VCC#AF11 VCC#AE9 VCC#AE23 VCC#AE22 VCC#AE21 VCC#AE19 VCC#AE18 VCC#AE15 VCC#AE14 VCC#AE12 VCC#AE11 VCC#AD8 VCC#AD30 VCC#AD29 VCC#AD28 VCC#AD27 VCC#AD26 VCC#AD25 VCC#AD24 VCC#AD23 VCC#AC8 VCC#AC30 VCC#AC29 VCC#AC28 VCC#AC27 VCC#AC26 VCC#AC25 VCC#AC24 VCC#AC23 VCC#AB8 VCC#AA8

VCC#AF9

VCC#AF8

VCC#AF22

VCC#AF21

VCC#Y28

VCC#Y29

VCC#Y30

VCC#Y8

Y8

Y28

Y29

Y30

VCC#AG21

VCC#AG19

VCC#AG18

VCC#AG15

VCC#AG14

VCC#AG12

VCC#AG11

VCC#W30

VCC#W8W8VCC#Y23

VCC#Y24

VCC#Y25

VCC#Y26

VCC#Y27

Y23

Y24

Y25

Y26

Y27

W30

VCCP

D D

C C

7

AH27

AH26

AH25

AH22

AH21

AH19

AH18

AH15

AH14

AH12

AH11

AG9

AG8

AG30

AG29

AG28

AG27

AG26

AG25

AG22

VCC#AG9

VCC#AG8

VCC#AH15

VCC#AH14

VCC#AH12

VCC#AH11

VCC#AG30

VCC#AG29

VCC#AG28

VCC#AG27

VCC#AG26

VCC#AG25

VCC#AG22

VCC#U27

VCC#U28

VCC#U29

VCC#U30

VCC#U8U8VCC#V8V8VCC#W23

VCC#W24

VCC#W25

VCC#W26

VCC#W27

VCC#W28

VCC#W29

U26

U27

U28

U29

U30

W23

W24

W25

W26

W27

W28

W29

AH28

AH29

VCC#AH27

VCC#AH26

VCC#AH25

VCC#AH22

VCC#AH21

VCC#AH19

VCC#AH18

VCC#U26

VCC#AH28

VCC#AH29

VCC#T27

VCC#T28

VCC#T29

VCC#T30

VCC#T8T8VCC#U23

VCC#U24

VCC#U25

T27

T28

T29

T30

U23

U24

U25

6

AH30

AH8

AH9

AJ11

AJ12

AJ14

AJ15

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

AJ9

AK11

AK12

AK14

AK15

AK18

AK19

AK21

AK22

VCC#AJ8

VCC#AH8

VCC#AH9

VCC#AJ11

VCC#AJ12

VCC#AJ14

VCC#AJ15

VCC#AH30

VCC#T26

T26

VCC#AJ18

VCC#N30

VCC#N8N8VCC#P8P8VCC#R8R8VCC#T23

VCC#T24

VCC#T25

T23

T24

T25

N30

VCC#AJ9

VCC#AJ19

VCC#AJ21

VCC#AJ22

VCC#AJ25

VCC#AJ26

VCC#AK11

VCC#AK12

VCC#AK14

VCC#AK15

VCC#AK18

VCC#AK19

VCC#AK21

VCC#M25

VCC#M26

VCC#M27

VCC#M28

VCC#M29

VCC#M30

VCC#M8M8VCC#N23

VCC#N24

VCC#N25

VCC#N26

VCC#N27

VCC#N28

VCC#N29

N23

N24

N25

N26

N27

N28

N29

M24

M25

M26

M27

M28

M29

M30

5

AK25

AK26

AK8

AK9

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AL30

AL8

AL9

AM11

AM12

AM14

AM15

VCC#AL8

VCC#AK8

VCC#AK9

VCC#AL11

VCC#AL12

VCC#AL14

VCC#AL15

VCC#AL18

VCC#AL19

VCC#AK22

VCC#AK25

VCC#AK26

VCC#K30

VCC#K8K8VCC#L8L8VCC#M23

VCC#M24

K30

M23

VCC#AL21

VCC#K24

VCC#K25

VCC#K26

VCC#K27

VCC#K28

VCC#K29

K23

K24

K25

K26

K27

K28

K29

VCC#AL9

VCC#AL22

VCC#AL25

VCC#AL26

VCC#AL29

VCC#AL30

VCC#AM11

VCC#AM12

VCC#AM14

VCC#J23

VCC#J24

VCC#J25

VCC#J26

VCC#J27

VCC#J28

VCC#J29

VCC#J30

VCC#J8J8VCC#J9J9VCC#K23

J22

J23

J24

J25

J26

J27

J28

J29

J30

4

AM18

AM19

AM21

AM22

AM25

AM26

AM29

AM30

AM8

AM9

AN11

AN12

AN14

AN15

AN18

AN19

AN21

AN22

VCCA

VCC#AN15

VCC#AN18

VCC#AN19

VCC#AN21

VTTPWRGD

VTT_OUT_RIGHT

VTT_OUT_LEFT

VCC#AN25

VCC#AN26

VCC#AN29

AN25

AN26

AN29

VSSA

VCC#AN22

VCCPLL

VCC-IOPLL

VTT#A25 VTT#A26 VTT#A27 VTT#A28 VTT#A29 VTT#A30 VTT#B25 VTT#B26 VTT#B27 VTT#B28 VTT#B29 VTT#B30 VTT#C25 VTT#C26 VTT#C27 VTT#C28 VTT#C29 VTT#C30 VTT#D25 VTT#D26 VTT#D27 VTT#D28 VTT#D29 VTT#D30

VTT_SEL

RSVD#F29

1122334

4

VCC#AM8

VCC#AM9

VCC#AN11

VCC#AN12

VCC#AM15

VCC#AM18

VCC#AM19

VCC#AM21

VCC#AM22

VCC#AM25

VCC#AM26

VCC#J14

VCC#J15

VCC#J18

VCC#J19

VCC#J20

VCC#J21

VCC#J22

J14

J15

J18

J19

J20

J21

VCC#AN14

VCC#AM29

VCC#AM30

VCC#AN30

VCC#AN8

VCC#AN9

VCC#J10

VCC#J11

VCC#J12

VCC#J13

J10

J11

J12

J13

AN8

AN9

AN30

A23 B23 D23 C23

A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 AM6

AA1 J1 F27

F29

3

H_VCCA H_VSSA

H_VCCA

VTT_PWG VTT_OUT_RIGHT

VTT_OUT_LEFT

1

TP9TP9

V_FSB_VTT

VTT_OUT_RIGHT 4,6 VTT_OUT_LEFT 4

2

V_FSB_VTT

C6 10u/8/YC610u/8/Y C7 10u/8/YC710u/8/Y C8 10u/8/YC810u/8/Y

CAPS FOR FSB GENERIC

1

R19

C9 1u/6/YC91u/6/Y

R21

680R0402

R19

10R0402

7

Q1

2N3904Q12N3904

VTT_PWG

C10

0.1u/4/Y

C14

C14 x_1u/6/Y

x_1u/6/Y

CPU_GTLREF0 4

6

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS

V_FSB_VTT

C13

C13 10u/8/Y

10u/8/Y

H_VCCA

H_VSSA

VTT_PWG SPEC : High > 0.9V Low < 0.3V Trise < 150ns

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel LGA775 - Power

MS-7210_051124K1

2

5 34Thursday, November 24, 2005

1

2.0

L1 X_10U125m_0805-1L1 X_10U125m_0805-1

CP1

1 2

X_COPPER

5

4

C11

C11 1u/6/Y

1u/6/Y

C12

C12 10u/8/Y

10u/8/Y

3

R18

VTT_OUT_RIGHT

GTLREF VOLTAGE SHOULD BE

0.63*VTT = 0.756V

B B

A A

PDF created with pdfFactory trial version www.pdffactory.com

R18

115/4/1%

VID_GD#29,30

8

R20

R20 210R1%0402

210R1%0402

VTT_OUT_LEFT

VCC5_SB

R22

R22 1KR0402

1KR0402

R23 4.7KR0402R23 4.7KR0402

8

7

6

5

4

3

2

1

MSID04 MSID14

VTT_OUT_RIGHT4,5

R25

R24

60.4R1%0402

U3C

VSS#A12 VSS#A15 VSS#A18 VSS#A2 VSS#A21 VSS#A24 VSS#A6 VSS#A9 VSS#AA23 VSS#AA24 VSS#AA25 VSS#AA26 VSS#AA27 VSS#AA28 VSS#AA29 VSS#AA3 VSS#AA30 VSS#AA6 VSS#AA7 VSS#AB1 VSS#AB23 VSS#AB24 VSS#AB25 VSS#AB26 VSS#AB27 VSS#AB28 VSS#AB29 VSS#AB30 VSS#AB7 VSS#AC3 VSS#AC6 VSS#AC7 VSS#AD4 VSS#AD7 VSS#AE10 VSS#AE13 VSS#AE16 VSS#AE17 VSS#AE2 VSS#AE20 VSS#AE24 VSS#AE25 VSS#AE26 VSS#AE27 VSS#AE28

VSS#AE29

AE29

H_COMP6

H_COMP7

AE3

COMP6Y3COMP7

VSS#AE30

AE5

AE30

60.4R1%0402

AE4

D1

D14

RSVD#D1

RSVD#D14

RSVD#AE4

VSS#AE5

VSS#AE7

VSS#AF10

VSS#AF13

AE7

AF10

AF13

TP12TP12

1

E23

AF16

TP10TP10

TP11TP11

1

TP13TP13

1

E7

F23

F6

B13

J3

P5

W1

AC4

IMPSEL#

RSVD#E5E5RSVD#E6E6RSVD#E7

RSVD#F23

RSVD#E23

VSS#AF16

RSVD#B13

VSS#AF17

VSS#AF20

VSS#AF23

VSS#AF24

VSS#AF25

VSS#AF26

VSS#AF27

AF17

AF20

AF23

AF24

AF25

AF26

AF27

MSID[1]V1MSID[0]

RSVD#J3

RSVD#N4N4RSVD#P5

RSVD#AC4

VSS#AF28

VSS#AF29

VSS#AF3

VSS#AF30

VSS#AF6

VSS#AF7

VSS#AG10

VSS#AG13

VSS#AG16

VSS#AG17

AF3

AF6

AF7

AF28

AF29

AF30

AG10

AG13

AG16

AG17

AG20

60.4R1%0402

D D

A12 A15 A18

A2 A21 A24

A6

A9

AA23 AA24 AA25 AA26 AA27 AA28 AA29

AA3

AA30

AA6 AA7 AB1

C C

B B

AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30

AE10 AE13 AE16 AE17

AE20 AE24 AE25 AE26 AE27 AE28

AB7 AC3 AC6 AC7 AD4 AD7

AE2

2005 Perf FMB 0 0 2005 Value FMB 0 1

Y2

W4

V6

V30

V3

V29

V28

V27

V26

VSS#Y7Y7VSS#Y5Y5VSS#Y2

VSS#V7V7VSS#V6

VSS#V3

VSS#W7W7VSS#W4

VSS#V30

VSS#V29

VSS#V28

VSS#V27

VSS#AG20

VSS#AG23

VSS#AG24

VSS#AG7

VSS#AH1

VSS#AH10

VSS#AH13

VSS#AH16

VSS#AH17

VSS#AH20

VSS#AH23

VSS#AH24

VSS#AH3

AH1

AG7

AH10

AG23

AG24

AH3

AH13

AH6

AH16

AH17

AH20

AH23

AH24

V25

VSS#V26

VSS#V25

VSS#AH6

VSS#AH7

AH7

V24

V23

U1

VSS#U7U7VSS#U1

VSS#V24

VSS#V23

VSS#AJ10

VSS#AJ13

VSS#AJ16

AJ10

AJ13

AJ16

AJ17

MSID1 MSID0

T3

R5

R30

VSS#T7T7VSS#T6T6VSS#T3

VSS#R7R7VSS#R5

VSS#R30

VSS#AJ17

VSS#AJ20

VSS#AJ23

VSS#AJ24

VSS#AJ27

VSS#AJ28

VSS#AJ29

AJ20

AJ23

AJ24

AJ27

AJ28

AJ29

R29

R28

R27

R26

R25

R24

R23

P4

P30

P29

P28

P27

P26

P25

P24

P23

N3

M1

L6

L30

L3

L29

L28

L27

VSS#L7L7VSS#L6

VSS#R29

VSS#AJ30

AJ30

VSS#R2R2VSS#P7P7VSS#P4

VSS#R28

VSS#R27

VSS#R26

VSS#R25

VSS#R24

VSS#R23

VSS#P30

VSS#P29

VSS#AJ4

VSS#AJ7

VSS#AK10

VSS#AK13

VSS#AK16

VSS#AK17

VSS#AK2

VSS#AK20

VSS#AK23

VSS#AK24

VSS#AK27

AJ4

AJ7

AK2

AK10

AK13

AK16

AK17

AK20

AK23

AK24

AK27

VSS#N7N7VSS#N6N6VSS#N3

VSS#P28

VSS#P27

VSS#P26

VSS#P25

VSS#P24

VSS#P23

VSS#AK28

VSS#AK29

VSS#AK30

VSS#AK5

VSS#AK7

VSS#AL10

VSS#AL13

VSS#AL16

AK5

AK7

AL10

AL13

AK28

AL16

AK29

AK30

VSS#L3

VSS#M7M7VSS#M1

VSS#L30

VSS#L29

VSS#L28

VSS#AL17

VSS#AL20

VSS#AL23

VSS#AL24

VSS#AL27

VSS#AL28

VSS#AL3

VSS#AL7

VSS#AM1

AL3

AL7

AL17

AL20

AM1

AL23

AL24

AL27

AL28

AM10

K2

L26

L25

L24

L23

K5

H14

VSS#J4J4VSS#J7

VSS#K2

VSS#K7K7VSS#K5

VSS#L27

VSS#L26

VSS#L25

VSS#L24

VSS#L23

VSS#AM10

VSS#AM13

VSS#AM16

VSS#AM17

VSS#AM20

VSS#AM23

VSS#AM24

VSS#AM27

AM13

AM16

AM17

AM20

AM23

AM24

AM27

VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9

VSS#H25

VSS#H26

VSS#H27

VSS#H28

VSS#AM28

VSS#AM4

VSS#AN1

VSS#AN10

VSS#AN13

VSS#AN16

VSS#AN17

VSS#AN2

VSS#AN20

VSS#AN23

VSS#AN24

AN1

AM4

AM28

AN2

AN10

AN13

AN16

AN17

AN20

AN23

AN24

VSS#H14

H13

VSS#H17

VSS#H18

VSS#H19

VSS#H20

VSS#H21

VSS#H22

VSS#H23

VSS#H24

VSS#H13

H12

VSS#H12

H11

VSS#H11

H10

VSS#H10

G1

VSS#G1

F7

VSS#F7

F4

VSS#F4

F22

VSS#F22

F19

VSS#F19

F16

VSS#F16

F13

VSS#F13

F10

VSS#F10

E8

VSS#E8

E29

VSS#E29

E28

VSS#E28

E27

VSS#E27

E26

VSS#E26

E25

VSS#E25

E20

VSS#E20

E2

VSS#E2

E17

VSS#E17

E14

VSS#E14

E11

VSS#E11

D9

VSS#D9

D6

VSS#D6

D5

VSS#D5

D3

VSS#D3

D24

VSS#D24

D21

VSS#D21

D18

VSS#D18

D15

VSS#D15

D12

VSS#D12

C7

VSS#C7

C4

VSS#C4

C24

VSS#C24

C22

VSS#C22

C19

VSS#C19

C16

VSS#C16

C13

VSS#C13

C10

VSS#C10

B8

VSS#B8

B5

VSS#B5

B24

VSS#B24

B20

VSS#B20

B17

VSS#B17

VSS#AN27

VSS#AN28

VSS#B1B1VSS#B11

VSS#B14

ZIF-SOCK775-15u-in

B11

B14

AN27

AN28

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H9

J7

Optics Orientation Holes

FM4

FM1

OPTICS-M120

FM7

OPTICS-M120

A A

FM11

OPTICS-M100

FM16

OPTICS-M100

PDF created with pdfFactory trial version www.pdffactory.com

FM4

1

OPTICS-M120

FM9

1

OPTICS-M120

FM12

OPTICS-M100

FM17

OPTICS-M100

8

FM2

1

OPTICS-M120

FM10

1

OPTICS-M120

FM13

OPTICS-M100

FM18

OPTICS-M100

FM3

1

OPTICS-M120

1

FM14

OPTICS-M100

FM19

OPTICS-M100

FM5

OPTICS-M120

FM15

OPTICS-M100

FM20

OPTICS-M100

1

6

1

7

9

8

H1

7 6

MH1H1MH1

H5

7 6

MH1H5MH1

2 3

5

4

9

8

2 3

5

4

9

8

H2

7 6

MH1H2MH1

H6

7 6

MH1H6MH1

2 3

5

4

9

8

2 3

5

4

5

9

8

H3

7 6

MH1H3MH1

H7

7 6

MH1H7MH1

2 3

5

4

9

8

2 3

5

4

9

8

H4

7 6

MH1H4MH1

H8

7 6

MH1H8MH1

2 3

5

4

9

8

2 3

5

4

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

2

Intel LGA775 - GND

MS-7210_051124K1

2.0

6 34Thursday, November 24, 2005

1

2.0

8

H_A#[3..31]4

D D

H_ADSTB#04 H_ADSTB#14

H_REQ#[0..4]4

H_RS#[0..2]4

R29

R28

16.9R1%

H_BR#04

H_BPRI#4

H_BNR#4

H_LOCK#4

H_ADS#4

H_HIT#4 H_HITM#4 H_DEFER#4

H_TRDY#4 H_DBSY#4

H_DRDY#4

CK_H_MCH17

CK_H_MCH#17

PWR_GD12,29

H_CPURST#4

ICH_SYNC#

MCH_GTLREF_CPU

HXSCOMP

C15

2.2p/4/N

HXRCOMP HXSCOMP HXSWING

C C

B B

PLTRST#_ICH711

ICH_SYNC#12

V_FSB_VTT

A A

PDF created with pdfFactory trial version www.pdffactory.com

60.4R1%0402

60.4R1%0402 R30

8

7

N17

P17

P18

P20

P21

AA22

AB21

AB22

AB23

AC22

U6A

AA37

AA41

W42

W41

W40

AJ12

K38 K35 M34

N35 R33 N32 N34 M38 N42 N37 N38 R32 R36 U37 R35 R38 V33 U34 U32 V42 U35 Y36 Y38

V32 Y34

M36 V35 F38

D42 U39 U40

E41 D41 K36 G37 E42

U41 P40

U42 V41 Y40

T40 Y43 T43

M31 M29

AJ9 C30

M18

A28 C27 B27

D27 D28

J39 J42 J37

U6A

HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HAD_STB0# HAD_STB1# HPCREQ#

HBREQ0# HBPRI#

HBNR# HLOCK# HADS# HREQ0#

HREQ1# HREQ2# HREQ3# HREQ4#

HHIT# HHITM# HDEFER#

HTRDY# HDBSY# HDRDY# HEDRDY#

RS0# RS1# RS2#

HCLKP HCLKN

PWROK HCPURST#

RSTIN# ICH_SYNC#

HRCOMP HSCOMP HSWING

HDVREF HACCVREF

VCC

V_FSB_VTT

H_A#3 H_D#0 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

AD14

VCC

RSVRD

L15

U27

M15

AA35

AA42

AA34

AA38

HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL SPACE" HD_SWING S/B 1/3*VTT +/- 2%

R31

PLACE DIVIDER RESISTOR NEAR VTT

301R1%

R35

C18

84.5/6/1%

0.01u/4/X

6

AF6

AF7

AF8

AF9

AF10

AF11

AF12

VCC

RSVRD

R27

A43

M11

AJ24

AG25

AG26

AG27

R33 62R0402R33 62R0402

5

V_1P5_CORE

AF13

AF14

AF30

AG2

AG3

AG4

AG5

AG6

AG7

AG8

AG9

AG10

AG11

AG12

AG13

AG14

AH1

AH2

AH4

AJ5

AJ13

AJ14

AK2

AK3

AK4

AK14

AK15

AK20

R15

R17

R18

R20

R21

R23

R24

U15

U17

U18

VCC

RSVRD

AJ21

AL20

AL26

AK27

R30

124R1%0402

RSVRD

V30

AJ29

AG29

V_FSB_VTT

R34

R34 210R1%0402

210R1%0402

NC

BC43NCBC42

NC

BC2NCBC1

BB2NCBB1NCBA2

BB43

AW26

GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V 124 OHM OVER 210 RESISTORS

R32 10R0402R32 10R0402

0.1u/4/Y

C16

RSVRD

AJ27

AL39

AK40

AY14

BC16

AD30

AC34

AW17

AW18

HXSWING

RSVRD

Y30

Y33

U30

V31

AJ23

AJ26

AF31

AD31

AL29

AC30

AK21

AA30

U19

VCC

NC

AW2

U20

VCC

NC

AV27NCAV26

U21

VCC

U22

U23

VCC

NC

E35NCC42

C17

C17 220p/4/N

220p/4/N

U24

VCC

4

U25

U26

V15

V17

V18

V19

VCC

NCC2NC

NCB3NCB2NC

B43NCB42NCB41

A42

MCH_GTLREF_CPU

V20

V21

VCC

Y17

V22

V23

V25

V27

VCC

Y18

Y19

Y21

Y23

W17

W18

W19

W20

W22

W24

W26

W27

VCC

Y25

Y27

AA15

AA17

AA18

AA19

AA20

MCH_GTLREF_CPU 4

3

Y15

M17

VCC

KDINV_0# HDINV_1# HDINV_2# HDINV_3#

HD_STBP0# HD_STBN0#

HD_STBP1# HD_STBN1#

HD_STBP2# HD_STBN2#

HD_STBP3# HD_STBN3#

Lakeport

V_1P5_CORE

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8#

HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

P41 M39 P42 M42 N41 M40 L40 M41 K42 G39 J41 G42 G40 G41 F40 F43 F37 E37 J35 D39 C41 B39 B40 H34 C37 J32 B35 J34 B34 F32 L32 J31 H31 M33 K31 M27 K29 F31 H29 F29 L27 M24 J26 K26 G26 H24 K24 F24 E31 A33 E40 D37 C39 D38 D33 C35 D34 C34 B31 C31 C32 D32 B30 D30

K40 A38 E29 B32

K41 L43

F35 G34

J27 M26

E34 B37

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

CAPS SHOULD BE PLACED NEAR MCH PIN

7

6

5

4

3

H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3

2

H_D#[0..63] 4

H_DBI#[0..3] 4

H_DSTBP#0 4 H_DSTBN#0 4

H_DSTBP#1 4 H_DSTBN#1 4

H_DSTBP#2 4 H_DSTBN#2 4

H_DSTBP#3 4 H_DSTBN#3 4

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel Lakeport - CPU

MS-7210_051124K1

2

1

2.0

7 34Thursday, November 24, 2005

1

2.0

8

7

6

5

4

3

2

1

DATA_A[0..63]14

DATA_A16

DATA_A21

DATA_A6

DATA_A0

DATA_A1

DATA_A3

D D

C C

B B

SCS_A#[0..3]14,16

RAS_A#14,16 CAS_A#14,16

MAA_A[0..13]14,16

ODT_A[0..3]14,16

SBS_A[0..2]14,16

DQS_A014

DQS_A#014

DQS_A114

DQS_A#114

DQS_A214

DQS_A#214

DQS_A314

DQS_A#314

DQS_A414

DQS_A#414

DQS_A514

DQS_A#514

DQS_A614

DQS_A#614

DQS_A714

DQS_A#714

P_DDR0_A14

N_DDR0_A14

P_DDR1_A14

N_DDR1_A14

P_DDR2_A14

N_DDR2_A14

P_DDR3_A14

N_DDR3_A14

P_DDR4_A14

N_DDR4_A14

P_DDR5_A14

N_DDR5_A14

SCS_A#0 SCS_A#1 SCS_A#2 SCS_A#3

RAS_A# CAS_A#

WE_A#14,16

WE_A# MAA_A0

MAA_A1 MAA_A2 MAA_A3 MAA_A4 MAA_A5 MAA_A6 MAA_A7 MAA_A8 MAA_A9 MAA_A10 MAA_A11 MAA_A12

ODT_A0 ODT_A1 ODT_A2 ODT_A3

SBS_A0 SBS_A1 SBS_A2

DQS_A0 DQS_A#0 DQS_A1 DQS_A#1 DQS_A2 DQS_A#2 DQS_A3 DQS_A#3 DQS_A4 DQS_A#4 DQS_A5 DQS_A#5 DQS_A6 DQS_A#6 DQS_A7 DQS_A#7

P_DDR0_A N_DDR0_A P_DDR1_A N_DDR1_A P_DDR2_A N_DDR2_A P_DDR3_A N_DDR3_A P_DDR4_A N_DDR4_A P_DDR5_A N_DDR5_A

SMPCOMP_N SMPCOMP_P MCH_VREF_A

BB37 BA39 BA35 AY38

BA34 BA37 BB35

BA32

AW32

BB30 BA30 AY30 BA27 BC28 AY27 AY28 BB27 AY33

AW27

BB26 BC38

AW37

AY39 AY37 BB40

BC33 AY34 BA26

AU4 AR2 BA3

BB4 AY11 BA10 AU18 AR18 AU35 AV35 AP42 AP40 AG42 AG41 AC42 AC41

BB32 AY32

AY5

BB5 AK42 AK41 BA31 BB31

AY6

BA5 AH40 AH43

AM3

AL5 AJ6 AJ8

U6B

SACS0# SACS1# SACS2# SACS3#

SARAS# SACAS# SAWE#

SAMA0 SAMA1 SAMA2 SAMA3 SAMA4 SAMA5 SAMA6 SAMA7 SAMA8 SAMA9 SAMA10 SAMA11 SAMA12 SAMA13

SAODT0 SAODT1 SAODT2 SAODT3

SABA0 SABA1 SABA2

SADQS0 SADQS0# SADQS1 SADQS1# SADQS2 SADQS2# SADQS3 SADQS3# SADQS4 SADQS4# SADQS5 SADQS5# SADQS6 SADQS6# SADQS7 SADQS7#

SACLK0 SACLK0# SACLK1 SACLK1# SACLK2 SACLK2# SACLK3 SACLK3# SACLK4 SACLK4# SACLK5 SACLK5#

MCH_SRCOMP0 MCH_SRCOMP1 SMOCDCOMP0 SMOCDCOMP1

DATA_A2

AP3

AP2

AU3

AV4

SADQ0

SADQ1

SADQ2

SBDQ0

Lakeport

R36

SMPCOMP_P

80.6R1%0402

VCC_DDR

A A

PDF created with pdfFactory trial version www.pdffactory.com

C21

0.1u/4/Y

R39

80.6R1%0402

8

SMPCOMP_N

Lakeport

DATA_B[0..63]15

AL6

AL8

DATA_B0

DATA_B1

7

DATA_A10

DATA_A8

DATA_A7

DATA_A9

DATA_A4

DATA_A5

AN1

AP4

AU5

AU2

AW3

AY3

BA7

SADQ3

SADQ4

SADQ5

SADQ6

SADQ7

SADQ8

SADQ9

SBDQ1

SBDQ2

SBDQ3

SBDQ4

SBDQ5

SBDQ6

SBDQ7

AL9

AP8

AP9

AP6

AU7

AJ11

AM10

DATA_B4

DATA_B5

DATA_B3

DATA_B7

DATA_B8

DATA_B2

DATA_B6

DATA_A17

DATA_A14

DATA_A15

DATA_A12

DATA_A11

DATA_A13

BB7

AV1

AW4

BC6

AY7

AW12

AY10

SADQ10

SADQ11

SADQ12

SADQ13

SADQ14

SADQ15

SADQ16

SBDQ8

SBDQ9

SBDQ10

SBDQ11

SBDQ12

SBDQ13

SBDQ14

AV6

AR5

AR7

AV12

AR12

AR10

AM11

DATA_B14

DATA_B15

DATA_B11

DATA_B10

DATA_B12

DATA_B13

DATA_B9

DATA_A24

DATA_A18

BA12

SADQ17

SBDQ15

AM15

DATA_B16

DATA_A25

DATA_A19

BB12

BA9

SADQ18

SADQ19

SBDQ16

SBDQ17

AV15

AM13

DATA_B17

DATA_B18

DATA_A27

BB9

BC11

AY12

AM20

AM18

AV20

AM21

SADQ20

SADQ21

SADQ22

SADQ23

SADQ24

SADQ25

SADQ26

SBDQ18

SBDQ19

SBDQ20

SBDQ21

SBDQ22

SBDQ23

SBDQ24

AT15

AN12

AR13

AP15

AM17

AM24

AM23

DATA_B21

DATA_B23

DATA_B20

DATA_B24

DATA_B22

DATA_B19

DATA_B25

6

DATA_A26

DATA_A22

DATA_A23

DATA_A20

DATA_A34

DATA_A32

DATA_A31

DATA_A35

DATA_A29

DATA_A28

AP17

AR17

SADQ27

SADQ28

SBDQ25

SBDQ26

AV24

AM26

DATA_B27

DATA_B26

DATA_A36

DATA_A33

DATA_A30

AP20

AT20

AP32

AV34

AV38

AU39

AV32

SADQ29

SADQ30

SADQ31

SADQ32

SADQ33

SADQ34

SADQ35

SBDQ27

SBDQ28

SBDQ29

SBDQ30

SBDQ31

SBDQ32

SBDQ33

AT24

AP21

AR21

AP24

AU27

AN29

AR31

DATA_B34

DATA_B32

DATA_B31

DATA_B30

DATA_B33

DATA_B28

DATA_B29

SCKE_A[0..3]14,16

DATA_A37

DATA_A38

AT32

AR34

SADQ36

SADQ37

SBDQ34

SBDQ35

AP27

AM31

DATA_B35

DATA_B36

DATA_A45

DATA_A41

DATA_A42

DATA_A40

DATA_A39

AU37

AR41

AR42

AN43

SADQ38

SADQ39

SADQ40

SADQ41

SBDQ36

SBDQ37

SBDQ38

SBDQ39

AR27

AP31

AU31

AP35

DATA_B40

DATA_B39

DATA_B37

DATA_B38

DATA_A49

DATA_A48

DATA_A43

DATA_A44

DATA_A47

DATA_A46

DATA_A50

AM40

AU41

AU42

AP41

AN40

AL41

AL42

AF39

SADQ42

SADQ43

SADQ44

SADQ45

SADQ46

SADQ47

SADQ48

SADQ49

SADQ50

SBDQ40

SBDQ41

SBDQ42

SBDQ43

SBDQ44

SBDQ45

SBDQ46

SBDQ47

SBDQ48

AL35

AP37

DATA_B41

5

AL34

AN32

AR35

AU38

AM38

AM34

DATA_B42

DATA_B46

DATA_B47

DATA_B48

DATA_B45

DATA_B43

DATA_B44

DQM_A[0..7]14

DQM_A6

DQM_A1

DQM_A4

DQM_A2

DQM_A7

DQM_A3

DATA_A56

DATA_A53

DATA_A57

DATA_A58

DATA_A54

DATA_A55

DATA_A52

DATA_A51

AE40

AM41

SADQ51

SBDQ49

AJ34

AF32

DATA_B49

DATA_B50

DATA_A59

AM42

AF41

AF42

AD40

AD43

AA39

AA40

SADQ52

SADQ53

SADQ54

SADQ55

SADQ56

SADQ57

SADQ58

SBDQ50

SBDQ51

SBDQ52

SBDQ53

SBDQ54

SBDQ55

SBDQ56

AJ32

AL31

AF34

AD32

AC32

AD34

AG35

DATA_B52

DATA_B55

DATA_B57

DATA_B54

DATA_B51

DATA_B56

DATA_B53

SCKE_B[0..3]15,16

DQM_B[0..7]15

SCKE_A1

DATA_A61

DATA_A60

AE42

AE41

SADQ59

SADQ60

SBDQ57

SBDQ58

Y32

AA32

DATA_B58

DATA_B59

SCKE_A3

DATA_A62

SCKE_A0

SCKE_A2

DATA_A63

AB41

AB42

BB25

AY25

BC24

BA25

SADQ61

SADQ62

SADQ63

SACKE0

SACKE1

SACKE2

SACKE3

SBDQ59

SBDQ60

SBDQ61

SBDQ62

SBDQ63

SBCKE0

SBCKE1

AF35

AF37

AC33

AC35

BA14

AY16

BA13

DATA_B61

DATA_B63

DATA_B60

DATA_B62

SCKE_B0

SCKE_B2

SCKE_B1

4

DQM_A5

DQM_A0

AR3

SBCS0# SBCS1# SBCS2#

SADM7

SADM6

SADM5

SADM4

SADM3

SADM2

SADM1

SADM0

SBDM7

SBCKE2

SBCKE3

AJ39

AD39

BB13

SCKE_B3

DQM_B7

DQM_B6

SBCS3#

SBRAS# SBCAS#

SBWE# SBMA0

SBMA1 SBMA2 SBMA3 SBMA4 SBMA5 SBMA6 SBMA7 SBMA8

SBMA9 SBMA10 SBMA11 SBMA12 SBMA13

SBODT0 SBODT1 SBODT2 SBODT3

SBBA0 SBBA1 SBBA2

SBDQS0

SBDQS0#

SBDQS1

SBDQS1#

SBDQS2

SBDQS2#

SBDQS3

SBDQS3#

SBDQS4

SBDQS4#

SBDQS5

SBDQS5#

SBDQS6

SBDQS6#

SBDQS7

SBDQS7#

SBCLK0

SBCLK0#

SBCLK1

SBCLK1#

SBCLK2

SBCLK2#

SBCLK3

SBCLK3#

SBCLK4

SBCLK4#

SBCLK5

SBCLK5#

SMVREF1 SMVREF0

SBDM0

SBDM1

SBDM2

SBDM3

SBDM4

SBDM5

SBDM6

AW7

AL11

AP13

AP23

AR29

AR38

DQM_B2

DQM_B3

DQM_B1

DQM_B5

DQM_B0

DQM_B4

BA40 AW41 BA41 AW40

BA23 AY24 BB23

BB22 BB21 BA21 AY21 BC20 AY19 AY20 BA18 BA19 BB18 BA22 BB17 BA17 AW42

AY42 AV40 AV43 AU40

AW23 AY23 AY17

AM8 AM6 AV7 AR9 AV13 AT13 AU23 AR23 AT29 AV29 AP36 AM35 AG34 AG32 AD36 AD38

AM29 AM27 AV9 AW9 AL38 AL36 AP26 AR26 AU10 AT10 AJ38 AJ36

AM2 AM4

SCS_B#0 SCS_B#1 SCS_B#2 SCS_B#3

RAS_B# CAS_B# WE_B#

MAA_B0 MAA_B1 MAA_B2 MAA_B3 MAA_B4 MAA_B5 MAA_B6 MAA_B7 MAA_B8 MAA_B9 MAA_B10 MAA_B11 MAA_B12 MAA_B13MAA_A13

ODT_B0 ODT_B1 ODT_B2 ODT_B3

SBS_B0 SBS_B1 SBS_B2

DQS_B0 DQS_B#0 DQS_B1 DQS_B#1 DQS_B2 DQS_B#2 DQS_B3 DQS_B#3 DQS_B4 DQS_B#4 DQS_B5 DQS_B#5 DQS_B6 DQS_B#6 DQS_B7 DQS_B#7

P_DDR0_B N_DDR0_B P_DDR1_B N_DDR1_B P_DDR2_B N_DDR2_B P_DDR3_B N_DDR3_B P_DDR4_B N_DDR4_B P_DDR5_B N_DDR5_B

3

AC40

AG40

AP39

AT34

AP18

BB10

AY2

SCS_B#[0..3] 15,16

RAS_B# 15,16 CAS_B# 15,16 WE_B# 15,16

MAA_B[0..13] 15,16

ODT_B[0..3] 15,16

SBS_B[0..2] 15,16

DQS_B0 15 DQS_B#0 15 DQS_B1 15 DQS_B#1 15 DQS_B2 15 DQS_B#2 15 DQS_B3 15 DQS_B#3 15 DQS_B4 15 DQS_B#4 15 DQS_B5 15 DQS_B#5 15 DQS_B6 15 DQS_B#6 15 DQS_B7 15 DQS_B#7 15

P_DDR0_B 15 N_DDR0_B 15 P_DDR1_B 15 N_DDR1_B 15 P_DDR2_B 15 N_DDR2_B 15 P_DDR3_B 15 N_DDR3_B 15 P_DDR4_B 15 N_DDR4_B 15 P_DDR5_B 15 N_DDR5_B 15

C19

C19 x_0.1u/4/Y

x_0.1u/4/Y

PLACE 0.1UF CAP CLOSE TO MCH

VCC_DDR

R37

MCH_VREF_A

R38

MSI

2

R38 1KR1%0402

1KR1%0402

MICRO-STAR INt'L CO., LTD.

Intel Lakeport - Memory

C20

0.1u/4/Y

MS-7210_051124K1

8 34Thursday, November 24, 2005

1

1KR1%0402

Title

Size Document Number Rev

Date: Sheet of

2.0

8

EXP_A_RXP_018 EXP_A_RXN_018 EXP_A_RXP_118 EXP_A_RXN_118

D D

C C

H_FSBSEL24,17 H_FSBSEL14,17 H_FSBSEL04,17

V_2P5_MCH

B B

V_2P5_MCH

V_1P5_CORE

EXP_A_RXP_218 EXP_A_RXN_218 EXP_A_RXP_318 EXP_A_RXN_318 EXP_A_RXP_418 EXP_A_RXN_418 EXP_A_RXP_518 EXP_A_RXN_518 EXP_A_RXP_618 EXP_A_RXN_618 EXP_A_RXP_718 EXP_A_RXN_718 EXP_A_RXP_818 EXP_A_RXN_818 EXP_A_RXP_918 EXP_A_RXN_918

EXP_A_RXP_1018

EXP_A_RXN_1018

EXP_A_RXP_1118

EXP_A_RXN_1118

EXP_A_RXP_1218

EXP_A_RXN_1218

EXP_A_RXP_1318

EXP_A_RXN_1318

EXP_A_RXP_1418

EXP_A_RXN_1418

EXP_A_RXP_1518

EXP_A_RXN_1518

EXP_EN_HDR18

DMI_ITP_MRP_011

DMI_ITN_MRN_011

DMI_ITP_MRP_111

DMI_ITN_MRN_111

DMI_ITP_MRP_211

DMI_ITN_MRN_211

DMI_ITP_MRP_311

DMI_ITN_MRN_311 CK_PE_100M_MCH17

CK_PE_100M_MCH#17

SDVO_CTRL_DATA18

SDVO_CTRL_CLK18

RN8

1 3 5 7

8P4R-10KR0402

L2

B_180L1500m_90

I = 70mA

EC1

100uF/16V/EL

0.1u/4/Y

V_2P5_DAC_FILTERED19

1 2

CP2

X_COPPER

EXP_A_RXP_0 EXP_A_RXN_0 EXP_A_RXP_1 EXP_A_RXN_1 EXP_A_RXP_2 EXP_A_RXN_2 EXP_A_RXP_3 EXP_A_RXN_3 EXP_A_RXP_4 EXP_A_RXN_4 EXP_A_RXP_5 EXP_A_RXN_5 EXP_A_RXP_6 EXP_A_RXN_6 EXP_A_RXP_7 EXP_A_RXN_7 EXP_A_RXP_8 EXP_A_RXN_8 EXP_A_RXP_9 EXP_A_RXN_9 EXP_A_RXP_10 EXP_A_RXN_10 EXP_A_RXP_11 EXP_A_RXN_11 EXP_A_RXP_12 EXP_A_RXN_12 EXP_A_RXP_13 EXP_A_RXN_13 EXP_A_RXP_14 EXP_A_RXN_14 EXP_A_RXP_15 EXP_A_RXN_15 EXP_EN_HDR

DMI_ITP_MRP_0 DMI_ITN_MRN_0 DMI_ITP_MRP_1 DMI_ITN_MRN_1 DMI_ITP_MRP_2 DMI_ITN_MRN_2 DMI_ITP_MRP_3 DMI_ITN_MRN_3

CK_PE_100M_MCH CK_PE_100M_MCH#

SDVO_CTRL_DATA SDVO_CTRL_CLK

2 4 6

EXTTS

8

R41 X_1KR0402R41 X_1KR0402

V_2P5_MCH

V_2P5_DAC_FILTERED

12

+

C33

SEL0 SEL1 SEL2

NOA_6

VCCA_HPLLVCCA_HPLL VCCA_MPLL VCCA_DPLLA VCCA_DPLLB VCCA_GPLL

C34

0.01u/4/X

U6C

G12

EXPARXP0

F12

EXPARXN0

D11

EXPARXP1

D12

EXPARXN1

J13

EXPARXP2

H13

EXPARXN2

E10

EXPARXP3

F10

EXPARXN3

J9

EXPARXP4

H10

EXPARXN4

F7

EXPARXP5

F9

EXPARXN5

C4

EXPARXP6

D3

EXPARXN6

G6

EXPARXP7

J6

EXPARXN7

K9

EXPARXP8

K8

EXPARXN8

F4

EXPARXP9

G4

EXPARXN9

M6

EXPARXP10

M7

EXPARXN10

K2

EXPARXP11

L1

EXPARXN11

U11

EXPARXP12

U10

EXPARXN12

R8

EXPARXP13

R7

EXPARXN13

P4

EXPARXP14

N3

EXPARXN14

Y10

EXPARXP15

Y11

EXPARXN15

F20

EXP_EN

Y7

DMI RXP0

Y8

DMI RXN0

AA9

DMI RXP1

AA10

DMI RXN1

AA6

DMI RXP2

AA7

DMI RXN2

AC9

DMI RXP3

AC8

DMI RXN3

B14

GCLKP

B16

GCLKN

F15

SDVOCTRLDATA

E15

SDVOCTRLCLK

F21

BSEL0

H21

BSEL1

L20

BSEL2

AK17

RSV_TP[0]

AL17

RSV_TP[1]

K21

EXP_SLR

AK23

RSV_TP[2]

AK18

RSV_TP[3]

L21

RSV_TP[4]

L18

RSV_TP[5]

N21

RSV_TP[6]

C21

VCCAHPLL

B20

VCCAMPLL

C19

VCCADPLLA

B19

VCCADPLLB

B17

VCCA_EXPPLL

D19

VCC2

C18

VCCADAC

B18

VCCADAC

A18

VSSA_DAC

Lakeport

V_FSB_VTT

I = 60mA

VCCA_MPLL

C35

C35 1u/6/Y

1u/6/Y

7

V_1P5_CORE VCC_DDR

AA26

AB17

AB18

AB19

AB20

AB24

AB25

AB26

AA24

VCC

VTT

B23

A24

V_1P5_CORE V_1P5_CORE

AB27

VCC

VTT

B24

B25

B26

C23

C25

C26

D23

AC15

AC17

AC18

VCC

VTT

D24

D25

E23

L4 X_10U125m_0805-1L4 X_10U125m_0805-1L3 X_600L200m_500-1L3 X_600L200m_500-1

1 2

CP3

X_COPPER

6

AE20

AD23

AD25

AD26

AE17

AE18

AE22

AE24

AE26

AC20

AD17

AD19

AD21

AC24

AC26

AC27

AD15

VCC

VTT

E27

E24

E26

VCC

VTT

J23

L23

F23

F27

K23

H23

G23

M23

V_1P5_CORE

I = 55mA

VCCA_DPLLA

12

EC2

+

220uF/10V/EL

AE27

VCC

VTT

VCC

N23

P23

AF21

AF23

C36

0.1u/4/Y

5

AV23

AF15

AF17

AV18

AY43

AF19

VCC

VCCSM

VCC

AF25

AF26

AF27

AF29

AG15

AG17

AW20

AV21

AV31

AV42

AW13

AW15

VCCSM

VCC

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AW21

AW24

AW29

AW34

AW31

VCCSM

VCC

AJ15

AJ17

AJ18

AJ20

L5 1U500m_0805L5 1U500m_0805

AY41

BB16

BB20

BB24

AW35

BB28

VCCSM

VCC_EXP

AE4

AE3

AE2

4

BB33

BB38

BC26

BC31

BC35

BB42

BC13

BC18

BC22

N5

BC40

VCCSM

VCC_EXP

AD1

AC13

AC6

AC5

AA13

I = 45mA

10u/8/Y

Y13

AA5

VCCA_GPLL

C37

AD8

AD6

AD5

AD4

AD2

AD12

AD10

R48

1/4/1%

R49

1/4/1%

R13

R11

R10

N12

N11

N10

VCC_EXP

VCC_EXPR5VCC_EXP

VCC_EXP

VCC_EXPN9VCC_EXPN7VCC_EXP

VCC_EXP

VCC_EXPV9VCC_EXP

VCC_EXPV7VCC_EXPV6VCC_EXP

V5

V13

V10

C38

C38 10u/8/Y

10u/8/Y

U13

VCC_EXP

VCC_EXPU8VCC_EXPU7VCC_EXPU6VCC_EXP

EXPATXP0 EXPATXN0 EXPATXP1 EXPATXN1 EXPATXP2 EXPATXN2 EXPATXP3 EXPATXN3 EXPATXP4 EXPATXN4 EXPATXP5 EXPATXN5 EXPATXP6 EXPATXN6 EXPATXP7 EXPATXN7 EXPATXP8 EXPATXN8 EXPATXP9

EXPATXN9 EXPATXP10 EXPATXN10 EXPATXP11 EXPATXN11 EXPATXP12 EXPATXN12 EXPATXP13 EXPATXN13 EXPATXP14 EXPATXN14 EXPATXP15 EXPATXN15

DMI TXP0 DMI TXN0 DMI TXP1 DMI TXN1 DMI TXP2 DMI TXN2 DMI TXP3 DMI TXN3

EXP_COMPO

EXP_COMPI

HSYNC VSYNC

GREEN

GREENB

DDC_DATA

DDC_CLK

DREFCLKINP DREFCLKINN

EXTTS#

XORTEST

ALLZTEST

RED BLUE RED#

BLUE#

IREF

3

V_1P5_CORE

EXP_A_TXP_0

D14

EXP_A_TXN_0

C13

EXP_A_TXP_1

A13

EXP_A_TXN_1

B12

EXP_A_TXP_2

A11

EXP_A_TXN_2

B10

EXP_A_TXP_3

C10

EXP_A_TXN_3

C9

EXP_A_TXP_4

A9

EXP_A_TXN_4

B7

EXP_A_TXP_5

D7

EXP_A_TXN_5

D6

EXP_A_TXP_6

A6

EXP_A_TXN_6

B5

EXP_A_TXP_7

E2

EXP_A_TXN_7

F1

EXP_A_TXP_8

G2

EXP_A_TXN_8

J1

EXP_A_TXP_9

J3

EXP_A_TXN_9

K4

EXP_A_TXP_10

L4

EXP_A_TXN_10

M4

EXP_A_TXP_11

M2

EXP_A_TXN_11

N1

EXP_A_TXP_12

P2

EXP_A_TXN_12

T1

EXP_A_TXP_13

T4

EXP_A_TXN_13

U4

EXP_A_TXP_14

U2

EXP_A_TXN_14

V1

EXP_A_TXP_15

V3

EXP_A_TXN_15

W4

DMI_MTP_IRP_0

W2

DMI_MTN_IRN_0

Y1

DMI_MTP_IRP_1

AA2

DMI_MTN_IRN_1

AB1

DMI_MTP_IRP_2

Y4

DMI_MTN_IRN_2

AA4

DMI_MTP_IRP_3

AB3

DMI_MTN_IRN_3

AC4 AC12

AC11 D17

C17 F17

K17 H18

G17 J17 J18

N18 N20

J15 H15

A20 J20 H20 K18

GRCOMP

HSYNC VSYNC

VGA_RED VGA_GREEN VGA_BLUE

VGA_RED# VGA_GREEN# VGA_BLUE#

DDC_DATA DDC_CLK

CK_96M_DREF CK_96M_DREF#

DACREFSET EXTTS

V_1P5_CORE

R40

24.9R1%0402

R42 B_255R1%R42 B_255R1%

PLACE CLOSE TO MCH

TP14TP14

1

TP15TP15

1

2

EXP_A_TXP_0 18 EXP_A_TXN_0 18 EXP_A_TXP_1 18 EXP_A_TXN_1 18 EXP_A_TXP_2 18 EXP_A_TXN_2 18 EXP_A_TXP_3 18 EXP_A_TXN_3 18 EXP_A_TXP_4 18 EXP_A_TXN_4 18 EXP_A_TXP_5 18 EXP_A_TXN_5 18 EXP_A_TXP_6 18 EXP_A_TXN_6 18 EXP_A_TXP_7 18 EXP_A_TXN_7 18 EXP_A_TXP_8 18 EXP_A_TXN_8 18 EXP_A_TXP_9 18 EXP_A_TXN_9 18 EXP_A_TXP_1018 EXP_A_TXN_1018 EXP_A_TXP_1118 EXP_A_TXN_1118 EXP_A_TXP_1218 EXP_A_TXN_1218 EXP_A_TXP_1318 EXP_A_TXN_1318 EXP_A_TXP_1418 EXP_A_TXN_1418 EXP_A_TXP_1518 EXP_A_TXN_1518

DMI_MTP_IRP_0 11 DMI_MTN_IRN_0 11 DMI_MTP_IRP_1 11 DMI_MTN_IRN_1 11 DMI_MTP_IRP_2 11 DMI_MTN_IRN_2 11 DMI_MTP_IRP_3 11 DMI_MTN_IRN_3 11

HSYNC 19 VSYNC 19

VGA_RED 19 VGA_GREEN 19 VGA_BLUE 19

DDC_DATA 19 DDC_CLK 19

CK_96M_DREF 17 CK_96M_DREF# 17

V_1P5_CORE

FOR 945G

V_1P5_CORE

VCC_DDR

MCH MEMORY DECOUPLING

V_FSB_VTT

C30

0.1u/4/Y

FSB GENERIC DECOUPLING

V_1P5_CORE

C22

C22 x_10u/8/Y

x_10u/8/Y C23

C23 x_10u/8/Y

x_10u/8/Y C128

C128 x_10u/8/Y

x_10u/8/Y C574

C574 100p/4/N

100p/4/N C575

C575 100p/4/N

100p/4/N

C24

C24 1u/6/Y

1u/6/Y C25

C25 1u/6/Y

1u/6/Y C26

C26

0.1u/4/Y

C27

C27 1u/6/Y

1u/6/Y C28

C28 1u/6/Y

1u/6/Y C29

C29

0.1u/4/Y

C31

C587

C587 x_10u/8/Y

x_10u/8/Y C588

C588 x_10u/8/Y

x_10u/8/Y C589

C589 x_0.1u/4/Y

x_0.1u/4/Y C590

C590 x_0.1u/4/Y

x_0.1u/4/Y C591

C591 x_0.1u/4/Y

x_0.1u/4/Y

1

C32

0.1u/4/Y

0.1u/4/Y x_0.1u/4/Y

x_0.1u/4/Y

A A

V_1P5_CORE V_1P5_CORE

PDF created with pdfFactory trial version www.pdffactory.com

L6 X_10U125m_0805-1L6 X_10U125m_0805-1

1 2

CP4

X_COPPER

8

I = 55mA

VCCA_DPLLB

12

EC3

+

220uF/10V/EL

C39

0.1u/4/Y

I = 45mA

L7 X_600L200m_500-1L7 X_600L200m_500-1

1 2

CP5

X_COPPER

7

VCCA_HPLL

C40

0.1u/4/Y

6

V_1P5_CORE

5

I = 1.5A

4

Vcc_PCI Express

C41

C41 10u/8/Y

10u/8/Y C42

C42 10u/8/Y

10u/8/Y

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel Lakeport - PCI EXPRESS

MS-7210_051124K1

2

2.0

9 34Thursday, November 24, 2005

1

2.0

5

AN42

AN31

AN27

AN26

AN24

AN23

AN21

AN20

AN18

AN17

AN15

AN13

AN4

AN2

AM39

AM37

AM36

AM33

AM9

AM7

AM5

AL43

AL37

U6D

D D

C C

B B

U6D

VSS

A16

VSS

A22

VSS

A26

VSS

A31

VSS

A35

VSS

B4

VSS

B6

VSS

B9

VSS

B11

VSS

B13

VSS

B21

VSS

B22

VSS

B28

VSS

B33

VSS

B38

VSS

C3

VSS

C5

VSS

C7

VSS

C12

VSS

C14

VSS

C22

VSS

C40

VSS

D2

VSS

D5

VSS

D10

VSS

D16

VSS

D20

VSS

D21

VSS

E3

VSS

E4

VSS

E7

VSS

E9

VSS

E12

VSS

E13

VSS

E17

VSS

E18

VSS

E20

VSS

E21

VSS

E32

VSS

F2

VSS

F6

VSS

F13

VSS

F18

VSS

F26

VSS

F34

VSS

F42

VSS

G3

VSS

G5

VSS

G7

VSS

G9

VSS

G10

VSS

G13

VSS

G15

VSS

G18

VSS

G20

VSS

G21

VSS

G24

VSS

G27

VSS

G29

VSS

G31

VSS

G32

VSS

G35

VSS

G38

VSS

H12

VSS

H17

VSS

H26

VSS

H27

VSS

H32

VSS

J2

VSS

J5

VSS

J7

VSS

J10

VSS

J12

J21

J24

J43

J38

J29

VSS

VSSK7VSSK6VSSK5VSSK3VSS

VSS

K20

K15

K13

K12

K10

K27

VSS

VSSL2VSS

VSS

L13

L12

K39

K37

K34

K32

4

AU32

AU29

AU26

AU24

AU21

AU20

AU17

AU15

AU13

AU12

AU9

AU6

AT31

AT27

AT26

AT23

AT21

AT18

AT17

AT12

AR43

AR39

AR37

AR32

AR24

AR20

AR15

AR6

AR1

AP38

AP34

AP29

AP12

AP10

AP7

AP5

VSS

L31

L29

L26

L24

L42

VSS

VSSM9VSSM8VSSM5VSSM3VSS

M21

M20

M13

M10

VSS

VSSN8VSSN6VSS

N2

N15

N13

M37

M35

VSS

N24

VSS

N36

N33

N31

N29

N27

N26

N39

VSS

VSSP3VSS

P29

P27

P26

P24

P15

P14

N43

3

Y29

Y26

Y24

Y22

Y20

W25

W23

W21

V29

V26

V24

U29

R29

R26

D43

A40

BC9

BB41

BB39

BB34

BB19

BB14

BB11

BB6

BB3

BA42

BA4

AW10

AV37

AV17

AV10

AV2

AU34

VSS

VSSD1VSS

VSSA4VSS

VSS

VSSR9VSSR6VSS

VSS

VSST2VSS

VSSU3VSSU5VSSU9VSS

VSS

VSSV2VSSV8VSS

VSS

VSSW3VSSY2VSSY5VSSY6VSSY9VSS

P30

R12

R14

T42

R30

R31

R34

R37

R39

U12

U14

U31

U33

U36

U38

V11

V12

V14

V34

V36

V37

V38

V39

V43

2

AE19

AD29

AD27

AD24

AD22

AD20

AD18

AC29

AC25

AC19

AA29

AA27

AA25

VSS

Y12

Y14

Y31

Y35

Y37

AF20

AF22

AF24

AY1

BC4

VSS

AL33

VSS

AL32

VSS

AL27

VSS

AL24

VSS

AL23

VSS

AL21

VSS

AL18

VSS

AL15

VSS

AL13

VSS

AL12

VSS

AL10

VSS

AL7

VSS

AL3

VSS

AL2

VSS

AL1

VSS

AK30

VSS

AK29

VSS

AK26

VSS

AK24

VSS

AJ37

VSS

AJ35

VSS

AJ33

VSS

AJ31

VSS

AJ30

VSS

AJ10

VSS

AJ7

VSS

AH42

VSS

AG39

VSS

AG38

VSS

AG37

VSS

AG36

VSS

AG33

VSS

AG31

VSS

AG30

VSS

AF43

VSS

AF38

VSS

AF36

VSS

AF33

VSS

AF5

VSS

AF3

VSS

AF2

VSS

AF1

VSS

AD42

VSS

AD37

VSS

AD35

VSS

AD33

VSS

AD13

VSS

AD11

VSS

AD9

VSS

AD7

VSS

AC39

VSS

AC38

VSS

AC37

VSS

AC36

VSS

AC31

VSS

AC23

VSS

AC21

VSS

AC14

VSS

AC10

VSS

AC7

VSS

AC3

VSS

AC2

VSS

AB43

VSS

AB2

VSS

AA36

VSS

AA33

VSS

AA31

VSS

AA23

VSS

AA21

VSS

AA14

VSS

AA12

VSS

AA11

VSS

Y39

Y42

AA3

AA8

AF18

VSS

Lakeport

L17

AE21

AE23

AE25

1

A A

MICRO-STAR INt'L CO., LTD.

Intel Lakeport - GND

MS-7210_051124K1

1

10 34Thursday, November 24, 2005

2.0

PDF created with pdfFactory trial version www.pdffactory.com

5

4

MSI

Title

Size Document Number Rev

Date: Sheet of

3

2

Date: Sheet of

8

D D

C C

Damping Resistor close to ICH7

PCIRST#20

PCIRST#_139422

R58 22R0402R58 22R0402

Intel REQ

PGNT#4

R336 X_2.2KR0402R336 X_2.2KR0402

PGNT#5

B B

R337 X_2.2KR0402R337 X_2.2KR0402

VCC3 VCC3

PGNT#5PGNT#4

0

SPI PCI LPC

Stuff if TEKOA not present or for Non-share SPI.

A A

1 0

1

11

RN11

SPI_MOSI21 SPI_MISO21

SPI_CS#21

1 3 5 7

8P4R-10KR0402

VCC3_SB

7

AD0

PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5

PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 PGNT#5

SERIRQ IDE_IRQ

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C_BE#0 C_BE#1 C_BE#2 C_BE#3

G15 G13

AH21 AH16

E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13

E12 C11 D11 A11 A10 F11 F10

E9 D9 B9 A8 A6 C7 B6 E6 D6

B15 C12 D12 C15

A12 F16

A7 F14 F15 E10 E11 B10

C9 B19

A9 B18

D7 C16 C17 E13 A13

C8

E7 D16 D17 F13 A14

D8

A3

B4

C5

B5

G8

F7

F8

G7

P5

P2

P6

R2

P1

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE0# C/BE1# C/BE2# C/BE3#

DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PLOCK# SERR# PERR# PME#

PCICLK PCIRST#

REQ0# REQ1# REQ2# REQ3# GPIO22/REQ4# GPIO1/REQ5#

GNT0# GNT1# GNT2# GNT3# GPIO48/GNT4# GPIO17/GNT5#

PIRQA# PIRQB# PIRQC# PIRQD# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#

SERIRQ IDEIRQ

SPI_MOSI SPI_MISO SPI_CS# SPI_CLK SPI_ARB

VSS_0A4VSS_1

A23

AD[0..31]20,22

C_BE#[0..3]20,22

DEVSEL#20,22

FRAME#20,22

IRDY#20,22

TRDY#20,22

STOP#20,22

PAR20,22

LOCK#20 SERR#20 PERR#20,22

PCI_PME#20 ICH_PCLK17

PREQ#020 PREQ#120 PREQ#220 PREQ#320 PREQ#420,22 PREQ#520

PGNT#020 PGNT#120 PGNT#2 PGNT#3 PGNT#422 PGNT#5

PIRQ#A20

PIRQ#B20 PIRQ#C20 PIRQ#D20

PIRQ#E20

PIRQ#F20,22 PIRQ#G20 PIRQ#H20

SERIRQ12,24 IDE_IRQ26

2 4 6 8

VSS_2B1VSS_3B8VSS_4

6

PCI INTERFACE INTERRUPT

ICH 7

PART 1/3

SPI

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10C2VSS_11C6VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17E1VSS_18E2VSS_19E8VSS_20

VSS_21F3VSS_22F4VSS_23F5VSS_24

B11

B14

B17

B20

B26

B28

D10

D13

D18

D21

D24

F12

E15

VSS_25

F27

F28

VSS_26

VSS_27G1VSS_28G2VSS_29G5VSS_30G6VSS_31G9VSS_32

5

U19A

AH28

A20M#

AG27

CPUSLP#

AG26

FERR#

AG22

IGNNE#

AF22

INIT#

AG21

INIT3_3V#

AF25

INTR

AH24

NMI

AF23

SMI#

AH22

STPCLK#

AG23

RCIN#

CPULAN PCI EXPRESSDIRECT MEDIA

GPO49/CPUPWRGD

LAN_RSTSYNC

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38H3VSS_39H4VSS_40

G14

G18

G21

G24

G25

G26

A20GATE

THRMTRIP#

PLTRST#

PERN_1 PERP_1 PETN_1 PETP_1

PERN_2 PERP_2 PETN_2 PETP_2

PERN_3 PERP_3 PETN_3 PETP_3

PERN_4 PERP_4 PETN_4 PETP_4

PERN_5 PERP_5 PETN_5 PETP_5

PERN_6 PERP_6 PETN_6 PETP_6

DMI_0RXN DMI_0RXP DMI_0TXN DMI_0TXP

DMI_1RXN DMI_1RXP DMI_1TXN DMI_1TXP

DMI_2RXN DMI_2RXP DMI_2TXN DMI_2TXP

DMI_3RXN DMI_3RXP DMI_3TXN DMI_3TXP

DMI_CLKN DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

LAN_CLK

LAN_RXD0 LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

EE_CS

EE_DIN

EE_DOUT

EE_SHCLK

H5

AE22 AF26 AG24

C26 F26

F25 E28 E27

H26 H25 G28 G27

K26 K25 J28 J27

M26 M25 L28 L27

P26 P25 N28 N27

T25 T24 R28 R27

V26 V25 U28 U27

Y26 Y25 W28 W27

AB26 AB25 AA28 AA27

AD25 AD24 AC28 AC27

AE28 AE27

C25 D25

V3 U3 U5 V4 T5

U7 V6 V7

W1 W3 Y2 Y1

ICH7R

4

H_A20M# 4 H_SLP# 4 H_FERR# 4 H_IGNNE# 4 H_INIT# 4 FWH_INIT# 27 H_INTR 4 H_NMI 4 ICH_H_SMI# 4 H_STPCLK# 4 KBRST# 24 A20GATE 24

TRMTRIP# 4

H_PWRGD 4

HSO_N1_C HSO_N1 HSO_P1_C HSO_P1

HSO_N2_C

HSO_P3_C HSO_P3

HSO_N4_C HSO_P4_C

HSO_N5_C HSO_P5_C

LAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

ICH_EE_CS

ICH_EE_DIN ICH_EE_DOUT ICH_EE_SHCLK

R59

24.9R1%0402

C43 0.1u/4/XC43 0.1u/4/X C44 0.1u/4/XC44 0.1u/4/X

C495 0.1u/4/XC495 0.1u/4/X C496 0.1u/4/XC496 0.1u/4/X

C497 0.1u/4/XC497 0.1u/4/X C498 0.1u/4/XC498 0.1u/4/X

C499 0.1u/4/XC499 0.1u/4/X C500 0.1u/4/XC500 0.1u/4/X

C585 0.1u/4/XC585 0.1u/4/X C586 0.1u/4/XC586 0.1u/4/X

DMI_MTN_IRN_0 9 DMI_MTP_IRP_0 9 DMI_ITN_MRN_0 9 DMI_ITP_MRP_0 9

DMI_MTN_IRN_1 9 DMI_MTP_IRP_1 9 DMI_ITN_MRN_1 9 DMI_ITP_MRP_1 9

DMI_MTN_IRN_2 9 DMI_MTP_IRP_2 9 DMI_ITN_MRN_2 9 DMI_ITP_MRP_2 9

DMI_MTN_IRN_3 9 DMI_MTP_IRP_3 9 DMI_ITN_MRN_3 9 DMI_ITP_MRP_3 9

CK_PE_100M_ICH# 17 CK_PE_100M_ICH 17

V_DMI 13

LAN_CLK 21 LAN_RSTSYNC 21 LAN_RXD0 21 LAN_RXD1 21 LAN_RXD2 21

LAN_TXD0 21 LAN_TXD1 21 LAN_TXD2 21

ICH_EE_CS 21 ICH_EE_DIN 21 ICH_EE_DOUT 21 ICH_EE_SHCLK 21

3

Damping Resistor close to ICH7

R54 22R0402R54 22R0402

HSI_N1 HSI_P1

HSI_N2 HSI_P2 HSO_N2 HSO_P2HSO_P2_C

HSI_N3 HSI_P3 HSO_N3HSO_N3_C

HSI_N4 HSI_P4 HSO_N4 HSO_P4

HSI_N5 HSI_P5 HSO_N5 HSO_P5

HSI_N1 18 HSI_P1 18 HSO_N1 18 HSO_P1 18

HSI_N2 18 HSI_P2 18 HSO_N2 18 HSO_P2 18

HSI_N3 18 HSI_P3 18 HSO_N3 18 HSO_P3 18

HSI_N4 18 HSI_P4 18 HSO_N4 18 HSO_P4 18

HSI_N5 21 HSI_P5 21 HSO_N5 21 HSO_P5 21

PLTRST#_ICH7 7 PLTRST#_MS7 29

2

V_FSB_VTT

RN74 8P4R-62R0402RN74 8P4R-62R0402

1

2

3

4

5

6

7

8

PLACE AT ICH7 END OF ROUTE

1

H_FERR# TRMTRIP#

PDF created with pdfFactory trial version www.pdffactory.com

8

7

6

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

ICH7 - PCI, DMI, CPU, IRQ

MS-7210_051124K1

2

2.0

11 34Thursday, November 24, 2005

1

2.0

MSI MS-7210 Schematics 200

Specifications and Main Features

Frequently Asked Questions

User Manual