MSI MS-7210 Schematics 101
1
COVER SHEET
BLOCK DIAGRAM
GPIO & JUMPER SETTING
Intel LGA775-CPU
Intel Lakeport -GMCH
ICH7/ICH7R
DDR II DIMM 1and DIMM2 1 & 2 & 3 & 4
Clock Generator - ICS954129
PCI EXPRESS X16 & X 4 SLOT
VGA CONNECTOR
1
2
3
4-6
7-10
11-13
14-16
17
18
19
MS-7210
CPU:
Intel Prescott ( L2=2MB ) - 3.8G
Intel Cendar Mill (65nm) - 3.73G & Above
Intel Smithfield (90nm Dual core) - 3.2G
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7/ICH7R (South Bridge)
On Board Chipset:
Version 101
20PCI Slot 1 & 2
PCI LAN - RTL8100C/8110S
VIA VT-6307/6308P
Azalia CODEC(ALC880)
SIO-W83627EHF & KB/MS
A A
USB CONNECTORS
IDE & SATA& COM1& COM2& LPT
FWH & FAN
ATX & Front Panel
MS7 ACPI Controller
VRM10.1 Intersil 6316 4Phase
EMI Cap
Auto BOM manual
PWOK MAP
History
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Main Memory:
Expansion Slots:
Intersil PWM:
BIOS -- FWH FLASH 4Mb
Azalia CODEC(ALC 880)
LPC Super I/O -- W83627EHF
LAN - RTL 8100/8110S
1394 -- VIA VT-6307/6308P
Clock Generator - ICS954129
DDR II * 4 (Max 4GB)
PCI Express X16 SLOT * 1
PCI Express X4 SLOT * 1
PCI 2.3 SLOT * 2
Controller:
Intersil 6316CR 4 Phase
Driver: Intersil 6614ACB
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
1
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7210
MS-7210
MS-7210
134Thursday, October 27, 2005
134Thursday, October 27, 2005
134Thursday, October 27, 2005
of
of
of
101
101
101
1
VRM_GD
VTT_PWG
PLTRST#2
HD_RST#
VRM 10.1
Intersil 6316CR
4-Phase PWM
PCI
EXPRESS
X16
Connector
Analog
Video
Out
IDE Primary
P.30
P.18
P.19
P.26
UltraDMA
33/66/100
Intel LGA775 Processor
FSB
H_PWRGD
H_CPURST#
Lakeport
GMCH
P.7~10
DMI
VRM_GD
PLRST#
P.3~5
DDRII
333/400/533
MHz
PWR_GD
PWR_GD
Block Diagram
PWR_GD
4 DDR II
DIMM
Modules
PCIRST#
MS7
VID_GD
RSMRST#
HD_RST#
PLTRST#_MS7
LPC Bus
P.27
SLP_S4#
SLP_S3#
PSON#
LPC SIO
W83627EHF
Keyboard
Mouse
PLTRST#1
P.24
P.24
PCI
PWR_OK
ATX1
P.24
Floopy Parallel Serial
P.24 P.26 P.26
PCI Slot 1
P.20 P.20
PCI Slot 2
SERIAL ATA1
SERIAL ATA2
A A
SERIAL ATA3
SERIAL ATA4
USB2.0
P.26
P.26
P.26
P.26
ICH7
P.11~13
USB
USB Port0~ 7
P.25
RSMRST#
PWRBTN#
ALC880
PCIRST#_LAN
PCIRST#_1394
Azalia Codec
PCI LAN
RTL
8100C/8110S
1394
VIA VT-
6307/6308P
P.23
P.21
P.22
PCI
PWRBTIN
FWH
FP_RST#
JFP1
P.28
PLTRST#1
1
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
MS-7210
MS-7210
MS-7210
234Monday, October 24, 2005
234Monday, October 24, 2005
234Monday, October 24, 2005
of
of
of
101
101
101
8
7
6
5
4
3
2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name
GPIO[0] BM_BUSY# AB18 I/O Vcc3p3 N Y 5 Input strapped hi
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
GPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] unmuxed AC18 I/O Vcc3p3 N Y 3.3 Input strapped hi
GPIO[8] unmuxed E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME#
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-up
FPGI[1] 5 Main 3.3 pull-up
FPGI[2] 4 Main 3.3 pull-up
FPGI[3] 3 Main 3.3 pull-up
FPGI[4] 30 Main 3.3 pull-down
PCI Config.
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input WOL#
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input BIOS_WP#
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT#
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input strapped hi
C C
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 FANTYP_DET
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input NC
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change NC
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 NC
GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#3
GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 1 NC
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 NC
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
B B
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A PGNT#4
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
DEVICE
MCP1 INT Pin
REQ#/GNT#
IDSEL
CLOCK
PIRQ#A
PCI SLOT 1
PIRQ#B
PIRQ#C
PIRQ#D
PREQ#0
PGNT#0
AD16
PCI_CLK0
PIRQ#B
PCI SLOT 2
PIRQ#C
PIRQ#D
PIRQ#A
PCI LAN
PIRQ#E
PCI 1394 PIRQ#F
PREQ#1
PGNT#1
PREQ#3
PGNT#3
PREQ#4
AD19
AD20
PCI_CLK1AD17
LAN_PCLK
1394_PCLK
PGNT#4
DDRII DIMM Config.
DEVICE ADDRESS
DIMM 1
DIMM 2
A0H
A2H
A4H
DIMM 2
A6H
CLOCK
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
MCLK_A3/MCLK_A#3
MCLK_A4/MCLK_A#4
MCLK_A5/MCLK_A#5
MCLK_B0/MCLK_B#0
MCLK_B1/MCLK_B#1DIMM 3
MCLK_B2/MCLK_B#2
MCLK_B3/MCLK_B#3
MCLK_B4/MCLK_B#4
MCLK_B5/MCLK_B#5
JUMPER SETTING
JBAT1
JCI1
(1-2)NORMAL
Chassis Intrision
Open
Normal
Chassis Open(1-2)
(2-3)CLEAR
A A
MSI
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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7
6
5
4
3
Date: Sheet
2
MICRO-STAR INt'L CO., LTD.
GPIO MAP
GPIO MAP
GPIO MAP
MS-7210
MS-7210
MS-7210
of
of
of
334Monday, October 24, 2005
334Monday, October 24, 2005
334Monday, October 24, 2005
1
101
101
101
8
7
6
5
4
3
2
1
CPU SIGNAL BLOCK
VCC_VRM_SENSE
VSS_VRM_SENSE
D D
H_INIT#11
H_BPRI#7
H_A20M#11
R12 X_62R0402R12 X_62R0402
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_IERR#
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_TESTHI13
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_DBI#[0..3]7
H_FERR#11
H_STPCLK#11
H_DBSY#7
H_DRDY#7
H_TRDY#7
H_D#[0..63]7
THERMDA_CPU24
VTIN_GND24
TRMTRIP#11
H_PROCHOT#30
R8
X_0R0402R8X_0R0402
H_ADS#7
H_LOCK#7
H_BNR#7
H_HIT#7
H_HITM#7
H_DEFER#7
H_IGNNE#11
ICH_H_SMI#11
H_FSBSEL09,17
H_FSBSEL19,17
H_FSBSEL29,17
H_PWRGD11
H_CPURST#7
C C
H_SLP#11
B B
A A
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
H_A#[3..31]7
U3A
U3A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
H_D#53
D53#
D52#
C14
H_D#52
D51#
A14
C15
H_D#50
H_D#51
D50#
D49#
D17
H_D#49
AJ6
AJ5
A35#
D48#
D20
G22
H_D#47
H_D#48
AH5
A34#
A33#
D47#
D46#
D22
H_D#46
H_A#31
AH4
AG5
A32#
D45#
E22
G21
H_D#45
H_D#44
H_A#30
AG4
A31#
A30#
D44#
D43#
F21
H_D#43
H_A#28
H_A#29
AG6
AF4
A29#
D42#
F20
E21
H_D#41
H_D#42
H_A#27
AF5
A28#
A27#
D41#
D40#
E19
H_D#40
H_A#26
H_A#25
AB4
AC5
A26#
D39#
F18
E18
H_D#38
H_D#39
H_A#24
AB5
A25#
A24#
D38#
D37#
F17
H_D#37
H_A#23
H_A#22
AA5
AD6
A23#
D36#
G17
G18
H_D#36
H_D#35
H_A#21
AA4
A22#
A21#
D35#
D34#
E16
H_D#34
H_A#18
H_A#19
H_A#20
A20#Y4A19#Y6A18#W6A17#
D33#
D32#
E15
G16
G15
H_D#32
H_D#33
H_D#31
H_A#17
H_A#15
H_A#14
H_A#16
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D31#
D30#
D29#
D28#
D27#
F15
F14
G14
G13
H_D#30
H_D#27
H_D#29
H_D#28
H_A#12
H_A#13
D26#
E13
D13
H_D#25
H_D#26
H_A#11
D25#
D24#
F12
H_D#24
H_A#10
H_A#9
U6
D23#
F11
D10
H_D#23
H_D#22
H_A#3
H_A#6
H_A#8
H_A#5
H_A#7
H_A#4
L5
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
H_D#17
H_D#19
H_D#20
H_D#21
H_D#18
H_D#16
AC2
D11
C12
H_D#15
H_D#14
DBR#
D14#
D13#
B12
H_D#13
AJ3
AN4
AN3
AN6
AN5
ITP_CLK1
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D12#D8D11#
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
B10
A11
A10
C11
H_D#8
H_D#7
H_D#9
H_D#12
H_D#10
H_D#11
TP1TP1
AK3
ITP_CLK0
H_D#5
H_D#6
1
VID5
AM7
AM5
AL4
VID6#
RSVD#AM7
H_D#2
H_D#3
H_D#4
VID3
VID4
VID2
VID1
AK4
AL6
AM3
AL5
VID5#
VID4#
VID3#
VID2#
VID1#
VID_SELECT
GTLREF0
GTLREF1
GTLREF_SEL
GTLREF2
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD#G6
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B4
H_D#0
H_D#1
VID[0..5] 24,30
VID0
AM2
VID0#
VID_SELECT
AN7
H1
H2
H29
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11 MSID1MSID1
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
H_FORCEPH
AK6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
U3
1
U2
1
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
TP_GTLREF_SEL
MCH_GTLREF_CPU
RN72 8P4R-62R0402RN72 8P4R-62R0402
R7 X_130R1%0402R7 X_130R1%0402
H_FORCEPH 30
CK_H_CPU# 17
CK_H_CPU 17
TP3TP3
TP4TP4
R9 100R1%0402R9 100R1%0402
R11 100R1%0402R11 100R1%0402
R10 X_60.4R1%0402R10 X_60.4R1%0402
R14 X_60.4R1%0402R14 X_60.4R1%0402
R13 60.4R1%0402R13 60.4R1%0402
R15 60.4R1%0402R15 60.4R1%0402
1
TP5TP5
1
TP6TP6
1
TP7TP7
1
TP8TP8
H_ADSTB#1 7
H_ADSTB#0 7
H_DSTBP#3 7
H_DSTBP#2 7
H_DSTBP#1 7
H_DSTBP#0 7
H_DSTBN#3 7
H_DSTBN#2 7
H_DSTBN#1 7
H_DSTBN#0 7
H_NMI 11
H_INTR 11
CPU_GTLREF0 5
1
MCH_GTLREF_CPU 7
H_REQ#[0..4] 7
RN2 8P4R-62R0402RN2 8P4R-62R0402
H_BR#0
H_TESTHI1
RN3 8P4R-62R0402RN3 8P4R-62R0402
1
2
3
4
5
6
7
8
H_RS#[0..2] 7
H_BR#0
TP2TP2
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
V_FSB_VTT
VTT_OUT_LEFT
VCC_VRM_SENSE 30
VSS_VRM_SENSE 30
VTT_OUT_LEFT
VTT_OUT_LEFT 5
H_BR#0 7
VTT_OUT_LEFT 5
C5
X_C0.1U16Y0402C5X_C0.1U16Y0402
VTT_OUT_RIGHT5,6
MSID1 6
VTT_OUT_LEFT
V_FSB_VTT
BSEL
1
02
FSB FREQUENCY
TABLE
267 MHZ (1067)000
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN1 8P4R-680RRN1 8P4R-680R
VID1
1
VID2
VID3
VID4
VID0
VID5
C2
C1
C0.1U16Y0402C1C0.1U16Y0402
X_C0.1U16Y0402C2X_C0.1U16Y0402
VTT_OUT_RIGHT
C3 C0.1U16Y0402C3 C0.1U16Y0402
C4 X_C0.1U16Y0402C4 X_C0.1U16Y0402
PLACE BPM TERMINATION NEAR CPU
PLACE AT CPU END OF ROUTE
R16 X_130R1%0402R16 X_130R1%0402
1
2
3
4
5
6
7
8
RN73 8P4R-62R0402RN73 8P4R-62R0402
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
RN7
RN7
1
3
5
7
8P4R-470R0402
8P4R-470R0402
H_FSBSEL1
2
H_FSBSEL0
4
H_FSBSEL2
6
8
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN75 8P4R-680RRN75 8P4R-680R
RN4 8P4R-62R0402RN4 8P4R-62R0402
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN5 8P4R-62R0402RN5 8P4R-62R0402
1
2
3
4
5
6
7
8
RN6 8P4R-62R0402RN6 8P4R-62R0402
H_PROCHOT#VTT_OUT_RIGHT
H_CPURST#
H_TESTHI13
MSID0
VID_SELECT
H_CPURST# 7VTT_OUT_LEFT5
MSID0 6
H_FSBSEL1 9,17
H_FSBSEL0 9,17
H_FSBSEL2 9,17
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TMS
H_TDI
H_BPM#2
H_BPM#4
H_TRST#
H_IERR#
H_TCK
H_PROCHOT# 30
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Signals
Intel LGA775 - Signals
Intel LGA775 - Signals
101
101
MS-7210
MS-7210
MS-7210
2
434Monday, October 24, 2005
434Monday, October 24, 2005
434Monday, October 24, 2005
1
101
of
of
of
8
VCCP
AF9
AF8
AF22
AF21
U3B
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
U3B
VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
VCCP
VCC#AF8
VCC#AF22
VCC#AF21
VCC#Y29
VCC#Y30
VCC#Y8
Y8
Y29
Y30
VCC#AF9
VCC#Y28
Y28
VCCP
D D
C C
AG14
AG12
AG11
VCC#AG14
VCC#AG12
VCC#AG11
VCC#Y25
VCC#Y26
VCC#Y27
Y25
Y26
Y27
AG19
AG18
AG15
VCC#AG19
VCC#AG18
VCC#AG15
VCC#W8W8VCC#Y23
VCC#Y24
Y23
Y24
AG21
VCC#AG21
VCC#W30
W30
AG26
AG25
AG22
VCC#AG26
VCC#AG25
VCC#AG22
VCC#W27
VCC#W28
VCC#W29
W27
W28
W29
AG29
AG28
AG27
VCC#AG29
VCC#AG28
VCC#AG27
VCC#W24
VCC#W25
VCC#W26
W24
W25
W26
7
AG30
AG9
AG8
VCC#AG9
VCC#AG8
VCC#AG30
VCC#U8
VCC#V8
VCC#W23
V8
U8
W23
AH14
AH12
AH11
VCC#AH14
VCC#AH12
VCC#AH11
VCC#U28
VCC#U29
VCC#U30
U28
U29
U30
AH19
AH18
AH15
VCC#AH19
VCC#AH18
VCC#AH15
VCC#U25
VCC#U26
VCC#U27
U25
U26
U27
AH25
AH22
AH21
VCC#AH25
VCC#AH22
VCC#AH21
VCC#T8
VCC#U23
VCC#U24
T8
U23
U24
AH27
AH26
AH28
VCC#AH27
VCC#AH26
VCC#AH28
VCC#T28
VCC#T29
VCC#T30
T28
T29
T30
AH8
AH29
AH30
VCC#AH8
VCC#AH29
VCC#AH30
VCC#T25
VCC#T26
VCC#T27
T25
T26
T27
AH9
AJ11
AJ12
VCC#AH9
VCC#AJ11
VCC#T23
VCC#T24
R8
T23
T24
6
AJ14
AJ15
AJ18
VCC#AJ12
VCC#AJ14
VCC#AJ15
VCC#N8
VCC#P8
VCC#R8
P8
N8
N30
AJ19
AJ21
AJ22
VCC#AJ18
VCC#AJ19
VCC#AJ21
VCC#N28
VCC#N29
VCC#N30
N27
N28
N29
AJ8
AJ25
AJ26
VCC#AJ22
VCC#AJ25
VCC#AJ26
VCC#N25
VCC#N26
VCC#N27
N24
N25
N26
AJ9
AK11
VCC#AJ8
VCC#AJ9
VCC#AK11
VCC#M8
VCC#N23
VCC#N24
M8
N23
AK12
AK14
AK15
VCC#AK12
VCC#AK14
VCC#AK15
VCC#M28
VCC#M29
VCC#M30
M28
M29
M30
AK18
AK19
AK21
VCC#AK18
VCC#AK19
VCC#M26
VCC#M27
M25
M26
M27
AK22
AK25
AK26
VCC#AK21
VCC#AK22
VCC#AK25
VCC#M23
VCC#M24
VCC#M25
L8
M23
M24
AL11
AK8
AK9
VCC#AK8
VCC#AK9
VCC#AK26
VCC#K30
VCC#K8
VCC#L8
K8
K29
K30
5
AL12
AL14
AL15
VCC#AL11
VCC#AL12
VCC#AL14
VCC#K27
VCC#K28
VCC#K29
K26
K27
K28
AL18
AL19
AL21
VCC#AL15
VCC#AL18
VCC#AL19
VCC#K24
VCC#K25
VCC#K26
K23
K24
K25
AL22
AL25
AL26
VCC#AL21
VCC#AL22
VCC#AL25
VCC#J8
VCC#J9
VCC#K23
J8
J9
J30
AL29
AL30
AL8
VCC#AL26
VCC#AL29
VCC#AL30
VCC#J28
VCC#J29
VCC#J30
J27
J28
J29
AL9
AM11
VCC#AL8
VCC#AL9
VCC#AM11
VCC#J25
VCC#J26
VCC#J27
J25
J26
AM12
AM14
AM15
VCC#AM12
VCC#AM14
VCC#AM15
VCC#J22
VCC#J23
VCC#J24
J22
J23
J24
AM18
AM19
AM21
VCC#AM18
VCC#AM19
VCC#AM21
VCC#J19
VCC#J20
VCC#J21
J19
J20
J21
AM22
AM25
AM26
VCC#AM22
VCC#AM25
VCC#AM26
VCC#J14
VCC#J15
VCC#J18
J14
J15
J18
4
AM8
AM29
AM30
VCC#AM8
VCC#AM29
VCC#AM30
VCC#J11
VCC#J12
VCC#J13
J11
J12
J13
AM9
AN11
AN12
VCC#AM9
VCC#AN11
VCC#AN9
VCC#J10
J10
AN8
AN9
AN14
AN15
AN18
VCC#AN12
VCC#AN14
VCC#AN15
VTT_OUT_RIGHT
VCC#AN29
VCC#AN30
VCC#AN8
AN26
AN29
AN30
AN19
AN21
AN22
VCCA
VSSA
VCC#AN18
VCC#AN19
VCC#AN21
VCC#AN22
VCCPLL
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
VCC#AN26
1122334
AN25
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
4
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
3
H_VCCA
H_VSSA
H_VCCA
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
1
TP9TP9
V_FSB_VTT
VTT_OUT_RIGHT 4,6
VTT_OUT_LEFT 4
2
V_FSB_VTT
C6
C6
C10U10Y0805
C10U10Y0805
C7
C7
X_C10U10Y0805
X_C10U10Y0805
C8
C8
C10U10Y0805
C10U10Y0805
CAPS FOR FSB GENERIC
1
R19
C9
C1U16YC9C1U16Y
R21
R21
680R0402
680R0402
R19
10R0402
10R0402
VTT_PWG
Q1
Q1
N-MMBT3904_SOT23
N-MMBT3904_SOT23
7
C10
C10
X_C0.1U16Y0402
X_C0.1U16Y0402
C14
C14
X_C1U16Y
X_C1U16Y
CPU_GTLREF0 4
6
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
C13
C13
C10U10Y0805
C10U10Y0805
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Power
Intel LGA775 - Power
Intel LGA775 - Power
MS-7210
MS-7210
MS-7210
2
534Monday, October 24, 2005
534Monday, October 24, 2005
534Monday, October 24, 2005
1
101
101
101
of
of
of
L1 X_10U125m_0805-1L1 X_10U125m_0805-1
CP1
CP1
1 2
X_COPPER
X_COPPER
5
4
C11
C11
C1U16Y
C1U16Y
C12
C12
X_C10U10Y0805
X_C10U10Y0805
3
R18
VTT_OUT_RIGHT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
A A
R18
124R1%0402
124R1%0402
VID_GD#29,30
8
R20
R20
210R1%0402
210R1%0402
VTT_OUT_LEFT
VCC5_SB
R22
R22
1KR0402
1KR0402
R23 4.7KR0402R23 4.7KR0402
8
7
6
5
4
3
2
1
MSID04
MSID14
VTT_OUT_RIGHT4,5
R25
R25
R24
R24
60.4R1%0402
U3C
U3C
VSS#A12
VSS#A15
VSS#A18
VSS#A2
VSS#A21
VSS#A24
VSS#A6
VSS#A9
VSS#AA23
VSS#AA24
VSS#AA25
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
H_COMP6
H_COMP7
AE3
COMP6Y3COMP7
VSS#AE29
VSS#AE30
AE5
AE29
AE30
60.4R1%0402
D1
AE4
D14
RSVD#D1
RSVD#D14
RSVD#AE4
VSS#AE5
VSS#AE7
VSS#AF10
VSS#AF13
AE7
AF10
AF13
TP12TP12
1
E23
RSVD#E5E5RSVD#E6E6RSVD#E7
RSVD#E23
VSS#AF16
VSS#AF17
VSS#AF20
AF16
AF17
AF20
TP10TP10
TP11TP11
1
1
F23
E7
VSS#AF23
VSS#AF24
AF23
AF24
AF25
TP13TP13
1
B13
F6
IMPSEL#
RSVD#F23
RSVD#B13
VSS#AF25
VSS#AF26
VSS#AF27
AF26
AF27
AF28
J3
N4
RSVD#J3
VSS#AF28
VSS#AF29
VSS#AF3
AF3
AF29
AF30
P5
RSVD#P5
RSVD#N4
VSS#AF30
VSS#AF6
VSS#AF7
AF6
AF7
AG10
W1
AC4
MSID[1]V1MSID[0]
RSVD#AC4
VSS#AG10
VSS#AG13
VSS#AG16
AG13
AG16
AG17
VSS#AG17
VSS#AG20
AG20
60.4R1%0402
60.4R1%0402
D D
A12
A15
A18
A2
A21
A24
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
C C
B B
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE20
AE24
AE25
AE26
AE27
AE28
AB7
AE2
2005 Perf FMB 0 0
2005 Value FMB 0 1
Y2
V6
V3
V30
V29
V28
V27
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#AG23
VSS#AG24
VSS#AG7
AH1
AG7
AG23
AG24
W4
VSS#V7V7VSS#V6
VSS#W7W7VSS#W4
VSS#AH1
VSS#AH10
VSS#AH13
AH10
AH13
VSS#V30
VSS#AH16
VSS#AH17
AH16
AH17
AH20
VSS#V3
VSS#V29
VSS#V28
VSS#AH20
VSS#AH23
VSS#AH24
AH3
AH23
AH24
V26
VSS#V27
VSS#V26
VSS#AH3
VSS#AH6
AH6
V25
V24
VSS#V25
VSS#V24
VSS#AH7
VSS#AJ10
AH7
AJ10
V23
AJ13
MSID1 MSID0
T3
U1
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#V23
VSS#AJ13
VSS#AJ16
VSS#AJ17
VSS#AJ20
VSS#AJ23
AJ16
AJ17
AJ20
AJ23
AJ24
R30
R5
VSS#R7R7VSS#R5
VSS#AJ24
VSS#AJ27
VSS#AJ28
AJ27
AJ28
AJ29
R29
R28
R27
VSS#R30
VSS#R29
VSS#R28
VSS#AJ29
VSS#AJ30
VSS#AJ4
AJ4
AJ7
AJ30
R26
R25
VSS#R27
VSS#R26
VSS#R25
VSS#AJ7
VSS#AK10
VSS#AK13
AK10
AK13
R24
R23
R2
VSS#R24
VSS#R23
VSS#AK16
VSS#AK17
AK2
AK16
AK17
P4
VSS#P7P7VSS#P4
VSS#R2
VSS#AK2
VSS#AK20
VSS#AK23
AK20
AK23
P30
P29
P28
VSS#P30
VSS#P29
VSS#AK24
VSS#AK27
AK24
AK27
AK28
P27
P26
P25
VSS#P28
VSS#P27
VSS#P26
VSS#AK28
VSS#AK29
VSS#AK30
AK5
AK29
AK30
P24
P23
VSS#P25
VSS#P24
VSS#P23
VSS#AK5
VSS#AK7
VSS#AL10
AK7
AL10
N3
VSS#N7N7VSS#N6N6VSS#N3
VSS#AL13
VSS#AL16
VSS#AL17
AL13
AL16
AL17
AL20
M1
L6
VSS#L7L7VSS#L6
VSS#M7M7VSS#M1
VSS#AL20
VSS#AL23
VSS#AL24
AL23
AL24
AL27
L30
L29
L3
VSS#L3
VSS#L30
VSS#AL27
VSS#AL28
VSS#AL3
AL3
AL7
AL28
L28
L27
VSS#L29
VSS#L28
VSS#L27
VSS#AL7
VSS#AM1
VSS#AM10
AM1
AM10
L26
L25
L24
VSS#L26
VSS#L25
VSS#L24
VSS#AM13
VSS#AM16
VSS#AM17
AM13
AM16
AM17
K5
L23
VSS#K7K7VSS#K5
VSS#L23
VSS#AM20
VSS#AM23
VSS#AM24
AM20
AM23
AM24
K2
J7
VSS#J4J4VSS#J7
VSS#K2
VSS#AM27
VSS#AM28
VSS#AM4
AM4
AM27
AM28
H8
H9
VSS#H9
AN1
H6
H7
VSS#H6
VSS#H7
VSS#H8
VSS#AN1
VSS#AN10
VSS#AN13
AN10
AN13
H28
H3
VSS#H3
VSS#H28
VSS#AN16
VSS#AN17
VSS#AN2
AN2
AN16
AN17
H25
H26
H27
VSS#H26
VSS#H27
VSS#AN20
VSS#AN23
AN20
AN23
AN24
H22
H23
H24
VSS#H23
VSS#H24
VSS#H25
VSS#AN24
VSS#AN27
VSS#AN28
AN27
AN28
H20
H21
VSS#H20
VSS#H21
VSS#H22
VSS#B1B1VSS#B11
B11
H17
H18
H19
VSS#H14
VSS#H13
VSS#H17
VSS#H18
VSS#H19
VSS#H12
VSS#H11
VSS#H10
VSS#G1
VSS#F7
VSS#F4
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E8
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E2
VSS#E17
VSS#E14
VSS#E11
VSS#D9
VSS#D6
VSS#D5
VSS#D3
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C7
VSS#C4
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B8
VSS#B5
VSS#B24
VSS#B20
VSS#B17
VSS#B14
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B14
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
Optics Orientation Holes
FM4
1
1
FM4
OPTICS-M120
OPTICS-M120
FM9
FM9
OPTICS-M120
OPTICS-M120
FM12
FM12
OPTICS-M100
OPTICS-M100
FM17
FM17
OPTICS-M100
OPTICS-M100
8
FM1
FM1
OPTICS-M120
OPTICS-M120
FM7
FM7
OPTICS-M120
OPTICS-M120
A A
FM11
FM11
OPTICS-M100
OPTICS-M100
FM16
FM16
OPTICS-M100
OPTICS-M100
FM2
FM2
1
OPTICS-M120
OPTICS-M120
FM10
FM10
1
OPTICS-M120
OPTICS-M120
FM13
FM13
OPTICS-M100
OPTICS-M100
FM18
FM18
OPTICS-M100
OPTICS-M100
1
1
FM3
FM3
OPTICS-M120
OPTICS-M120
FM14
FM14
OPTICS-M100
OPTICS-M100
FM19
FM19
OPTICS-M100
OPTICS-M100
1
7
FM5
FM5
OPTICS-M120
OPTICS-M120
FM15
FM15
OPTICS-M100
OPTICS-M100
FM20
FM20
OPTICS-M100
OPTICS-M100
1
6
9
8
H1
7
6
MH1H1MH1
H5
7
6
MH1H5MH1
2
3
5
4
9
8
2
3
5
4
9
8
H2
7
6
MH1H2MH1
H6
7
6
MH1H6MH1
2
3
5
4
9
8
2
3
5
4
5
9
8
H3
7
6
MH1H3MH1
H7
7
6
MH1H7MH1
2
3
5
4
9
8
2
3
5
4
4
9
8
H4
7
6
MH1H4MH1
H8
7
6
MH1H8MH1
2
3
5
4
9
8
2
3
5
4
MSI
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - GND
Intel LGA775 - GND
Intel LGA775 - GND
101
101
MS-7210
MS-7210
MS-7210
2
634Monday, October 24, 2005
634Monday, October 24, 2005
634Monday, October 24, 2005
1
101
of
of
of
8
H_A#[3..31]4
D D
H_ADSTB#04
H_ADSTB#14
H_REQ#[0..4]4
R29
R29
H_RS#[0..2]4
R28
R28
16.9R1%
16.9R1%
H_TRDY#4
H_DBSY#4
H_DRDY#4
CK_H_MCH17
CK_H_MCH#17
PWR_GD12,29
H_CPURST#4
H_BR#04
H_BPRI#4
H_BNR#4
H_LOCK#4
H_ADS#4
H_HIT#4
H_HITM#4
H_DEFER#4
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF_CPU
HXSCOMP
C15
C15
X_C2.2P50N0402
X_C2.2P50N0402
C C
B B
PLTRST#_ICH711
ICH_SYNC#12
V_FSB_VTT
A A
8
60.4R1%0402
60.4R1%0402
7
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
U6A
AA37
AA41
AJ12
K38
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
M36
V35
D42
U39
U40
W42
E41
D41
K36
G37
E42
U41
W41
P40
W40
U42
V41
Y40
Y43
M31
M29
C30
M18
A28
C27
B27
D27
D28
J39
J42
J37
F38
T40
T43
AJ9
U6A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
VCC
VCC
VCC
V_FSB_VTT
VCC
VCC
RSVRD
AA35
H_A#3 H_D#0
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
AF6
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
L15
U27
R27
M15
AA42
AA34
AA38
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
R31
R31
PLACE DIVIDER RESISTOR NEAR VTT
301R1%
301R1%
R33 62R0402R33 62R0402
R35
R35
C18
C18
84.5R1%
84.5R1%
C0.01U25X0402
C0.01U25X0402
AF7
VCC
VCC
RSVRD
RSVRD
A43
AF8
VCC
RSVRD
M11
AF9
AF10
VCC
RSVRD
AG25
AG26
AF11
VCC
VCC
RSVRD
RSVRD
AG27
6
AF12
AF13
VCC
RSVRD
AJ24
AJ27
AF14
VCC
VCC
RSVRD
RSVRD
AK40
AF30
AG2
VCC
RSVRD
AL39
AW17
HXSWING
AG3
VCC
VCC
RSVRD
RSVRD
AW18
V_1P5_CORE
AG4
AG5
AG6
AG7
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
AY14
BC16
AD30
AC34
AG8
VCC
VCC
RSVRD
RSVRD
Y30
AG9
AG10
VCC
RSVRD
Y33
AF31
AG11
VCC
VCC
RSVRD
RSVRD
AD31
AG12
VCC
RSVRD
U30
AG13
VCC
RSVRD
V31
AG14
VCC
RSVRD
AA30
AH1
AH2
VCC
RSVRD
AK21
AC30
AH4
VCC
VCC
RSVRD
RSVRD
AJ23
AJ5
AJ13
VCC
RSVRD
AJ26
AL29
VCC
RSVRD
5
AJ14
AK2
AK3
AK4
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
AJ21
AL20
AL26
AK27
R30
R30
124R1%0402
124R1%0402
AK14
AK15
AK20
R15
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
V30
AJ29
AG29
V_FSB_VTT
R34
R34
210R1%0402
210R1%0402
R17
VCC
BC43NCBC42
VCC
NC
R18
VCC
4
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
E35
B43NCB42NCB41
BC2NCBC1
BB43
BB2NCBB1NCBA2
R32 10R0402R32 10R0402
C42
AW2
AV27NCAV26
AW26
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
C17
C17
C16
C16
X_C220P50N0402
X_C220P50N0402
C0.1U16Y0402
C0.1U16Y0402
A42
MCH_GTLREF_CPU
V21
V22
V23
VCC
VCC
VCC
VCC
VCC
VCC
Y17
Y18
Y19
V25
V27
W17
W18
W19
W20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y21
Y23
Y25
Y27
AA15
AA17
MCH_GTLREF_CPU 4
W22
VCC
VCC
AA18
W24
VCC
VCC
AA19
W26
VCC
VCC
AA20
W27
Y15
M17
VCC
VCC
VCC
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
3
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
Lakeport
Lakeport
V_1P5_CORE
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
CAPS SHOULD BE PLACED NEAR MCH PIN
7
6
5
4
3
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
2
H_D#[0..63] 4
H_DBI#[0..3] 4
H_DSTBP#0 4
H_DSTBN#0 4
H_DSTBP#1 4
H_DSTBN#1 4
H_DSTBP#2 4
H_DSTBN#2 4
H_DSTBP#3 4
H_DSTBN#3 4
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU
Intel Lakeport - CPU
Intel Lakeport - CPU
MS-7210
MS-7210
MS-7210
2
1
101
101
734Monday, October 24, 2005
734Monday, October 24, 2005
734Monday, October 24, 2005
1
101
of
of
of
8
7
6
5
4
3
2
1
DATA_A37
DATA_A38
AT32
AR34
SADQ37
SBDQ35
AP27
AM31
DATA_B35
DATA_B36
DATA_A40
DATA_A39
AU37
AR41
SADQ38
SADQ39
SBDQ36
SBDQ37
AP31
AR27
DATA_B37
DATA_B38
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
DATA_B40
DATA_B39
SCKE_A[0..3]14,16
DATA_A43
DATA_A44
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
DATA_B42
DATA_B41
5
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_B43
DATA_B44
DATA_A48
DATA_A47
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_B46
DATA_B45
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AL34
AM34
DATA_B47
DATA_B48
SADQ50
SBDQ48
DATA_A[0..63]14
DATA_A16
DATA_A21
DATA_A6
DATA_A4
AN1
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
DATA_B2
DATA_A5
AP4
SADQ5
SBDQ3
AP9
DATA_B3
AU5
SADQ6
SBDQ4
AJ11
DATA_B4
DATA_A7
AU2
SADQ7
SBDQ5
AL9
DATA_B5
DATA_A8
AW3
SADQ8
SBDQ6
AM10
DATA_B6
DATA_A9
AY3
SADQ9
SBDQ7
AP6
DATA_B7
DATA_A10
DATA_A11
BA7
BB7
SADQ10
SBDQ8
AV6
AU7
DATA_B8
DATA_B9
DATA_A12
DATA_A13
AV1
AW4
SADQ11
SADQ12
SBDQ9
SBDQ10
AV12
AM11
DATA_B11
DATA_B10
DATA_A14
DATA_A15
BC6
AY7
SADQ13
SADQ14
SBDQ11
SBDQ12
AR5
AR7
DATA_B12
DATA_B13
DATA_A17
AW12
AY10
SADQ15
SADQ16
SBDQ13
SBDQ14
AR12
AR10
DATA_B14
DATA_B15
DATA_A0
DATA_A1
DATA_A3
D D
C C
B B
A A
VCC_DDR
SCS_A#[0..3]14,16
MAA_A[0..13]14,16
ODT_A[0..3]14,16
SBS_A[0..2]14,16
P_DDR0_A14
N_DDR0_A14
P_DDR1_A14
N_DDR1_A14
P_DDR2_A14
N_DDR2_A14
P_DDR3_A14
N_DDR3_A14
P_DDR4_A14
N_DDR4_A14
P_DDR5_A14
N_DDR5_A14
R36
R36
80.6R1%0402
80.6R1%0402
R39
R39
80.6R1%0402
80.6R1%0402
C21
C21
C0.1U16Y0402
C0.1U16Y0402
DQS_A014
DQS_A#014
DQS_A114
DQS_A#114
DQS_A214
DQS_A#214
DQS_A314
DQS_A#314
DQS_A414
DQS_A#414
DQS_A514
DQS_A#514
DQS_A614
DQS_A#614
DQS_A714
DQS_A#714
8
U6B
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AK42
AK41
BA31
BB31
AH40
AH43
AU4
AR2
BA3
BB4
AY5
BB5
AY6
BA5
AM3
AL5
AJ6
AJ8
DATA_B[0..63]15
U6B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
Lakeport
Lakeport
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#14,16
CAS_A#14,16
WE_A#14,16
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_A
SMPCOMP_P
SMPCOMP_N
DATA_A2
AP3
AP2
AU3
AV4
SADQ0
SADQ1
SADQ2
SBDQ0
AL6
AL8
DATA_B0
DATA_B1
7
DATA_A18
DATA_A19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
DATA_B17
DATA_B16
DATA_A20
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
DATA_B18
DATA_B19
6
DATA_A22
DATA_A23
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
DATA_B21
DATA_B20
DATA_A24
DATA_A25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
DATA_B23
DATA_B22
DATA_A26
DATA_A27
AV20
AM21
SADQ25
SADQ26
SBDQ23
SBDQ24
AM24
AM23
DATA_B24
DATA_B25
DATA_A29
DATA_A28
AP17
AR17
SADQ27
SADQ28
SBDQ25
SBDQ26
AV24
AM26
DATA_B27
DATA_B26
DATA_A31
DATA_A30
AP20
AT20
SADQ29
SADQ30
SBDQ27
SBDQ28
AP21
AR21
DATA_B28
DATA_B29
DATA_A32
DATA_A33
AP32
AV34
SADQ31
SADQ32
SBDQ29
SBDQ30
AT24
AP24
DATA_B31
DATA_B30
DATA_A34
DATA_A35
AV38
AU39
SADQ33
SADQ34
SBDQ31
SBDQ32
AU27
AN29
DATA_B32
DATA_B33
DATA_A36
AV32
SADQ35
SADQ36
SBDQ33
SBDQ34
AR31
DATA_B34
DATA_A52
DATA_A51
AE40
AM41
SADQ51
SBDQ49
AJ34
AF32
DATA_B49
DATA_B50
DATA_A53
DATA_A54
AM42
AF41
SADQ52
SADQ53
SBDQ50
SBDQ51
AL31
AF34
DATA_B52
DATA_B51
SCKE_B[0..3]15,16
DATA_A56
DATA_A55
AF42
AD40
SADQ54
SADQ55
SBDQ52
SBDQ53
AJ32
AG35
DATA_B54
DATA_B53
DQM_A[0..7]14
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SBDQ54
SBDQ55
AD32
AC32
DATA_B55
DATA_B56
DQM_B[0..7]15
DATA_A60
DATA_A59
AA40
AE42
SADQ58
SADQ59
SBDQ56
SBDQ57
Y32
AD34
DATA_B57
DATA_B58
DATA_A61
DATA_A62
AE41
AB41
SADQ60
SADQ61
SBDQ58
SBDQ59
AF35
AA32
DATA_B60
DATA_B59
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
DATA_B61
DATA_B62
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SBDQ62
SBDQ63
AC35
DATA_B63
4
SCKE_A3
SCKE_A2
BC24
BA25
SACKE1
SACKE2
SBCKE0
BA14
AY16
SCKE_B0
SCKE_B1
SACKE3
SBCKE1
SBCKE2
BA13
BB13
SCKE_B3
SCKE_B2
DQM_A1
DQM_A0
AY2
AR3
SADM0
SBCKE3
AD39
DQM_B7
DQM_A2
BB10
SADM2
SADM1
SBDM6
SBDM7
AJ39
DQM_B6
DQM_A3
AP18
SADM3
SBDM5
AR38
DQM_B5
DQM_A4
AT34
SADM4
SBDM4
AR29
DQM_B4
DQM_A5
AP39
AP23
DQM_B3
DQM_A6
AG40
SADM6
SADM5
SBDM2
SBDM3
AP13
DQM_B2
DQM_A7
AC40
SADM7
SBDM1
AW7
DQM_B1
DQM_B0
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
AL11
BA40
AW41
BA41
AW40
BA23
AY24
BB23
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
AY42
AV40
AV43
AU40
AW23
AY23
AY17
AM8
AM6
AV7
AR9
AV13
AT13
AU23
AR23
AT29
AV29
AP36
AM35
AG34
AG32
AD36
AD38
AM29
AM27
AV9
AW9
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AM2
AM4
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13MAA_A13
ODT_B0
ODT_B1
ODT_B2
ODT_B3
SBS_B0
SBS_B1
SBS_B2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B
3
SCS_B#[0..3] 15,16
RAS_B# 15,16
CAS_B# 15,16
WE_B# 15,16
MAA_B[0..13] 15,16
ODT_B[0..3] 15,16
SBS_B[0..2] 15,16
DQS_B0 15
DQS_B#0 15
DQS_B1 15
DQS_B#1 15
DQS_B2 15
DQS_B#2 15
DQS_B3 15
DQS_B#3 15
DQS_B4 15
DQS_B#4 15
DQS_B5 15
DQS_B#5 15
DQS_B6 15
DQS_B#6 15
DQS_B7 15
DQS_B#7 15
P_DDR0_B 15
N_DDR0_B 15
P_DDR1_B 15
N_DDR1_B 15
P_DDR2_B 15
N_DDR2_B 15
P_DDR3_B 15
N_DDR3_B 15
P_DDR4_B 15
N_DDR4_B 15
P_DDR5_B 15
N_DDR5_B 15
C19
C19
X_C0.1U16Y0402
X_C0.1U16Y0402
PLACE 0.1UF CAP CLOSE TO MCH
VCC_DDR
R37
R37
MSI
2
MCH_VREF_A
R38
R38
1KR1%0402
1KR1%0402
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - Memory
Intel Lakeport - Memory
Intel Lakeport - Memory
C20
C20
C0.1U16Y0402
C0.1U16Y0402
MS-7210
MS-7210
MS-7210
834Monday, October 24, 2005
834Monday, October 24, 2005
834Monday, October 24, 2005
of
of
of
1
1KR1%0402
1KR1%0402
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
101
101
101
8
EXP_A_RXP_018
EXP_A_RXN_018
EXP_A_RXP_118
EXP_A_RXN_118
D D
C C
H_FSBSEL24,17
H_FSBSEL14,17
H_FSBSEL04,17
V_2P5_MCH
B B
V_2P5_MCH
V_1P5_CORE
EXP_A_RXP_218
EXP_A_RXN_218
EXP_A_RXP_318
EXP_A_RXN_318
EXP_A_RXP_418
EXP_A_RXN_418
EXP_A_RXP_518
EXP_A_RXN_518
EXP_A_RXP_618
EXP_A_RXN_618
EXP_A_RXP_718
EXP_A_RXN_718
EXP_A_RXP_818
EXP_A_RXN_818
EXP_A_RXP_918
EXP_A_RXN_918
EXP_A_RXP_1018
EXP_A_RXN_1018
EXP_A_RXP_1118
EXP_A_RXN_1118
EXP_A_RXP_1218
EXP_A_RXN_1218
EXP_A_RXP_1318
EXP_A_RXN_1318
EXP_A_RXP_1418
EXP_A_RXN_1418
EXP_A_RXP_1518
EXP_A_RXN_1518
EXP_EN_HDR18
DMI_ITP_MRP_011
DMI_ITN_MRN_011
DMI_ITP_MRP_111
DMI_ITN_MRN_111
DMI_ITP_MRP_211
DMI_ITN_MRN_211
DMI_ITP_MRP_311
DMI_ITN_MRN_311
CK_PE_100M_MCH17
CK_PE_100M_MCH#17
SDVO_CTRL_DATA18
SDVO_CTRL_CLK18
RN8
RN8
1
3
5
7
8P4R-10KR0402
8P4R-10KR0402
L2
L2
B_180L1500m_90
B_180L1500m_90
I = 70mA
EC1
EC1
X_.CD100U16EL11
X_.CD100U16EL11
B_C0.1U16Y0402
B_C0.1U16Y0402
V_2P5_DAC_FILTERED19
L3 X_600L200m_500-1L3 X_600L200m_500-1 L4 X_10U125m_0805-1L4 X_10U125m_0805-1
1 2
CP2
CP2
X_COPPER
X_COPPER
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
EXP_EN_HDR
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
2
4
6
EXTTS
8
R41 X_1KR0402R41 X_1KR0402
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_2P5_MCH
V_2P5_DAC_FILTERED
12
+
+
C33
C33
SEL0
SEL1
SEL2
NOA_6
C34
C34
C0.01U25X0402
C0.01U25X0402
7
U6C
U6C
G12
EXPARXP0
F12
EXPARXN0
D11
EXPARXP1
D12
EXPARXN1
J13
EXPARXP2
H13
EXPARXN2
E10
EXPARXP3
F10
EXPARXN3
J9
EXPARXP4
H10
EXPARXN4
F7
EXPARXP5
F9
EXPARXN5
C4
EXPARXP6
D3
EXPARXN6
G6
EXPARXP7
J6
EXPARXN7
K9
EXPARXP8
K8
EXPARXN8
F4
EXPARXP9
G4
EXPARXN9
M6
EXPARXP10
M7
EXPARXN10
K2
EXPARXP11
L1
EXPARXN11
U11
EXPARXP12
U10
EXPARXN12
R8
EXPARXP13
R7
EXPARXN13
P4
EXPARXP14
N3
EXPARXN14
Y10
EXPARXP15
Y11
EXPARXN15
F20
EXP_EN
Y7
DMI RXP0
Y8
DMI RXN0
AA9
DMI RXP1
AA10
DMI RXN1
AA6
DMI RXP2
AA7
DMI RXN2
AC9
DMI RXP3
AC8
DMI RXN3
B14
GCLKP
B16
GCLKN
F15
SDVOCTRLDATA
E15
SDVOCTRLCLK
F21
BSEL0
H21
BSEL1
L20
BSEL2
AK17
RSV_TP[0]
AL17
RSV_TP[1]
K21
EXP_SLR
AK23
RSV_TP[2]
AK18
RSV_TP[3]
L21
RSV_TP[4]
L18
RSV_TP[5]
N21
RSV_TP[6]
C21
VCCAHPLL
B20
VCCAMPLL
C19
VCCADPLLA
B19
VCCADPLLB
B17
VCCA_EXPPLL
D19
VCC2
C18
VCCADAC
B18
VCCADAC
A18
VSSA_DAC
Lakeport
Lakeport
V_FSB_VTT
I = 60mA
VCCA_MPLL
C35
C35
C1U16Y
C1U16Y
6
V_1P5_CORE VCC_DDR
AA26
AB17
AB18
AB19
AB20
AB24
AB25
AB26
AB27
AA24
VCC
AC15
AC17
AC18
AC20
AD17
AD19
AC24
AC26
AC27
AD15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
B23
A24
B24
B25
B26
C23
C25
C26
VTT
VTT
VTT
VTT
VTT
VTT
VTT
D23
VTT
VTT
VTT
F23
F27
E27
E23
E24
E26
D24
D25
H23
G23
VCC
VTT
AD21
VCC
VTT
J23
AD23
K23
AD25
AD26
AE17
AE18
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
L23
P23
N23
M23
V_1P5_CORE
VCC
VTT
AE20
VCC
AE22
VCC
AE24
VCC
AE26
VCC
VCC
AF21
AE27
AF23
VCC
VCC
AF15
AF25
AF17
VCC
VCC
AF26
VCC
VCC
AF19
AF27
VCC
VCC
AF29
VCC
AV18
AY43
VCCSM
VCC
AG15
AG17
AV21
VCCSM
VCCSM
VCC
VCC
AG18
5
AV23
AV31
VCCSM
VCC
AG19
AG20
AV42
AW13
VCCSM
VCCSM
VCC
VCC
AG21
AG22
VCCSM
VCC
I = 55mA
V_1P5_CORE V_1P5_CORE
1 2
CP3
CP3
X_COPPER
X_COPPER
VCCA_DPLLA
12
EC2
EC2
+
+
.CD220U10EL7
.CD220U10EL7
C36
C36
C0.1U16Y0402
C0.1U16Y0402
AW20
AW15
AW21
AW24
AW29
VCCSM
VCCSM
VCCSM
VCCSM
VCC
VCC
VCC
VCC
AJ15
AJ17
AJ18
AG23
AG24
L5 1U500m_0805L5 1U500m_0805
AW31
VCCSM
VCCSM
VCC
VCC
AJ20
AW34
AW35
VCCSM
AY41
VCCSM
VCCSM
BB16
BB20
VCCSM
AE4
BB24
BB28
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AE3
AE2
BB33
BB38
BB42
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AD8
AD12
AD10
1R1%0402
1R1%0402
1R1%0402
1R1%0402
BC13
BC18
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AD6
AD5
R48
R48
R49
R49
4
BC26
BC31
BC22
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AD4
AD2
AD1
BC35
BC40
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AC6
AC13
N9
N7
N5
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
Y13
AA5
AC5
AA13
I = 45mA
VCCA_GPLL
C37
C37
C10U10Y0805
C10U10Y0805
N12
N11
N10
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXPV9VCC_EXP
V13
V10
R11
R10
R5
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXPV7VCC_EXPV6VCC_EXP
V5
C38
C38
C10U10Y0805
C10U10Y0805
U7
U6
R13
VCC_EXP
VCC_EXP
U13
U8
VCC_EXP
VCC_EXP
VCC_EXP
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
EXPATXP8
EXPATXN8
EXPATXP9
EXPATXN9
EXPATXP10
EXPATXN10
EXPATXP11
EXPATXN11
EXPATXP12
EXPATXN12
EXPATXP13
EXPATXN13
EXPATXP14
EXPATXN14
EXPATXP15
EXPATXN15
EXP_COMPO
EXP_COMPI
DDC_DATA
DREFCLKINP
DREFCLKINN
ALLZTEST
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
HSYNC
VSYNC
RED
GREEN
BLUE
RED#
GREENB
BLUE#
DDC_CLK
IREF
EXTTS#
XORTEST
3
V_1P5_CORE
EXP_A_TXP_0
D14
EXP_A_TXN_0
C13
EXP_A_TXP_1
A13
EXP_A_TXN_1
B12
EXP_A_TXP_2
A11
EXP_A_TXN_2
B10
EXP_A_TXP_3
C10
EXP_A_TXN_3
C9
EXP_A_TXP_4
A9
EXP_A_TXN_4
B7
EXP_A_TXP_5
D7
EXP_A_TXN_5
D6
EXP_A_TXP_6
A6
EXP_A_TXN_6
B5
EXP_A_TXP_7
E2
EXP_A_TXN_7
F1
EXP_A_TXP_8
G2
EXP_A_TXN_8
J1
EXP_A_TXP_9
J3
EXP_A_TXN_9
K4
EXP_A_TXP_10
L4
EXP_A_TXN_10
M4
EXP_A_TXP_11
M2
EXP_A_TXN_11
N1
EXP_A_TXP_12
P2
EXP_A_TXN_12
T1
EXP_A_TXP_13
T4
EXP_A_TXN_13
U4
EXP_A_TXP_14
U2
EXP_A_TXN_14
V1
EXP_A_TXP_15
V3
EXP_A_TXN_15
W4
DMI_MTP_IRP_0
W2
DMI_MTN_IRN_0
Y1
DMI_MTP_IRP_1
AA2
DMI_MTN_IRN_1
AB1
DMI_MTP_IRP_2
Y4
DMI_MTN_IRN_2
AA4
DMI_MTP_IRP_3
AB3
DMI_MTN_IRN_3
AC4
AC12
AC11
D17
C17
F17
K17
H18
G17
J17
J18
N18
N20
J15
H15
A20
J20
H20
K18
GRCOMP
HSYNC
VSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
VGA_RED#
VGA_GREEN#
VGA_BLUE#
DDC_DATA
DDC_CLK
CK_96M_DREF
CK_96M_DREF#
DACREFSET
EXTTS
V_1P5_CORE
R40
R40
24.9R1%0402
24.9R1%0402
R42 B_255R1%R42 B_255R1%
PLACE CLOSE TO MCH
TP14TP14
1
TP15TP15
1
2
EXP_A_TXP_0 18
EXP_A_TXN_0 18
EXP_A_TXP_1 18
EXP_A_TXN_1 18
EXP_A_TXP_2 18
EXP_A_TXN_2 18
EXP_A_TXP_3 18
EXP_A_TXN_3 18
EXP_A_TXP_4 18
EXP_A_TXN_4 18
EXP_A_TXP_5 18
EXP_A_TXN_5 18
EXP_A_TXP_6 18
EXP_A_TXN_6 18
EXP_A_TXP_7 18
EXP_A_TXN_7 18
EXP_A_TXP_8 18
EXP_A_TXN_8 18
EXP_A_TXP_9 18
EXP_A_TXN_9 18
EXP_A_TXP_10 18
EXP_A_TXN_10 18
EXP_A_TXP_11 18
EXP_A_TXN_11 18
EXP_A_TXP_12 18
EXP_A_TXN_12 18
EXP_A_TXP_13 18
EXP_A_TXN_13 18
EXP_A_TXP_14 18
EXP_A_TXN_14 18
EXP_A_TXP_15 18
EXP_A_TXN_15 18
DMI_MTP_IRP_0 11
DMI_MTN_IRN_0 11
DMI_MTP_IRP_1 11
DMI_MTN_IRN_1 11
DMI_MTP_IRP_2 11
DMI_MTN_IRN_2 11
DMI_MTP_IRP_3 11
DMI_MTN_IRN_3 11
HSYNC 19
VSYNC 19
VGA_RED 19
VGA_GREEN 19
VGA_BLUE 19
DDC_DATA 19
DDC_CLK 19
CK_96M_DREF 17
CK_96M_DREF# 17
V_1P5_CORE
FOR 945G
1
V_1P5_CORE
VCC_DDR
VCC_DDR
C22
C22
C100P50N0805
C100P50N0805
C23
C23
C100P50N0805
C100P50N0805
C128
C128
X_C10U10Y0805
X_C10U10Y0805
C574
C574
X_C100P50N0402
X_C100P50N0402
C575
C575
X_C100P50N0402
X_C100P50N0402
C24
C24
C1U10Y
C1U10Y
C25
C25
C1U10Y
C1U10Y
C26
C26
C0.1U16Y0402
C0.1U16Y0402
C27
C27
C1U10Y
C1U10Y
C28
C28
C1U10Y
C1U10Y
C29
C29
C0.1U16Y0402
C0.1U16Y0402
MCH MEMORY DECOUPLING
V_FSB_VTT
C31
C31
C30
C30
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
FSB GENERIC DECOUPLING
C32
C32
X_C0.1U16Y0402
X_C0.1U16Y0402
A A
V_1P5_CORE V_1P5_CORE
L6 X_10U125m_0805-1L6 X_10U125m_0805-1
1 2
CP4
CP4
X_COPPER
X_COPPER
8
I = 55mA
VCCA_DPLLB
12
EC3
EC3
+
+
.CD220U10EL7
.CD220U10EL7
C39
C39
C0.1U16Y0402
C0.1U16Y0402
7
L7 X_600L200m_500-1L7 X_600L200m_500-1
1 2
CP5
CP5
X_COPPER
X_COPPER
6
I = 45mA
VCCA_HPLL
C40
C40
C0.1U16Y0402
C0.1U16Y0402
5
V_1P5_CORE
I = 1.5A
4
Vcc_PCI Express
C41
C41
C10U6.3X50805
C10U6.3X50805
C42
C42
C10U6.3X50805
C10U6.3X50805
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - PCI EXPRESS
Intel Lakeport - PCI EXPRESS
Intel Lakeport - PCI EXPRESS
101
101
MS-7210
MS-7210
MS-7210
2
934Monday, October 24, 2005
934Monday, October 24, 2005
934Monday, October 24, 2005
1
101
of
of
of
5
AN42
AN31
AN27
AN26
AN24
AN23
AN21
AN20
AN18
AN17
AN15
AN13
AN4
AN2
AM39
AM37
AM36
AM33
AM9
AM7
AM5
AL43
AL37
U6D
D D
C C
B B
U6D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A16
VSS
A22
VSS
A26
VSS
A31
VSS
A35
VSS
B4
VSS
B6
VSS
B9
VSS
B11
VSS
B13
VSS
B21
VSS
B22
VSS
B28
VSS
B33
VSS
B38
VSS
C3
VSS
C5
VSS
C7
VSS
C12
VSS
C14
VSS
C22
VSS
C40
VSS
D2
VSS
D5
VSS
D10
VSS
D16
VSS
D20
VSS
D21
VSS
E3
VSS
E4
VSS
E7
VSS
E9
VSS
E12
VSS
E13
VSS
E17
VSS
E18
VSS
E20
VSS
E21
VSS
E32
VSS
F2
VSS
F6
VSS
F13
VSS
F18
VSS
F26
VSS
F34
VSS
F42
VSS
G3
VSS
G5
VSS
G7
VSS
G9
VSS
G10
VSS
G13
VSS
G15
VSS
G18
VSS
G20
VSS
G21
VSS
G24
VSS
G27
VSS
G29
VSS
G31
VSS
G32
VSS
G35
VSS
G38
VSS
H12
VSS
H17
VSS
H26
VSS
H27
VSS
H32
VSS
J2
VSS
J5
VSS
J7
VSS
J10
VSS
VSS
VSS
VSS
VSS
VSS
J12
J21
J24
J43
J38
J29
VSS
VSS
VSS
VSS
VSS
VSSK7VSSK6VSSK5VSSK3VSS
VSS
K20
K15
K13
K12
K10
K27
VSS
VSS
VSSL2VSS
VSS
VSS
VSS
L13
L12
K39
K37
K34
K32
4
AU32
AU29
AU26
AU24
AU21
AU20
AU17
AU15
AU13
AU12
AU9
AU6
AT31
AT27
AT26
AT23
AT21
AT18
AT17
AT12
AR43
AR39
AR37
AR32
AR24
AR20
AR15
AR6
AR1
AP38
AP34
AP29
AP12
AP10
AP7
AP5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L31
L29
L26
L24
L42
VSS
VSS
VSS
VSS
VSS
VSS
VSSM9VSSM8VSSM5VSSM3VSS
M21
M20
M13
M10
VSS
VSS
VSSN8VSSN6VSS
N2
N15
N13
M37
M35
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N24
VSS
N36
N33
N31
N29
N27
N26
N43
N39
VSS
VSS
VSS
VSS
VSS
VSS
VSSP3VSS
P29
P27
P26
P24
P15
P14
AU34
VSS
P30
3
AA25
Y29
Y26
Y24
Y22
Y20
W25
W23
W21
V29
V26
V24
U29
R29
R26
D43
A40
BC9
BB41
BB39
BB34
BB19
BB14
BB11
BB6
BB3
BA42
BA4
AW10
AV37
AV17
AV10
AV2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSD1VSS
VSSA4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR9VSSR6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSST2VSS
VSSU3VSSU5VSSU9VSS
VSS
VSS
VSS
VSS
VSS
VSSV2VSSV8VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSW3VSSY2VSSY5VSSY6VSSY9VSS
R12
R14
T42
R30
R31
R34
R37
R39
U12
U14
V11
V12
V14
V34
V36
V37
V38
V39
U31
U33
U36
U38
V43
VSS
AA27
VSS
AA29
VSS
Y12
AC19
VSS
VSS
Y14
AC25
VSS
VSS
Y31
AC29
VSS
VSS
Y35
AD18
VSS
VSS
Y37
2
AD20
VSS
VSS
Y39
AD22
Y42
VSS
VSS
AD24
VSS
VSS
AA3
AD27
VSS
VSS
AA8
AD29
VSS
VSS
AF18
AE19
VSS
VSS
AE21
AF20
VSS
VSS
AE23
AF22
VSS
VSS
AE25
AF24
L17
VSS
VSS
1
AY1
BC4
VSS
VSS
AL33
VSS
AL32
VSS
AL27
VSS
AL24
VSS
AL23
VSS
AL21
VSS
AL18
VSS
AL15
VSS
AL13
VSS
AL12
VSS
AL10
VSS
AL7
VSS
AL3
VSS
AL2
VSS
AL1
VSS
AK30
VSS
AK29
VSS
AK26
VSS
AK24
VSS
AJ37
VSS
AJ35
VSS
AJ33
VSS
AJ31
VSS
AJ30
VSS
AJ10
VSS
AJ7
VSS
AH42
VSS
AG39
VSS
AG38
VSS
AG37
VSS
AG36
VSS
AG33
VSS
AG31
VSS
AG30
VSS
AF43
VSS
AF38
VSS
AF36
VSS
AF33
VSS
AF5
VSS
AF3
VSS
AF2
VSS
AF1
VSS
AD42
VSS
AD37
VSS
AD35
VSS
AD33
VSS
AD13
VSS
AD11
VSS
AD9
VSS
AD7
VSS
AC39
VSS
AC38
VSS
AC37
VSS
AC36
VSS
AC31
VSS
AC23
VSS
AC21
VSS
AC14
VSS
AC10
VSS
AC7
VSS
AC3
VSS
AC2
VSS
AB43
VSS
AB2
VSS
AA36
VSS
AA33
VSS
AA31
VSS
AA23
VSS
AA21
VSS
AA14
VSS
AA12
VSS
AA11
VSS
Lakeport
Lakeport
A A
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - GND
Intel Lakeport - GND
Intel Lakeport - GND
MS-7210
MS-7210
MS-7210
1
10 34Monday, October 24, 2005
10 34Monday, October 24, 2005
10 34Monday, October 24, 2005
of
of
of
101
101
101
8
D D
C C
Damping Resistor
close to ICH7
PCIRST#20
PCIRST#_139422
PCIRST#_LAN21
R58 22R0402R58 22R0402
R57 22R0402R57 22R0402
Intel REQ
PGNT#4
R336 X_2.2KR0402R336 X_2.2KR0402
PGNT#5
B B
R337 X_2.2KR0402R337 X_2.2KR0402
VCC3
VCC3
PGNT#5 PGNT#4
1
0
SPI
1
PCI
LPC
A A
0
11
VCC3_SB
Stuff if TEKOA not
present or for
Non-share SPI.
AD[0..31]20,21,22
C_BE#[0..3]20,21,22
DEVSEL#20,21,22
FRAME#20,21,22
PCI_PME#20,21
ICH_PCLK17
PREQ#020
PREQ#120
PREQ#220
PREQ#320,21
PREQ#420,22
PREQ#520
PGNT#020
PGNT#120
PGNT#2
PGNT#321
PGNT#422
PGNT#5
PIRQ#C20
PIRQ#D20
PIRQ#G20
PIRQ#H20
SERIRQ12,24
IDE_IRQ26
RN11
RN11
1
3
5
7
8P4R-10KR0402
8P4R-10KR0402
7
AD0
E18
AD0
AD1
C18
AD1
AD2
A16
AD2
AD3
F18
AD3
AD4
E16
AD4
AD5
A18
AD5
AD6
E17
AD6
AD7
A17
AD7
AD8
A15
AD8
AD9
C14
AD9
AD10
E14
AD10
AD11
D14
AD11
AD12
B12
AD12
AD13
C13
AD13
AD14
G15
AD14
AD15
G13
AD15
AD16
E12
AD16
AD17
C11
AD17
AD18
D11
AD18
AD19
A11
AD19
AD20
A10
AD20
AD21
F11
AD21
AD22
F10
AD22
AD23
E9
AD23
AD24
D9
AD24
AD25
B9
AD25
AD26
A8
AD26
AD27
A6
AD27
AD28
C7
AD28
AD29
B6
AD29
AD30
E6
AD30
AD31
D6
AD31
C_BE#0
B15
C/BE0#
C_BE#1
C12
C/BE1#
C_BE#2
D12
C/BE2#
C_BE#3
C15
C/BE3#
A12
DEVSEL#
F16
FRAME#
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5
PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5
SERIRQ
IDE_IRQ
AH21
AH16
A7
F14
F15
E10
E11
B10
C9
B19
A9
B18
D7
C16
C17
E13
A13
C8
E7
D16
D17
F13
A14
D8
A3
B4
C5
B5
G8
F7
F8
G7
P5
P2
P6
R2
P1
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#
PCICLK
PCIRST#
REQ0#
REQ1#
REQ2#
REQ3#
GPIO22/REQ4#
GPIO1/REQ5#
GNT0#
GNT1#
GNT2#
GNT3#
GPIO48/GNT4#
GPIO17/GNT5#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
SERIRQ
IDEIRQ
SPI_MOSI
SPI_MISO
SPI_CS#
SPI_CLK
SPI_ARB
VSS_0A4VSS_1
A23
IRDY#20,21,22
TRDY#20,21,22
STOP#20,21,22
PAR20,21,22
LOCK#20
SERR#20,21
PERR#20,21,22
PIRQ#A20
PIRQ#B20
PIRQ#E20,21
PIRQ#F20,22
2
4
6
8
VSS_2B1VSS_3B8VSS_4
VSS_5
B11
B14
6
PCI INTERFACE INTERRUPT
PCI INTERFACE INTERRUPT
PART 1/3
PART 1/3
SPI
SPI
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10C2VSS_11C6VSS_12
VSS_13
B17
B20
B26
B28
D10
D13
ICH 7
ICH 7
VSS_14
VSS_15
VSS_16
VSS_17E1VSS_18E2VSS_19E8VSS_20
E15
D18
D21
D24
VSS_21F3VSS_22F4VSS_23F5VSS_24
VSS_25
F12
F27
F28
5
CPULAN PCI EXPRESSDIRECT MEDIA
CPULAN PCI EXPRESSDIRECT MEDIA
GPO49/CPUPWRGD
VSS_26
VSS_27G1VSS_28G2VSS_29G5VSS_30G6VSS_31G9VSS_32
VSS_33
VSS_34
VSS_35
G14
G18
G21
G24
G25
THRMTRIP#
DMI_0RXN
DMI_0RXP
DMI_1RXN
DMI_1RXP
DMI_2RXN
DMI_2RXP
DMI_3RXN
DMI_3RXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
EE_SHCLK
VSS_36
VSS_37
VSS_38H3VSS_39H4VSS_40
G26
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INIT3_3V#
INTR
SMI#
STPCLK#
RCIN#
A20GATE
PLTRST#
PERN_1
PERP_1
PETN_1
PETP_1
PERN_2
PERP_2
PETN_2
PETP_2
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
DMI_0TXN
DMI_0TXP
DMI_1TXN
DMI_1TXP
DMI_2TXN
DMI_2TXP
DMI_3TXN
DMI_3TXP
LAN_CLK
EE_CS
EE_DIN
EE_DOUT
H5
4
U19A
U19A
AH28
AG27
AG26
AG22
AF22
AG21
AF25
AH24
NMI
AF23
AH22
AG23
AE22
AF26
AG24
C26
F26
F25
HSO_N1_C HSO_N1
E28
HSO_P1_C HSO_P1
E27
H26
H25
HSO_N2_C
G28
G27
K26
K25
J28
HSO_P3_C HSO_P3
J27
M26
M25
HSO_N4_C
L28
HSO_P4_C
L27
P26
P25
N28
N27
T25
T24
R28
R27
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
C25
D25
V3
U3
U5
V4
T5
U7
V6
V7
W1
W3
Y2
Y1
ICH7
ICH7
R59
R59
24.9R1%0402
24.9R1%0402
H_A20M# 4
H_SLP# 4
H_FERR# 4
H_IGNNE# 4
H_INIT# 4
FWH_INIT# 27
H_INTR 4
H_NMI 4
ICH_H_SMI# 4
H_STPCLK# 4
KBRST# 24
A20GATE 24
TRMTRIP# 4
H_PWRGD 4
C43 C0.1U16X0402C43 C0.1U16X0402
C44 C0.1U16X0402C44 C0.1U16X0402
C495 C0.1U16X0402C495 C0.1U16X0402
C496 C0.1U16X0402C496 C0.1U16X0402
C497 C0.1U16X0402C497 C0.1U16X0402
C498 C0.1U16X0402C498 C0.1U16X0402
C499 C0.1U16X0402C499 C0.1U16X0402
C500 C0.1U16X0402C500 C0.1U16X0402
DMI_MTN_IRN_0 9
DMI_MTP_IRP_0 9
DMI_ITN_MRN_0 9
DMI_ITP_MRP_0 9
DMI_MTN_IRN_1 9
DMI_MTP_IRP_1 9
DMI_ITN_MRN_1 9
DMI_ITP_MRP_1 9
DMI_MTN_IRN_2 9
DMI_MTP_IRP_2 9
DMI_ITN_MRN_2 9
DMI_ITP_MRP_2 9
DMI_MTN_IRN_3 9
DMI_MTP_IRP_3 9
DMI_ITN_MRN_3 9
DMI_ITP_MRP_3 9
CK_PE_100M_ICH# 17
CK_PE_100M_ICH 17
V_DMI 13
3
Damping Resistor
close to ICH7
R54 22R0402R54 22R0402
HSI_N1
HSI_P1
HSI_N2
HSI_P2
HSO_N2
HSO_P2HSO_P2_C
HSI_N3
HSI_P3
HSO_N3HSO_N3_C
HSI_N4
HSI_P4
HSO_N4
HSO_P4
HSI_N1 18
HSI_P1 18
HSO_N1 18
HSO_P1 18
HSI_N2 18
HSI_P2 18
HSO_N2 18
HSO_P2 18
HSI_N3 18
HSI_P3 18
HSO_N3 18
HSO_P3 18
HSI_N4 18
HSI_P4 18
HSO_N4 18
HSO_P4 18
PLTRST#_ICH7 7
PLTRST#_MS7 29
2
V_FSB_VTT
RN74 8P4R-62R0402RN74 8P4R-62R0402
1
2
3
4
5
6
7
8
PLACE AT ICH7 END OF ROUTE
U910
U910
Intel
Intel
ICH7R
ICH7R
INTEL-NH82801GR-A1-LF
INTEL-NH82801GR-A1-LF
1
H_FERR#
TRMTRIP#
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
ICH7 - PCI, DMI, CPU, IRQ
ICH7 - PCI, DMI, CPU, IRQ
ICH7 - PCI, DMI, CPU, IRQ
101
101
MS-7210
MS-7210
MS-7210
2
11 34Monday, October 24, 2005
11 34Monday, October 24, 2005
11 34Monday, October 24, 2005
1
101
of
of
of
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