MSI MS-7204 Schematics
1
2
3
4
5
MS-7204
Version 20
Intel (R) Lakeport (GMCH) + ICH7 Chipset
Title
A A
B B
C C
D D
COVER SHEET
BLOCK DIAGRAM
Intel LGA775
Intel Lakeport
ICH7
ICS954119DF Clock Gen
LPC I/O - W83627EHF
LAN - INTEL 82562GZ/82573
IEEE1394 VT-6308P
Azalia CODEC-ALC883
Audio Jacks 19
USB CONNECTORS
DDR II DIMM 1 & 2 Channel A
DDR II DIMM 3 & 4 Channel B
DDR II VTT Decoupling
BTX ,Front Panel,IDE
MS7 ACPI Controller
Intersil 6316 4Phase
PCI Slot 1,2
Misc
HISTORY
PCIRST & POWER OK MAP 31
POWER MAP 32
History 33
PCI Routing Table
PCI Device
PCI Slot 1
PCI Slot 2
(Add MEDION SPEC)
1394.
LAN (INTERNAL)
1
AD16
AD17
AD20
AD19 4 D
AD24
0
1
3
5 FAD21
INTERRUPTIDSEL REQ/GNT
2
Page
1
2
3 , 4 , 5
6 , 7 , 8 , 9
10,11,12
13
14
15FWH/FAN/SATA
16
17
18
20
21
22
23
24
25PCI -Express X16 Slot & X1 Slot
26
27
28
29
30
A
B
E
PCI CLK
PCI_CLK1
PCI_CLK0
PCI_CLK3
PCI_CLK4
1394_PCLK
Intel LGA775 Processor
CPU:
Intel - up to 3.8G(Single core) & 3.2G(Dual core)
System Chipset:
Intel Lakeport (945P)- GMCH (North Bridge)
Intel ICH7/7R/7DH (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM- 4M
Azalia Codec -- RLK- ALC883 7.1+2 channel
LPC Super I/O -- W83637HF
LAN - INTEL 82562GZ/82573
1394 -- VIA- VT6307/8 with PHY
CLOCK -- ICS954119DF
Main Memory:
DDR II * 4 (Max 4GB)
Expansion Slots:
PCI EXPRESS X16 SLOT * 1
PCI EXPRESS X1 SLOT * 1
PCI 2.3 SLOT * 2
SATA *4
Intersil PWM:
Controller: HIP6316 4 Phase
Driver: ISL6614ACB * 1 + ISL6612ACBZT *2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
COVER SHEET 2.0
COVER SHEET 2.0
COVER SHEET 2.0
1 33Tuesday, March 07, 2006
1 33Tuesday, March 07, 2006
1 33Tuesday, March 07, 2006
5
1
2
3
4
5
VRM_GD
VTT_PWG
A A
PCIRST_SLOT#
B B
C C
HD_RST#
VRM 10.1
Intersil 6316
4-Phase PWM
PCI
EXPRESS
X16
Connector
IDE Primary
IDE Primary
SERIAL ATA1
SERIAL ATA2
USB2.0
USB Port0~ 7
P.28
P.15
P.19
P.18
P.18
P.18
P.18
P.25
UltraDMA
33/66/100
USB
RSMRST#
Intel LGA775 Processor
H_PWRGD
FSB
Lakeport-945P
DMI
PLRST#
VRM_GD
ICH7
P.10~12
H_CPURST#
P.6~9
PWR_GD
LPC Bus
P.3~5
CHANNEL A
CHANNEL B
SLP_S4#
SLP_S3#
Block Diagram
2 DDR II
DIMM
Modules
P.20
2 DDR II
DIMM
Modules
P.21
PCIRST_ICH7#
PCI
PWR_OK
PCIRST_BUF#
ATX1
PWR_GD
PCIRST_SLOT#
PCI Slot 1
PCI Slot 2
P.23 P.23
MS7
VID_GD
RSMRST#
HD_RST#
PCIRST_BUF#
RLK
Azalia Codec
P.16
LPC SIO
W83627EHF
P.14
LAN
RLK
PCIRST_BUF#
8100C/8110S(B)
1394
VIA VT6308P
D D
1
P.17
P.26
PCI
FWH
P.30
FP_RST#SW_ON#
JFP1
2
Keyboard
Mouse
PCIRST_ICH6#
3
Floopy Parallel Serial
P.14
P.14
P.14 P.18 P.18
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
BLOCK DIAGRAM 2.0
BLOCK DIAGRAM 2.0
BLOCK DIAGRAM 2.0
2 33Tuesday, March 07, 2006
2 33Tuesday, March 07, 2006
2 33Tuesday, March 07, 2006
5
1
CPU SIGNAL BLOCK
H_A#[3..31][6]
A A
U11A
U11A
H_DBI#0[6]
H_DBI#1[6]
H_DBI#2[6]
H_DBI#3[6]
H_IERR#[4]
H_FERR#[4,10]
H_STPCLK#[10]
H_INIT#[10]
H_DBSY#[6]
H_DRDY#[6]
H_TRDY#[6]
H_ADS#[6]
H_LOCK#[6]
H_BNR#[6]
H_HIT#[6]
B B
C C
D D
H_HITM#[6]
H_BPRI#[6]
H_DEFER#[6]
H_THERMDA[14]
VTIN_GND[14]
TRMTRIP#[4,10]
H_PROCHOT#[4,27]
H_IGNNE#[10]
ICH_H_SMI#[10]
H_A20M#[10]
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_OUT_RIGHT
H_FSBSEL0[4,8,13]
H_FSBSEL1[4,8,13]
H_FSBSEL2[4,8,13]
H_PWRGD[4,10]
H_CPURST#[4,6]
H_D#[0..63][6]
LL_ID1
R305
R305
X_0R0402
X_0R0402
TP16TP16
R284
R284
H_TESTHI13
62R0402
62R0402
R291
R291
X_62R0402
X_62R0402
R303 62R0402R303 62R0402
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
LL_ID1
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
D53#
B15
C14
H_D#52
H_D#53
D52#
D51#
C15
H_D#51
D50#
A14
D17
H_D#49
H_D#50
AJ6
A35#
D49#
D48#
D20
H_D#48
AJ5
AH5
A34#
D47#
G22
D22
H_D#47
H_D#46
AH4
A33#
D46#
E22
H_D#45
H_A#31
AG5
A32#
A31#
D45#
D44#
G21
H_D#44
H_A#29
H_A#30
AG4
AG6
A30#
D43#
F21
E21
H_D#43
H_D#42
H_A#28
AF4
A29#
A28#
D42#
D41#
F20
H_D#41
H_A#26
H_A#27
AF5
AB4
A27#
D40#
E19
E18
H_D#39
H_D#40
H_A#25
AC5
A26#
A25#
D39#
D38#
F18
H_D#38
H_A#24
H_A#23
AB5
AA5
A24#
D37#
F17
G17
H_D#37
H_D#36
2
H_A#22
AD6
A23#
D36#
G18
H_D#35
H_A#21
AA4
A22#
A21#
D35#
D34#
E16
H_D#34
H_A#20
E15
H_D#33
H_A#18
H_A#17
H_A#16
H_A#19
AB6
A20#Y4A19#Y6A18#W6A17#
D33#
D32#
D31#
D30#
F15
G16
G15
G14
H_D#32
H_D#30
H_D#29
H_D#31
H_A#10
H_A#15
H_A#11
H_A#9
H_A#12
H_A#13
H_A#14
U6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
F14
F12
F11
G13
E13
D13
D10
H_D#26
H_D#28
H_D#22
H_D#25
H_D#27
H_D#23
H_D#24
H_A#5
H_A#8
H_A#6
H_A#7
H_A#3
H_A#4
L5
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
H_D#17
H_D#18
H_D#20
H_D#16
H_D#21
H_D#19
AC2
D11
C12
H_D#15
H_D#14
AN3
DBR#
VCC_SENSE
D14#
D13#
D12#D8D11#
B12
H_D#12
H_D#13
TP22TP22
VCC_VRM_SENSE
VSS_VRM_SENSE
AN4
AN5
AN6
AJ3
AK3
AM7
RSVD
ITP_CLK1
ITP_CLK0
VSS_SENSE
VCC_MB_REGULATION
VSS_MB_REGULATION
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
C11
B10
A11
A10
H_D#9
H_D#6
H_D#10
H_D#5
H_D#7
H_D#11
H_D#8
H_D#4
3
AM5
VID6#
H_D#3
AL4
VID5#
H_D#2
AK4
VID4#
H_D#1
AL6
B4
H_D#0
C377
C377
C10U6.3X51206
C10U6.3X51206
VID5
VID4
VID3
VID2
VID1
VID0
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
_ZIF-SOCK775-15u-in
_ZIF-SOCK775-15u-in
VID5 [27]
VID4 [27]
VID3 [27]
VID2 [27]
VID1 [27]
VID0 [27]
R298 62R0402R298 62R0402
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
H_FORCEPH
RSVD_G6
TP18TP18
TP20TP20
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
VCC_VRM_SENSE [27]
VSS_VRM_SENSE [27]
GTLREF_SEL
H_REQ#[0..4] [6]
R301 62R0402R301 62R0402
R290 62R0402R290 62R0402
R281 62R0402R281 62R0402
R274 62R0402R274 62R0402
R275 62R0402R275 62R0402
R183 62R0402R183 62R0402
R304 62R0402R304 62R0402
R184 62R0402R184 62R0402
R321 X_62R0402R321 X_62R0402
R272 X_62R0402R272 X_62R0402
CK_H_CPU# [13]
CK_H_CPU [13]
H_RS#2 [6]
H_RS#1 [6]
H_RS#0 [6]
R296 60.4R1%0402R296 60.4R1%0402
R278 60.4R1%0402R278 60.4R1%0402
R287 60.4R1%0402R287 60.4R1%0402
R271 60.4R1%0402R271 60.4R1%0402
R289 60.4R1%0402R289 60.4R1%0402
R204 60.4R1%0402R204 60.4R1%0402
TP11TP11
TP8TP8
TP10TP10
TP12TP12
H_ADSTB#1 [6]
H_ADSTB#0 [6]
H_DSTBP#3 [6]
H_DSTBP#2 [6]
H_DSTBP#1 [6]
H_DSTBP#0 [6]
H_DSTBN#3 [6]
H_DSTBN#2 [6]
H_DSTBN#1 [6]
H_DSTBN#0 [6]
H_NMI [10]
H_INTR [10]
CPU_GTLREF0 [4]
CPU_GTLREF1 [4]
VTT_OUT_LEFT
4
V_FSB_VTT
VTT_OUT_RIGHT [4,5]
H_FORCEPH [27]
TP2TP2
C370
C370
C0.1U16Y0402
C0.1U16Y0402
VTT_OUT_RIGHT
X_C0.1U16Y0402
X_C0.1U16Y0402
MCH_GTLREF_CPU [6]
H_BR#0 [4,6]
VTT_OUT_LEFT [4]
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
C378
C378
C371
C371
C0.1U16Y0402
C0.1U16Y0402
PLACE BPM TERMINATION NEAR CPU
5
VID Pull-Up Resistor
VTT_OUT_RIGHT
VID3
VID1
VID4
VID2
VID0
VID5
RN33
RN33
RN31
RN31
R309 X_62R0402R309 X_62R0402
R315 62R0402R315 62R0402
R308 62R0402R308 62R0402
RN348P4R-680R RN348P4R-680R
R313 680RR313 680R
R310 680RR310 680R
8P4R-62R0402
8P4R-62R0402
8P4R-62R0402
8P4R-62R0402
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TMS
H_TDI
H_BPM#2
H_BPM#4
H_TDO
H_TRST#
H_TCK
The LL_ID[]1:0] signals are used to select the
correct loading slope for the processor.
ITPCLK[0:1] are copies of BCLK that are used only in processor systems where no debug
port is implemented on the system board.
The signal VID_SELECT(previously known as FC16, land number AN7) on the processor socket
should have a 62 ohm 5% pull-down resistor to ground.
1
LL_ID[]1:0]=00 for the P4 processor in the
775-land package.
2
BSEL
2
1
0
0
1 0 200 MHZ (800)
0
0
3
TABLE
FSB FREQUENCY0
0
267 MHZ (1067)
10133 MHZ (533)
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
Intel LGA775 - Signals 2.0
Intel LGA775 - Signals 2.0
Intel LGA775 - Signals 2.0
3 33Tuesday, March 07, 2006
3 33Tuesday, March 07, 2006
3 33Tuesday, March 07, 2006
5
1
VCCP
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
U11B
VCCP
A A
U11B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH26
VCC
AH27
VCC
VCC
AH28
VCC
AH29
VCC
AH30
VCC
AH8
2
VCC
AH9
AJ11
VCC
AJ12
VCC
VCC
AJ14
AJ15
VCC
AJ18
VCC
VCC
AJ19
AJ21
VCC
AJ22
VCC
AJ25
VCC
VCC
AJ26
AJ8
VCC
AJ9
VCC
VCC
AK11
VCC
AK12
VCC
AK14
VCC
AK15
VCC
AK18
VCC
AK19
VCC
AK21
VCC
AK22
VCC
AK25
VCC
AK26
VCC
AK8
AK9
VCC
AL11
VCC
VCC
AL12
VCC
AL14
VCC
AL15
VCC
AL18
VCC
AL19
VCC
AL21
VCC
3
AL22
VCC
AL25
VCC
AL26
VCC
AL29
VCC
AL30
VCC
AL8
AL9
VCC
AM11
VCC
AM12
VCC
AM14
VCC
AM15
VCC
AM18
VCC
AM19
VCC
AM21
VCC
AM22
VCC
AM25
VCC
AM26
VCC
AM29
VCC
AM30
VCC
AM8
VCC
AM9
VCC
VCC
AN11
VCC
AN12
VCC
AN14
VCC
AN15
VCC
AN18
VCC
AN19
VCC
AN21
VCC
AN22
VCC
4
VccPLL for Ssmithfield define the support
future processor.
H_VCCA
H_VSSA
H_VCCIOPLL
V_FSB_VTT
5
V_FSB_VTT
C222 C10U10Y0805C222 C10U10Y0805
C223 C10U10Y0805C223 C10U10Y0805
C224 C10U10Y0805C224 C10U10Y0805
CAPS FOR FSB GENERIC
V_FSB_VTT
C219
C220
C220
C0.1U16Y0402
C0.1U16Y0402
FSB GENERIC DECOUPLING
VTT_OUT_RIGHT
VID_GD#[26,27]
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
R318 680R0402R318 680R0402
VCC5_SB
R320
R320
1KR0402
1KR0402
R322
R322
10KR0402
10KR0402
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Intel LGA775 - Power 2.0
Intel LGA775 - Power 2.0
Intel LGA775 - Power 2.0
_ZIF-SOCK775-15u-in
_ZIF-SOCK775-15u-in
4
100mA
100mA
4
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
B B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
VCCP
C C
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
VTT_OUT_RIGHT[3,5]
VTT_OUT_LEFT[3]
D D
Y30
R279 124R1%0402R279 124R1%0402
R285 124R1%0402R285 124R1%0402
VTT_OUT_RIGHT
Y29
Y23
Y24
Y25
Y26
Y27
Y28
R280
R280
210R1%0402
210R1%0402
R282
R282
210R1%0402
210R1%0402
V_FSB_VTT
1
W25
W26
W27
W28
W29
W30
C364
C364
C1U6.3Y50402/80-20%
C1U6.3Y50402/80-20%
C369
C369
C1U6.3Y50402/80-20%
C1U6.3Y50402/80-20%
R316 130R1%0402R316 130R1%0402
R182 62R0402R182 62R0402
R286 X_100R0402R286 X_100R0402
R276 62R0402R276 62R0402
R306 62R0402R306 62R0402
R283 62R0402R283 62R0402
R288 62R0402R288 62R0402
W24
W23
R273
R273
10R0402
10R0402
R277
R277
10R0402
10R0402
U30
U29
U28
TRMTRIP#
H_FERR#
U27
U26
U23
U24
U25
CPU_GTLREF0VTT_OUT_RIGHT
C362
C362
C220P25N0402
C220P25N0402
CPU_GTLREF1VTT_OUT_LEFT
C363
C363
C220P25N0402
C220P25N0402
H_PROCHOT#
H_CPURST#
H_PWRGDVTT_OUT_LEFT
H_BR#0
H_IERR#
T30
T23
T24
T25
T26
T27
T28
T29
H_PROCHOT# [3,27]
H_CPURST# [3,6]
H_PWRGD [3,10]
H_BR#0 [3,6]
H_IERR# [3]
TRMTRIP# [3,10]
H_FERR# [3,10]
2
N28
N29
N30
CPU_GTLREF0 [3]
CPU_GTLREF1 [3]
N27
N26
N25
N24
N23
M30
M28
M29
V_FSB_VTT
V_FSB_VTT
V_FSB_VTT
M27
M26
K23
K24
K25
K26
K27
K28
K29
K30
M23
M24
M25
L5
L5
10uH/8/125mA/Rdc=0.7
10uH/8/125mA/Rdc=0.7
L6 10uH/8/125mA/Rdc=0.7L6 10uH/8/125mA/Rdc=0.7
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
J28
J29
J30
R189
R189
0R0805
0R0805
C231
C231
X_C1U10X
X_C1U10X
RN20
RN20
8P4R-470R0402
8P4R-470R0402
3
J26
J27
J19
J20
J21
J22
J23
J24
J25
C229
C229
C22U10X50805
C22U10X50805
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
J10
J11
J12
J13
J14
J15
J18
AN8
AN9
H_VCCIOPLL
C230
C230
X_C10U10Y0805
X_C10U10Y0805
H_VSSA
H_FSBSEL1 [3,8,13]
H_FSBSEL0 [3,8,13]
H_FSBSEL2 [3,8,13]
AN29
AN30
H_VCCA
AN26
HS11HS22HS33HS4
AN25
C219
C0.1U16Y0402
C0.1U16Y0402
Q37
Q37
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
X__C1U6.3Y50402/80-20%
X__C1U6.3Y50402/80-20%
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
C221
C221
C0.1U16Y0402
C0.1U16Y0402
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
VTT_PWG
C384
C384
4 33Tuesday, March 07, 2006
4 33Tuesday, March 07, 2006
4 33Tuesday, March 07, 2006
5
1
2
3
4
5
VTT_OUT_RIGHT[3,4]
A A
B B
VTT_OUT_RIGHT
60.4R1%0402
60.4R1%0402
U11C
U11C
R300
R300
H_COMP7
H_COMP6
AE3
AE4
COMP6Y3COMP7
R311
R311
60.4R1%0402
60.4R1%0402
TP3TP3
D14
E23
RSVD
RSVDD1RSVD
RSVD
TP14TP14
TP13TP13
TP4TP4
F23
F6
RSVDE5RSVDE6RSVDE7RSVD
IMPSEL#
B13
RSVD
P5
RSVDJ3RSVDN4RSVD
MSID1
MSID0
W1
AC4
MSID[1]V1MSID[0]
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
RSVD
R295 62R0402R295 62R0402
R299 62R0402R299 62R0402
R302 X_62R0402R302 X_62R0402
V30
V29
V28
V27
V26
V25
V24
VSSV3VSS
VSS
VSS
VSS
VSS
V_FSB_VTT
V23
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
R30
R29
R28
VSS
MSID1 0 0
MSID0 0 NC
R27
R26
R25
R24
R23
P30
P29
P28
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
2005 Performance
FMB platform
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
2005 Mainstream/Value
FMB platform
L30
L29
L28
L27
L26
VSSL3VSS
VSS
VSS
L25
VSS
L24
VSS
L23
VSS
VSS
K2
K5
VSSK7VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
C C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSB1VSS
VSS
_ZIF-SOCK775-15u-in
AJ4
AF3
AF6
AE5
AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AE29
AE30
D D
1
AF26
AF27
AF28
AF29
AF30
AF7
AG10
AG13
AG16
AG17
2
AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ7
AK10
AK13
AK16
AK17
3
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3
AL7
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM4
AM28
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
AN27
4
_ZIF-SOCK775-15u-in
B11
B14
AN28
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
Intel LGA775- GND 2.0
Intel LGA775- GND 2.0
Intel LGA775- GND 2.0
5 33Tuesday, March 07, 2006
5 33Tuesday, March 07, 2006
5 33Tuesday, March 07, 2006
5
1
N17
P17
P18
P20
P21
VCC
VCC
VCC
VCC
AA22
VCC
U14A
H_A#3
H_A#3[3]
H_A#4
H_A#4[3]
H_A#5
H_A#5[3]
H_A#6
H_A#6[3]
H_A#7
H_A#7[3]
H_A#8
H_ADSTB#0[3]
H_ADSTB#1[3]
H_BR#0[3,4]
H_BPRI#[3]
H_BNR#[3]
H_LOCK#[3]
H_ADS#[3]
H_HIT#[3]
H_HITM#[3]
CK_H_MCH[13]
CK_H_MCH#[13]
PWR_GD[11,26]
H_CPURST#[3,4]
R248
R248
16.9R1%
16.9R1%
H_A#8[3]
H_A#9[3]
H_A#10[3]
H_A#11[3]
H_A#12[3]
H_A#13[3]
H_A#14[3]
H_A#15[3]
H_A#16[3]
H_A#17[3]
H_A#18[3]
H_A#19[3]
H_A#20[3]
H_A#21[3]
H_A#22[3]
H_A#23[3]
H_A#24[3]
H_A#25[3]
H_A#26[3]
H_A#27[3]
H_A#28[3]
H_A#29[3]
H_A#30[3]
H_A#31[3]
H_REQ#0[3]
H_REQ#1[3]
H_REQ#2[3]
H_REQ#3[3]
H_REQ#4[3]
TP23TP23
H_RS#0[3]
H_RS#1[3]
H_RS#2[3]
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF_CPU
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
A A
B B
H_TRDY#[3]
H_DBSY#[3]
H_DRDY#[3]
C C
PLTRST#[10]
ICH_SYNC#[11]
U14A
RSVRD
AA35
AA42
V_FSB_VTT V_FSB_VTT
R228
R228
301R1%0402
D D
R245
V_FSB_VTT
R245
60.4R1%0402
60.4R1%0402
1
HXSCOMPV_FSB_VTT
C316
C316
X_C2.2P25N0402
X_C2.2P25N0402
301R1%0402
R232
R232
84.5R1%0402-LF
84.5R1%0402-LF
HSWING VOLTAGE "10mil trace 7mil space"
place divider resistors near VTT.
2
AB21
AB22
AB23
AC22
AD14
AF6
AF7
AF8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
L15
U27
R27
A43
M15
AA38
M11
AA34
HD_SWING S/B 0.22*VTT
2
AF9
AF10
AF11
AF12
AF13
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
AJ24
AJ27
AG25
AG26
AG27
R241
R241
62R0402
62R0402
C292
C292
C0.01U25X0402
C0.01U25X0402
V_1P5_CORE
AF14
AF30
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AH1
AH2
AH4
AJ5
AJ13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
AK40
AL39
Y30
AY14
BC16
AD30
AC34
AW17
AW18
HXSWING MCH_GTLREF_CPU
RSVRD
RSVRD
Y33
AF31
RSVRD
RSVRD
U30
AD31
RSVRD
RSVRD
V31
AA30
RSVRD
AC30
AK21
AJ23
AJ26
AL29
3
AJ14
AK2
AK3
AK4
AK14
AK15
AK20
R15
R17
R18
R20
R21
R23
R24
U15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
NC
NC
NC
NC
V30
BC2NCBC1
AJ21
AJ29
AL20
AL26
AK27
AG29
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
R233
R233
124R1%0402
124R1%0402
R237
R237
210R1%0402
210R1%0402
3
BC43NCBC42
R244
R244
10R0402
10R0402
C305
C305
C0.1U16Y0402
C0.1U16Y0402
BB43
BB2NCBB1NCBA2
U17
VCC
U18
VCC
AW26
VCC
NC
4
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
W24
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NCC2NC
NCB3NCB2NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E35NCC42
B43NCB42NCB41
A42
Y17
Y18
Y19
Y21
Y23
Y25
AW2
AV27NCAV26
C315
C315
X_C220P25N0402
X_C220P25N0402
Y27
AA15
AA17
AA18
AA19
MCH_GTLREF_CPU [3]
CAPS SHOULD BE PLACED NEAR MCH PIN
CAP for GTLREF inputs GMCH use 12mil trace,
isolate W 15mil space.
4
W26
VCC
VCC
AA20
W27
VCC
Y15
M17
VCC
VCC
V_1P5_CORE
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
(INTEL-QG82945G-A2-LF)
(INTEL-QG82945G-A2-LF)
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Intel lakeport - CPU
Intel lakeport - CPU
Date: Sheet of
Date: Sheet of
Date: Sheet of
Intel lakeport - CPU
H_D#0 [3]
H_D#1 [3]
H_D#2 [3]
H_D#3 [3]
H_D#4 [3]
H_D#5 [3]
H_D#6 [3]
H_D#7 [3]
H_D#8 [3]
H_D#9 [3]
H_D#10 [3]
H_D#11 [3]
H_D#12 [3]
H_D#13 [3]
H_D#14 [3]
H_D#15 [3]
H_D#16 [3]
H_D#17 [3]
H_D#18 [3]
H_D#19 [3]
H_D#20 [3]
H_D#21 [3]
H_D#22 [3]
H_D#23 [3]
H_D#24 [3]
H_D#25 [3]
H_D#26 [3]
H_D#27 [3]
H_D#28 [3]
H_D#29 [3]
H_D#30 [3]
H_D#31 [3]
H_D#32 [3]
H_D#33 [3]
H_D#34 [3]
H_D#35 [3]
H_D#36 [3]
H_D#37 [3]
H_D#38 [3]
H_D#39 [3]
H_D#40 [3]
H_D#41 [3]
H_D#42 [3]
H_D#43 [3]
H_D#44 [3]
H_D#45 [3]
H_D#46 [3]
H_D#47 [3]
H_D#48 [3]
H_D#49 [3]
H_D#50 [3]
H_D#51 [3]H_DEFER#[3]
H_D#52 [3]
H_D#53 [3]
H_D#54 [3]
H_D#55 [3]
H_D#56 [3]
H_D#57 [3]
H_D#58 [3]
H_D#59 [3]
H_D#60 [3]
H_D#61 [3]
H_D#62 [3]
H_D#63 [3]
H_DBI#0 [3]
H_DBI#1 [3]
H_DBI#2 [3]
H_DBI#3 [3]
H_DSTBP#0 [3]
H_DSTBN#0 [3]
H_DSTBP#1 [3]
H_DSTBN#1 [3]
H_DSTBP#2 [3]
H_DSTBN#2 [3]
H_DSTBP#3 [3]
H_DSTBN#3 [3]
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
5
2.0
2.0
6 33Tuesday, March 07, 2006
6 33Tuesday, March 07, 2006
6 33Tuesday, March 07, 2006
2.0
1
SDQ_A[0..63][21]
SDQ_A2
SDQ_A0
SDQ_A1
SDQ_A3
AP3
AP2
AU3
SADQ0
SADQ1
AV4
SADQ2
U14B
SCS_A#0[21,23]
SCS_A#1[21,23]
A A
B B
C C
SCS_A#2[21,23]
SCS_A#3[21,23]
RAS_A#[21,23]
CAS_A#[21,23]
WE_A#[21,23]
MAA_A0[21,23]
MAA_A1[21,23]
MAA_A2[21,23]
MAA_A3[21,23]
MAA_A4[21,23]
MAA_A5[21,23]
MAA_A6[21,23]
MAA_A7[21,23]
MAA_A8[21,23]
MAA_A9[21,23]
MAA_A10[21,23]
MAA_A12[21,23]
MAA_A13[21,23]
SODT_A0[21,23]
SODT_A1[21,23]
SODT_A2[21,23]
SODT_A3[21,23]
SBS_A0[21,23]
SBS_A1[21,23]
SBS_A2[21,23]
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
SBS_A0
SBS_A1
SBS_A2
SDQS_A0[21]
SDQS_A#0[21]
SDQS_A1[21]
SDQS_A#1[21]
SDQS_A2[21]
SDQS_A#2[21]
SDQS_A3[21]
SDQS_A#3[21]
SDQS_A4[21]
SDQS_A#4[21]
SDQS_A5[21]
SDQS_A#5[21]
SDQS_A6[21]
SDQS_A#6[21]
SDQS_A7[21]
SDQS_A#7[21]
SCLKA0[21]
SCLKA#0[21]
SCLKA1[21]
SCLKA#1[21]
SCLKA2[21]
SCLKA#2[21]
SCLKA3[21]
SCLKA#3[21]
SCLKA4[21]
SCLKA#4[21]
SCLKA5[21]
SCLKA#5[21]
SMPCOMP_N
SMPCOMP_P
RAS_A#
CAS_A#
WE_A#
U14B
SDQ_A4
SDQ_A5
AN1
AP4
SADQ3
SADQ4
SDQ_A7
SDQ_A6
AU5
AU2
SADQ5
SADQ6
SDQ_A9
SDQ_A8
AW3
AY3
SADQ7
SADQ8
2
SDQ_A10
SDQ_A11
BA7
BB7
SADQ9
SADQ10
SDQ_A13
SDQ_A12
AV1
AW4
SADQ11
SADQ12
SADQ13
SDQ_A14
SDQ_A15
SDQ_A16
BC6
AY7
AW12
SADQ14
SADQ15
SDQ_A18
SDQ_A19
SDQ_A17
AY10
BA12
BB12
SADQ16
SADQ17
SADQ18
SDQ_A21
SDQ_A20
BA9
BB9
SADQ19
SADQ20
SADQ21
SDQ_A22
SDQ_A24
SDQ_A23
BC11
AY12
AM20
SADQ22
SADQ23
SDQ_A25
SDQ_A26
AM18
AV20
SADQ24
SADQ25
SADQ26
SDQ_A28
SDQ_A29
SDQ_A27
AM21
AP17
AR17
SADQ27
SADQ28
SDQ_A31
SDQ_A30
AP20
AT20
SADQ29
SADQ30
SADQ31
SDQ_A32
SDQ_A34
SDQ_A33
AP32
AV34
AV38
SADQ32
SADQ33
SDQ_A36
SDQ_A35
AU39
AV32
SADQ34
SADQ35
SADQ36
SDQ_A39
SDQ_A37
SDQ_A38
AT32
AR34
AU37
SADQ37
SADQ38
SDQ_A41
SDQ_A40
AR41
AR42
SADQ39
SADQ40
SADQ41
3
SDQ_A44
SDQ_A43
SDQ_A42
AN43
AM40
AU41
SADQ42
SADQ43
SDQ_A45
SDQ_A46
AU42
AP41
SADQ44
SADQ45
SADQ46
SDQ_A47
SDQ_A48
SDQ_A49
AN40
AL41
AL42
SADQ47
SADQ48
SDQ_A51
AF39
AE40
SADQ49
SADQ50
SADQ51
SDQ_A53
SDQ_A52
SDQ_A54
AM41
AM42
AF41
SADQ52
SADQ53
SDQ_A56
SDQ_A55
AF42
AD40
SADQ54
SADQ55
SADQ56
SDQ_A59
SDQ_A57
SDQ_A58
AD43
AA39
AA40
SADQ57
SADQ58
SDQ_A60
SDQ_A61
AE42
AE41
SADQ59
SADQ60
SADQ61
SDQ_A62
SDQ_A63
AB41
AB42
SADQ62
SADQ63
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SACKE1
SCKE_A2
SCKE_A3
BC24
BA25
SACKE2
SACKE3
SDM_A0
SDM_A1
AY2
AR3
SADM0
SDM_A3
SDM_A2
AP18
BB10
SADM2
SADM1
4
SDM_A5
SDM_A4
AP39
AT34
SADM4
SADM3
SDM_A6
SDM_A7
AC40
AG40
SADM6
SADM5
SADM7
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
SBS_B0
SBS_B1
SBS_B2
MCH_VREF_B
MCH_VREF_A
SDM_A[0:7][21]
SCKE_A[0:3][21,23]
SCS_B#0 [22,23]
SCS_B#1 [22,23]
SCS_B#2 [22,23]
SCS_B#3 [22,23]
RAS_B# [22,23]
CAS_B# [22,23]
WE_B# [22,23]
MAA_B0 [22,23]
MAA_B1 [22,23]
MAA_B2 [22,23]
MAA_B3 [22,23]
MAA_B4 [22,23]
MAA_B5 [22,23]
MAA_B6 [22,23]
MAA_B7 [22,23]
MAA_B8 [22,23]
MAA_B9 [22,23]
MAA_B10 [22,23]
MAA_B11 [22,23]MAA_A11[21,23]
MAA_B12 [22,23]
MAA_B13 [22,23]
SODT_B0 [22,23]
SODT_B1 [22,23]
SODT_B2 [22,23]
SODT_B3 [22,23]
SBS_B0 [22,23]
SBS_B1 [22,23]
SBS_B2 [22,23]
SDQS_B0 [22]
SDQS_B#0 [22]
SDQS_B1 [22]
SDQS_B#1 [22]
SDQS_B2 [22]
SDQS_B#2 [22]
SDQS_B3 [22]
SDQS_B#3 [22]
SDQS_B4 [22]
SDQS_B#4 [22]
SDQS_B5 [22]
SDQS_B#5 [22]
SDQS_B6 [22]
SDQS_B#6 [22]
SDQS_B7 [22]
SDQS_B#7 [22]
SCLKB0 [22]
SCLKB#0 [22]
SCLKB1 [22]
SCLKB#1 [22]
SCLKB2 [22]
SCLKB#2 [22]
SCLKB3 [22]
SCLKB#3 [22]
SCLKB4 [22]
SCLKB#4 [22]
SCLKB5 [22]
SCLKB#5 [22]
5
SDM_A[0:7]
SCKE_A[0..3]
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
(INTEL-QG82945G-A2-LF)
(INTEL-QG82945G-A2-LF)
VCC_DDR
R252
R252
80.6R1%0402
80.6R1%0402
C323
C323
D D
C0.1U25Y
C0.1U25Y
R250
R250
80.6R1%0402
80.6R1%0402
SMPCOMP_N
1
SDQ_B[0..63][22]
SMPCOMP_P
AL6
AL8
AL9
AP8
AP9
AP6
AU7
AV6
AR5
SDQ_B8
SDQ_B7
2
AV12
SDQ_B10
SDQ_B9
AR7
AM11
SDQ_B13
SDQ_B11
SDQ_B12
R255
R255
1KR1%0402
1KR1%0402
AR12
AR10
AM15
SDQ_B16
SDQ_B14
SDQ_B15
AV15
AM13
SDQ_B17
SDQ_B18
AN12
AR13
AM17
SDQ_B20
SDQ_B19
SDQ_B21
AT15
AP15
AM24
SDQ_B24
SDQ_B23
SDQ_B22
AV24
AM23
AM26
SDQ_B27
SDQ_B25
SDQ_B26
AP21
AR21
AP24
SDQ_B29
SDQ_B28
SDQ_B30
AT24
AU27
AN29
SDQ_B33
SDQ_B31
SDQ_B32
AR31
SDQ_B34
PLACE CLOSE TO MCH
MCH_VREF_A MCH_VREF_B
C334
C334
C0.1U25Y
C0.1U25Y
AJ11
AM10
SDQ_B0
SDQ_B3
SDQ_B4
SDQ_B1
SDQ_B5
SDQ_B2
SDQ_B6
VCC_DDR VCC_DDR
R253 1KR1%0402R253 1KR1%0402
C356
C356
C0.1U10Y
C0.1U10Y
AP27
AR27
AP31
AU31
AM31
SDQ_B39
SDQ_B36
SDQ_B38
SDQ_B35
SDQ_B37
R256 1KR1%0402R256 1KR1%0402
C345
C345
C0.1U10Y
C0.1U10Y
AP35
AP37
AN32
SDQ_B42
SDQ_B40
SDQ_B41
3
AL35
AR35
AU38
SDQ_B43
SDQ_B45
SDQ_B44
AJ34
AL34
AM38
AM34
SDQ_B47
SDQ_B49
SDQ_B46
SDQ_B48 SDQ_A50
R258
R258
1KR1%0402
1KR1%0402
AF32
AF34
AL31
SDQ_B51
SDQ_B52
SDQ_B50
SCKE_B[0..3][22,23]
AJ32
AG35
AD32
SDQ_B53
SDQ_B54
SDQ_B55
SDM_B[0..7][22]
C335
C335
C0.1U25Y
C0.1U25Y
Y32
AC32
AD34
SDQ_B58
SDQ_B57
SDQ_B56
AF35
AF37
AA32
SDQ_B61
SDQ_B60
SDQ_B59
AC33
AC35
SDQ_B62
SDQ_B63
SBCKE0
SBCKE1
BA14
AY16
SCKE_B1
SCKE_B0
SBCKE2
SBCKE3
BA13
BB13
SCKE_B3
SCKE_B2
SBDM7
AJ39
AD39
SDM_B7
SDM_B6
AR29
AR38
SDM_B4
SDM_B5
4
AP13
AP23
SDM_B3
SDM_B2
AW7
AL11
SDM_B1
SDM_B0
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
Intel lakeport - Memory 2.0
Intel lakeport - Memory 2.0
Intel lakeport - Memory 2.0
7 33Tuesday, March 07, 2006
7 33Tuesday, March 07, 2006
7 33Tuesday, March 07, 2006
5
SBDM0
SBDM1
SBDM2
SBDM3
SBDM4
SBDM5
SBDM6
1
V_1P5_CORE VCC_DDR
U14C
U14C
EXP_A_RXP_0[25]
EXP_A_RXN_0[25]
EXP_A_RXP_1[25]
EXP_A_RXN_1[25]
A A
EXP_EN_HDR[25]
R111
R111
0R0402
0R0402
EXP_EN
R214
R214
X_1.1KR1%0402
X_1.1KR1%0402
V_2P5_MCH
R219
R219
X_1.1KR1%0402
X_1.1KR1%0402
EXP_EN
B B
should be
connected
SDVO_CTRL_DATA[25]
SDVO_CTRL_CLK[25]
C C
V_2P5_MCH
I = 70mA
V_1P5_CORE
D D
EXP_A_RXP_2[25]
EXP_A_RXN_2[25]
EXP_A_RXP_3[25]
EXP_A_RXN_3[25]
EXP_A_RXP_4[25]
EXP_A_RXN_4[25]
EXP_A_RXP_5[25]
EXP_A_RXN_5[25]
EXP_A_RXP_6[25]
EXP_A_RXN_6[25]
EXP_A_RXP_7[25]
EXP_A_RXN_7[25]
EXP_A_RXP_8[25]
EXP_A_RXN_8[25]
EXP_A_RXP_9[25]
EXP_A_RXN_9[25]
EXP_A_RXP_10[25]
EXP_A_RXN_10[25]
EXP_A_RXP_11[25]
EXP_A_RXN_11[25]
EXP_A_RXP_12[25]
EXP_A_RXN_12[25]
EXP_A_RXP_13[25]
EXP_A_RXN_13[25]
EXP_A_RXP_14[25]
EXP_A_RXN_14[25]
EXP_A_RXP_15[25]
EXP_A_RXN_15[25]
CK_PE_100M_MCH[13]
CK_PE_100M_MCH#[13]
H_FSBSEL0[3,4,13]
H_FSBSEL1[3,4,13]
H_FSBSEL2[3,4,13]
L9 180L1500m_90L9 180L1500m_90
CD100U16EL7
CD100U16EL7
L13
L13
DMI_TXP0[10]
DMI_TXN0[10]
DMI_TXP1[10]
DMI_TXN1[10]
DMI_TXP2[10]
DMI_TXN2[10]
DMI_TXP3[10]
DMI_TXN3[10]
SDVO_CTRL_DATA
SDVO_CTRL_CLK
R218 10KR0402R218 10KR0402
R215 10KR0402R215 10KR0402
R223 10KR0402R223 10KR0402
R220 1KR1%0402R220 1KR1%0402
V_2P5_DAC_FILTERED
+
+
C260
C260
C255
C255
C0.1U16Y0402
C0.1U16Y0402
CP6
CP6
X_COPPER
X_COPPER
X_600L200m_500-1
X_600L200m_500-1
EXP_EN
R216 X_220R0402R216 X_220R0402
R217 X_220R0402R217 X_220R0402
EXPSLR
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_2P5_MCH
C264
C264
C0.01U16X0402
C0.01U16X0402
SEL0
SEL1
SEL2
(INTEL-QG82945G-A2-LF)
(INTEL-QG82945G-A2-LF)
V_FSB_VTT
I = 60mA
VCCA_MPLL
C285
C285
_C1U6.3Y50402/80-20%
_C1U6.3Y50402/80-20%
V_1P5_CORE V_1P5_CORE
I = 55mA
L11
V_1P5_CORE V_1P5_CORE
L11
10U125m_0805-1
10U125m_0805-1
1
+
+
C253
C253
.CD220U10EL7
.CD220U10EL7
C295
C295
C0.1U16X0402
C0.1U16X0402
2
L10
L10
10U125m_0805-1
10U125m_0805-1
CP7
CP7
X_COPPER
X_COPPER
L14
L14
X_600L200m_500-1
X_600L200m_500-1
2
3
V_1P5_CORE
I = 55mA
VCCA_DPLLA VCCA_GPLL
+
+
C252
C252
.CD220U10EL7
.CD220U10EL7
C294
C294
C0.1U16X0402
C0.1U16X0402
I = 45mA
VCCA_HPLL
C286
C286
C0.1U16X0402
C0.1U16X0402
V_1P5_CORE
L12 1U500m_0805L12 1U500m_0805
S6 X_COPPERS6 X_COPPER
R211
R211
X_0R0805
X_0R0805
R427
R427
X_0R0805
X_0R0805
S7 X_COPPERS7 X_COPPER
3
R206 1R1%R206 1R1%
R210 1R1%R210 1R1%
+
+
C254
C254
CD220U10EL7
CD220U10EL7
C263
C263
C10U10Y0805
C10U10Y0805
I = 1.5A
V_1P5_PCIEXPRESSVCCA_DPLLB
C266
C266
C261 C10U10Y0805C261 C10U10Y0805
C10U10Y0805
C10U10Y0805
V_1P5_PCIEXPRESS
I = 45mA
C262
C262
C1U10X
C1U10X
C258
C258
C0.1U16Y0402
C0.1U16Y0402
4
V_1P5_PCIEXPRESS
HSYNC
VSYNC
EXTTS
4
GPCOMP
R247 24.9R1%R247 24.9R1%
R230 10KRR230 10KR
R222 10KRR222 10KR
V_2P5_MCH
R226 10KR0402R226 10KR0402
TP21TP21
5
EXP_A_TXP_0 [25]
EXP_A_TXN_0 [25]
EXP_A_TXP_1 [25]
EXP_A_TXN_1 [25]
EXP_A_TXP_2 [25]
EXP_A_TXN_2 [25]
EXP_A_TXP_3 [25]
EXP_A_TXN_3 [25]
EXP_A_TXP_4 [25]
EXP_A_TXN_4 [25]
EXP_A_TXP_5 [25]
EXP_A_TXN_5 [25]
EXP_A_TXP_6 [25]
EXP_A_TXN_6 [25]
EXP_A_TXP_7 [25]
EXP_A_TXN_7 [25]
EXP_A_TXP_8 [25]
EXP_A_TXN_8 [25]
EXP_A_TXP_9 [25]
EXP_A_TXN_9 [25]
EXP_A_TXP_10 [25]
EXP_A_TXN_10 [25]
EXP_A_TXP_11 [25]
EXP_A_TXN_11 [25]
EXP_A_TXP_12 [25]
EXP_A_TXN_12 [25]
EXP_A_TXP_13 [25]
EXP_A_TXN_13 [25]
EXP_A_TXP_14 [25]
EXP_A_TXN_14 [25]
EXP_A_TXP_15 [25]
EXP_A_TXN_15 [25]
DMI_RXP0 [10]
DMI_RXN0 [10]
DMI_RXP1 [10]
DMI_RXN1 [10]
DMI_RXP2 [10]
DMI_RXN2 [10]
DMI_RXP3 [10]
DMI_RXN3 [10]
V_1P5_CORE
V_2P5_MCH
V_2P5_MCH
BSEL
1
2 FSB FREQUENCY
00
1
0
0
EXP_EN
State Description
LOW
HIGH
EXP_SLR (R46 and Normal high)
State Description
LOW
HIGH
V_1P5_PCIEXPRESS
V_1P5_CORE
C326
C326
C10U10Y0805
C10U10Y0805
V_2P5_MCH
R221 1KRR221 1KR
R229 1KRR229 1KR
TABLE
0
267 MHZ (1067)
0
200 MHZ (800)
00
133 MHZ (533)
1
Only SDVO or PCI-e
operating
SDVO and PCI-e
operating
simultaneously
Only SDVO or PCI-e
operating
SDVO and PCI-e
operating
simultaneously
C332
C332
C10U10Y0805
C10U10Y0805
CAPS for specific core MCH
VCC_DDR VCC_DDR
C407 C10U10Y0805C407 C10U10Y0805
C379 C10U10Y0805C379 C10U10Y0805
C375 C0.1U16Y0402C375 C0.1U16Y0402
C393 C10U10Y0805C393 C10U10Y0805
C394 C0.1U16Y0402C394 C0.1U16Y0402
C406 C10U10Y0805C406 C10U10Y0805
MCH MEMORY DECOUPLING
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Intel Lakeport-PCI EXPRESS
Intel Lakeport-PCI EXPRESS
Intel Lakeport-PCI EXPRESS
5
8 33Tuesday, March 07, 2006
8 33Tuesday, March 07, 2006
8 33Tuesday, March 07, 2006
2.0
2.0
2.0
1
AN26
AN24
AN23
AN21
AN20
AN18
AN17
AN15
AN13
AN4
AN2
AM39
AM37
AM36
AM33
AM9
AM7
AM5
AL43
AL37
U14D
A A
B B
U14D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN27
VSS
AN31
VSS
VSS
AN42
VSS
AP5
AP7
VSS
AP10
VSS
2
VSS
AP12
VSS
AP29
VSS
AP34
VSS
AP38
VSS
AR1
AR6
VSS
VSS
AR15
VSS
AR20
VSS
AR24
VSS
AR32
VSS
AR37
VSS
AR39
VSS
AR43
VSS
AT12
VSS
AT17
VSS
AT18
VSS
AT21
VSS
AT23
VSS
AT26
VSS
AT27
VSS
AT31
VSS
AU6
AU9
VSS
VSS
AU12
VSS
AU13
VSS
AU15
VSS
AU17
VSS
AU20
VSS
AU21
VSS
AU24
VSS
AU26
VSS
AU29
VSS
3
AU32
VSS
AU34
VSS
AV2
AV10
VSS
VSS
AV17
VSS
AV37
VSS
BA4
AW10
VSS
VSS
BA42
VSS
BB3
BB6
VSS
VSS
BB11
VSS
BB14
VSS
BB19
VSS
BB34
VSS
BB39
VSS
BB41
VSS
BC9
4
AE19
AD29
AD27
AD24
AD22
AD20
AD18
AC29
AC25
AC19
AA29
AA27
AA25
Y29
Y26
Y24
Y22
Y20
W25
W23
W21
V29
V26
V24
U29
R29
R26
D43
A40
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSD1VSS
VSSA4VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF20
VSS
AF22
VSS
VSS
AF24
VSS
AY1
BC4
VSS
VSS
5
C C
VSS
VSS
VSS
VSS
VSS
J12
J21
J24
J43
J38
J29
D D
1
VSS
VSS
VSS
VSS
VSS
VSSK7VSSK6VSSK5VSSK3VSS
K13
K12
K10
K15
K20
K27
VSS
K32
VSS
K34
VSS
K37
VSS
K39
VSS
VSS
VSS
VSS
VSS
VSS
VSSL2VSS
L31
L29
L26
L24
L13
L12
L42
2
VSS
VSS
VSS
VSS
VSS
VSS
VSSM9VSSM8VSSM5VSSM3VSS
M35
M21
M20
M13
M10
M37
VSS
VSS
VSSN8VSSN6VSS
N2
N24
N15
N13
VSS
N26
VSS
N27
VSS
N29
VSS
N31
VSS
N33
VSS
N36
VSS
N39
VSS
N43
VSSP3VSS
P26
P24
P15
P14
P27
P29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSST2VSS
VSSU3VSSU5VSSU9VSS
VSS
VSS
VSS
VSS
VSS
VSSV2VSSV8VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSW3VSSY2VSSY5VSSY6VSSY9VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(INTEL-QG82945G-A2-LF)
R30
R31
R34
R37
R39
T42
U12
U14
U31
U33
U36
U38
V11
V12
V14
V34
V36
V37
V38
V39
V43
Y12
Y14
Y31
Y35
Y37
Y39
Y42
AA3
AA8
AF18
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
Date: Sheet of
P30
R12
R14
3
(INTEL-QG82945G-A2-LF)
L17
AE21
AE23
AE25
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Intel lakeport GND 2.0
Intel lakeport GND 2.0
Intel lakeport GND 2.0
5
9 33Tuesday, March 07, 2006
9 33Tuesday, March 07, 2006
9 33Tuesday, March 07, 2006
VSSR9VSSR6VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
AD0[17,28]
AD1[17,28]
AD2[17,28]
AD3[17,28]
C_BE#0[17,28]
C_BE#1[17,28]
C_BE#2[17,28]
C_BE#3[17,28]
DEVSEL#[17,28]
FRAME#[17,28]
IRDY#[17,28]
TRDY#[17,28]
STOP#[17,28]
LOCK#[28]
SERR#[28]
PERR#[17,28]
PCI_PME#[17,28]
R193
R193
33R0402-2
33R0402-2
PREQ#0[28]
PREQ#1[28]
PREQ#2[28]
PREQ#3[28]
PREQ#4[17,28]
PREQ#5[28]
PGNT#0[28]
PGNT#1[28]
PGNT#3[28]
PGNT#4[17]
PGNT#5[28]
PIRQ#A[28]
PIRQ#B[28]
PIRQ#C[28]
PIRQ#D[17,28]
PIRQ#E[28]
PIRQ#F[28]
PIRQ#G[28]
PIRQ#H[28]
IDE_IRQ[24]
AD4[17,28]
AD5[17,28]
AD6[17,28]
AD7[17,28]
AD8[17,28]
AD9[17,28]
AD10[17,28]
AD11[17,28]
AD12[17,28]
AD13[17,28]
AD14[17,28]
AD15[17,28]
AD16[17,28]
AD17[17,28]
AD18[17,28]
AD19[17,28]
AD20[17,28]
AD21[17,28]
AD22[17,28]
AD23[17,28]
AD24[17,28]
AD25[17,28]
AD26[17,28]
AD27[17,28]
AD28[17,28]
AD29[17,28]
AD30[17,28]
AD31[17,28]
PAR[17,28]
SERIRQ
PCIRSTICH#
A A
B B
C246
C246
C10P25N0402
C10P25N0402
RN51
RN51
ICH_PCLK[13]
SERIRQ[14]
PCIRST_ICH#[25,26]
C C
VCC3
R191 X_1KR0402-1R191 X_1KR0402-1
R190 X_1KR0402-1R190 X_1KR0402-1
VCC3_SB
PGNT#4
PGNT#5
PGNT#4
PGNT#5
2
PCI INTERFACE INTERRUPT
PCI INTERFACE INTERRUPT
ICH 7
ICH 7
PART 1/3
PART 1/3
SPI
SPI
3
CPULAN PCI EXPRESSDIRECT MEDIA
CPULAN PCI EXPRESSDIRECT MEDIA
U10A
U10A
R_PLTRST#
HSO_CN1
HSO_CP1
KBRST#
A20GATE
R205
R205
33R0402-2
33R0402-2
C267 C0.1U16X0402C267 C0.1U16X0402
C271 C0.1U16X0402C271 C0.1U16X0402
Closer ICH7 5/7/20
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
4
H_A20M# [3]
H_FERR# [3,4]
H_IGNNE# [3]
H_INIT# [3]
FWH_INIT# [15]
H_INTR [3]
H_NMI [3]
ICH_H_SMI# [3]
H_STPCLK# [3]
TRMTRIP# [3,4]
H_PWRGD [3,4]
PLTRST# [6]
DMI_RXN0 [8]
DMI_RXP0 [8]
DMI_TXN0 [8]
DMI_TXP0 [8]
DMI_RXN1 [8]
DMI_RXP1 [8]
DMI_TXN1 [8]
DMI_TXP1 [8]
DMI_RXN2 [8]
DMI_RXP2 [8]
DMI_TXN2 [8]
DMI_TXP2 [8]
DMI_RXN3 [8]
DMI_RXP3 [8]
DMI_TXN3 [8]
DMI_TXP3 [8]
CK_PE_100M_ICH# [13]
CK_PE_100M_ICH [13]
R209 24.9R1%R209 24.9R1%
LAN_CLK [16]
LAN_RSTSYNC [16]
LAN_RXD0 [16]
LAN_RXD1 [16]
LAN_RXD2 [16]
LAN_TXD0 [16]
LAN_TXD1 [16]
LAN_TXD2 [16]
KBRST# [14]
A20GATE [14]
HSI_N1 [25]
HSI_P1 [25]
HSO_N1 [25]
HSO_P1 [25]
V_DMI
for 82562
VCC3_SB
R420
R420
10KR0402
10KR0402
SERIRQ
KBRST#
A20GATE
U33
U33
AT93C46-10SI-2.7-A
AT93C46-10SI-2.7-A
5
R262 10KR0402R262 10KR0402
R259 10KR0402R259 10KR0402
R268 10KR0402R268 10KR0402
VCC3
VCC3_SB
C550
8P4R-10KR0402
If SPI not be
used, should
be NC
D D
GNT5 GNT4
0 1 Flash cycles routed to SPI
1 0 Flash cycles routed to PCI
1 1 Flash cycles routed to LPC
1
8P4R-10KR0402
VSS_0A4VSS_1
VSS_2B1VSS_3B8VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10C2VSS_11C6VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17E1VSS_18E2VSS_19E8VSS_20
VSS_21F3VSS_22F4VSS_23F5VSS_24
VSS_25
VSS_26
VSS_27G1VSS_28G2VSS_29G5VSS_30G6VSS_31G9VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38H3VSS_39H4VSS_40
F12
F27
A23
B11
B14
B17
B20
B26
B28
D10
D13
D18
D21
D24
2
E15
F28
G14
G18
G21
G24
G25
G26
3
H5
(INTEL-NH82801GR-A1-LF)
(INTEL-NH82801GR-A1-LF)
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7204-0306A
MS-7204-0306A
MS-7204-0306A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
ICH7 - PCI, DMI, CPU, IRQ 2.0
ICH7 - PCI, DMI, CPU, IRQ 2.0
ICH7 - PCI, DMI, CPU, IRQ 2.0
5
C550
X_C10P10N
X_C10P10N
10 33Tuesday, March 07, 2006
10 33Tuesday, March 07, 2006
10 33Tuesday, March 07, 2006
Loading...