MSI MS-7135 Schematic 200

5
4
3
2
1
MS-7135 VER:100 ATX
PageTitle
Cover Sheet 1
*AMD PGA 754 K8-Processor (DDR 400)
D D
*Nvidia CK8S04 *Winbond 83627THF LPC I/O *MARVELL/88E1111L Giga Bit LAN Support *8201CL 100/10 Bit LAN Support *USB 2.0 support (10 Port,integrated into Chip) *ALC655 6 channel S/W Audio *DDR DIMM * 2 *PCI-EXPRESS X16 SLOT * 1 *PCI-EXPRESS X1 SLOT * 1
C C
*AGP SLOT * 1 ( PCI Mode )
*PCI SLOT * 3
B B
Block Diagram 2 GPIO SPEC
3 AMD K8 -> 754 PGA Socket 4,5,6 System Memory
DDR DIMM 1 & 2 DDR Terminations R & C DDR Damping R & Bypass Cap. SYSTEM CHIP NVIDIA CK8S-04 K8 Vcore Power(ISL6568) PCI -Express PO R T(X1,X16) ATA66/100/133 IDE connector AGP & PCI Connectors X 3 Front and Rear USB Port LPC I/O W83627THF& ROM & Floppy&Fan KeyBoard/M o u s e/LPT/COM Connectors LAN_ 88E1111CAA/8201CL ALCALC655 6 channel S/W Audio ACPI Power CONTROLLER (MS-6) System Regulator&Front Panel Decoupling Cap. Power Sequence History OPTION PARTS
7 8 9 10,11,12,13,14,15 16 17 18 19,20 21 22 23 24 25 26 27 28 29 30 31
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li- De St, Ju ng- He City, Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Cover Sheet
MS-7135
1
Last Revision Date:
Thursday, Jan ua r y 19, 2006
Sheet
Rev
200
131
5
4
3
2
1
Block Diagram
VRM ISL6568CB
2-Phase PWM
D D
PCI EXPRESS X16 Connector
C C
Gigabit LAN
10/100 LAN
PCI EXPRESS X16
RGMII/MII
K8 754
Crushk8-04
PCI EXPRESS X 1
D
D
I
I
M
M
M
M
2
1
PCI EXPRESS X1
X 4
Serial ATA
I
I
D
1 AGP Slots
Dual ATA
B B
33/66/100/133
D E 1
E 2
PCI-33
4 PCI Slots
LPC BUS
USB 2.0
SUPER I/OBIOS
AC97 Codec
A A
AC-LINK
Dual USB 1.1 OHCI /2.0 EHCI 8 Ports
Keyboard
Floopy
Parallel
Serial
Mouse
Rear x4 Front x6
5
4
3
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li - D e S t , Jung- He City, Taipei Hsien, Taiwan http://www.msi.com.tw
1
Block Diagram
MS-7135
Last Revision Date: Sheet
Thursday, January 19, 2006
231
of
Rev
200
5
4
3
2
1
GPIO FUNCTION
CK8S-04
D D
C C
NAME Function Description
GPIO_1
GPIO_2/CPU_SLP*
GPIO_3/CPU_CLKRUN*
GPIO_4/SUS_STAT* LAN_RST# ( 88E1111 )
GPIO_5/SYS_ERR*
NC
NC
S/IO GPIO Function Define
Function definePIN NAME
BIOS WRITE PROTECTPin70/GP44
PCI Routing
DEVICES
AGP SLOT
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
INT#
INT#A INT#B
INT#B INT#C INT#D INT#A
INT#C INT#D INT#A INT#B
INT#D INT#A INT#B INT#C
IDSEL
AD22
AD23
AD24
AD25
REQ#/GNT#
PREQ#1 PGNT#1
PREQ#2
PGNT#2
PREQ#3 PGNT#3
PREQ#4 PGNT#4
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
B B
A A
Micro Star Res tricted Secret
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
GPIO Spec.
MS-7135
Last Revision Date: Sheet
Thursday, January 19, 2006
331
1
Rev
200
of
5
4
3
2
1
C173
X_C0.22U16Y
VDD_12_A
VDD_12_A
CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CTLIP1
CTLIN1
C186 C0.22U16Y
D29 D27 D25 C28 C26 B29 B27
T25 R25 U27 U26 V25
U25 W27 W26
AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25
T27
T28
V29
U29
V27
V28
Y29 W29
AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28
Y25 W25
Y27
Y28
R27
R26
T29
R29
C160 C0.22U16Y
U2A
N12-7540051-L06
VLDT0_A6 VLDT0_A5 VLDT0_A4 VLDT0_A3 VLDT0_A2 VLDT0_A1 VLDT0_A0
L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0
L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0
HYPER TRANSPORT - LINK0
2
C174 X_C0.22U16Y
C179 C0.22U16Y
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0 L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
C420 C0.22U16Y
VLDT0_B6 VLDT0_B5 VLDT0_B4 VLDT0_B3 VLDT0_B2 VLDT0_B1 VLDT0_B0
AH29 AH27 AG28 AG26 AF29 AE28 AF25
N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29
J26 J27 J29 K29
N25 P25 P28 P27
C159 C1U10Y
CADON15 CADON14 CADON13 CADON12 CADON11 CADON10 CADON9 CADON8 CADON7 CADON6 CADON5 CADON4 CADON3 CADON2 CADON1 CADON0
CLKOP1 CLKON1 CLKOP0 CLKON0
CTLOP0 CTLON0
Micro Star Res tricted Secret
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
CADOP15 CADOP14 CADOP13 CADOP12 CADOP11 CADOP10 CADOP9 CADOP8 CADOP7 CADOP6 CADOP5 CADOP4 CADOP3 CADOP2 CADOP1 CADOP0
K8 DDR & HT
MS-7135
VLDT0
VLDT0
C60 C4.7U10Y0805
CADOP[0..15] CADON[0..15]CADIN[0..15]
CLKOP1 CLKON1 CLKOP0 CLKON0
CTLOP0 CTLON0
Last Revision Date:
Thursday, January 19, 2006
Sheet
431
1
Rev
200
of
VREF routed as 40~50 mils trace wide , Space>25 mils
D D
C C
B B
DDR_VREF
VDD_25_SUS
Place near CPU in 1" , Routed => 5:10/Trace:Space , Same Length
R63 15R1% R62 15R1%
MD[63..0]
DM[7..0]
A A
-MDQS[7..0]
5
C51 X_C1000P50X
U2B
C65
AE13
AG12
D14 C14
VTT_SENSE
MEMVREF1 MEMZN
MEMZP
C1000P50X
MEMZN MEMZP
MEMRESET_L
MD63
A16 B15 A12 B11 A17 A15 C13 A11 A10
C11
AC1 AC3
AC2 AD1 AE1 AE3
AG3
AJ4
AE2
AF1
AH3
AJ3 AJ5 AJ6
AJ7 AH9 AG5 AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12 AJ14 AJ16
A13
AA1 AG1 AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9 C7 A6
A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3
J2
L2 M1 W1 W3
W2
Y1
R1
A7 C2 H1
T1
A8 D1
J1
MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0
MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0
RSVD_MEMADDA15 RSVD_MEMADDA14
RSVD_MEMADDB15 RSVD_MEMADDB14
MEMORY INTERFACE
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0
MEMRASA_L MEMCASA_L
MEMWEA_L
MEMBANKA1 MEMBANKA0
MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10
MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0
MEMRASB_L MEMCASB_L
MEMWEB_L
MEMBANKB1 MEMBANKB0
MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10
MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0
MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0
MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MAA3 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
VTT_A4 VTT_A1 VTT_A2 VTT_A3 VTT_B1 VTT_B2 VTT_B3 VTT_B4
MEMCKEA MEMCKEB
4
D17 A18 B17 C17 AF16 AG16 AH16 AJ17
AG10 AE8
AE7 D10
C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4
D8 C8 E8 E7 D6 E6 C4 E5
H5 D4 G5
K3 H3
E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5
H4 F5 F4
L5 J5
E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3
N3 N1 U3 V1 N2 P1 U1 U2
VTT_DDR_SUS
MCKE0 MCKE1
MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4
MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13 MAA12 MAA11 MAA10 MAA9 MAA8 MAA7 MAA6 MAA5 MAA4
MAA2 MAA1 MAA0
MAB13 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0
MCKE0 MCKE1
MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4
MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
-MSWEA MEMBANKA1
MEMBANKA0
MAA[13..0]
-MSRASB
-MSCASB
-MSWEB MEMBAKB1
MEMBAKB0
MAB[13..0]
CADIP[0..15]
CLKIP1
CLKIN1
CLKIP0
CLKIN0
VLDT0
R32 49.9R1%
CTLIP0 CTLIN0
3
R39 49.9R1%
5
D D
4
VDDA_25
LAYOUT: Ro ute V DDA trace approx. 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long.
FB1 300L700m_250_0805
VDDIO_SENSE
C52 X_C1000P50X
3
CPU_VDDA_25
C75 C4.7U10Y0805
C63 C0.22U16Y
2
VCCA_PLL trace length from the VR1 to the PGA must be 0.75".
Place al filters close to the PGA.
Keep all power and signal trce away from the VR1.
Place a cut in the GND plane around the VCCA_PLL regulator circuit.
VCC2_5
RN7
7
8
5
6
3
4
1
2
C76 C1000P50X
8P4R-680R
CPU_GD THRM#
-CPURST
-LDTSTOP
FB2
X_120S/0603
1
THERMDC_CPU
AH25
C50 X_C1000P50X
CPU_GD
VLDT0
CPUCLK0_H
CPUCLK0_L
R31 44.2R1% R30 44.2R1%
C1000P50X
X_200R1%
R34
C62
C61 C1000P50X
R35 X_200R1%
Near CPU in 0.5" .
C C
VLDT0
Place near CPU in 1" , Routed => 5:10/Trace:Space , Same Length
VER:A02 CHIP REMOVE
B B
HDT Test Port Signal .
DBREQ_L DBRDY TCK TMS TDI TRST_L
NC_AG17 NC_AH18 NC_AG18
A A
NC_AJ18 NC_D18 NC_B19 NC_C19 NC_D20
5
R29 X_1KR R33 X_1KR
1
2
3
4
5
6
7
8
RN43 X_8P4R-1KR
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
VDDA_25
C53 C4.7U10Y0805
RN13 8P4R-1KR
RN40 8P4R-1KR
VDDA_25 VDD_25_SUS
NC_C18 NC_A19 NC_C21 TDO
4
1 3 5 7
RN46 8P4R-1KR
2 4 6 8
-CPURST
-LDTSTOP
COREFB_H
COREFB_L
Differential , "10:10:5:10:10" .
C70 C0.039U16X
C69 C0.039U16X
VDD_25_SUS
3
CPU_GD
L0_REF1 L0_REF0
R42 169R1%
R36 820R R40 820R
VDDIO_SENSE
VTT_DDR_SUS
246
8
135
7
CLKIN_H
CLKIN_L
NC_AJ23 NC_AH23
DBRDY
TMS TCK TRST_L TDI
NC_C18 NC_A19
NC_AE23 NC_AF23 NC_AF22 NC_AF21
RN9 X_8P4R-1KR
AJ25
AF20 AE18
AJ27
AF27 AE26
A23 A24 B23
AE12 AF12 AE11
AJ21
AH21
AJ23
AH23
AE24 AF24
C16
AG15 AH17
C15 E20
E17 B21 A21
C18 A19 A28
AJ28
AE23 AF23 AF22 AF21
AA2
AG2
B18
AH1
AE21
C20
AG4 AG6
AE9 AG9
C1
J3
R3 D3
C6
VDDA1 VDDA2
RESET_L PWROK LDTSTOP_L
L0_REF1 L0_REF0
COREFB_H COREFB_L CORE_SENSE
VDDIOFB_H VDDIOFB_L VDDIO_SENSE
CLKIN_H CLKIN_L
NC_AJ23 NC_AH23
NC_AE24 NC_AF24
VTT_A5 VTT_B5
DBRDY NC_C15 TMS
TCK TRST_L TDI
NC_C18 NC_A19 KEY1
KEY0 NC_AE23
NC_AF23 NC_AF22 NC_AF21
FREE29 FREE31 FREE33 FREE35 FREE1 FREE37 FREE4 FREE38 FREE41 FREE7 FREE11 FREE12 FREE13 FREE14 FREE40
U2C
THERMTRIP_L
THERMDA THERMDC
VID4 VID3 VID2 VID1 VID0
NC_AG18 NC_AH18 NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20 NC_C21 NC_D18 NC_C19 NC_B19
TDO
NC_AF18
RSVD_SCL RSVD_SDA
FREE26 FREE28 FREE30 FREE32 FREE34 FREE36 FREE10 FREE18 FREE19 FREE42 FREE24 FREE25 FREE27
2
THRM#
A20
THERMDA_CPU
A26
THERMDC_CPU
A27
VID4
AG13 AF14 AG14 AF15 AE15
AG18 AH18 AG17 AJ18
AH19 AJ19
AE19 D20
C21 D18 C19 B19
A22
AF18
D22 C22
B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9
VID4
VID3
VID3
VID2
VID2
VID1
VID1
VID0
VID0
NC_AG18 NC_AH18 NC_AG17 NC_AJ18
FBCLKOUT_H
R41
80.6R1%
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L NC_D20
NC_C21 NC_D18 NC_C19 NC_B19
TDO
Micro Star Res tricted Secret
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
THRM# THERMDA_CPU
THERMDC_CPU
LAYOUT: Route FBCLKOUT_H/L differentially with 20/8/5/ 8 / 2 0 s pacing and trace width. ( In CPU breakout => ro u t e d 5:5:5 )
K8 HDT & MISC
MS-7135
Last Revision Date:
Thursday, January 19, 2006
Sheet
531
1
of
Rev
200
5
U2E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
AA10
AE16
AA20 AC20 AE20
AG20
AJ20
AD21
AG21
AG29
AA22 AC22
AG22
AH22
AJ22
AB23 AD23
AG23
AA24 AC24
AG24
AJ24
AD26 AF26 AH26
AB17 AD17
AA18 AC18
AB19 AD19 AF19
AF2
AA8 AB9
G20 R20 U20 W20
D21 H21 M21
G22
N22 R22 U22
D23 H23
G24 N24
R24 U24 W24
C25 D26
H26 M26
C27 D28
G28 H15
G18
D19 H19
N20
D2
VSS10 VSS11
W6
VSS12
Y7
VSS13 VSS14 VSS15 VSS16
J12
VSS17
B14
VSS18
Y15
VSS19 VSS20
J18
VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31
F21
VSS32 VSS33
K21
VSS34 VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39 VSS40 VSS41
B22
VSS42
E22
VSS43 VSS44
J22
VSS45
L22
VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56
F23
VSS57 VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63 VSS64 VSS65 VSS66
E24
VSS67 VSS68
J24
VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77
B25
VSS78 VSS79
B26
VSS80 VSS81 VSS82 VSS83
T26
VSS84
Y26
VSS85 VSS86 VSS87 VSS88 VSS89
B28
VSS90 VSS91 VSS92
F15
VSS187 VSS188 VSS206 VSS207
B16
VSS208 VSS209 VSS210 VSS211 VSS212
F19
VSS213 VSS214
K19
VSS215
Y19
VSS216 VSS217 VSS218 VSS219
J20
VSS220
L20
VSS221 VSS222
GROUND
5
D D
C C
B B
A A
VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS189 VSS190 VSS191 VSS192 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS223 VSS201 VSS202 VSS203 VSS204 VSS205
L28 R28 W28 AC28 AF28 AH28 C29 F2 H2 K2 M2 P2 T2 V2 Y2 AB2 AD2 AH2 B4 AH4 B6 G6 J6 L6 N6 R6 U6 AA6 AC6 AH6 F7 H7 K7 M7 P7 T7 V7 AB7 AD7 B8 G8 J8 L8 N8 R8 U8 W8 AC8 AH8 F9 H9 K9 M9 P9 T9 V9 Y9 AD9 B10 G10 J10 L10 N10 R10 U10 W10 AC10 AH10 F11 H11 K11 Y11 AB11 AD11 B12 G12 AA12 AC12 AH12 F13 H13 K13 Y13 AB13 AD13 AF17 G14 J14 AA14 AC14 AE14 D16 E15 K15 AB15 AD15 AH14 E16 G16 J16 AA16 AC16 AE29 AJ26 E18 F17 H17 K17 Y17
VCORE
AC15
AB14
AA15
AB16
AA17 AC17 AE17
AB18 AD18 AG19
AC19 AA19
AB20 AD20
W21 AA21 AC21
AB22 AD22
W23 AA23 AC23
AB24 AD24 AH24 AE25
GNDGND
H18 B20 E21 H22
H24 F26
V10 G13 K14 Y14
G15
H16 K16 Y16
G17
F18 K18 Y18
E19 G19
F20 H20 K20 M20 P20 T20 V20 Y20
G21
N21 R21 U21
F22 K22 M22 P22 T22 V22 Y22
E23 G23
N23 R23 U23
B24 D24 F24 K24 M24 P24 T24 V24 Y24
K26 P26 V26
U2D
L7
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6
J23
VDD7 VDD8 VDD9
N7
VDD10
L9
VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17
J15
VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24
J17
VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD39 VDD38
J19
VDD37 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50
J21
VDD51
L21
VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69
L23
VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92
POWER
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO7 VDDIO8
VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29 VDDIO30 VDDIO31 VDDIO32 VDDIO33 VDDIO34 VDDIO35 VDDIO36 VDDIO37 VDDIO38 VDDIO39 VDDIO40 VDDIO41 VDDIO42 VDDIO43 VDDIO44 VDDIO45 VDDIO46 VDDIO47 VDDIO48 VDDIO49 VDDIO50
VDDIO6
VDD96 VDD97 VDD98
VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133
VDD93
VDD94
VDD95
4
VDD_25_SUS
E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4
N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28
4
VCORE
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer, 2 in middle of HT link, and 12 along bottom left side of
VCORE
Claw-hammer.
C540
C538
VCORE
C108
C0.22U16Y
Buck-decoupling Mid-Freq. decoupling Cap. ( 7 * 4.7uF / 0805 , 4*10uF/1206)
VCORE
C33
X_C10U10Y1206
C113 C180P50N
C10U10Y1206
C56
X_C10U10Y1206
In CPU.
C55
X_C1U10Y
C10U10Y1206
C124 X_C0.22U16Y
C10U10Y1206
C57
C541
X_C10U10Y1206
3
C10U10Y1206
C543
C127 X_C0.22U16Y
C74
C34
C0.01U25Y
3
C545
X_C6.8P50N
C10U10Y1206
C132 C0.22U16Y
C503
X_C6.8P50N
C539
C544 X_C0.22U16Y
X_C6.8P50N
GND
C109 C180P50N
C0.22U16Y
C72 X_C0.01U25Y
C73 X_C6.8P50N
C114
C119 C8.2P50N
C125 X_C0.22U16Y
C0.22U16Y
C128
2
C133 C8.2P50N
2
C112 C0.22U16Y
C130 C180P50N
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT ' L C O.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hs i e n, Taiwan http://www.msi.com.tw
1
K8 POWER & GND
MS-7135
Last Revision Date:
Thursday, January 19, 2006
Sheet
1
Rev
200
631
of
5
VDD_25_SUS
4
SYSTEM MEMORY
3
2
VDD_25_SUS
1
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
DR_MD[63..0]
D D
C C
B B
VDD_25_SUS
R82 4.7KR
DDR_VREF
VREF routed as 40~50 mils trace wide , Space>25 mils
-MSWEA
DR_MD0 DR_MD1 DR_MD2 DR_MD3 DR_MD4 DR_MD5 DR_MD6 DR_MD7 DR_MD8 DR_MD9 DR_MD10 DR_MD11 DR_MD12 DR_MD13 DR_MD14 DR_MD15 DR_MD16 DR_MD17 DR_MD18 DR_MD19 DR_MD20 DR_MD21 DR_MD22 DR_MD23 DR_MD24 DR_MD25 DR_MD26 DR_MD27 DR_MD28 DR_MD29 DR_MD30 DR_MD31 DR_MD32 DR_MD33 DR_MD34 DR_MD35 DR_MD36 DR_MD37 DR_MD38 DR_MD39 DR_MD40 DR_MD41 DR_MD42 DR_MD43 DR_MD44 DR_MD45 DR_MD46 DR_MD47 DR_MD48 DR_MD49 DR_MD50 DR_MD51 DR_MD52 DR_MD53 DR_MD54 DR_MD55 DR_MD56 DR_MD57 DR_MD58 DR_MD59 DR_MD60 DR_MD61 DR_MD62 DR_MD63
WP1 WP2
-MSWEA
C17 C0.1U25Y
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VDD8
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
Place 104p and 1000p Cap. near the DIMM
104
112
128
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VDDQ7
DDR DIMM
SOCKET
100
116
136
VDDQ8
VDDQ9
184
VSS14
VSS15
124
143
VDDQ10
VSS16
132
156
164
VDDQ11
VDDQ12
PIN
VSS17
VSS18
139
145
172
VDDQ13
VSS19
152
180
VDDQ14
VSS20
160
82
15
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
SDA
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC5
NC(RESET#)
CKE0 CKE1 CAS# RAS#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VSS21
176
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
BA0 BA1 BA2 SCL
SA0 SA1 SA2
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
-MCS0
157
-MCS1
158 71 163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86 47
103
MAA0
48
MAA1
43
MAA2
41
MAA3
130
MAA4
37
MAA5
32
MAA6
125
MAA7
29
MAA8
122
MAA9
27
MAA10
141
MAA11
118
MAA12 MAB12
115
MAA13
167 59
52 113
SMB_MEM_CLK
92
SMB_MEM_DATA
91 181 182 183
44 45 49 51 134 135 142 144
MEMCLK_H5
16
MEMCLK_L5
17
MEMCLK_H0
137
MEMCLK_L0
138
MEMCLK_H7
76
MEMCLK_L7
75 173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_DM0
97
DR_DM1
107
DR_DM2
119
DR_DM3
129
DR_DM4
149
DR_DM5
159
DR_DM6
169
DR_DM7
177 140
Dimm1
DIMM-184_green
N13-1840141-K06
MAA[13..0]
MEMBANKA0 MEMBANKA1
MEMCLK_H5 MEMCLK_L5 MEMCLK_H0 MEMCLK_L0 MEMCLK_H7 MEMCLK_L7
MCKE0 MCKE1
-MSCASA
-MSRASA
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAA[13..0]
SMB_MEM_CLK SMB_MEM_DATA
VDD_25_SUS
-MSWEB
R84 4.7KR
DDR_VREF
DR_MD0 DR_MD1 DR_MD2 DR_MD3 DR_MD4 DR_MD5 DR_MD6 DR_MD7 DR_MD8 DR_MD9 DR_MD10 DR_MD11 DR_MD12 DR_MD13 DR_MD14 DR_MD15 DR_MD16 DR_MD17 DR_MD18 DR_MD19 DR_MD20 DR_MD21 DR_MD22 DR_MD23 DR_MD24 DR_MD25 DR_MD26 DR_MD27 DR_MD28 DR_MD29 DR_MD30 DR_MD31 DR_MD32 DR_MD33 DR_MD34 DR_MD35 DR_MD36 DR_MD37 DR_MD38 DR_MD39 DR_MD40 DR_MD41 DR_MD42 DR_MD43 DR_MD44 DR_MD45 DR_MD46 DR_MD47 DR_MD48 DR_MD49 DR_MD50 DR_MD51 DR_MD52 DR_MD53 DR_MD54 DR_MD55 DR_MD56 DR_MD57 DR_MD58 DR_MD59 DR_MD60 DR_MD61 DR_MD62 DR_MD63
-MSWEB
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VDD8
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
104
112
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VDDQ7
DDR DIMM
SOCKET
100
128
VDDQ8
VSS14
116
136
VDDQ9
184
VSS15
124
143
VDDQ10
VSS16
132
156
164
VDDQ11
VDDQ12
PIN
VSS17
VSS18
139
145
172
VDDQ13
VSS19
152
180
VDDQ14
VSS20
160
82
15
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
SDA
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
NC(RESET#)
CKE0 CKE1 CAS# RAS#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VSS21
176
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
BA0 BA1 BA2 SCL
SA0 SA1 SA2
-MCS2
157
-MCS3
158 71 163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86 47
103
MAB0
48
MAB1
43
MAB2
41
MAB3
130
MAB4
37
MAB5
32
MAB6
125
MAB7
29
MAB8
122
MAB9
27
MAB10
141
MAB11
118 115
MAB13
167
MEMBAKB0
59
MEMBAKB1
52 113
SMB_MEM_CLK
92
SMB_MEM_DATA
91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
MCKE0
21
MCKE1
111
-MSCASB
65
-MSRASB
154 97
107 119 129 149 159 169 177 140
Dimm2
DIMM-184_green
N13-1840141-K06
VDD_25_SUS
DR_DM0 DR_DM1 DR_DM2 DR_DM3 DR_DM4 DR_DM5 DR_DM6 DR_DM7
-MCS2
-MCS3
MAB[13..0]
MEMBAKB0 MEMBAKB1
MEMCLK_H4 MEMCLK_L4 MEMCLK_H1 MEMCLK_L1 MEMCLK_H6 MEMCLK_L6
-MSCASB
-MSRASB
Place near the DIMM
VDD_25_SUS
R20
1KR1%
A A
C536 X_C0.1U25Y
DDR_VREF
VREF routed as 40~50 mils trace wide , Space>25 mils
DDR_VREF
DIMM1 SLAVE AD D RESS = (1010000X)B = A0
DR_DM[7..0]
DR_DM[7..0]
DIMM2 SLAVE AD D RESS = (1010001X)B = A2
Micro Star Res tricted Secret
R21
1KR1%
C16 C1U10Y
Title
System Memory : DDR DIMM 1,2
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
MS-7135
Last Revision Date:
Thursday, January 19, 2006
Sheet
731
1
Rev
200
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
DR_MD44 DR_MD35 DR_MD40
D D
DR_MD59 DR_MD63 DR_MD62 DR_MD58
-DR_MDQS7 DR_DM7 DR_MD57 DR_MD61
DR_MD60 DR_MD56 DR_MD51 DR_MD55
-MCS1
-MCS0
DR_MD50 DR_MD54
-DR_MDQS6 DR_DM6
MAA13 MAB13 DR_MD53 DR_MD52
DR_MD48 DR_MD49 DR_MD47 DR_MD46
DR_MD43 DR_MD42 DR_DM5 DR_MD41
-MCS1
-MCS0
-DR_MDQS5
-MSCASA
-MSWEB
DR_MD45
-MSRASB
-MSRASA
DR_MD37
DR_MD33
C C
B B
-MSCASA
-MSWEB
-MSRASB
-MSRASA
MEMBAKB0
MEMBANKA0
RN62
7 5 3 1
8P4R-47R0402
RN60
7 5 3 1
8P4R-47R0402
RN58
7 5 3 1
8P4R-47R0402
RN56
7 5 3 1
8P4R-47R0402
RN54
7 5 3 1
8P4R-47R0402
RN53
7 5 3 1
8P4R-47R0402
RN51
7 5 3 1
8P4R-47R0402
RN47
7 5 3 1
8P4R-47R0402
RN44
7 5 3 1
8P4R-47R0402
RN36
7 5 3 1
8P4R-47R0402
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
MEMBAKB1
MEMBANKA1
DR_MD39
DR_MD38 DR_MD34 DR_DM4
-DR_MDQS4
DR_MD36 DR_MD32
MAB0 MAB10 MAA10 MAA0
MAA2 MAB2 DR_MD30 MAA3
MAA4 MAA6 MAB6 MAB5
DR_MD26 DR_DM3
-DR_MDQS3 DR_MD25
DR_MD29 DR_MD28 MAB3 MAB4
MAA5 MAA8 DR_MD24 DR_MD19
VTT_DDR_SUS
RN42
7 5 3 1
8P4R-47R0402
RN38
7 5 3 1
8P4R-47R0402
RN35
7 5 3 1
8P4R-47R0402
RN34
7 5 3 1
8P4R-47R0402
RN32
7 5 3 1
8P4R-47R0402
RN27
7 5 3 1
8P4R-47R0402
RN30
7 5 3 1
8P4R-47R0402
RN29
7 5 3 1
8P4R-47R0402
RN25
7 5 3 1
8P4R-47R0402
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
MCKE0 MCKE1
DR_MD23 MAB8 MAB7 DR_MD22
MAA11 MAB11 MAB9 DR_MD21
DR_MD18 MAA7 MAA9 DR_DM2
-DR_MDQS2 DR_MD17 MAA12 MAB12
DR_MD16 DR_MD11
DR_MD20 DR_MD10 DR_MD15 DR_MD14
DR_DM1 DR_MD13
-DR_MDQS1 DR_MD12
DR_MD9 DR_MD8 DR_MD3 DR_MD6
DR_MD7 DR_MD2 DR_DM0
-DR_MDQS0
DR_MD1 DR_MD5 DR_MD4 DR_MD0
DR_MD27 DR_MD31 MAB1 MAA1
RN22
7 5 3 1
8P4R-47R0402
RN20
7 5 3 1
8P4R-47R0402
RN21
7 5 3 1
8P4R-47R0402
RN17
7 5 3 1
8P4R-47R0402
RN16
7 5 3 1
8P4R-47R0402
RN14
7 5 3 1
8P4R-47R0402
RN11
7 5 3 1
8P4R-47R0402
RN6
7 5 3 1
8P4R-47R0402
RN4
7 5 3 1
8P4R-47R0402
RN2
7 5 3 1
8P4R-47R0402
RN33
7 5 3 1
8P4R-47R0402
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
8 6 4 2
-MSCASB
-MSWEA
-MCS3
-MCS2
-MCS3
-MCS2
-MSCASB
-MSWEA
RN49
7 5 3 1
8P4R-47R0402
VTT_DDR_SUS
8 6 4 2
A A
For DIMM2 Clock
MEMCLK_H4 MEMCLK_L5 MEMCLK_H1 MEMCLK_H6
MEMCLK_H4 MEMCLK_H1
C79 X_C10P50N C80 X_C10P50N C123 X_C10P50N C168 X_C10P50N
5
MEMCLK_L4
MEMCLK_L1 MEMCLK_L6MEMCLK_H6
MEMCLK_L4 MEMCLK_L1 MEMCLK_L6
4
For DIMM1 Clock
MEMCLK_H5 MEMCLK_H7 MEMCLK_H0
MEMCLK_H5 MEMCLK_H7
C167 X_C10P50N C129 X_C10P50N
MEMCLK_L5
MEMCLK_L7 MEMCLK_L0MEMCLK_H0
3
MEMCLK_L7 MEMCLK_L0
DR_DM[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MAB[13..0] MAA[13..0]
DR_DM[7..0]
-DR_MDQS[7..0]
DR_MD[63 ..0] MAB[13..0] MAA[13..0]
2
Micro Star Res tricted Secret
Title
DDR Terminations Bank 0
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-7135
Last Revision Date: Sheet
1
Rev
Thursday, January 19, 2006
831
of
200
5
DDR Terminations
-MDQS0 -DR_MDQS0
R27 10R0402
RN3 8P4R-10R0402
MD0
1
MD4
3
MD5
D D
MD15
C C
B B
MD18
-MDQS[7..0]
-DR_MDQS[7..0] DR_MD[63..0]
MD[63..0]
DR_DM[7..0]
5
MD1
7
RN5 8P4R-10R0402
DM0
1 3
MD7
5
MD6
7
RN8 8P4R-10R0402
1
MD8 DR_MD8
3
MD9 DR_MD9
5 7
R38 10R0402
RN10 8P4R-10R0402
-MDQS1
1
MD13 DR_MD13
3
DM1
5
MD14 DR_MD14
7
RN19 8P4R-10R0402
MD17
1
-MDQS2
3
MD21 DR_MD21
5
DM2
7
R44 10R0402
RN15 8P4R-10R0402
MD10
1
MD20
3
MD11
5
MD16 DR_MD16
7
RN24 8P4R-10R0402
1
MD23 DR_MD23
3 5
MD24
7
RN28 8P4R-10R0402
1
MD29
3 5
-MDQS3
7
RN31 8P4R-10R0402
MD26
1
MD30
3
MD31
5
MD27 DR_MD27
7
DM[7..0]
DR_MD0
2
DR_MD4
4
DR_MD5
6
DR_MD1
8
DR_DM0
2
DR_MD2MD2
4
DR_MD7
6
DR_MD6
8
DR_MD3MD3
2 4 6
DR_MD12MD12
8
-DR_MDQS1
2 4
DR_DM1
6 8
DR_MD17
2
-DR_MDQS2
4 6
DR_DM2
8
DR_MD10
2
DR_MD20
4
DR_MD11
6 8
DR_MD22MD22
2 4
DR_MD19MD19
6
DR_MD24
8
DR_MD28MD28
2
DR_MD29
4
DR_MD25MD25
6
-DR_MDQS3
8
DR_MD26
2
DR_MD30
4
DR_MD31
6 8
-MDQS[7..0]
-DR_MDQS[7..0] DR_MD[63 ..0]
MD[63..0]
DR_DM[7..0]
DM[7..0]
DR_MD15
DR_MD18
MD38
RN37 8P4R-10R0402
RN39 8P4R-10R0402
-MDQS4 -DR_MDQS4 DM4 MD34 DR_MD34
MD42
R64 10R0402
RN41 8P4R-10R0402
MD39 MD40 MD35 MD44 DR_MD44
RN48 8P4R-10R0402
-MDQS5 MD41 DM5 DR_DM5
RN52 8P4R-10R0402
MD43 MD46 DR_MD46 MD47 DR_MD47 MD49 DR_MD49
RN55 8P4R-10R0402
MD48 DR_MD48 MD53 DR_MD53
MD51
RN57 8P4R-10R0402
1 3
MD50
5
MD55
7
RN59 8P4R-10R0402
MD56
1
MD60
3
MD61 DR_MD61
5
MD57 DR_MD57
7
RN61 8P4R-10R0402
DM7
1
-MDQS7
3
MD58 DR_MD58
5 7
MD59
R81 10R0402
MD63
R80 10R0402
DM3
R45 10R0402
4
R58 10R0402
1
2 3 5 7
1 3 5 7
1 3 5 7
1 3 5 7
1 3 5 7
1 3 5 7
DR_MD32MD32
4
DR_MD36MD36
6
DR_MD33MD33
8
DR_MD37MD37
2
4
DR_DM4
6
8
DR_MD39
2
DR_MD40
4
DR_MD35
6
8
DR_MD45MD45
2
-DR_MDQS5
4
DR_MD41
6
8
DR_MD43
2
4
6
8
2
DR_MD52MD52
4
6
DR_DM6DM6
8
R73 10R0402
-DR_MDQS6-MDQS6
2
DR_MD54MD54
4
DR_MD50
6
DR_MD55
8
DR_MD56
2
DR_MD60
4 6 8
DR_DM7
2
-DR_MDQS7
4 6
DR_MD62MD62
8
DR_MD38
DR_MD42
DR_MD51
DR_MD59
DR_MD63
DR_DM3
3
LAYOUT: Place Locate close to Dimm Slot LAYOUT: Locate arround to
C26 C1U10Y C37 X_C1U10Y C45 X_C1U10Y C54 X_C1U10Y C67 C1U10Y C81 X_C1U10Y C87 X_C1U10Y C90 C0.1U25Y C95 C1U10Y C98 X_C1U10Y C110 X_C1U10Y C121 X_C1U10Y C131 C1U10Y C139 X_C1U10Y C144 X_C1U10Y C147 C0.1U25Y
VDD_25_SUS
VTT_DDR_SUSVTT_DDR_SUSVDD_25_SUS
C152
C1U10Y C158 X_C1U10Y C169 X_C1U10Y C181 X_C1U10Y C185 C1U10Y C191 X_C1U10Y C195 X_C1U10Y C199 X_C1U10Y C201 X_C1U10Y C207 C0.1U25Y C214 C1U10Y
VTT_Plane
VDD_25_SUS
LAYOUT: Pl ace on backside,
C546
C542
C1U10Y
C1U10Y
LAYOUT: Lo cate close to Clawhammer socket.
VTT_DDR_SUS
+
12
EC26
_CD1000U6.3EL15
VTT_DDR_SUS
C15
C4.7U10Y0805
VTT_DDR_SUS
LAYOUT: Place Locate close to Dimm Slot
C23 X_C1U10Y
C30 X_C1U10Y
C42 C1U10Y
C47 X_C1U10Y
C49 C0.1U25Y
C58 C1U10Y
C71 X_C1U10Y
C77 X_C1U10Y
C86 C1U10Y
2
VTT_DDR_SUS
C44 C0.1U25Y C41 X_C0.1U25Y C22 C0.1U25Y C533 C0.1U25Y
VDD_25_SUS
C537
C1U10Y
GND
+
12
EC9 _CD1000U6.3EL15
GND
C88 X_C1U10Y
C92 C0.1U25Y
LAYOUT: Lo cate close to Dimm2 socket.
VDD_25_SUS
C93 C1U10Y
C97 X_C1U10Y
C103 X_C1U10Y
GND
C105 C1U10Y
C39 C1U10Y C48 C0.1U25Y C143 C1U10Y C146 C0.1U25Y C164 C1U10Y C198 C0.1U25Y C208 C1U10Y C222 C0.1U25Y C226 C1U10Y C205 C0.1U25Y C194 C4.7U10Y0805 C177 C0.1U25Y C150 C1U10Y C142 C0.1U25Y C135 C1U10Y C106 C0.1U25Y C91 C1U10Y C85 C4.7U10Y0805 C64 C0.1U25Y C43 C4.7U10Y0805
C116 X_C1U10Y
1
LAYOUT: Place between CPU and DIMM
VDD_25_SUS
Power Source
C137 C1U10Y
C140 X_C1U10Y
C126 C0.1U25Y
C28 C1U10Y C40 C0.1U25Y C102 C1U10Y C104 C0.1U25Y C115 X_C1U16Y0805
C136 C0.1U25Y
C141 C1U10Y
C148 C0.1U25Y C157 C1U10Y C165 X_C1U16Y0805 C170 X_C1U16Y0805 C166 C0.1U25Y
C188 C0.1U25Y
GND
C145 X_C1U10Y
C149 C1U10Y
C154
X_C1U10Y
GND
C212
C175
C162
C155 C0.1U25Y
A A
VTT_DDR_SUS
X_C1U10Y
C1U10Y
LAYOUT: Locate arround to VTT_Plane
C176 X_C1U10Y
C184 C1U10Y
C189
C187
C0.1U25Y
X_C1U10Y
C193 C1U10Y
C196 X_C1U10Y
C200 X_C1U10Y
C204 C1U10Y
C209 C0.1U25Y
C1U10Y
GND
Micro Star Res tricted Secret
Title
C24
C13
C21
C27 C0.1U25Y
C9 C0.1U25Y
X_C0.1U25Y
5
4
X_C1U16Y0805
3
C14 X_C0.1U25Y
X_C4.7U10Y0805
C32
C1U16Y0805
C68 X_C0.1U25Y
C82 C0.1U25Y
C227 X_C0.1U25Y
C223 C0.1U25Y
C182
C218 X_C1U16Y0805
2
X_C1U16Y0805
C183 X_C0.1U25Y
C163
GND
X_C0.1U25Y
DDR Terminations Bank 1
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-7135
Last Revision Date:
Thursday, January 19, 2006
Sheet
931
1
Rev
200
of
5
4
3
2
1
U6ABGA740_CRUSHK8_04
SEC 1 OF 7
D D
CADOP[0..15]
CADON[0..15]
C C
VCC3
R139 10KR
-LDTSTOP
VCC3
B B
L10 X_300L700m_250_0805
CP2 X_COPPER
1 2
CADOP0 CADOP1 CADOP2 CADOP3 CADOP4 CADOP5 CADOP6 CADOP7 CADOP8 CADOP9 CADOP10 CADOP11 CADOP12 CADOP13
CADOP14
CADOP15
CADON0 CADON1 CADON2 CADON3 CADON4 CADON5 CADON6 CADON7 CADON8 CADON9 CADON10 CADON11 CADON12 CADON13 CADON14 CADON15
CLKOP0
CLKOP0
CLKON0
CLKON0
CLKOP1
CLKOP1
CLKON1
CLKON1
CTLOP0
CTLOP0
CTLON0
CTLON0
-LDTSTOP
R91 49.9R1% R87 150R1%
HT_VLD VCORE_VLD MEM_VLD HTVDD_EN VCORE_EN
+3.3V_PLL_HT
C235 C1U10Y
VCC3
L11 X_300L700m_250_0805
CP3 X_COPPER
1 2
+3.3V_PLL_CPU
C230 C1U10Y
C220 X_C0.1U25Y
C228 X_C1000P50X
AG30 AF30 AE29 AD27 AC29 AB30 AA30 AA28 AE26 AD26 AC24 AC26 AB26
AG29 AF29 AE28 AD28 AB28 AB29 AA29 AA27 AF26 AD25 AD24 AC25 AB25 AA22
AC27 AC28 AB24 AB23
W27
AF27 AF28
AG28
AG27
Y22 Y24 Y26
Y23 Y25
Y28
M22 N22
AK5 AJ4 AK4 AE3 AD3
HT_RXD0 HT_RXD1 HT_RXD2 HT_RXD3 HT_RXD4 HT_RXD5 HT_RXD6 HT_RXD7 HT_RXD8 HT_RXD9 HT_RXD10 HT_RXD11 HT_RXD12 HT_RXD13 HT_RXD14 HT_RXD15
HT_RXD0* HT_RXD1* HT_RXD2* HT_RXD3* HT_RXD4* HT_RXD5* HT_RXD6* HT_RXD7* HT_RXD8* HT_RXD9* HT_RXD10* HT_RXD11* HT_RXD12* HT_RXD13* HT_RXD14* HT_RXD15*
HT_RX_CLK0 HT_RX_CLK0* HT_RX_CLK1 HT_RX_CLK1*
HT_RXCTL HT_RXCTL*
HT_REQ*/GPIO HT_STOP*
HT_CAL_GND1 HT_CAL_GND2
HT_VLD CPU_VLD MEM_VLD HTVDD_EN CPUVDD_EN
+3.3V_PLL_HT
+3.3V_PLL_CPU
I151
CK804
HT_TXD0 HT_TXD1 HT_TXD2 HT_TXD3 HT_TXD4 HT_TXD5 HT_TXD6 HT_TXD7 HT_TXD8
HT_TXD9 HT_TXD10 HT_TXD11 HT_TXD12 HT_TXD13 HT_TXD14 HT_TXD15
HT_TXD0* HT_TXD1* HT_TXD2* HT_TXD3* HT_TXD4* HT_TXD5* HT_TXD6* HT_TXD7* HT_TXD8* HT_TXD9*
HT_TXD10* HT_TXD11* HT_TXD12* HT_TXD13* HT_TXD14* HT_TXD15*
HT_TX_CLK0
HT_TX_CLK0*
HT_TX_CLK1
HT_TX_CLK1*
HT_TXCTL
HT_TXCTL*
CPU_CLK CPU_CLK*
CPU_CLK_66 CPU_PWROK
CPU_RST*
THERMTRIP*/GPIO
CPU_COMP
TRST*
CADIP0
N27
CADIP1
N29
CADIP2
P29
CADIP3
P28
CADIP4
T28
CADIP5
U28
CADIP6
U30
CADIP7
V29
CADIP8
P25
CADIP9
P26
CADIP10
P22
CADIP11
T25
CADIP12
U22
CADIP13
V26
CADIP14
V24
CADIP15
V22
CADIN0
N28
CADIN1
N30
CADIN2
P30
CADIN3
R29
CADIN4
U27
CADIN5
U29
CADIN6
V30
CADIN7
V28
CADIN8
P24
CADIN9
N26
CADIN10
P23
CADIN11
T26
CADIN12
T22
CADIN13
U26
CADIN14
V25
CADIN15
V23
CLKIP0
R28
CLKIN0
R27
CLKIP1
T23
CLKIN1
T24
CTLIP0
W29
CTLIN0
W28
CPUCLK0_H
L28
CPUCLK0_L
L29 L27
CPU_GD
M26
-CPURST
M28
THRM#
AF25
CPU_COMP
M25
CK8_TCK
AD5
TCK
TDI TDO TMS
AC6 AB6 AC3 AC5
CK8_TDI CK8_TMS
CK8_TRST*
CPUCLK0_H CPUCLK0_L
CPU_GD
-CPURST THRM#
R161 10KR
R173 10KR
CADIP[0..15]
CADIN[0..15]
CLKIP0 CLKIN0 CLKIP1 CLKIN1
CTLIP0 CTLIN0
R165 10KR R172 10KR
VCC3
R112 549R1%
HTVDD_EN
HT_PWRGD
SLP_S5#
VCORE_EN
R136 1KR
R119 0R
R124 0R
R140 0R
MEM_VLD
C280 C0.1U25Y
VCORE_VLD
C277 C0.1U25Y
R123 0R
HT_VLD
C273 C0.1U25Y
A A
Micro Star Restricted Secret
Title
NVIDIA CrushK8-04 Part 1
Document Number
MICRO-STAR INT ' L C O.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hs i e n, Taiwan
5
4
3
2
http://www.msi.com.tw
MS-7135
1
Last Revision Date: Sheet
Thursday, January 19, 2006
10 31
Rev
200
of
+ 21 hidden pages