MSI MS-7115 Schematic 0A
1
2
3
4
5
MS-7115
Title
A A
B B
C C
COVER SHEET
BLOCK DIAGRAM
Intel LGA775
Intel Grantsdale
ICH6
ICS954119 Gen. & FWH
LPC I/O - W83627THF&LM86
Azalia Audio
RTL8110S(B)/8100C
DDR DIMM 1 & 2
DDR Termination Resistors
PCI -Express X16 Port
PCI Slot &MINI PCI 20
VIA-6307 IEEE1394 Controller
USB CONNECTORS
ATX ,Front Panel&LCM&IR
MS7 ACPI Controller
SATA1,2 , IDE1& Fan control
VGA Connector
&Misc
EQ&SRS&FRONT AUDIO
POWER MAP
Clock Distribution Diagram
HISTORY
Version 0A
Page
1
2
3 , 4 , 5
6 , 7 , 8 , 9
10,11,12
13
14
15
16
17
18
19
21
22
23
24
25VRM10.1 Intersil 6565 4Phase
26
27
28
29
30
31
Intel (R) Grantsdale (GMCH) + ICH6 Chipset
Intel Prescott LGA775 Processor
CPU:
Intel Prescott - 3.0G & Above
System Chipset:
Intel Grantsdale - GMCH (North Bridge)
Intel ICH6 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
AC'97 Codec -- ALC 880
LPC Super I/O -- W83627THF
LAN -- Realtek 8100C/8110SB
EEE1394 -- VIA VT6307
CLOCK -- ICS954119
Main Memory:
DDR 1 * 2 (Max 2GB)
Expansion Slots:
PCI EXPRESS X16 SLOT * 1
PCI 2.3 SLOT * 1
MINI PCI SLOT * 1
Intersil PWM:
PCI Routing Table
Controller: HIP6561 3 Phase
Driver: HIP6602B * 1 + HIP6601B * 1
PCI Device
D D
PCI Slot
MINI PCI
VT6307 EEE1394
RTL8110SB/8100C LAN
1
AD17 1 B
AD19 4 D
INTERRUPTIDSEL REQ/GNT
CAD18 2
C3AD22
2
3
4
Title
COVER SHEET
Size Document Number Rev
A3
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
131Wednesday, December 15, 2004
5
of
1
2
3
4
5
VRM 10.1
A A
Intersil
6565A
3-Phase PWM
Intel LGA775 Processor
FSB 133/200MHz Core Clock
Block Diagram
PCI EXPRESS
X16
Connector
Analog
Grantsdale
P/G
Video
Out
B B
UltraDMA
33/66/100
DMI
IDE Primary
SATA
SATA 0~1
USB
ICH6
64bit DDR
133/166/200MHz
2 DDR 1
DIMM
Modules
PCI CNTRL
PCI ADDR/DATA
PCI Slot x
1&MINIPCI
RTL8100C
/8110S(B)
LAN
VT6307
IEEE-1394
USB Port 0~7
AC'97 / Azalia
ALC880
C C
Azalia Codec
33MHz@16.5MB/s
LPC Bus
LPC SIO
Winbond
83627THF
Flash
Keyboard
Serial
Mouse
D D
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
1
2
3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
231Wednesday, December 15, 2004
5
of
1
A A
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
CPU1A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
H_D#[0..63]6
H_PROCHOT#
TP12
H_BSL04,8,13
H_BSL14,8,13
H_BSL24,8,13
H_PWRGD
H_CPURST#
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
LL_ID0
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_DBI#[0..3]6
H_EDRDY#6
H_IERR#4
H_FERR#4,10
H_STPCLK#10
H_INIT#10
H_DBSY#6
H_DRDY#6
H_TRDY#6
B B
VTT_OUT_RIGHT
H_CPURST#
C C
H_PWRGD
D D
THERM#10,11
C537
X_10p
C256
X_10p
VCCP
R424
4.7K
Q63
N-MMBT3904_SOT23
1
H_ADS#6
H_LOCK#6
H_BNR#6
H_HIT#6
H_HITM#6
H_BPRI#6
H_DEFER#6
RN27B 8P4R-51R
3 4
RN28B 8P4R-51R
3 4
RN27A 8P4R-51R
1 2
RN28D 8P4R-51R
7 8
RN27D 8P4R-51R
7 8
CPU_TMPA14
VTIN_GND14
TRMTRIP#4,10
H_PROCHOT#4
H_IGNNE#10
ICH_H_SMI#10
H_SLP#10
H_PWRGD4,10
H_CPURST#4,6
H_PROCHOT#THERM#
2
CPU SIGNAL BLOCK
H_A#[3..31]6
H_A#25
H_A#22
H_A#26
H_A#24
H_A#23
H_A#27
H_A#30
H_A#31
H_A#29
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
AB5
AA5
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
B15
C14
C15
A14
D17
D20
G22
D22
E22
G21
F21
E21
F20
E19
E18
F18
F17
G17
H_D#53
H_D#49
H_D#48
H_D#47
H_D#51
H_D#52
H_D#50
H_D#46
2
H_D#39
H_D#41 H_A#28
H_D#38
H_D#44
H_D#40
H_D#45
H_D#37
H_D#35
H_D#36
H_D#42
H_D#43
H_A#16
H_A#19
H_A#14
H_A#11
H_A#20
H_A#21
AD6
AA4Y4Y6W6AB6W5V4V5U4U5T4U6T5R4M4L4M5P6L5
A22#
A21#
A20#
D35#
D34#
D33#
G18
E16
E15
H_D#33
H_D#34
H_A#13
H_A#18
H_A#17
H_A#12
H_A#15
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
G16
G15
F15
G14
F14
G13
E13
D13
F12
H_D#32
H_D#28
H_D#30
H_D#25
H_D#29
H_D#31
H_D#26
H_D#27
H_D#24
H_A#8
H_A#7
H_A#9
H_A#10
A9#
A8#
A10#
D23#
D22#
D21#
F11
D10
E10D7E9F9F8G9D11
H_D#23
H_D#20
H_D#21
H_D#22
A7#
D20#
3
VRM_SENSE_VCC
C217
X_10u-1206
AM5
AM7
VID7#
ITP_CLK0
D6#
D5#
D4#
H_D#5
H_D#4
H_D#3
<VOLTAGE>
VID5
VID3
VID4
AL4
AK4
AL6
VID6#
VID5#
VID4#
VID_SELECT
GTLREF_SEL
LINT1/NMI
LINT0/INTR
D3#
D2#
D1#
H_D#0
H_D#2
H_D#1
VID0
VID2
VID1
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
GTLREF0
H2
GTLREF1
H29
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
RSVD
G6
RSVD
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
K1
D0#
ZIF-SOCK775-15u
VID[0..5] 25
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_PCREQ#
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_RS#2
H_RS#1
H_RS#0
H_COMP3
H_COMP2
H_COMP1
H_COMP0
VRM_SENSE_VSS
H_A#6
H_A#5
H_A#4
H_A#3
AC2
AN3
AN4
AN5
AN6
AJ3
AK3
A6#
A5#
A4#
A3#
DBR#
RSVD
RSVD
ITP_CLK1
VSS_SENSE
VCC_SENSE
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
C12
B12D8C11
B10
A11
A10A7B7B6A5C6A4C5B4
H_D#16
H_D#18
H_D#19
H_D#17
3
H_D#10
H_D#13
H_D#15
H_D#14
H_D#11
H_D#12
H_D#8
H_D#6
H_D#9
H_D#7
4
VCC_VRM_SENSE 25
VSS_VRM_SENSE 25
VID_SELECT
CPU_GTLREF
GTLREF_SEL
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
TP9
RN29A 8P4R-51R
RN28A 8P4R-51R
RN28C 8P4R-51R
RN27C 8P4R-51R
RN29B 8P4R-51R
RN29C 8P4R-51R
H_PCREQ# 6
H_REQ#4 6
H_REQ#3 6
H_REQ#2 6
H_REQ#1 6
H_REQ#0 6
R244 62R
RN26A 8P4R-62R
1 2
RN26B 8P4R-62R
3 4
RN26D 8P4R-62R
7 8
RN26C 8P4R-62R
5 6
R406 62R
R230 62R
R405 62R
CK_H_CPU# 13
CK_H_CPU 13H_A20M#10
H_RS#[0..2] 6
TP13
TP11
R227 100R/1%
R226 100R/1%
R228 60.4R/1%
R162 60.4R/1%
PLACE RESISTORS OUTSIDE SOCKET
TP4
CAVITY IF NO ROOM FOR VARIABLE
TP5
TP7
RESISTOR DON'T PLACE
TP6
H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 10
H_INTR 10
4
5
RN25
8P4R-680R
VID3
1
VID1
3
VID2
5
VID4
7
VID0
R212 680R
VID5
R210 680R
CPU_GTLREF 4
12
12
56
56
34
56
VTT_OUT_RIGHT
VTT_OUT_LEFT
C268
X_C0.1U25Y
GTLREF_SEL
VCC3
Title
Intel LGA775 - Signals
Size Document Number Rev
A3
Date: Sheet
VTT_OUT_RIGHT 4
V_FSB_VTT
GTLREF_SEL
H_BR#0 4,6
VTT_OUT_LEFT 4
G
R402 110R1%
MICRO-START INT'L CO.,LTD.
MS-7115 0A
2
4
6
8
DS
Q56
2N7002
R404
61.9R1%
VTT_OUT_RIGHT
0.1uF
+12V
R398 249R1%
5
VCCP
R399
10K
G
C264
DS
1.18V
H_TESTHI0
C536
0.1uF
331Wednesday, December 15, 2004
C245
0.1uF
R403
619R1%
Q57
2N7002
MCH_GTLREF 6
of
VCC3
1
VCCP
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U28
U29
U30U8V8
W23
W24
W25
W26
W27
W28
W29
W30W8Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
VCCP
A A
B B
AH15
VCC
VCC
U27
AH18
VCC
VCC
U26
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
VCC
AH25
VCC
VCC
2
AH26
VCC
VCC
T30T8U23
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
3
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30J8J9
K23
K24
K25
K26
K27
K28
K29
K30K8L8
M23
M24
M25
M26
M27
M28
M29
M30M8N23
N24
N25
N26
N27
N28
N29
N30N8P8R8T23
4
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC-IOPLL
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD/VTT_PKGSENSE
HS1
VCC
VCC
VCC
VCC
VCC
VCC
AN25
AN26
AN29
AN30
AN8
123
ROUTEING AS DIFFERENCIAL PAIR
MIN WIDTH 12mils
A23
VCCA
B23
VSSA
D23
RSVD
C23
A25
VTT
A26
VTT
A27
VTT
A28
VTT
A29
VTT
A30
VTT
B25
VTT
B26
VTT
B27
VTT
B28
VTT
B29
VTT
B30
VTT
C25
VTT
C26
VTT
C27
VTT
C28
VTT
C29
VTT
C30
VTT
D25
VTT
D26
VTT
D27
VTT
D28
VTT
D29
VTT
D30
VTT
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
VTT_SEL
F27
F29
HS2
HS3
HS4
ZIF-SOCK775-15u
4
It support DC current if 100mA.
H_VCCIOPLL
components close to cpu 600mils
V_FSB_VTT
L15 10U100m_0805
L14 10U100m_0805
C137
C138
X_10u-1206
22U-1206
<VOLTAGE>
<VOLTAGE>
H_VSSA
C127 C10U10Y0805
C123 C10U10Y0805
C124 X_22u-1206_X5R
CAPS FOR FSB GENERIC
TP1
5
DC voltage drop should
be less than 70mV.
V_FSB_VTT
V_FSB_VTT
component NEAR CPU <1.5 inch
C267
C220P50N
NEAR CPU PIN
TRMTRIP# 3,10
H_FERR# 3,10
CPU_GTLREF ref GND
W>=5MILS; S=15MILS
CPU_GTLREF 3
H_PROCHOT# 3
H_CPURST# 3,6
H_PWRGD 3,10
H_BR#0 3,6
H_IERR# 3
2
VTT_OUT_LEFT
VID_GD#25
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
V_FSB_VTTTRMTRIP#
3
R420
1K
RN20 8P4R-470R
1
2
3
4
5
6
7
8
R419
1.25V VTT_PWRGOOD
1K
VTT_PWG
Q60
N-MMBT3904_SOT23
H_BSL1 3,8,13
H_BSL2 3,8,13
H_BSL0 3,8,13
Title
Intel LGA775 - Power
Size Document Number Rev
A3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
431Wednesday, December 15, 2004
5
of
C C
100 OHMS OVER 210 OHMS RESISTORS
VTT_OUT_RIGHT CPU_GTLREF
GTLREF VOLTAGE SHOULD BE
0.67*VTT = 0.8V
R242
100R/1%
R241
210R/1%
C266
1u
PLACE AT CPU END OF ROUTE
H_FERR#
H_PROCHOT#
H_CPURST#
H_PWRGD
H_BR#0
H_IERR#
VTT_OUT_RIGHT3
VTT_OUT_LEFT3
VTT_OUT_RIGHT3
D D
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
1
R232 X_120R
R245 62R
R229 100R
R225 62R
R246 62R
PLACE AT ICH END OF ROUTE
R151 62R
R152 62R
1
A A
2
3
4
5
TP3
TP2 TP8
AC4
AE3
AE4D1D14
CPU1C
RSVD
RSVD
RSVD
RSVD
VSS
AE29
VSS
AE30
AE5
VSS
AE7
VSS
VSS
AF10
RSVD
VSS
AF13
A12
VSS
A15
VSS
A18
VSS
A2
VSS
A21
VSS
A24
VSS
A6
VSS
A9
VSS
AA23
VSS
AA24
VSS
AA25
VSS
AA26
B B
C C
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TP10
E23
E24E5E6E7F23F6B13J3N4P5V1W1Y3Y7Y5Y2W7W4V7V6V30V3V29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG24
AG7
VSS
AH1
VSS
VSS
AH10
VSS
AH13
VSS
VSS
AH16
RSVD
VSS
AF16
RSVD
VSS
AF17
RSVD
VSS
AF20
RSVD
VSS
AF23
RSVD
VSS
AF24
RSVD
VSS
AF25
RSVD
VSS
AF26
RSVD
VSS
AF27
VSS
AF28
VSS
AF29
RSVD
VSS
AF3
RSVD
VSS
AF30
RSVD
VSS
AF6
AF7
VSS
RSVD
VSS
AG10
RSVD
VSS
AG13
RSVD
VSS
AG16
VSS
AG17
VSS
AG20
AG23
VSS
VSS
AH17
VSS
VSS
AH20
VSS
VSS
AH23
V28
AH24
VSS
VSS
V27
AH3
VSS
VSS
V26
AH6
V25
VSS
VSS
AH7
V24
V23U7U1T7T6T3R7R5R30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
VSS
VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
VSS
AN1
VSS
VSS
VSS
VSS
AN10
VSS
VSS
AN13
VSS
VSS
AN16
VSS
AN17
H28H3H6H7H8H9J4J7K2
AN2
VSS
VSS
VSS
VSS
AN20
VSS
VSS
AN23
VSS
VSS
AN24
VSS
VSS
VSS
VSS
AN27
AN28B1B11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B14
ZIF-SOCK775-15u
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R29
R28
R27
R26
R25
R24
R23R2P7P4P30
P29
P28
P27
P26
P25
P24
P23N7N6N3M7M1L7L6L30L3L29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
VSS
VSS
AL23
VSS
VSS
AL24
VSS
VSS
AL27
VSS
VSS
AL28
AL3
VSS
VSS
AL7
VSS
VSS
L28
L27
L26
L25
L24
L23K7K5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
VSS
VSS
VSS
VSS
AM1
AM10
AM13
D D
Title
Intel LGA775- GND
Size Document Number Rev
A3
1
2
3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
531Wednesday, December 15, 2004
5
of
1
AC11
AB11
Y20
Y19
Y17
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
AJ21
AK21
Y16
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AK24
AL21
H29
K29
J29
G30
G32
K30
L29
M30
L31
L28
J28
K27
K33
M28
R29
L26
N26
M26
N31
P26
N29
P28
R28
N33
T27
T31
U28
T26
T29
J31
N27
E31
R33
E30
M35
L33
M31
F33
E32
H31
G31
F31
L34
N35
J35
N34
L35
M32
P33
K34
P34
J32
M23
M22
AG7
G24
AF7
M14
B23
D24
A23
A24
HXSCOMP
U12A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
DBSY#
DRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
CPURST#
RSTIN#
ICH_SYNC#
HDRCOMP
HDSCOMP
HDSWING
HDVREF
H_A#[3..31]3
A A
H_ADSTB#03
H_ADSTB#13
H_RS#[0..2]3
PLTRST#10,19,24
ICH_SYNC#11
R137
20R1%
R407
8.2K
V_FSB_VTT
1
H_PCREQ#3
H_BR#03,4
H_BPRI#3
H_BNR#3
H_LOCK#3
H_ADS#3
H_REQ#03
H_REQ#13
H_REQ#23
H_REQ#33
H_REQ#43
H_HIT#3
H_HITM#3
H_DEFER#3
H_TRDY#3
H_DBSY#3
H_DRDY#3
H_EDRDY#3
CK_H_MCH13
CK_H_MCH#13
PWRGD11,24
H_CPURST#3,4
R146
60.4R/1%
B B
C C
HXRCOMP W=10MILS;S=7MILS;L=MAX0.5 INCH
V_2P5_MCH
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
PWRGD
PLTRST#
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
ICH_SYNC#
HXSCOMP W=5MILS;S=8MILS;L=MAX 750mils
breakout area spacing can be 5mils
should be routed on single layer
C181
X_C2.2P50N
W20
W16
U20
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AL20
AK18
AJ24
PWRGD
PLTRST#
U16
T20
T19
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AJ23
AJ18
AJ20
2
T17
T16
AA13
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
V31
V30
U30
2
AA14
AA16
AA18
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
V32
Y30
AB29
C539
X_10p
C542
X_10p
AA20
AA21
AA22
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
R31
R30
AA31
V_FSB_VTT
AA23
AA24
AB13
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AA30
AC12
AC13
V_1P5_CORE
AB14
AB15
AB16
AB17
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
RSVRD
AC14
AC15
AC16
AC17
3
AB18
AB19
AB20
AB21
AB22
AB23
AB24
N13
N14
N15
N16
N18
N20
N21
P13
P14
P15
P17
P19
P21
P22
R13
R14
R15
R16
R18
R20
R22
R23
T13
T14
T15
T21
T23
T24
U13
U14
U22
U24
V13
V14
V15
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
RSVRDNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
AC18
AC19
AC20
AC21
AC22
N12
N22
N23
N24
P12
P23
P24
R12
R24
T12
U12
V12
W12
Y12
AA12
AB12
AC23
AC24
AN19
AL28
AJ14
AH24
AG6
AD30
P30
L19
L12
K12
J12
H17
H15
H12
G12
F24
F12
E16
V_FSB_VTT
R141
100R/1%
MCH_GTLREF
R144
210R/1%
GTLREF VOLTAGE SHOULD BE
0.67*VTT=0.8V
100 OHM OVER 210 RESISTORS
C177
0.1uF
C179
X_C220P50N
MCH_GTLREF 3
CAPS SHOULD BE PLACED NEAR MCH PIN
3
V21
V23
V24
VCCNCTF
VCCNCTF
VCCNCTF
C16
AR35
AR34
4
W13
W14
W22
W24
Y13
Y14
Y15
Y21
Y23
Y24
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
NC
AR2
AR1
301R/1%
100R/1%
R138
R139
Intel Grantsdale
AP35
AP1
B35B1A34
A2
HD_SWING VOLTAGE 12MIL TRACE , 10 MIL
SPACE" HD_SWING S/B 1/4*VTT +/- 2%
MAX Length=3 inch
PLACE DIVIDER RESISTOR NEAR VTT
HXSWING
C170
0.01uF
4
H_D#0
J33
HD0#
H_D#1
H33
HD1#
H_D#2
J34
HD2#
H_D#3
G35
HD3#
H_D#4
H35
HD4#
H_D#5
G34
HD5#
H_D#6
F34
HD6#
H_D#7
G33
HD7#
H_D#8
D34
HD8#
H_D#9
C33
HD9#
H_D#10
D33
H_D#11
B34
H_D#12
C34
H_D#13
B33
H_D#14
C32
H_D#15
B32
H_D#16
E28
H_D#17
C30
H_D#18
D29
H_D#19
H28
H_D#20
G29
H_D#21
J27
H_D#22
F28
H_D#23
F27
H_D#24
E27
H_D#25
E25
H_D#26
G25
H_D#27
J25
H_D#28
K25
H_D#29
L25
H_D#30
L23
H_D#31
K23
H_D#32
J22
H_D#33
J24
H_D#34
K22
H_D#35
J21
H_D#36
M21
H_D#37
H23
H_D#38
M19
H_D#39
K21
H_D#40
H20
H_D#41
H19
H_D#42
M18
H_D#43
K18
H_D#44
K17
H_D#45
G18
H_D#46
H18
H_D#47
F17
H_D#48
A25
H_D#49
C27
H_D#50
C31
H_D#51
B30
H_D#52
B31
H_D#53
A31
H_D#54
B27
H_D#55
A29
H_D#56
C28
H_D#57
A28
H_D#58
C25
H_D#59
C26
H_D#60
D27
H_D#61
A27
H_D#62
E24
H_D#63
B25
E34
J26
K19
B26
E33
E35
H26
F26
J19
F19
B29
C29
Title
Size Document Number Rev
A3
Date: Sheet
5
H_D#[0..63] 3
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 3
H_DSTBN#0 3
H_DSTBP#1 3
H_DSTBN#1 3
H_DSTBP#2 3
H_DSTBN#2 3
H_DSTBP#3 3
H_DSTBN#3 3
H_DBI#[0..3] 3
MICRO-START INT'L CO.,LTD.
Intel Grantsdale - CPU
MS-7115 0A
5
631Wednesday, December 15, 2004
of
1
DATA_A[0..63]17,18
A A
SCS_A#017,18
SCS_A#117,18
SCS_A#0
SCS_A#1
RAS_A#17,18
CAS_A#17,18
WE_A#17,18
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A[0..13]17,18
B B
SBS_A017,18
SBS_A117,18
DQS_A[0..7]17,18
SBS_A0
SBS_A1
DQS_A0
DQS_A1
DQS_A2
DQS_A3
DQS_A4
DQS_A5
DQS_A6
DQS_A7
P_DDR0_A17
N_DDR0_A17
P_DDR1_A17
N_DDR1_A17
P_DDR2_A17
N_DDR2_A17
C C
SM_XSLEWIN W=5MILS;S=10MILS;L=MAX 200mils
REF TO GND
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
SM_XSLEWIN
MCH_VREF_AB
SMPCOMP_P
SMPCOMP_N
AM34
AL35
AK34
AL33
AN29
AL34
AP31
AN22
AP22
AN21
AP21
AM21
AP19
AR20
AN16
AN18
AM15
AN23
AP15
AP13
AB33
AP33
AR24
AR28
AR29
AN28
AP26
AR23
AG1
AG2
AL3
AL2
AP7
AR7
AF17
AG17
AM30
AL29
AG35
AG33
AA34
AA35
U34
U35
AM24
AN25
AN2
AN3
AB34
AC33
AP25
AN26
AM2
AM3
AC35
AC34
AN31
AH15
AE16
AJ12
AK12
AE7
AG8
AG4
AE5
AF5
U12B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
RSV
RSV
RSV
RSV
SABA0
SABA1
RSV
SADQS0
RSV
SADQS1
RSV
SADQS2
RSV
SADQS3
RSV
SADQS4
RSV
SADQS5
RSV
SADQS6
RSV
SADQS7
RSV
SACK0
SACK0#
SACK1
SACK1#
SACK2
SACK2#
SACK3
SACK3#
SACK4
SACK4#
SACK5
SACK5#
RSV
RSV_TP1
RSV_TP0
SMXSLEWIN
SMXSLEWOUT
SMVREF0
SRCOMP1
SRCOMP0
RSV
RSV
MCH_VREF_AB
PLACE 0.1UF CAP CLOSE TO MCH
C544
0.1uF
DATA_B[0..63]17,18
D D
SMPCOMP_P MCH_VREF_ABSMPCOMP_N
SMPCOMP_P W=10MILS;S=10MILS;L=MAX 1000mils
REF TO GND
1
VCC_DDR POWER TRACE
VCC_DDR
W=10MILS;S=10MILS
R411 80.6R1%R412 80.6R1%
SMPCOMP_N W=10MILS;S=10MILS;L=MAX 1000mils
C546
REF TO GND
0.1uF
DATA_A0
AE3
SADQ0
DATA_A1
AF3
SADQ1
DATA_A2
AH2
SADQ2
SBDQ0
AH7
DATA_B0
DATA_A3
AJ2
SADQ3
SBDQ1
AJ6
DATA_B1
DATA_A4
AE2
SADQ4
SBDQ2
AL5
DATA_B2
2
DATA_A6
DATA_A5
AE1
SADQ5
SBDQ3
AN6
DATA_B3
DATA_B4
2
DATA_A7
AG3
AH3
SADQ6
SBDQ4
AG9
AH4
DATA_B5
DATA_A8
DATA_A9
AJ1
AK2
SADQ7
SADQ8
SBDQ5
SBDQ6
AM5
AL6
DATA_B6
DATA_B7
DATA_A10
DATA_A11
AN4
SADQ9
SADQ10
SBDQ7
SBDQ8
AJ7
DATA_B9
DATA_B8
DATA_A12
AP4
AJ3
SADQ11
SADQ12
SBDQ9
SBDQ10
AL7
AF11
DATA_B10
DATA_A14
DATA_A15
DATA_A13
AK3
AP2
AP3
SADQ13
SADQ14
SADQ15
SBDQ11
SBDQ12
SBDQ13
AE11
AJ8
AL8
DATA_B12
DATA_B13
DATA_B11
VCC_DDR
DATA_A19
DATA_A18
DATA_A17
DATA_A21
DATA_A20
DATA_A16
AP5
AR5
AN8
AP9
AN5
AP6
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
AG10
AG11
AE13
AF13
AG14
AD14
DATA_B15
DATA_B18
DATA_B16
DATA_B14
DATA_B17
DATA_B19
R409 1K/1%
DATA_A22
DATA_A23
AR8
AN9
SADQ22
SADQ23
SBDQ20
SBDQ21
AD12
AH12
DATA_B20
DATA_B21
DATA_A25
DATA_A24
AK16
AL17
SADQ24
SADQ25
SBDQ22
SBDQ23
AF14
AD15
DATA_B22
DATA_B23
DATA_A26
DATA_A27
AD17
AF19
SADQ26
SADQ27
SBDQ24
SBDQ25
AD18
AK19
DATA_B25
DATA_B24
R408
1K/1%
3
DATA_A34
DATA_A28
DATA_A32
DATA_A33
DATA_A36
DATA_A40
DATA_A42
DATA_A41
DATA_A45
DATA_A48
DATA_A29
DATA_A30
DATA_A31
DATA_A35
AF16
AJ17
AE19
AH18
AH27
AK27
AN30
AK31
AL27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
AE22
AH21
AL18
AH19
AF22
AD21
AF23
AF25
AL25
DATA_B29
DATA_B32
DATA_B28
DATA_B27
DATA_B26
DATA_B34
DATA_B31
DATA_B33
DATA_B30
MCH_VREF_AB W=12MILS;S=12 MILS
BREAK-OUT(BELOW CHIP)W=5MILS;S=5MILS;L=MAX 300MILS
DATA_A37
DATA_A38
AJ28
AL30
SADQ37
SADQ38
SBDQ35
SBDQ36
AJ26
AD23
DATA_B35
DATA_B36
3
DATA_A39
AL31
AJ34
SADQ39
SADQ40
SBDQ37
SBDQ38
AF24
AJ25
DATA_B37
DATA_B38
AH35
AG32
SADQ41
SADQ42
SBDQ39
SBDQ40
AL26
AJ29
DATA_B40
DATA_B39
DATA_A43
DATA_A44
AF34
AJ33
SADQ43
SADQ44
SBDQ41
SBDQ42
AJ31
AG30
DATA_B41
DATA_B42
DATA_A46
AH33
AF33
SADQ45
SADQ46
SBDQ43
SBDQ44
AG31
AK33
DATA_B44
DATA_B43
DATA_A47
AE33
AE35
SADQ47
SADQ48
SBDQ45
SBDQ46
AK32
AG27
DATA_B46
DATA_B45
DATA_A49
AE34
AF28
DATA_B47
DATA_A51
DATA_A50
Y33
W34
SADQ49
SADQ50
SBDQ47
SBDQ48
AE31
AF27
DATA_B48
DATA_B49
DATA_A53
DATA_A52
AD31
AD35
SADQ51
SADQ52
SBDQ49
SBDQ50
AB27
AB26
DATA_B51
DATA_B50
DQM_A[0..7]17,18
SCKE_A117,18
SCKE_A017,18
DATA_A54
DATA_A55
AA32
Y35
SADQ53
SADQ54
SBDQ51
SBDQ52
AE29
AE27
DATA_B52
DATA_B53
DATA_A56
DATA_A57
V34
V33
SADQ55
SADQ56
SBDQ53
SBDQ54
AC28
AC26
DATA_B54
DATA_B55
SCKE_B017,18
SCKE_B117,18
DQM_B[0..7]17,18
DATA_A59
DATA_A58
R32
R34
SADQ57
SADQ58
SBDQ55
SBDQ56
AA29
W29
DATA_B56
DATA_B57
DATA_A61
DATA_A60
W35
W33
SADQ59
SADQ60
SBDQ57
SBDQ58
U26
V29
DATA_B58
DATA_B59
DATA_A62
DATA_A63
T33
T35
SADQ61
SADQ62
SBDQ59
SBDQ60
Y26
AA28
DATA_B60
DATA_B61
SCKE_A0
AL12
SADQ63
SBDQ61
SBDQ62
W26
V28
DATA_B62
DATA_B63
SCKE_A1
AN11
AP11
SACKE0
SACKE1
SACKE2
SBDQ63
SBCKE0
AN10
SCKE_B0
4
DQM_A0
AR11
AF2
SACKE3
SBCKE1
SBCKE2
AM9
AP10
AR9
SCKE_B1
4
DQM_A2
DQM_A1
AL1
AN7
SADM0
SADM1
SBCKE3
AJ5
DQM_B0
SADM2
SBDM0
DQM_A3
AH16
SADM3
SBDM1
AH9
DQM_B1
DQM_A4
AK29
AH13
DQM_B2
DQM_A5
AG34
SADM4
SBDM2
AG20
DQM_B3
DQM_A6
DQM_A7
AA33
U33
SADM5
SADM6
SADM7
SMYSLEWIN
SMYSLEWOUT
SBDM3
SBDM4
SBDM5
SBDM6
AG24
AH31
AD24
DQM_B5
DQM_B6
DQM_B4
5
SCS_B#0
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBBA0
SBBA1
SBDQS0
SBDQS1
SBDQS2
SBDQS3
SBDQS4
SBDQS5
SBDQS6
SBDQS7
SBCK0
SBCK0#
SBCK1
SBCK1#
SBCK2
SBCK2#
SBCK3
SBCK3#
SBCK4
SBCK4#
SBCK5
SBCK5#
RSV_TP3
RSV_TP2
SMVREF1
SBDM7
W31
Intel Grantsdale
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
AP34
SCS_B#1
AN34
AN33
AM33
RAS_B#
AP27
CAS_B#
AN27
WE_B#
AR27
MAA_B0
AM18
MAA_B1
AP18
MAA_B2
AN17
MAA_B3
AR16
MAA_B4
AR15
MAA_B5
AN15
MAA_B6
AP17
MAA_B7
AL15
MAA_B8
AP14
MAA_B9
AN13
MAA_B10
AN20
MAA_B11
AR12
MAA_B12
AM12
MAA_B13MAA_A13
AD32
AN32
AP29
AP30
AP32
SBS_B0
AM27
SBS_B1
AR19
AP23
DQS_B0
AK5
AL4
DQS_B1
AK10
AH10
DQS_B2
AK13
AL14
DQS_B3
AD20
AF20
DQS_B4
AH25
AG26
DQS_B5
AH28
AH30
DQS_B6
AB31
AC30
DQS_B7
W27
Y28
P_DDR0_B
AH22
N_DDR0_B
AG23
P_DDR1_B
AL11
N_DDR1_B
AJ11
P_DDR2_B
AE26
N_DDR2_B
AE25
AL23
AK22
AK9
AL9
AD29
AD28
AL24
AK15
AN14
SM_YSLEWIN
AF9
AE10
MCH_VREF_AB
AE8
PLACE 0.1UF CAP CLOSE TO MCH
SCS_B#0 17,18
SCS_B#1 17,18
RAS_B# 17,18
CAS_B# 17,18
WE_B# 17,18
MAA_B[0..13] 17,18
SBS_B0 17,18
SBS_B1 17,18
DQS_B[0..7] 17,18
P_DDR0_B 17
N_DDR0_B 17
P_DDR1_B 17
N_DDR1_B 17
P_DDR2_B 17
N_DDR2_B 17
SM_YSLEWIN W=5MILS;S=10MILS;L=MAX 200mils
REF TO GND
C545
0.1uF
DQM_B7
Title
Intel Grantsdale - Memory
Size Document Number Rev
A3
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
5
731Wednesday, December 15, 2004
of
1
EXP_A_RXP_019
EXP_A_RXN_019
EXP_A_RXP_119
EXP_A_RXN_119
EXP_A_RXP_219
A A
B B
H_BSL03,4,13 VGA_RED 27
H_BSL13,4,13
H_BSL23,4,13
C C
EXP_A_RXN_219
EXP_A_RXP_319
EXP_A_RXN_319
EXP_A_RXP_419
EXP_A_RXN_419
EXP_A_RXP_519
EXP_A_RXN_519
EXP_A_RXP_619
EXP_A_RXN_619
EXP_A_RXP_719
EXP_A_RXN_719
EXP_A_RXP_819
EXP_A_RXN_819
EXP_A_RXP_919
EXP_A_RXN_919
EXP_A_RXP_1019
EXP_A_RXN_1019
EXP_A_RXP_1119
EXP_A_RXN_1119
EXP_A_RXP_1219
EXP_A_RXN_1219
EXP_A_RXP_1319
EXP_A_RXN_1319
EXP_A_RXP_1419
EXP_A_RXN_1419
EXP_A_RXP_1519
EXP_A_RXN_1519
DMI_ITP_MRP_010
DMI_ITN_MRN_010
DMI_ITP_MRP_110
DMI_ITN_MRN_110
DMI_ITP_MRP_210
DMI_ITN_MRN_210
DMI_ITP_MRP_310
DMI_ITN_MRN_310
CK_PE_100M_MCH13
CK_PE_100M_MCH#13
SDVO_CTRL_DATA19
SDVO_CTRL_CLK19
H_BSL0 BSEL0
H_BSL1 BSEL1
H_BSL2 BSEL2
RN19
1 2
3 4
5 6
7 8
8P4R-10K
R135 X_1KR1%
V_2P5_MCH
V_2P5_DAC_FILTERED
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXN_7 EXP_A_TXP_6
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
EXP_SLR
V_1P5_CORE
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
C148
V_FSB_VTT
0.1uF
U12C
E11
EXPARXP0
F11
EXPARXN0
J11
EXPARXP1
H11
EXPARXN1
F9
EXPARXP2
E9
EXPARXN2
F7
EXPARXP3
E7
EXPARXN3
B3
EXPARXP4
B4
EXPARXN4
D5
EXPARXP5
E5
EXPARXN5
G6
EXPARXP6
G5
EXPARXN6
H8
EXPARXP7
H7
EXPARXN7
J6
EXPARXP8
J5
EXPARXN8
K8
EXPARXP9
K7
EXPARXN9
L6
EXPARXP10
L5
EXPARXN10
P10
EXPARXP11
R10
EXPARXN11
M8
EXPARXP12
M7
EXPARXN12
N6
EXPARXP13
N5
EXPARXN13
P7
EXPARXP14
P8
EXPARXN14
R6
EXPARXP15
R5
EXPARXN15
U5
DMI RXP0
U6
DMI RXN0
T9
DMI RXP1
T8
DMI RXN1
V7
DMI RXP2
V8
DMI RXN2
V10
DMI RXP3
U10
DMI RXN3
A11
GCLKINP
B11
GCLKINN
K13
SDVOCTRLDATA
J13
SDVOCTRLCLK
H16
BSEL0
E15
BSEL1
D17
BSEL2
M16
RSV
F15
RSV
C15
MTYPE
A16
EXP_SLR
B15
RSV
C14
RSV
K15
RSV
L10
VCC
M10
VSS
A17
VCCAHPLL
B17
VCCAMPLL
A12
VCCADPLLA
B13
VCCADPLLB
A14
VCCA3GPLL
A13
VCCHV
E13
VCCACRTDAC
D13
VCCACRTDAC
F13
VSSACRTDAC
Intel Grantsdale
V_1P5_CORE
AD10
AD9
AD8
AD7
AD6
VCC
VCC
VCC
VCC
VTT
VTT
VTT
H22
G22
G21
F22
2
VCC
VTT
AD5
F21
VCC
VTT
AD4
F20
VCC
VTT
AD3
E22
VCC
VTT
AD2
E21
VCC
VTT
AD1
E20
VCC
VTT
AC10
VCC
VTT
E19
AC9
D22
VCC
VTT
AC8
D21
VCC
VTT
AC7
D20
VCC
VTT
AC6
D19
VCC
VTT
AC5
C22
VCC
VTT
AC4
C21
VCC
VTT
AC3
C20
VCC
VTT
AC2
C19
VCC
VTT
AC1
B22
VCC
VTT
AB10
VCC
VTT
B21
3
VCC_DDR
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
W18
V19
V17
U18
AR33
AR31
AR26
AR22
AR18
AR14
AR10
AP28
AP24
AP20
AP16
AP12
AN35
AM32
AM28
AM26
AM25
AM23
AM22
AM20
AM19
AM17
AM16
AM14
AM13
AM11
AM10
AK35W1W2W3W4W6W7W8W9Y1Y2Y3Y4Y5Y6Y7Y8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VTT
VTT
VTT
VTT
VTT
VTT
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
B20
B19
A22
A21
A20
A19
AC25
AB25
AA25
AA11
Y25
Y18
Y11
W25
W11
V25
V20
V16
V11
U25
U11
T25
T18
T11
R25
R11
P25
P11
N25
AD25
N11
M11
AA15
AA17
AA19
N17
VCCSM
VCCSM
VSSNCTF
VSSNCTF
N19
P16
P18
VCCSM
VCCSM
VCCSM
VSSNCTF
VSSNCTF
VSSNCTF
P20
R17
R19
VCC3G
VCC3G
VSSNCTF
VSSNCTF
VSSNCTF
R21
T22
VCC3G
VCC3G
VSSNCTF
VSSNCTF
U15
U21
VCC3G
VCC3G
VSSNCTF
VSSNCTF
U23
V22
W15
VCC3G
VCC3G
VCC3G
VSSNCTF
VSSNCTF
VSSNCTF
W21
W23
4
VCC3G
VCC3G
VSSNCTF
Y22
VCC3G
VCC3G
VCC3G
EXPACOMPO
EXPACOMPI
CRTGREENB
CRTDDCDATA
CRTDDCCLK
DREFCLKINP
DREFCLKINN
PMBMBUSY#
MCHDETECT
V_1P5_PCIEXPRESS
Y9
VCC3G
VCC3G
VCC3G
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
EXPATXP8
EXPATXN8
EXPATXP9
EXPATXN9
EXPATXP10
EXPATXN10
EXPATXP11
EXPATXN11
EXPATXP12
EXPATXN12
EXPATXP13
EXPATXN13
EXPATXP14
EXPATXN14
EXPATXP15
EXPATXN15
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
CRTHSYNC
CRTVSYNC
CRTRED
CRTGREEN
CRTBLUE
CRTREDB
CTRBLUEB
CRTIREF
PMEXTTS
TESTIN#
C159
0.1uF
EXP_A_TXP_0
C10
EXP_A_TXN_0
C9
EXP_A_TXP_1
A9
EXP_A_TXN_1
A8
EXP_A_TXP_2
C8
EXP_A_TXN_2
C7
EXP_A_TXP_3
A7
EXP_A_TXN_3
A6
EXP_A_TXP_4
C6
EXP_A_TXN_4
C5
EXP_A_TXP_5
C2
EXP_A_TXN_5EXP_A_RXP_7
D2
E3
EXP_A_TXN_6EXP_A_RXP_8
F3
EXP_A_TXP_7
F1
EXP_A_TXN_7
G1
EXP_A_TXP_8
G3
EXP_A_TXN_8
H3
EXP_A_TXP_9
H1
EXP_A_TXN_9
J1
EXP_A_TXP_10
J3
EXP_A_TXN_10
K3
EXP_A_TXP_11
K1
EXP_A_TXN_11
L1
EXP_A_TXP_12
L3
EXP_A_TXN_12
M3
EXP_A_TXP_13
M1
EXP_A_TXN_13
N1
EXP_A_TXP_14
N3
EXP_A_TXN_14
P3
EXP_A_TXP_15
P1
EXP_A_TXN_15
R1
DMI_MTP_IRP_0
R3
DMI_MTN_IRN_0
T3
DMI_MTP_IRP_1
T1
DMI_MTN_IRN_1
U1
DMI_MTP_IRP_2
U3
DMI_MTN_IRN_2
V3
DMI_MTP_IRP_3
V5
DMI_MTN_IRN_3
W5
GRCOMP V_1P5_PCIEXPRESS
CRTHSYNC
CRTVSYNC
MCH_DDC_DATA
MCH_DDC_CLK
CK_96M_DREF
CK_96M_DREF#
DACREFSET
EXTTS
R140
24.9R/1%
R136 255R/1%
R392 10K
Y10
W10
E12
D12
F14
D14
H14
G14
E14
J14
L14
M15
M13
M12
A15
K16
G16
R35
A35
EXP_A_TXP_0 19
EXP_A_TXN_0 19
EXP_A_TXP_1 19
EXP_A_TXN_1 19
EXP_A_TXP_2 19
EXP_A_TXN_2 19
EXP_A_TXP_3 19
EXP_A_TXN_3 19
EXP_A_TXP_4 19
EXP_A_TXN_4 19
EXP_A_TXP_5 19
EXP_A_TXN_5 19
EXP_A_TXP_6 19
EXP_A_TXN_6 19
EXP_A_TXP_7 19
EXP_A_TXN_7 19
EXP_A_TXP_8 19
EXP_A_TXN_8 19
EXP_A_TXP_9 19
EXP_A_TXN_9 19
EXP_A_TXP_10 19
EXP_A_TXN_10 19
EXP_A_TXP_11 19
EXP_A_TXN_11 19
EXP_A_TXP_12 19
EXP_A_TXN_12 19
EXP_A_TXP_13 19
EXP_A_TXN_13 19
EXP_A_TXP_14 19
EXP_A_TXN_14 19
EXP_A_TXP_15 19
EXP_A_TXN_15 19
DMI_MTP_IRP_0 10
DMI_MTN_IRN_0 10
DMI_MTP_IRP_1 10
DMI_MTN_IRN_1 10
DMI_MTP_IRP_2 10
DMI_MTN_IRN_2 10
DMI_MTP_IRP_3 10
DMI_MTN_IRN_3 10
close to GMCH 500MILS
R400 39R
R401 39R
MCH_DDC_DATA 27
MCH_DDC_CLK 27
CK_96M_DREF 13
CK_96M_DREF# 13
V_2P5_MCH
5
V_1P5_CORE
C166
VCC_DDR
C232 C10U10Y0805
C221 C10U10Y0805
C241 X_C10U10Y0805
MCH MEMORY DECOUPLING
R2249 CLOSE TO GMCH 500MILSR2249 CLOSE TO GMCH 500MILS
HSYNC 27
VSYNC 27
VGA_GREEN 27
VGA_BLUE 27
DACREFSET SPACING 20MILS
R206 CLOSE TO PINA15
C10U10Y0805
VCC_DDR
C238
X_0.1uF
C10U10Y0805
C158
X_C10U10Y0805
VCCA_DPLLB
C143
X_C10U10Y0805
C154
C153
0.1uF
C161
C157
0.1uF
V_1P5_CORE V_1P5_CORE
C165
0.1uF
FSB GENERIC DECOUPLING
0.1uF
CP9
X_COPPER
L11 X_10U100m_0805
C10U10Y1206
CP7
X_COPPER
L7 X_10U100m_0805
C139
C10U10Y1206
C10U10Y1206
C520
C151
2
VCCA_DPLLA
C528
X_C10U10Y0805
VCCA_HPLL
C164
X_C10U10Y0805
C533
0.1uF
C168
0.1uF
V_1P5_CORE
L10
10uH/100mA_0805
CP11
1 2
X_COPPER
L16 X_90nH
CP10 X_COPPER
R129 X_0R
3
C146
X_C10U10Y0805
V_1P5_PCI
EC18
100U10V
VCCA_GPLL
EXPRESS
C163
0.1uF
C160
0.1uF
V_2P5_MCH
L12 180OHM/1500mA
C126
C10U10Y1206
C10U10Y0805
4
C133
C140
0.1uF
BSEL
1
0
0 133 MHZ (533)
C144
0.01uF
Title
Intel Grantsdale-PCI EXPRESS
Size Document Number Rev
Custom
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
02
PSB FREQUENCY
1
01 200 MHZ (800)0
5
TABLE
831Wednesday, December 15, 2004
of
C149
X_C10U10Y0805
CP6
X_COPPER
VCCA_MPLL V_2P5_DAC_FILTERED
V_1P5_CORE
D D
V_1P5_CORE V_1P5_CORE
L6
X_10U100m_0805
X_COPPER
L8 X_10U100m_0805
C132
C10U10Y1206
CP8
C131
C10U10Y1206
1
C145
C10U10Y1206
1
AR30
AR25
AR21
AR17
AR13
AR6
AR3
AP8
AN1
AM31
AM29
AM8
AM7
AM6
AM4
AL32
AL22
AL19
AL16
AL13
AL10
AK30
AK28
AK26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK25
VSS
VSS
VSS
VSS
VSS
VSS
H13
H21
H24
A10
A18
A26
A30
A33
B10
B12
B14
B16
B18
B24
B28
C11
C13
C17
C18
C23
C35
D10
D11
D15
D16
D18
D23
D25
D26
D28
D30
D31
D32
E10
E17
E18
E23
E26
E29
F10
F16
F18
F23
F25
F29
F30
F32
F35
U12D
A3
A5
B2
B5
B6
B7
B8
B9
C1
C3
C4
D3
D4
D6
D7
D8
D9
E1
E2
E4
E6
E8
F2
F4
F5
F6
F8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G2G4G7G8G9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G10
G11
G13
G15
G17
G19
G20
G23
G26
G27
G28H2H4H5H6H9H10
A A
B B
C C
AK23
VSS
VSS
H25
AK20
VSS
VSS
H27
AK17
VSS
VSS
H30
2
AK14
AK11
AK8
AK7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H32
H34J2J4J7J8J9J10
AK6
VSS
VSS
AK4
VSS
VSS
AK1
VSS
VSS
3
AJ35
AJ32
AJ30
AJ27
AJ22
AJ19
AJ16
AJ15
AJ13
AJ10
AJ9
AJ4
AH34
AH32
AH29
AH26
AH23
AH20
AH17
AH14
AH11
AH8
AH6
AH5
AH1
AG29
AG28
AG25
AG22
AG21
AG19
AG18
AG16
AG15
AG13
AG12
AG5
AF35
AF32
AF31
AF30
AF29
AF26
AF21
AF18
AF15
AF12
AF10
AF8
AF6
AF4
AF1
AE32
AE30
AE28
AE24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J15
J16
J17
J18
J20
J23
J30K2K4K5K6K9K10
K11
K14
K20
K24
K26
K28
K31
K32
K35L2L4L7L8L9L11
L13
L15
L16
L17
L18
L20
L21
L22
L24
L27
L30
L32M2M4M5M6M9M17
M20
M24
M25
M27
M29
M34N2N4N7N8N9N10
VSS
VSS
AE23
VSS
VSS
AE21
VSS
VSS
AE20
VSS
VSS
AE18
VSS
VSS
N28
4
AE17
AE15
AE14
AE12
AE9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N30
N32P2P4P5P6P9P27
AE6
VSS
VSS
AE4
VSS
VSS
AD34
VSS
VSS
AD27
VSS
VSS
P29
AD26
AD22
AD19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P31
Intel Grantsdale
AD16
AD13
AD11
AC32
AC31
AC29
AC27
AB35
AB32
AB30
AB28
AA27
AA26
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
Y34
Y32
Y31
Y29
Y27
W32
W30
W28
W19
W17
V35
V27
V26
V18
V9
V6
V4
V2
V1
U32
U31
U29
U27
U19
U17
U9
U8
U7
U4
U2
T34
T32
T30
T28
T10
T7
T6
T5
T4
T2
R27
R26
R9
R8
R7
R4
R2
P35
P32
5
HS4
NBHeatsink
D D
Title
Intel Grantsdale GND
Size Document Number Rev
A3
1
2
3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7115 0A
931Wednesday, December 15, 2004
5
of
1
2
3
4
5
AF23
A20M#
AE27
CPUSLP#
AF24
FERR#
AG26
A A
B B
C C
D D
AD[31..0]16,20,21
PIRQ#E
PIRQ#H
PIRQ#F
PIRQ#G
1
AD[31..0]
C_BE#[3..0]16,20,21
DEVSEL#16,20,21
PCI_PME#16,20
ICH_PCLK13
PCIRST_ICH6#16,20,21
SERIRQ14
IDE_IRQ26
12
34
56
78
FRAME#16,20,21
TRDY#16,20,21
SERR#16,20
PERR#16,20,21
PREQ#120
PREQ#220
PREQ#316
PREQ#421
PGNT#120
PGNT#220
PGNT#316
PGNT#421
PIRQ#A20
PIRQ#B20
PIRQ#C16,20
PIRQ#D20,21
VCC3
IRDY#16,20,21
STOP#16,20,21
LOCK#20
PAR16,20,21
RN15
8P4R-8.2K
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE#0
C_BE#1
C_BE#2
C_BE#3
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5
PREQ#6
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PIRQ#E
PIRQ#F
PIRQ#G
PIRQ#H
SERIRQ
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
J6
H6
G4
G2
C3
J3
A3
J2
J1
E1
C5
G5
E3
P6
G6
R2
L5
B5
M5
B8
F7
E8
B7
C1
B6
F1
C8
E7
F6
D8
N2
L2
M1
L3
D9
C7
C6
M3
AB20
AB16
U11A
ICH6_716
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#
PCICLK
PCIRST#
REQ0#
REQ1#
REQ2#
REQ3#
GPI40/REQ4#
GPI1/REQ5#
GPI0/REQ6#
GNT0#
GNT1#
GNT2#
GNT3#
GPO48/GNT4#
GPO17/GNT5#
GPO16/GNT6#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPI2/PIRQE#
GPI3/PIRQF#
GPI4/PIRQG#
GPI5/PIRQH#
SERIRQ
IDEIRQ
VSS_0
VSS_1
VSS_2
A1
A12
A15
A19
VSS_3
VSS_4
A21
VSS_5
A23
PCI INTERFACE INTERRUPT
PART 1/3
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
A26A4A7A9AA11
AA13
AA16
AA4
2
ICH 6
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
AB1
AB10
AB19
AB2
AB7
AB9
AC10
VSS_21
AC12
AC22
VSS_22
VSS_23
AC23
AC24
CPULAN PCI EXPRESSDIRECT MEDIA
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
AC26
AC3
AC6
AD1
AD10
AD15
AD18
AD2
VSS_33
AD24
AD6
VSS_34
IGNNE#
INIT3_3V#
STPCLK#
A20GATE
THRMTRIP#
GPO49/CPUPWRGD
PLTRST#
PERN_1
PERP_1
PETN_1
PETP_1
PERN_2
PERP_2
PETN_2
PETP_2
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
DMI_0RXN
DMI_0RXP
DMI_0TXN
DMI_0TXP
DMI_1RXN
DMI_1RXP
DMI_1TXN
DMI_1TXP
DMI_2RXN
DMI_2RXP
DMI_2TXN
DMI_2TXP
DMI_3RXN
DMI_3RXP
DMI_3TXN
DMI_3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
EE_DOUT
EE_SHCLK
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
AE10
AE11
AE12
AE2
AE21
AE25
3
INIT#
INTR
NMI
SMI#
RCIN#
EE_CS
EE_DIN
AF27
AE22
AG24
AF25
AG27
AE26
AD23
AF22
AE23
AG25
R5
H25
H24
G27
G26
K25
K24
J27
J26
M25
M24
L27
L26
P24
P23
N27
N26
T25
T24
R27
R26
V25
V24
U27
U26
Y25
Y24
W27
W26
AB24
AB23
AA27
AA26
AD25
AC25
F24
F23
F12
B11
E12
E11
C13
C12
C11
E13
D12
F13
D11
B12
DMI_BIAS
R125 24.9R/1%
<200mils
DMI_BIAS W=5MILS;S=7MILS
H_A20M# 3
H_SLP# 3
H_FERR# 3,4
H_IGNNE# 3
H_INIT# 3
FWH_INIT 13
H_INTR 3
H_NMI 3
ICH_H_SMI# 3
H_STPCLK# 3
KBRST# 14
A20GATE 14
TRMTRIP# 3,4
H_PWRGD 3,4
PLTRST# 6,19,24
DMI_MTN_IRN_0 8
DMI_MTP_IRP_0 8
DMI_ITN_MRN_0 8
DMI_ITP_MRP_0 8
DMI_MTN_IRN_1 8
DMI_MTP_IRP_1 8
DMI_ITN_MRN_1 8
DMI_ITP_MRP_1 8
DMI_MTN_IRN_2 8
DMI_MTP_IRP_2 8
DMI_ITN_MRN_2 8
DMI_ITP_MRP_2 8
DMI_MTN_IRN_3 8
DMI_MTP_IRP_3 8
DMI_ITN_MRN_3 8
DMI_ITP_MRP_3 8
CK_PE_100M_ICH# 13
CK_PE_100M_ICH 13
V_1P5_CORE
THERM#3,11
DMI Interface
Trace width 5 mils & 7 mils space.
GMCH breakout space 5 mils, length <
250 mils
Length matching < 5 mils
Trace Length 2" to 11"
PREQ#2
PREQ#3
PREQ#1
PREQ#0
PREQ#6
PREQ#4
PREQ#5
Title
ICH6 - PCI, DMI, CPU, IRQ
Size Document Number Rev
A3
4
Date: Sheet
MS-7115 0A
KBRST#
A20GATE
THERM#
SERIRQ
RN24
1 2
3 4
5 6
7 8
8P4R-10K
12
34
56
78
12
34
56
78
VCC5
RN11
8P4R-2.7K
RN71
8P4R-2.7K
VCC3
MICRO-START INT'L CO.,LTD.
10 31Wednesday, December 15, 2004
5
of
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