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W370
User Manual
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Block Diagram
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User Manual
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Table of contents
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Motorola W370, W375 Service Manual

W370/W375
Level 3
Circuit Description
10 August 2006
V1.0
W370/W375 Level 3 C
Index
1.1 Band selection........................................................................................... 5
1.2 Frontend................................................................................................... 5
1.3 Demodulation............................................................................................ 7
1.4 Audio Codec.............................................................................................. 9
1.4.1 Voice Downlink Patch ...............................................................................9
1.5 Earpiece Receiver .................................................................................... 10
1.6 Headset.................................................................................................. 10
1.7 Speaker Phone ........................................................................................ 10
1.8 Data Download Receive Path.................................................................... 10
1.9 26MHz System Clock................................................................................ 11
2.1 Audio (Voice uplink Patch)........................................................................ 12
2.2 Data Download Transmit Path .................................................................. 13
2.3 Stereo Audio Path.................................................................................... 13
2.4 Modulation.............................................................................................. 14
2.5 Transceiver IC......................................................................................... 16
2.5.1 Function Description .......................................................................... 16
2.5.2 Receiver Section................................................................................ 17
2.5.3 Transmit Section ............................................................................... 18
2.5.4 Digitally- Controlled Crystal Oscillator (DCXO)...................................... 19
2.6 RF TX PA ................................................................................................ 19
7.1 Display Backlights.................................................................................... 23
7.2 Image Processor (For W375 only)............................................................. 24
7.3 Camera Module (For W375 only)............................................................... 24
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W370/W375 Level 3 C
9.1 SIM Card Supply Voltage Generation......................................................... 26
10.1 Keypad Matrix ......................................................................................... 27
13.1 Low-Dropout Voltage Regulators............................................................... 28
13.2 Power Down Methods .............................................................................. 29
14.1 Sleep Up Sequence.................................................................................. 30
14.2 Sleep off Sequence.................................................................................. 31
16.1 Battery Support....................................................................................... 32
16.2 Charger Support...................................................................................... 32
16.3 USB Data Cable Support........................................................................... 33
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W370/W375 Level 3 C
Figures
Figure 1: Receiver Path ..............................................................................6
Figure 2: Syren and Calypso-Plus IC............................................................ 7
Figure 3: Baseband Downlink Block Diagram................................................8
Figure 4: Audio Codec Block Diagram ..........................................................9
Figure 5: Voice Codec Downlink Patch ....................................................... 11
Figure 6: Aero II 26MHz clock circuit ......................................................... 11
Figure 7: Voice Uplink Paths ..................................................................... 12
Figure 8: Stereo Audio Path ...................................................................... 14
Figure 9: Baseband Uplink Block Diagram .................................................. 16
Figure 10: Aero II IC................................................................................ 16
Figure 11: Aero II Transceiver Block Diagram............................................. 17
Figure 12: Aero II Receiver Block Diagram................................................. 18
Figure 13: Aero II Transmit Block Diagram.................................................19
Figure 14: Power Amplifier and Antenna Switch.......................................... 20
Figure 15: Baseband interface................................................................... 21
Figure 16: The pin connections of TFT LCD and U100 Calypso-Plus.............. 23
Figure 17: Function Block Diagram of PAP1312 ..........................................24
Figure 18: SIM interface ........................................................................... 25
Figure 19: Keyboard scanning sequence .................................................... 26
Figure 20: Keyboard connection................................................................ 27
Figure 21: Memory interface ..................................................................... 28
Figure 22: Power Distribution Tree ............................................................ 32
Figure 23: FM Radio Function....................................................................33
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W370/W375 Level 3 C

1 Receive

1.1 Band selection

The radio frequency signal is received from the tri-band antenna. Received GSM RF signal enters the unit at the antenna. L812, C825 and L811 components provide antenna matching. The RF signal then enters mechanical 50-ohm RF connector J800. This RF connector was used for conductive phasing testing. After J800 the RF signal enters
U803 (RF PA and front-end-module) on Pin 15 (ANT), where through control voltages
the RX path is isolated from the TX path. The following table describes how the voltages control the switch of RF path:
W370/
W375 EU
W375 US
Standby Low x x x
EGSM900 GSM850 High Low Low Low
DCS1800 PCS1900 High Low High Low
PCS1900 DCS1800 High Low High High
TX GSM850/900 High High Low x
TX DCS1800/PCS1900 High High High x
The low band GSM850/900 RX signal from U803 (Pin 19) is connected to the SAW filter
BF800. The DCS1800 and PCS1900 band RX signals from U803 (Pin 22 and Pin 23) are
connected to the SAW filter BF801 and BR802 respectively. Those SAW filters also act as Balun transformers. The balanced RF signal of the selected frequency band is then sent to the front end IC U802 (Aero II).

1.2 Frontend

VLogic
PIN 27
TX_EN
PIN 28
BS1
PIN 2
BS2
PIN 1
The receiver block diagram in the Aero II IC U802 is shown in
U802 transceiver uses a digital low-IF receiver architecture that allows for the on-chip
integration of the channel selection filters, eliminating the external RF image reject filters, and the IF SAW filter required in conventional superheterodyne architectures. Compared with direct-conversion architectures, the digital low-IF architecture has a much greater degree of immunity to dc offsets that can arise from RF local oscillator (RFLO) self-mixing, second-order distortion of blockers (AM suppression), and device 1/f noise. The digital low-IF receiver's immunity to dc offsets has the benefit of expanding part selection and improving manufacturing.
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Figure 1. The Aero II IC
W370/W375 Level 3 C
Figure 1: Receiver Path
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W370/W375 Level 3 C
Figure 2: Syren and Calypso-Plus IC

1.3 Demodulation The RXI and RXQ signals are feed in the - Dual ADC stage on Syren IC U101 (Pin

G11, G12, F11 and F12). The baseband codec (BBC) is composed of a baseband uplink
path (BUL) and a baseband downlink path (BDL).
The BDL path includes two identical circuits for processing the analog baseband I and Q components generated by the RF circuits. The first stage of the BDL path is a continuous second-order anti-aliasing filter that prevents aliasing of out-of-band frequency components due to sampling in the ADC. This filter serves also as an adaptation stage between external and on-chip circuitry.
The anti-aliasing filter is followed by a fourth-order - modulator that performs analog-to-digital conversion at a sampling rate of 6.5 MHz. The ADC provides 2-bit words to a digital filter that performs the decimation by a ratio of 24 to lower the sampling rate to 270.833 kHz. The ADC also provides channel separation by providing enough rejection of the adjacent channels to allow the demodulation performances required by the GSM specification.
The BDL path includes an offset register, in which the value representing the channel dc offset is stored. This value is subtracted from the output of the digital filter before transmitting the digital samples to the Calypso-Plus IC U100 (DSP) via the BSP. Upon reset, the offset register is loaded with 0s; its content is updated during the calibration process.
The typical sequence of burst reception consists of:
1. Power up the BDL path
2. Perform an offset calibration
3. Convert and filter the I and Q components and transmit digital samples
Timing of this sequence is controlled via the TSP, which receives serial real-time control signals from the TPU of the Calypso-Plus IC U100 (DSP) device. Three real-time signals
control the transmission of a burst: BDLON, BDLCAL, and BDLENA. Each signal
corresponds to a time window.
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W370/W375 Level 3 C
BDLON high sets the BDL path in power-on mode after a delay corresponding to the
power-on settling time of the analog block. BDLCAL enables the offset calibration
window. Two offset calibration modes are possible and are selected by the state of bit 9
(EXTCAL) of the baseband codec control register. When EXTCAL is 0, the analog inputs
are disconnected from the external world and internally shorted. The result of conversion
done in this state is stored in the offset register. When EXTCAL is 1, the analog input
remains connected to external circuitry, and the result of conversion, including in this case internal offset plus external circuitry offset, is stored in the offset register. The duration of the calibration window depends mainly on the settling time of the digital filter.
Data conversion starts with the rising edge of the BDLENA signal; however, the first
eight I and Q samples are not transmitted to the Calypso-Plus IC U100 (DSP), since they
are meaningless due to the group delay of the digital filter. The rising edge of BDLENA is
also used by the IBIC to affect the transmit path of the BSP to the BUL path during the
entire reception window. At the falling edge of BDLENA, the conversion in progress is
completed and samples are transmitted before stopping the conversion process. Finally,
BDLON low sets the BDL path in power-down mode.
Figure 3: Baseband Downlink Block Diagram
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W370/W375 Level 3 C
Figure 4: Audio Codec Block Diagram

1.4 Audio Codec

The Audio codec consist of a voice codec dedicated to GSM application and an audio stereo line. The voice codec circuitry processes analog audio components in the uplink path and applies this signal to the voice signal interface for eventual baseband modulation. In the downlink path, the codec circuitry changes voice component data received from the voice serial interface into analog audio. The voice codec support an 8/16 kHz sampling frequency. The stereo audio path converts audio component data received from the I2S serial interface into analog audio. The following paragraphs describe these uplink/downlink and audio stereo functions in more details.

1.4.1 Voice Downlink Patch

The VDL path receives speech samples at the rate of 8 kHz from the Calypso-Plus IC U100
(DSP) via the VSP and converts them to analog signals to drive the external speech
transducer.
The digital speech coming from the Calypso-Plus IC U100 (DSP) is first fed to a speech digital filter that has two functions. The first function is to interpolate the input signal and to increase the sampling rate from 8 kHz up to 40 kHz to allow the digital-to-analog conversion to be performed by an over-sampling digital modulator. The second function is to band-limit the speech signal with both low-pass and high-pass transfer functions. The filter, the PGA gain, and the volume gain can be bypassed by programming.
The interpolated and band-limited signal is fed to a second order - digital modulator
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W370/W375 Level 3 C
sampled at 1 MHz to generate a 4-bit (9 levels) over-sampled signal. This signal is then passed through a dynamic element-matching block and then to a 4-bit digital-to-analog converter (DAC).
Due to the over-sampling conversion, the analog signal obtained at the output of the 4–bit DAC is mixed with a high frequency noise. Because a 4–bit digital output is used, a first–order RC filter (included in the output stage) is enough to filter this noise.
The volume control and the programmable gain are performed in the TX digital filter. Volume control is performed in steps of 6 dB from 0 dB to -24 dB. In mute state, attenuation is higher than 40 dB. A fine adjustment of gain is possible from -6 dB to +6 dB in 1–dB steps to calibrate the system depending on the earphone characteristics. The
earphone amplifier provides a full differential signal on the terminals EARP Syren Pin A8 and EARN Syren Pin B8. The 8Ohm speaker amplifier provides a differential signal on the terminals SPKP Syren Pin A6, B6 and SPKN Syren Pin A7, B7.

1.5 Earpiece Receiver The Receiver J10 is connected to EARP Syren Pin A8 and EARN Syren Pin B8.

1.6 Headset

The headset uses a standard 2.5mm phone jack. The headset circuit contains analog switches (U302 and U303), which are normally switched to receiver earpiece after power
on. When system turns on, the signal HS_EN1 and HS_EN2 (U100 Pin Y14, R13) are
applied. When earphone plug in, the phone will detect this action and make an appropriate response to answer a call while incoming call occur. The interrupt for the
headphones is detected on the HS_DETECT (U100 Pin M4) line from Pin 6 of Headset
Jack J301. This signal will be pulled to high when the headset is connected.

1.7 Speaker Phone

When the handset set the hand-free mode, the Syren will switch from EARP/EARN to
SPKP/SPKN trace and receiver signal will be through Audio amplifier U301 to Speaker.

1.8 Data Download Receive Path

The External download cable is connected to the Earphone Jack J301, the headset
connector of the mobile phone. The download path is routed from J301 Pin 2 via U302
Pin 3 to RX_Modem. The RX_Modem signal connects to Calypso-Plus IC U100 Pin C18 to provide this capability. When software is set to download mode, the signal
HS_EN1 (U100 Pin Y14) is applied low, the phone will entered to download state till
download cable pulls out.
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