MOTOROLA SN74LS299DW, SN74LS299DWR2, SN74LS299H, SN74LS299N Datasheet
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS299/D
SN74LS299
8-Bit Shift/Storage Register
with 3-State Outputs
The SN74LS299 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Separate outputs are provided
for flip-flops Q
0
and Q7 to allow easy cascading. A separate active
LOW Master Reset is used to reset the register.
• Common I/O for Reduced Pin Count
• Four Operation Modes: Shift Left, Shift Right, Load and Store
• Separate Shift Right Serial Input and Shift Left Serial Input for Easy
Cascading
• 3-State Outputs for Bus Oriented Applications
• Input Clamp Diodes Limit High-Speed Termination Effects
• ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High
Q
0
, Q
7
–0.4 mA
I
OL
Output Current – Low
Q
0
, Q
7
8.0 mA
I
OH
Output Current – High
I/O
0
– 1/O
7
–2.6 mA
I
OL
Output Current – Low
I/O
0
– 1/O
7
24 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS299N 16 Pin DIP 1440 Units/Box
SN74LS299DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
SN74LS299
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
CP
DS0
DS7
I/O
n
OE1, OE
2
Q0, Q
7
MR
S0, S
1
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
18 17 16 15 14 13
123456
7
20 19
8
V
CC
S
0
S1Ds7Q7I/O
7
I/O
3
I/O
5
I/O
1
OE1OE2I/O6I/O4I/O2I/O0Q
0
910
MR
GND
12 11
CP DS
0
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
S1S
0
DS
0
CLOCK
Q
0
MR
OE
1
OE
2
D
CLR
Q
CK
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
D
S7
Q
7
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
14
1
2
67
3
8
45
9
11
12
13 15 16
17
18
19
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
LOGIC DIAGRAM
SN74LS299
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3
FUNCTION TABLE
INPUTS RESPONSE
MR S1S0OE1OE2CP DS0DS
7
L X X H X X X X
;
L X X X H X X X
Asynchronous Reset Q
0
= Q
7
= LOW
L H H X X X X X
I/O Voltage Undetermined
L L X L L X X X Asynchronous Reset; Q
0
= Q7 = LOW
L X L L L X X X I/O V oltage LOW
H L H X X D X Shift Right; D³Q0; Q0³
Q1; etc.
H L H L L D X Shift Right; D³Q0 & I/O0; Q0³
O1 & I/O1; etc.
H H L X X X D Shift Left; D³Q7; Q7³
Q6; etc.
H H L L L X D Shift Left; D³Q
7
& I/O7; Q7³
Q6 & I/O6; etc.
H H H X X X X Parallel Load; I/On³
Q
n
H L L H X X X X
H L L X H X X X
Hold: I/O Voltage undetermined
H L L L L X X X Hold: I/On = Q
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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